US20090243048A1 - Metallic nanocrystal encapsulation - Google Patents

Metallic nanocrystal encapsulation Download PDF

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Publication number
US20090243048A1
US20090243048A1 US12/055,262 US5526208A US2009243048A1 US 20090243048 A1 US20090243048 A1 US 20090243048A1 US 5526208 A US5526208 A US 5526208A US 2009243048 A1 US2009243048 A1 US 2009243048A1
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US
United States
Prior art keywords
metallic
metallic nanocrystals
nanocrystals
oxide
protective shells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/055,262
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English (en)
Inventor
Joel Dufourcq
Laurent Vandroux
Pierre Mur
Sylvie Bodnar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Microchip Technology Rousset SAS
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Individual
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Priority to US12/055,262 priority Critical patent/US20090243048A1/en
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE reassignment COMMISSARIAT A L'ENERGIE ATOMIQUE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DUFOURCQ, JOEL, MUR, PIERRE, VANDROUX, LAURENT, BODNAR, SYLVIE
Priority to PCT/EP2009/053539 priority patent/WO2009118353A2/fr
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE, ATMEL ROUSSET reassignment COMMISSARIAT A L'ENERGIE ATOMIQUE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DUFOUREQ, JOEL, MUR, PIERRE, VANDROUX, LAURENT, BODNAR, SYLVIE
Publication of US20090243048A1 publication Critical patent/US20090243048A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4417—Methods specially adapted for coating powder
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate

Definitions

  • Non-volatile nanocrystal transistor memory cells use a transistor floating gate as a charge storage region, transferring charge through a tunneling barrier to nanocrystals.
  • the electrostatic properties of a nanocrystal layer are modified, influencing a subsurface channel between source and drain in a MOS transistor to represent various logical values.
  • FIG. 1 is a perspective block diagram of a device having a metal layer to be elaborated into metallic nanocrystals according to an example embodiment.
  • FIG. 2 is a perspective block diagram of a device illustrating formation or elaboration of metallic nanocrystals according to an example embodiment.
  • FIG. 3 is a side cross-section representation of an exposed metallic nanocrystal according to an example embodiment.
  • FIG. 4 is a side cross-section representation of a Silicon precursor exposed metallic nanocrystal according to an example embodiment.
  • FIG. 5 is a side cross-section representation of a metallic nanocrystal having a protective oxide shell according to an example embodiment.
  • FIG. 6 is a block cross-section representation of a memory device having patterned metallic nanocrystals according to an example embodiment.
  • Metallic nanocrystals are used in various embodiments to replace silicon nanocrystals in nanocrystal floating gate memories.
  • Various methods and resulting devices forming protective shells are used to create patterned nanocrystal device for use in floating gate memories and other devices.
  • FIG. 1 is a perspective block diagram of a device 100 having a metal layer 110 to be elaborated into metallic nanocrystals according to an example embodiment.
  • Metal layer 110 is supported by a tunnel oxide layer 115 supported by a substrate 120 in one embodiment.
  • FIG. 2 is a perspective block diagram of a device 200 illustrating formation or elaboration of metallic nanocrystals 210 supported by the substrate 120 .
  • Reference number 210 points to only a few of the metallic nanocrystals to simplify the drawing.
  • the metallic nanocrystals 210 are formed on the oxide layer 115 supported by the substrate 120 .
  • FIG. 3 is a side cross-section representation of an exposed metallic nanocrystal 210 according to an example embodiment, wherein the numbering is consistent with FIGS. 1 and 2 .
  • the metallic nanocrystals may be formed with Pt.
  • Pt nanocrystals with a density above 10 12 /cm 2 the distance between 2 nanocrystals (center to center) is above 4 nm.
  • the metallic nanocrystals 210 are fairly uniformly distributed about the surface of the oxide layer 115 with a density in the 10 10 ⁇ 10 14 /cm 2 range and diameter ranging between 2 and 20 nm in various embodiments.
  • the metallic nanocrystal 210 diameter is a function of the annealing time and thickness of the initial metal layer 110 .
  • the density could be 10 12 /cm 2 and the diameter in the 2-10 nm range. These parameters may be varied significantly in further embodiments.
  • the silanization process can lead to silanized metallic nanocrystals for low thickness of the initial metal layer 110 or a stabilized continuous layer for higher. initial thickness.
  • initial thickness For example, in the case of Pt, an initial Pt layer with a thickness in the range 1-5 nm leads to separated nanocrystals after annealing around 400° C. and an initial metal layer 110 with a thickness around 100 nm leads to a continuous stabilized layer after annealing in the same conditions.
  • the metallic nanocrystals 210 include a metal nobler than silicon according to Ellingham diagrams, which are plots of the free energy of formation of a metal oxide per mole of oxygen (O 2 ) against temperature.
  • Some example metals include but are not limited to Ni, Pt, Ag, and W. Further metals may include Ag and Au.
  • the metallic nanocrystals 210 are then exposed to a Silicon precursor gas, such as SiH 4 , Si 2 H 6 , etc., at a low temperature, such as less than approximately 450° C. This creates a layer of silicon 410 covering the exposed metallic nanocrystals 210 , one of which is shown in FIG. 4 . This may also be referred to as silanization of the metallic nanoparticles.
  • the silicon layer 410 is thick enough to protect the metallic nanoparticles from further selected processing steps.
  • One approach of determining a proper thickness of the silicon layer 410 after silanization involves exposing the metallic nanocrystals 210 to an oxidant, annealing (for example 20% O 2 in nitrogen) and observing with MEB that there is no coalescence of the metallic nanocrystals 210 .
  • dewetting may happen at the same time as the silanization.
  • the silanized metallic nanocrystals 210 are exposed to an oxidizing environment, resulting in oxidation of the silicon layer 410 resulting in a silicon dioxide (SiO 2 ,) protective shell 510 as shown in cross section in FIG. 5 .
  • the protective shell 510 is thick enough to protect the metallic nanocrystals 210 .
  • the forming of the protective shell 510 may also be referred to as passivation of the metallic nanocrystals, e.g., 210 .
  • the protective shell 510 is formed by exposing the metallic nanocrystals 210 to a silicon precursor gas at a temperature less than approximately 450° C.
  • a silicon precursor gas at a temperature less than approximately 450° C.
  • an exposition to a SiH 4 flow at a temperature around 200° C. leads to the formation of a Si protective shell 510 around the metallic nanocrystals 210 .
  • the protective shell 510 may include a metal oxide having a metal similar or different to the metal used to form the metallic nanocrystals 210 .
  • the exposition of silanized metallic nanocrystals 210 formed of Ni (obtained using an exposition to a Silicon precursor at 200° C. for example) to an oxidant atmosphere at temperature above 200° C. could give a protective shell 510 formed by both Nickel oxide and Silicon oxide.
  • the metals used for the nanocrystals are nobler than silicon or other material used to form the protective shell 510 . This facilitates the oxidation of silanized nanocrystals, leading to formation of the protective shell 510 of oxide.
  • protection of the metallic nanocrystals 210 may be provided by other dielectric materials, such as nitrides or silicon with nitride for example.
  • a device 600 illustrated in FIG. 6 comprises silicon substrate 610 , a patterned plurality of metallic nanocrystals 615 supported by the substrate 610 , wherein the metallic nanoparticles 615 have protective oxide shells.
  • Device 600 may be formed using CMOS processing technology.
  • the patterned plurality of metallic nanocrystals 615 comprises a charge storage area for a memory device in one embodiment.
  • a gate 620 is separated from the patterned plurality of metallic nanocrystals 615 by an electrically insulating layer 625 , referred to as a control oxide having an electrical equivalent oxide (EOT) thickness in the 1-20 nm range in one embodiment.
  • EOT electrical equivalent oxide
  • the thickness could be in the range 8-12 nm.
  • control oxide 625 may be varied significantly in further embodiments consistent with desired operation of the device.
  • Layer 625 may be formed of a dielectric material such as SiO 2 , HfA1O, HfO 2 , ONO, SiON or an oxide in various embodiments.
  • the formation of the control oxide may be performed at a high temperature, in the 150-950° C. range (greater than 700° C. for HTO oxide deposition), and may also include oxidant precursors.
  • the formation of the control oxide 625 may require thermal conditions which are not compatible with stability of high density and small size unprotected metallic nanocrystals 615 . Without the process of embodiments of the invention, such temperatures may adversely affect non-encapsulated metallic nanocrystals, and may cause coalescence of the metallic nanocrystals 110 , degrading their ability to hold a charge. When using the process of embodiments of the invention, such a temperature results in an oxide that helps maintain overall device 600 integrity and performance characteristics.
  • the protective shells 510 serve to ensure that the metallic nanocrystals 615 maintain their integrity during formation of the control oxide, and function as desired to hold a charge.
  • a tunnel oxide 630 separates the patterned plurality of metallic nanocrystals 615 from substrate 610 , which includes a transistor channel 635 formed in the substrate 610 opposite the tunnel oxide 630 , patterned metallic nanocrystals 615 and gate 620 such that a charge on the metallic nanocrystals 615 affects the conductive properties of the transistor channel 635 .
  • Tunnel oxide 630 may have an equivalent oxide thickness in the 1-10 nm range in one embodiment and may be varied significantly in further embodiments. Especially for SiO 2 , the thickness may be in the 30-60 nm range.
  • Typical materials for tunnel oxide 630 include but are not limited to SiO 2 , SiON, HfA1O, and HfO 2 . Other materials may also be used.
  • the silanization or passivation includes silanization followed by reoxidation
  • the silanization or passivation helps block metallic nanocrystal diffusion on the tunnel dielectric surface.
  • the passivation in one embodiment begins with a selective deposition of silicon on the metallic nanocrystals.
  • the deposition method may be a chemical vapor deposition with a silicon precursor such as silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ) or other gaseous precursor of silicon.
  • the temperature of the deposition may be selected to avoid diffusion of metal on the tunnel dielectric surface and to allow catalytic reaction between the silicon precursor and the metal. It is a compromise between temperature and pressure.
  • One such temperature range may be above 25° C. and less than approximately 450° C. for SiH 4 used on Pt dots.
  • selective silicon deposition is performed on the metallic nanocrystals without inter-diffusion between metal and silicon.
  • a selective silanization of the metallic nanocrystals results in the formation of a metal-Si compound by reaction between the silicon of the gaseous precursor and the metal of the nanocrystals.
  • a selective oxidation of the silicon part present on the metallic nanocrystals encapsulates the metallic nanocrystals in a protective shell of oxide.
  • the selective oxidation occurs when the metal of the nanocrystals is nobler than the material to be oxidized to form the shell.
  • a silicon oxide shell is formed and may be thermodynamically stable around the metallic nanocrystals.
  • oxidation processes such as natural air oxidation, an annealing under an oxidant atmosphere such as O 2 , NO 2 , NO, etc., or a chemical oxidation using an oxidant liquid solution that is aqueous or organic.
  • the control dielectric may be deposited at high temperature to form a high quality control oxide.
  • the temperature used for dielectric process may range from 150 to 900° C.
  • the temperature may be around or above 700° C.
  • a metal for the metallic nanocrystals is selected that oxidizes in ambient air (especially Ni). This leads to ensuring that no exposure to ambient air is allowed between the metallic nanocrystal formation and the beginning of silanization or passivation.
  • the metallic nanocrystals may be formed with several different metal alloys, such as PtNi. In such a case, the metallic nanocrystal is formed with a core of one metal such as Pt, and is then surrounded by a shell of an oxide of the second metal, such as NiO.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Inorganic Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
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US12/055,262 2008-03-25 2008-03-25 Metallic nanocrystal encapsulation Abandoned US20090243048A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/055,262 US20090243048A1 (en) 2008-03-25 2008-03-25 Metallic nanocrystal encapsulation
PCT/EP2009/053539 WO2009118353A2 (fr) 2008-03-25 2009-03-25 Encapsulation de nanocristal métallique

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110180766A1 (en) * 2008-05-30 2011-07-28 Samsung Electronics Co., Ltd. Nanocrystal-metal oxide-polymer composites and preparation method thereof
US20160126329A1 (en) * 2014-10-30 2016-05-05 City University Of Hong Kong Electronic device for data storage and a method of producing an electronic device for data storage
US9356106B2 (en) 2014-09-04 2016-05-31 Freescale Semiconductor, Inc. Method to form self-aligned high density nanocrystals
US20190319193A1 (en) * 2018-04-11 2019-10-17 Soochow University Auto-polymerization electric storage material based on dopamine, preparation method thereof and application to electric storage device thereof
US10454114B2 (en) 2016-12-22 2019-10-22 The Research Foundation For The State University Of New York Method of producing stable, active and mass-producible Pt3Ni catalysts through preferential co etching

Citations (11)

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US6344403B1 (en) * 2000-06-16 2002-02-05 Motorola, Inc. Memory device and method for manufacture
US20020098653A1 (en) * 2000-06-29 2002-07-25 Flagan Richard C. Aerosol process for fabricating discontinuous floating gate microelectronic devices
US20040180491A1 (en) * 2003-03-13 2004-09-16 Nobutoshi Arai Memory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body
US20050072989A1 (en) * 2003-10-06 2005-04-07 Bawendi Moungi G. Non-volatile memory device
US20060040103A1 (en) * 2004-06-08 2006-02-23 Nanosys, Inc. Post-deposition encapsulation of nanostructures: compositions, devices and systems incorporating same
US20060046384A1 (en) * 2004-08-24 2006-03-02 Kyong-Hee Joo Methods of fabricating non-volatile memory devices including nanocrystals
US20070178291A1 (en) * 2004-08-30 2007-08-02 Sharp Kabushiki Kaisha Fine particle-containing body, fine-particle-containing body manufacturing method, storage element, semiconductor device and electronic equipment
US20070202645A1 (en) * 2006-02-28 2007-08-30 Tien Ying Luo Method for forming a deposited oxide layer
US20080203460A1 (en) * 2006-12-15 2008-08-28 Commissariat A L'energie Atomique Manufacturing method for a nanocrystal based device covered with a layer of nitride deposited by cvd
US20090246510A1 (en) * 2008-03-25 2009-10-01 Commissariat A L'energie Atomique Metallic nanocrystal patterning

Family Cites Families (1)

* Cited by examiner, † Cited by third party
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KR100678477B1 (ko) * 2005-06-15 2007-02-02 삼성전자주식회사 나노크리스탈 비 휘발성 메모리소자 및 그 제조방법

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054735A (en) * 1995-11-16 2000-04-25 Advanced Micro Devices, Inc. Very thin PECVD SiO2 in 0.5 micron and 0.35 micron technologies
US6344403B1 (en) * 2000-06-16 2002-02-05 Motorola, Inc. Memory device and method for manufacture
US20020098653A1 (en) * 2000-06-29 2002-07-25 Flagan Richard C. Aerosol process for fabricating discontinuous floating gate microelectronic devices
US20040180491A1 (en) * 2003-03-13 2004-09-16 Nobutoshi Arai Memory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body
US20050072989A1 (en) * 2003-10-06 2005-04-07 Bawendi Moungi G. Non-volatile memory device
US20060040103A1 (en) * 2004-06-08 2006-02-23 Nanosys, Inc. Post-deposition encapsulation of nanostructures: compositions, devices and systems incorporating same
US20060046384A1 (en) * 2004-08-24 2006-03-02 Kyong-Hee Joo Methods of fabricating non-volatile memory devices including nanocrystals
US20070178291A1 (en) * 2004-08-30 2007-08-02 Sharp Kabushiki Kaisha Fine particle-containing body, fine-particle-containing body manufacturing method, storage element, semiconductor device and electronic equipment
US20070202645A1 (en) * 2006-02-28 2007-08-30 Tien Ying Luo Method for forming a deposited oxide layer
US20080203460A1 (en) * 2006-12-15 2008-08-28 Commissariat A L'energie Atomique Manufacturing method for a nanocrystal based device covered with a layer of nitride deposited by cvd
US20090246510A1 (en) * 2008-03-25 2009-10-01 Commissariat A L'energie Atomique Metallic nanocrystal patterning

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110180766A1 (en) * 2008-05-30 2011-07-28 Samsung Electronics Co., Ltd. Nanocrystal-metal oxide-polymer composites and preparation method thereof
US8105507B2 (en) * 2008-05-30 2012-01-31 Samsung Electronics Co., Ltd. Nanocrystal-metal oxide-polymer composites and preparation method thereof
US9356106B2 (en) 2014-09-04 2016-05-31 Freescale Semiconductor, Inc. Method to form self-aligned high density nanocrystals
US20160126329A1 (en) * 2014-10-30 2016-05-05 City University Of Hong Kong Electronic device for data storage and a method of producing an electronic device for data storage
US9812545B2 (en) * 2014-10-30 2017-11-07 City University Of Hong Kong Electronic device for data storage and a method of producing an electronic device for data storage
US10454114B2 (en) 2016-12-22 2019-10-22 The Research Foundation For The State University Of New York Method of producing stable, active and mass-producible Pt3Ni catalysts through preferential co etching
US20190319193A1 (en) * 2018-04-11 2019-10-17 Soochow University Auto-polymerization electric storage material based on dopamine, preparation method thereof and application to electric storage device thereof
US10714690B2 (en) * 2018-04-11 2020-07-14 Soochow University Auto-polymerization electric storage material based on dopamine, preparation method thereof and application to electric storage device thereof

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WO2009118353A2 (fr) 2009-10-01
WO2009118353A3 (fr) 2009-12-17

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