US20090152639A1 - Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement - Google Patents

Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement Download PDF

Info

Publication number
US20090152639A1
US20090152639A1 US11/959,111 US95911107A US2009152639A1 US 20090152639 A1 US20090152639 A1 US 20090152639A1 US 95911107 A US95911107 A US 95911107A US 2009152639 A1 US2009152639 A1 US 2009152639A1
Authority
US
United States
Prior art keywords
deposition chamber
forming
gas
layer stack
sccm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/959,111
Inventor
Haowen Bu
Jerry Che-Jen Hu
Rajesh Khamankar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US11/959,111 priority Critical patent/US20090152639A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BU, HAOWEN, KHAMANKAR, RAJESH, CHE-JEN-HU, JERRY
Publication of US20090152639A1 publication Critical patent/US20090152639A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0641Nitrides
    • C23C14/0652Silicon nitride
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • H01L21/3185Inorganic layers composed of nitrides of siliconnitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832Multiple layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

Description

    FIELD OF THE INVENTION
  • This invention relates to the field of integrated circuits. More particularly, this invention relates to methods to improve MOS transistors.
  • BACKGROUND OF THE INVENTION
  • Designers and fabricators of integrated circuits (ICs) strive to increase speeds of operation of circuits in ICs. A common method of increasing operating speed is to increase current supplied by MOS transistors, known as drive current. One technique for increasing drive current is to increase electron mobilities in inversion layers of n-channel MOS transistors and increase hole mobilities in inversion layers of p-channel MOS transistors by increasing stress on the silicon lattice in the inversion layers. This is frequently accomplished by forming a dielectric layer on the MOS transistors, typically containing silicon nitride, known as the pre-metal dielectric (PMD) liner, with compressive stress. The increase in drive currents achievable by this method is limited by the thickness of the PMD liner, which is constrained by minimum gate spacing and other considerations.
  • SUMMARY OF THE INVENTION
  • This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
  • The instant invention is a multi-layered pre-metal dielectric (PMD) liner in an integrated circuit, in which each layer is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
  • DESCRIPTION OF THE VIEWS OF THE DRAWING
  • FIG. 1 is a cross-section of an IC with MOS transistors and a PMD liner formed according to an embodiment of the instant invention.
  • FIGS. 2A through 2D are cross-sections of an IC with MOS transistors during the process of formation of a PMD liner according to an embodiment of the instant invention.
  • DETAILED DESCRIPTION
  • The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • FIG. 1 is a cross-section of an IC with MOS transistors and a PMD liner formed according to an embodiment of the instant invention. IC (100) includes a substrate (102) typically p-type silicon, an n-well (104) formed in the substrate, typically by ion implantation of an n-type dopant such as phosphorus, a p-well (106) formed in the substrate adjacent to the n-well (104), typically by ion implantation of a p-type dopant such as boron, and regions of field oxide (108), typically silicon dioxide, formed in the substrate, typically by Shallow Trench Isolation (STI). An n-channel MOS transistor (110) is formed in the p-well (106); a p-channel MOS transistor (112) is formed in the n-well (104). The n-channel MOS transistor is formed by forming a gate dielectric (114), typically silicon dioxide with optional nitrogen, then forming a gate structure (116), typically polycrystalline silicon, followed by gate sidewall spacers (118), typically made of layers of silicon nitride and silicon dioxide, abutting the gate structure, followed by formation of n-type source and drain regions (120) by ion implantation of n-type dopants such as phosphorus and arsenic. Metal silicide (122), commonly nickel silicide or cobalt silicide, is formed on top surfaces of the n-type source and drain regions. Optional metal silicide (124), commonly nickel silicide or cobalt silicide, is formed on a top surface of the gate structure (116). Similarly, the p-channel MOS transistor is formed by forming a gate dielectric (126), typically silicon dioxide with optional nitrogen, then forming a gate structure (128), typically polycrystalline silicon, followed by gate sidewall spacers (130), typically made of layers of silicon nitride and silicon dioxide, abutting the gate structure, followed by formation of p-type source and drain regions (132) by ion implantation of p-type dopants such as boron. Metal silicide (134), commonly nickel silicide or cobalt silicide, is formed on top surfaces of the p-type source and drain regions. Optional metal silicide (136), commonly nickel silicide or cobalt silicide, is formed on a top surface of the gate structure (128).
  • To increase the mobility of electrons and holes in the n-channel MOS and p-channel MOS transistors, respectively, a PMD liner layer stack according to an embodiment of the instant invention (138) is formed on a top surface of the n-channel MOS transistor, the p-channel MOS transistor, and the field oxide (108). In an embodiment of the instant invention, the PMD liner layer stack is made up of 3 to 10 individual layers containing silicon nitride; each layer is deposited in a deposition chamber and then exposed to a nitrogen-containing plasma in the deposition chamber prior to deposition of a next layer. The nitrogen-containing plasma may be formed by a breakdown of N2 or NH3 gas. When N2 is used, the hydrogen content tends to be reduced after the plasma exposure. If the hydrogen concentration is to be maintained or increased during the nitrogen-containing plasma exposure, then NH3 should be used to form the plasma after deposition of each layer. Nitrogen from the nitrogen-containing plasma increases the compressive stress of the just-deposited layer. Successive layers are deposited and exposed to nitrogen-containing plasmas in a similar manner. This process generates a PMD liner layer stack with higher stress than a single layer PMD liner of the same total thickness; for example, a laminated PMD layer stack has been demonstrated with 200 to 300 MPa higher stress than a comparable single layer PMD liner. This is advantageous because the higher stress in the PMD liner layer stack of the instant invention increases the electron and hole mobilities more than would a single layer PMD liner of the same total thickness; for the example given above, n-channel MOS transistor rive currents were 3 to 5 percent higher. It is not necessary to remove the ICs from the deposition chamber between layer depositions; this is advantageous as it increase fabrication throughput compared to other laminated layer processes. In another embodiment, the chemical composition of each layer may be altered to enhance a performance parameter of an underlying MOS transistor. For example, a first layer in a PMD liner layer stack formed according to an embodiment of the instant invention may have a higher hydrogen content than typical PMD liner materials, typically 25 atomic percent or more, which would reduce low frequency fluctuations in current through the MOS transistor, known as flicker noise, and reduce p-channel MOS transistor threshold instability, known as Negative Bias Temperature Instability (NBTI), during operation of the IC. The capability to tailor chemical compositions of individual layers in the PMD liner layer stack embodied in the instant invention is advantageous because it allows enhancement of selected performance parameters while maintaining higher stress values compared to a single layer PMD liner of the same total thickness.
  • Still referring to FIG. 1, following formation of the PMD liner, a pre-metal dielectric (PMD) layer (146), typically silicon dioxide, is deposited on a top surface of the PMD liner. Contacts (148), typically tungsten, are formed in the PMD (146) to connect to the source and drain regions (120, 132) of the MOS transistors (110, 112).
  • FIGS. 2A through 2D are cross-sections of an IC with MOS transistors during the process of formation of a PMD liner according to an embodiment of the instant invention. FIG. 2A depicts a first layer of the PMD liner being deposited on the IC. IC (200) includes a substrate (202) typically p-type silicon, an n-well (204) formed in the substrate, typically by ion implantation of an n-type dopant such as phosphorus, a p-well (206) formed in the substrate adjacent to the n-well (204), typically by ion implantation of a p-type dopant such as boron, and regions of field oxide (208), typically silicon dioxide, formed in the substrate, typically by Shallow Trench Isolation (STI). An n-channel MOS transistor (210) is formed in the p-well (206); a p-channel MOS transistor (212) is formed in the n-well (204). The n-channel MOS transistor is formed by forming a gate dielectric (214), typically silicon dioxide with optional nitrogen, then forming a gate structure (216), typically polycrystalline silicon, followed by gate sidewall spacers (218), typically made of layers of silicon nitride and silicon dioxide, abutting the gate structure, followed by formation of n-type source and drain regions (220) by ion implantation of n-type dopants such as phosphorus and arsenic. Metal silicide (222), commonly nickel silicide or cobalt silicide, is formed on top surfaces of the n-type source and drain regions. Optional metal silicide (224), commonly nickel silicide or cobalt silicide, is formed on a top surface of the gate structure (216). Similarly, the p-channel MOS transistor is formed by forming a gate dielectric (226), typically silicon dioxide with optional nitrogen, then forming a gate structure (228), typically polycrystalline silicon, followed by gate sidewall spacers (230), typically made of layers of silicon nitride and silicon dioxide, abutting the gate structure, followed by formation of p-type source and drain regions (232) by ion implantation of p-type dopants such as boron. Metal silicide (234), commonly nickel silicide or cobalt silicide, is formed on top surfaces of the p-type source and drain regions. Optional metal silicide (236), commonly nickel silicide or cobalt silicide, is formed on a top surface of the gate structure (228). Deposition of the first PMD liner layer (240) of the PMD liner according to an embodiment of the instant invention proceeds by inserting the IC (200) into a deposition chamber (244). Deposition of the first PMD liner layer (240) containing silicon nitride may be performed on 200 mm diameter wafers by flowing SiH4 gas at 5 to 80 sccm, NH3 gas at 20 to 320 sccm, N2 gas at 2500 to 40,000 sccm, and possibly other gases, into the deposition chamber (244) to maintain a pressure of 1 to 100 torr. Deposition chamber temperature is maintained at 300 C to 400 C. A plasma (246) is formed in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power. These process conditions provide a deposition rate of 1 to 20 Angstroms per second on 200 mm diameter wafers. SiH4 gas, NH3 gas, and N2 gas flow rates and RF power level may be adjusted to maintain a desired deposition rate on another size wafer, for example a 300 mm diameter wafer.
  • FIG. 2B depicts the IC during an exposure of the first PMD liner layer to a nitrogen-containing plasma. The IC (200) remains in the deposition chamber (244) after deposition of the first PMD liner layer (240). In the instant embodiment, the first PMD liner layer (240) is exposed to a plasma formed from NH3 gas. Exposure to a nitrogen-containing plasma based on NH3 may be performed on 200 mm diameter wafers by flowing NH3 gas at 500 to 10,000 sccm, and possibly other gases, into the deposition chamber (244) to maintain a pressure of 1 to 100 torr. Deposition chamber temperature is maintained at 300 C to 400 C. A plasma (248) is formed in the NH3 gas by supplying 10 to 200 watts RF power, for 10 to 150 seconds. These process conditions provide a hydrogen content in the silicon nitride containing film of 10 to 35 atomic percent on 200 mm diameter wafers. NH3 gas flow rate and RF power level may be adjusted to achieve a desired hydrogen content on another size wafer, for example a 300 mm diameter wafer.
  • FIG. 2C depicts a second layer of the PMD liner being deposited on the IC. The IC (200) remains in the deposition chamber (244) after exposure of the first PMD liner layer to the nitrogen-containing plasma. Deposition of the second PMD liner layer (242) containing silicon nitride may be similarly performed on 200 mm diameter wafers by flowing SiH4 gas at 5 to 80 sccm, NH3 gas at 20 to 320 sccm, N2 gas at 2500 to 40,000 sccm, and possibly other gases, into the deposition chamber (244) to maintain a pressure of 1 to 100 torr. Deposition chamber temperature is maintained at 300 C to 400 C. A plasma (250) is formed in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power. These process conditions provide a deposition rate of 1 to 20 Angstroms per second on 200 mm diameter wafers. SiH4 gas, NH3 gas, and N2 gas flow rates and RF power level may be adjusted to maintain a desired deposition rate on another size wafer, for example a 300 mm diameter wafer.
  • FIG. 2D depicts the IC during an exposure of the second PMD liner layer to a nitrogen-containing plasma. The IC (200) remains in the deposition chamber (244) after deposition of the second PMD liner layer (242). In the instant embodiment, the second PMD liner layer (242) is exposed to a plasma formed from N2 gas. Exposure to a nitrogen-containing plasma based on N2 may be performed on 200 mm diameter wafers by flowing N2 gas at 2500 to 40,000 sccm, and possibly other gases, into the deposition chamber (244) to maintain a pressure of 1 to 100 torr. Deposition chamber temperature is maintained at 300 C to 400 C. A plasma (252) is formed in the N2 gas by supplying 10 to 200 watts RF power, for 5 to 60 seconds. These process conditions provide a compressive stress of 500 to 2000 MPa on 200 mm diameter wafers. N2 gas flow rate and RF power level may be adjusted to achieve a desired stress level on another size wafer, for example a 300 mm diameter wafer.
  • Subsequent layers of the PMD liner are formed by repeating the processes discussed in reference to FIG. 2C and FIG. 2D above.
  • It is within the scope of the instant invention to expose the first layer of the PMD liner to a plasma formed from N2 instead of a plasma formed from NH3.

Claims (20)

1. A dielectric layer stack in an integrated circuit comprised of 3 to 10 layers of dielectric material, comprised substantially of silicon nitride, wherein each layer is deposited in a deposition chamber and exposed to a nitrogen-containing plasma in the deposition chamber before deposition of a next layer.
2. The dielectric layer stack of claim 1, wherein said layers of dielectric material, are formed by flowing SiH4 gas at 5 to 80 sccm, NH3 gas at 20 to 320 sccm and N2 gas at 2500 to 40,000 sccm into said deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and forming a plasma in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power.
3. The dielectric layer stack of claim 2, wherein said nitrogen-containing plasma is formed by flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of the deposition chamber at 300 C to 400 C, and forming a plasma in the N2 gas by supplying 10 to 200 watts RF power.
4. The dielectric layer stack of claim 2, wherein a compressive stress is higher than 1300 MPa.
5. The dielectric layer stack of claim 2, wherein chemical compositions of all said layers are not identical.
6. The dielectric layer stack of claim 5, wherein a hydrogen content of a first layer is at least 25 atomic percent.
7. The dielectric layer stack of claim 6, wherein a first layer is exposed for 10 to 150 seconds to a nitrogen-containing plasma formed of NH3, which is formed by flowing NH3 gas at 500 to 10,000 sccm into the deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and supplying 10 to 200 watts RF power.
8. An integrated circuit, comprising:
provided a substrate;
a region of field oxide in said substrate;
an n-well in said substrate;
a p-well in said substrate;
an n-channel MOS transistor in said p-well comprising:
a first gate dielectric on a top surface of said p-well;
a first gate structure on a top surface of said first gate dielectric;
n-type source and drain regions in said p-well adjacent to said first gate structure; and
a first set of silicide regions on, and in contact with, top surfaces of said n-type source and drain regions;
a p-channel MOS transistor in said n-well comprising:
a second gate dielectric on a top surface of said n-well;
a second gate structure on a top surface of said second gate dielectric;
p-type source and drain regions in said n-well adjacent to said second gate structure; and
a second set of silicide regions on, and in contact with, top surfaces of said p-type source and drain regions;
a pre-metal dielectric liner layer stack on said n-channel transistor and said p-channel transistor, comprised of 3 to 10 layers of dielectric material, comprised substantially of silicon nitride, wherein each layer is deposited in a deposition chamber and exposed to a nitrogen-containing plasma in the deposition chamber before deposition of a next layer;
a pre-metal dielectric layer on said pre-metal dielectric liner layer stack; and
contacts in said pre-metal dielectric layer and said pre-metal dielectric liner layer stack, on, and electrically connected to, said n-type source and drain regions and said p-type source and drain regions.
9. The integrated circuit of claim 8, wherein said layers of dielectric material, are formed by flowing SiH4 gas at 5 to 80 sccm, NH3 gas at 20 to 320 sccm and N2 gas at 2500 to 40,000 sccm into said deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and forming a plasma in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power.
10. The integrated circuit of claim 9, wherein said nitrogen-containing plasma is formed by flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of the deposition chamber at 300 C to 400 C, and forming a plasma in the N2 gas by supplying 10 to 200 watts RF power.
11. The integrated circuit of claim 9, wherein a compressive stress in said pre-metal dielectric liner layer stack is higher than 1300 MPa.
12. The integrated circuit of claim 9, wherein chemical compositions of all said layers in said pre-metal dielectric liner layer stack are not identical.
13. The integrated circuit of claim 12, wherein a hydrogen content of a first layer in said pre-metal dielectric liner layer stack is at least 25 atomic percent.
14. The integrated circuit of claim 13, wherein a first layer is exposed for 10 to 150 seconds to a nitrogen-containing plasma formed of NH3, which is formed by flowing NH3 gas at 500 to 10,000 sccm into said deposition chamber while maintaining a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and supplying 10 to 200 watts RF power.
15. A method of forming an integrated circuit, comprising the steps of:
providing a substrate;
forming field oxide in said substrate;
forming an n-well in said substrate;
forming a p-well in said substrate;
forming an n-channel MOS transistor in said p-well by a process comprising the steps of:
forming a first gate dielectric on a top surface of said p-well;
forming a first gate structure on a top surface of said first gate dielectric;
forming n-type source and drain regions in said p-well adjacent to said first gate structure; and
forming a first set of silicide regions on, and in contact with, top surfaces of said n-type source and drain regions;
forming a p-channel MOS transistor in said n-well by a process comprising the steps of:
forming a second gate dielectric on a top surface of said n-well;
forming a second gate structure on a top surface of said second gate dielectric;
forming p-type source and drain regions in said n-well adjacent to said second gate structure; and
forming a second set of silicide regions on, and in contact with, top surfaces of said p-type source and drain regions;
forming a pre-metal dielectric liner layer stack on said n-channel transistor and said p-channel transistor, by a process comprised of the steps of:
providing a deposition chamber;
inserting said substrate into said deposition chamber;
depositing a first silicon nitride layer on said n-channel transistor and said p-channel transistor by a process comprising the steps of:
flowing SiH4 gas at 5 to 80 sccm into the deposition chamber;
flowing NH3 gas at 20 to 320 sccm into the deposition chamber;
flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber;
maintaining a pressure of 1 to 100 torr in the deposition chamber;
maintaining a temperature of 300 C to 400 C in the deposition chamber; and
forming a plasma in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power;
exposing said first silicon nitride layer to a nitrogen-containing plasma in said deposition chamber; and
repeating said steps of depositing a silicon nitride layer and exposing the silicon nitride layer to a nitrogen-containing plasma for a plurality of iterations;
forming a pre-metal dielectric layer on said pre-metal dielectric liner layer stack; and
forming contacts in said pre-metal dielectric layer stack and in said pre-metal dielectric liner layer stack, on, and electrically connected to, said n-type source and drain regions and said p-type source and drain regions.
16. The method of claim 15, wherein said nitrogen-containing plasma is formed by a process comprising the steps of:
flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber;
maintaining a pressure of 1 to 100 torr in the deposition chamber;
maintaining a temperature of 300 C to 400 C in the deposition chamber; and
forming a plasma in the N2 gas by supplying 10 to 200 watts RF power.
17. The method of claim 15, wherein a compressive stress in said pre-metal dielectric liner layer stack is higher than 1300 MPa.
18. The method of claim 15, wherein chemical compositions of all said layers in said pre-metal dielectric liner layer stack are not identical.
19. The method of claim 18, wherein a hydrogen content of a first layer in said pre-metal dielectric liner layer stack is at least 25 atomic percent.
20. The method of claim 19, wherein a first layer is exposed for 10 to 150 seconds to a nitrogen-containing plasma formed of NH3, which is formed by a process comprising the steps of:
flowing NH3 gas at 500 to 10,000 sccm into said deposition chamber;
maintaining a pressure of 1 to 100 torr in said deposition chamber;
maintaining a temperature of 300 C to 400 C in said deposition chamber; and supplying 10 to 200 watts RF power.
US11/959,111 2007-12-18 2007-12-18 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement Abandoned US20090152639A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/959,111 US20090152639A1 (en) 2007-12-18 2007-12-18 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/959,111 US20090152639A1 (en) 2007-12-18 2007-12-18 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement
US12/904,593 US8114784B2 (en) 2007-12-18 2010-10-14 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/904,593 Division US8114784B2 (en) 2007-12-18 2010-10-14 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

Publications (1)

Publication Number Publication Date
US20090152639A1 true US20090152639A1 (en) 2009-06-18

Family

ID=40752071

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/959,111 Abandoned US20090152639A1 (en) 2007-12-18 2007-12-18 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement
US12/904,593 Active US8114784B2 (en) 2007-12-18 2010-10-14 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/904,593 Active US8114784B2 (en) 2007-12-18 2010-10-14 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

Country Status (1)

Country Link
US (2) US20090152639A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283874A1 (en) * 2008-05-15 2009-11-19 Toshiaki Idaka Semiconductor device manufacturing method and semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8870382B2 (en) 2012-05-29 2014-10-28 Vladimir Yankov Method of reducing speckles in liquid-crystal display with coherent illumination
US9484431B1 (en) * 2015-07-29 2016-11-01 International Business Machines Corporation Pure boron for silicide contact

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US7397073B2 (en) * 2004-11-22 2008-07-08 International Business Machines Corporation Barrier dielectric stack for seam protection

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004026149B4 (en) * 2004-05-28 2008-06-26 Advanced Micro Devices, Inc., Sunnyvale A method of producing a semiconductor device having transistor elements with voltage-inducing etch stop layers
US7585704B2 (en) * 2005-04-01 2009-09-08 International Business Machines Corporation Method of producing highly strained PECVD silicon nitride thin films at low temperature
US8440580B2 (en) * 2007-09-11 2013-05-14 United Microelectronics Corp. Method of fabricating silicon nitride gap-filling layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US7397073B2 (en) * 2004-11-22 2008-07-08 International Business Machines Corporation Barrier dielectric stack for seam protection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283874A1 (en) * 2008-05-15 2009-11-19 Toshiaki Idaka Semiconductor device manufacturing method and semiconductor device
US7803706B2 (en) * 2008-05-15 2010-09-28 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device
US20100320512A1 (en) * 2008-05-15 2010-12-23 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device
US7960764B2 (en) 2008-05-15 2011-06-14 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device

Also Published As

Publication number Publication date
US20110027953A1 (en) 2011-02-03
US8114784B2 (en) 2012-02-14

Similar Documents

Publication Publication Date Title
CN100403540C (en) Integrated circuit component and forming method thereof
US6773999B2 (en) Method for treating thick and thin gate insulating film with nitrogen plasma
KR101001083B1 (en) Gate electrode structures and methods of manufacture
US6734069B2 (en) Method of forming a high dielectric constant insulating film and method of producing semiconductor device using the same
EP1766691B1 (en) Selective implementation of barrier layers to achieve threshold voltage control in cmos device fabrication with high k dielectrics
US7709902B2 (en) Metal gate CMOS with at least a single gate metal and dual gate dielectrics
JP4890448B2 (en) Techniques for generating different mechanical stresses by forming etch stop layers with different intrinsic stresses in different channel regions
JP5336857B2 (en) Method for changing work function of conductive electrode by introducing metal impurity (and semiconductor structure thereof)
US8329564B2 (en) Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method
US8836039B2 (en) Semiconductor device including high-k/metal gate electrode
US8222099B2 (en) Semiconductor device and method of manufacturing the same
US7314793B2 (en) Technique for controlling mechanical stress in a channel region by spacer removal
US7872317B2 (en) Dual metal gate self-aligned integration
JP5128121B2 (en) High performance CMOS circuit and manufacturing method thereof
US20140273530A1 (en) Post-Deposition Treatment Methods For Silicon Nitride
US8334198B2 (en) Method of fabricating a plurality of gate structures
US7820552B2 (en) Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack
US20020086504A1 (en) Method of manufacturing semiconductor devices
US7880228B2 (en) Semiconductor device including MISFET
JP5070702B2 (en) Semiconductor device manufacturing method and manufacturing apparatus
US7754570B2 (en) Semiconductor device
US20080014759A1 (en) Method for fabricating a gate dielectric layer utilized in a gate structure
US6218274B1 (en) Semiconductor device and manufacturing method thereof
TWI411100B (en) Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility
US10020397B2 (en) Bottle-neck recess in a semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BU, HAOWEN;CHE-JEN-HU, JERRY;KHAMANKAR, RAJESH;REEL/FRAME:020504/0372;SIGNING DATES FROM 20080111 TO 20080206

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION