US20090108394A1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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US20090108394A1
US20090108394A1 US11/966,424 US96642407A US2009108394A1 US 20090108394 A1 US20090108394 A1 US 20090108394A1 US 96642407 A US96642407 A US 96642407A US 2009108394 A1 US2009108394 A1 US 2009108394A1
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substrate
peripheral region
semiconductor device
insulating layer
region
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Tae Su Jang
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells

Definitions

  • the present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising of a Silicon-On-Insulator (SOI) substrate having cell/core regions and a peripheral region, which is formed to have the same structure as that of a conventional substrate to obtain a floating body effect.
  • SOI Silicon-On-Insulator
  • a DRAM for performing a general storage process is manufactured with a bulk silicon substrate.
  • a semiconductor device for performing a storage process has a cell structure including a transistor and a capacitor.
  • a semiconductor device comprising a SOI substrate has been developed.
  • a top silicon substrate of the SOI substrate is isolated from a bottom silicon substrate by an insulating layer so that the transistor form the top silicon substrate can obtain a floating body effect.
  • the semiconductor device can serve as a memory device without a capacitor.
  • a SOI substrate is used for a DRAM cell.
  • a model parameter which has been developed in a conventional DRAM technology, is changed to develop a new circumstance.
  • the floating body effect is not required.
  • a developing period for the model parameter of the peripheral region where various circuits are irregularly formed would be increased which would also increase the cost.
  • Various embodiments of the present invention are directed at providing a semiconductor device comprising a first substrate, an insulating layer and a second substrate.
  • a region where a peripheral circuit is formed is isolated from a region where cell/core circuits are formed.
  • the second substrate and the insulating layer of the peripheral region are removed, and an epitaxial layer is formed so that the semiconductor substrate of the peripheral region may have a similar circumstance as that of a bulk silicon substrate.
  • the cell/core regions are advantageous to the floating body effect, thereby shortening the developing period for forming a semiconductor device and improving a process yield of the semiconductor device.
  • a semiconductor device comprises a first substrate disposed in a cell region, a core region and a peripheral region, an insulating layer and a second substrate sequentially deposited over the first substrate of the cell region and the core region, an epitaxial layer formed over the first substrate of the peripheral region to the height of the second substrate, and an isolating film formed in a boundary of the peripheral region and the cell and core regions to isolate the epitaxial layer from the insulating layer and the second substrate.
  • a method for fabricating a semiconductor device comprises: forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer.
  • SEG selective epitaxial growth
  • CMP chemical mechanical polishing
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.
  • a body which is a semiconductor substrate where a cell transistor is formed is isolated (i.e., floating).
  • a memory device of a semiconductor device using the FBC does not require a storage capacitor. In comparison with a conventional memory device, it is necessary to secure cell capacitance.
  • a silicon-on-insulator (SOI) substrate is used.
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • a first substrate 100 defines a cell/core region 1000 A and a peripheral region 1000 B.
  • An insulating layer 115 and a second substrate 125 are sequentially deposited over the first substrate 100 of the cell/core region 1000 A.
  • the first substrate 100 or the second substrate 125 includes an n-type or p-type silicon substrate.
  • the insulating layer 115 includes an oxide film.
  • An expitaxial layer 165 is formed over the first substrate 100 of the peripheral region 1000 B to the height of the second substrate 125 .
  • An isolating film 145 is formed between the second substrate 125 and the epitaxial layer 165 , which is a boundary of the cell/core region 1000 A and the peripheral region 1000 B.
  • the epitaxial layer 165 is grown with the same type as that of the first substrate 100 and with an undoped type.
  • the isolating film 145 includes a high density plasma (HDP), chemical vapor deposition (CVD) or spin-on dielectric (SOD) oxide film formed by a Shallow Trench Isolation (STI) process.
  • HDP high density plasma
  • CVD chemical vapor deposition
  • SOD spin-on dielectric
  • a SOI substrate structure where a FBC can be formed is disposed in the cell/core region 1000 A, and a bulk silicon substrate is located in the peripheral region 1000 B.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.
  • a first substrate 100 , an insulating layer 110 and a second substrate 120 are sequentially deposited to obtain a FBC in the cell/core region 1000 A.
  • the first and second substrates 100 and 120 are ion-implanted with n-type or p-type impurities.
  • the insulating layer 100 includes an oxide film.
  • a first mask pattern 130 to expose a boundary of the cell/core region 1000 A and the peripheral region 1000 B is formed over the second substrate 120 .
  • the first mask pattern 130 includes a photoresist film, a nitride film and a carbon layer which have an etch selectivity of silicon and oxide films.
  • the second substrate 120 is etched with the first mask pattern 130 as an etching mask to form a second substrate pattern 125 that exposes the insulating layer 110 .
  • the second substrate pattern 125 includes a device isolating trench, which is called a STI process.
  • a device isolating insulating layer 140 is formed to fill a region between the second substrate patterns 125 .
  • the device isolating insulating layer 140 includes a high density plasma (HDP), chemical vapor deposition (CVD) or spin-on dielectric (SOD) oxide film.
  • HDP high density plasma
  • CVD chemical vapor deposition
  • SOD spin-on dielectric
  • a CMP process is performed to remove the first mask pattern 130 and to isolate the device isolating insulating layer 140 .
  • An isolating film 145 is formed to isolate the cell/core region 1000 A from the peripheral region 1000 B.
  • a second mask pattern 150 that exposes the peripheral region 1000 B is formed over the second substrate pattern 125 and the isolating film 145 .
  • the second mask pattern 150 includes a photoresist film, a nitride film and a carbon layer which have an etch selectivity of silicon and oxide films.
  • the second substrate pattern 125 is etched with the second mask pattern 150 as an etching mask.
  • an insulating layer 110 exposed by the second mask pattern 150 is formed to obtain an insulating pattern 115 that exposes the first substrate 100 of the peripheral region 1000 B.
  • a SEG process is performed with the first substrate 100 as a seed to form an epitaxial growth layer 160 .
  • the n-type or p-type impurities implanted into the first substrate 100 are not implanted into the epitaxial growth layer 160 .
  • a CMP process is performed to remove the second mask pattern 150 and planarize the epitaxial growth layer 160 .
  • a gate 170 is formed in the peripheral region 1000 B.
  • the peripheral region 1000 B has the same state as that of a general semiconductor substrate. As a result, the same design pattern of the prior art can be applied to the gate 170 of the peripheral region 1000 B, thereby shortening a design change period.
  • a semiconductor substrate has a deposition structure including a first substrate, an insulating layer and a second substrate in order to obtain a FBC without a storage capacitor.
  • a new process performed on a peripheral region which does not require a floating body effect, causes an unnecessary developing period.
  • a cell/core region has a deposition structure including the first substrate, the insulating layer and the second substrate, and a peripheral region includes a bulk type semiconductor substrate.
  • a STI process is performed on a boundary of the cell/core region and the peripheral region to form an isolating film and an epitaxial growth layer in the peripheral region.

Abstract

A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer. As a result, the method has a floating body effect to shorten a developing period and improve a process yield.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • The priority of Korean patent application number 10-2007-0110695, filed on Oct. 31, 2007, which is incorporated by reference in its entirety, is claimed.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising of a Silicon-On-Insulator (SOI) substrate having cell/core regions and a peripheral region, which is formed to have the same structure as that of a conventional substrate to obtain a floating body effect.
  • A DRAM for performing a general storage process is manufactured with a bulk silicon substrate. A semiconductor device for performing a storage process has a cell structure including a transistor and a capacitor.
  • Due to high integration of semiconductor devices, the cell structure has become complicated, and it is difficult to secure electric characteristics of the transistor and the capacitor. As a result, a semiconductor device comprising a SOI substrate has been developed. A top silicon substrate of the SOI substrate is isolated from a bottom silicon substrate by an insulating layer so that the transistor form the top silicon substrate can obtain a floating body effect.
  • If electrons passing through a channel of the transistor increases, a current flowing is increased and a drain voltage is also increased. When the drain voltage is larger, collision of silicon molecules is increased in the drain region to increase silicon electrons and holes. In the case of a general bulk substrate, the holes are passed through a ground to increase a threshold voltage of the transistor. In the case of a SOI substrate, holes are accumulated in the top silicon substrate to obtain a floating body effect for generating a voltage. As a result, it is easy to regulate a voltage of the body, thereby improving an electric characteristic of the transistor. The semiconductor device can serve as a memory device without a capacitor.
  • A SOI substrate is used for a DRAM cell. In this case, a model parameter, which has been developed in a conventional DRAM technology, is changed to develop a new circumstance. As a result, the floating body effect is not required. Moreover, a developing period for the model parameter of the peripheral region where various circuits are irregularly formed would be increased which would also increase the cost.
    • BRIEF SUMMARY OF THE INVENTION
  • Various embodiments of the present invention are directed at providing a semiconductor device comprising a first substrate, an insulating layer and a second substrate. A region where a peripheral circuit is formed is isolated from a region where cell/core circuits are formed. The second substrate and the insulating layer of the peripheral region are removed, and an epitaxial layer is formed so that the semiconductor substrate of the peripheral region may have a similar circumstance as that of a bulk silicon substrate. The cell/core regions are advantageous to the floating body effect, thereby shortening the developing period for forming a semiconductor device and improving a process yield of the semiconductor device.
  • According to an embodiment of the present invention, a semiconductor device comprises a first substrate disposed in a cell region, a core region and a peripheral region, an insulating layer and a second substrate sequentially deposited over the first substrate of the cell region and the core region, an epitaxial layer formed over the first substrate of the peripheral region to the height of the second substrate, and an isolating film formed in a boundary of the peripheral region and the cell and core regions to isolate the epitaxial layer from the insulating layer and the second substrate.
  • According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises: forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • In order to obtain a floating body cell (FBC), a body which is a semiconductor substrate where a cell transistor is formed is isolated (i.e., floating). A memory device of a semiconductor device using the FBC does not require a storage capacitor. In comparison with a conventional memory device, it is necessary to secure cell capacitance. In the embodiment of the present invention, a silicon-on-insulator (SOI) substrate is used.
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • Referring to FIG. 1, a first substrate 100 defines a cell/core region 1000A and a peripheral region 1000B.
  • An insulating layer 115 and a second substrate 125 are sequentially deposited over the first substrate 100 of the cell/core region 1000A. The first substrate 100 or the second substrate 125 includes an n-type or p-type silicon substrate. The insulating layer 115 includes an oxide film.
  • An expitaxial layer 165 is formed over the first substrate 100 of the peripheral region 1000B to the height of the second substrate 125. An isolating film 145 is formed between the second substrate 125 and the epitaxial layer 165, which is a boundary of the cell/core region 1000A and the peripheral region 1000B. The epitaxial layer 165 is grown with the same type as that of the first substrate 100 and with an undoped type. The isolating film 145 includes a high density plasma (HDP), chemical vapor deposition (CVD) or spin-on dielectric (SOD) oxide film formed by a Shallow Trench Isolation (STI) process.
  • As a result, a SOI substrate structure where a FBC can be formed is disposed in the cell/core region 1000A, and a bulk silicon substrate is located in the peripheral region 1000B.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.
  • Referring to FIG. 2 a, a first substrate 100, an insulating layer 110 and a second substrate 120 are sequentially deposited to obtain a FBC in the cell/core region 1000A. The first and second substrates 100 and 120 are ion-implanted with n-type or p-type impurities. The insulating layer 100 includes an oxide film.
  • When a FBC is located in the peripheral region 1000B, a design burden is increased in the second substrate 120. As a result, a process for isolating the peripheral region 1000B is performed to reduce the design burden.
  • Referring to FIG. 2 b, a first mask pattern 130 to expose a boundary of the cell/core region 1000A and the peripheral region 1000B is formed over the second substrate 120. The first mask pattern 130 includes a photoresist film, a nitride film and a carbon layer which have an etch selectivity of silicon and oxide films.
  • Referring to FIG. 2 c, the second substrate 120 is etched with the first mask pattern 130 as an etching mask to form a second substrate pattern 125 that exposes the insulating layer 110. The second substrate pattern 125 includes a device isolating trench, which is called a STI process.
  • Referring to FIG. 2 d, a device isolating insulating layer 140 is formed to fill a region between the second substrate patterns 125. The device isolating insulating layer 140 includes a high density plasma (HDP), chemical vapor deposition (CVD) or spin-on dielectric (SOD) oxide film.
  • Referring to FIG. 2 e, a CMP process is performed to remove the first mask pattern 130 and to isolate the device isolating insulating layer 140. An isolating film 145 is formed to isolate the cell/core region 1000A from the peripheral region 1000B.
  • Referring to FIG. 2 f, a second mask pattern 150 that exposes the peripheral region 1000B is formed over the second substrate pattern 125 and the isolating film 145. The second mask pattern 150 includes a photoresist film, a nitride film and a carbon layer which have an etch selectivity of silicon and oxide films.
  • Referring to FIG. 2 g, the second substrate pattern 125 is etched with the second mask pattern 150 as an etching mask.
  • Referring to FIG. 2 h, an insulating layer 110 exposed by the second mask pattern 150 is formed to obtain an insulating pattern 115 that exposes the first substrate 100 of the peripheral region 1000B.
  • Referring to FIG. 2 i, a SEG process is performed with the first substrate 100 as a seed to form an epitaxial growth layer 160. The n-type or p-type impurities implanted into the first substrate 100 are not implanted into the epitaxial growth layer 160.
  • Referring to FIG. 2 j, a CMP process is performed to remove the second mask pattern 150 and planarize the epitaxial growth layer 160.
  • A gate 170 is formed in the peripheral region 1000B. The peripheral region 1000B has the same state as that of a general semiconductor substrate. As a result, the same design pattern of the prior art can be applied to the gate 170 of the peripheral region 1000B, thereby shortening a design change period.
  • As described above, according to an embodiment of the present invention, a semiconductor substrate has a deposition structure including a first substrate, an insulating layer and a second substrate in order to obtain a FBC without a storage capacitor. However, a new process performed on a peripheral region, which does not require a floating body effect, causes an unnecessary developing period. A cell/core region has a deposition structure including the first substrate, the insulating layer and the second substrate, and a peripheral region includes a bulk type semiconductor substrate. A STI process is performed on a boundary of the cell/core region and the peripheral region to form an isolating film and an epitaxial growth layer in the peripheral region. As a result, a design pattern for the peripheral region is not required but the process yield and reliability of the semiconductor device can be improved.
  • The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims (10)

1. A semiconductor device comprising:
a first substrate defining a cell region, a core region and a peripheral region;
an insulating layer and a second substrate sequentially provided over the first substrate of the cell region and the core region;
an epitaxial layer formed over the first substrate of the peripheral region to the height of the second substrate; and
an isolating film formed in a boundary of the peripheral region and the cell and core regions to isolate the epitaxial layer from the insulating layer and the second substrate.
2. The semiconductor device according to claim 1, wherein the first substrate includes an n-type or p-type silicon substrate, and the second substrate includes an n-type or p-type silicon substrate.
3. The semiconductor device according to claim 1, wherein the insulating layer includes an oxide film.
4. The semiconductor device according to claim 1, wherein the epitaxial layer is grown without being doped.
5. The semiconductor device according to claim 1, wherein the isolating film includes a high density plasma (HDP), chemical vapor deposition (CVD) or spin-on dielectric (SOD) oxide film.
6. A method for fabricating a semiconductor device, the method comprising:
forming a deposition structure including a first substrate, an insulating layer and a second substrate, thereby defining a SOI substrate;
etching a portion of the second substrate located at a boundary of the cell region and the peripheral region, or the core region and the peripheral region, to form a line-type trench;
filling an isolating film in the trench;
removing portions of the second substrate and the insulating layer provided at the peripheral region;
performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and
performing a chemical mechanical polishing (CMP) process on the epitaxial layer.
7. The method according to claim 6, wherein the first substrate or the second substrate includes an n-type or p-type silicon substrate.
8. The method according to claim 6, wherein the insulating layer includes an oxide film.
9. The method according to claim 6, wherein the epitaxial layer is grown without being doped.
10. The method according to claim 6, wherein the isolating film includes a high density plasma (HDP), chemical vapor deposition (CVD) or spin-on dielectric (SOD) oxide film.
US11/966,424 2007-10-31 2007-12-28 Semiconductor device and method for fabricating the same Expired - Fee Related US7750430B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
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