US20090059697A1 - Method and apparatus for implementing sram cell write performance evaluation - Google Patents
Method and apparatus for implementing sram cell write performance evaluation Download PDFInfo
- Publication number
- US20090059697A1 US20090059697A1 US11/845,866 US84586607A US2009059697A1 US 20090059697 A1 US20090059697 A1 US 20090059697A1 US 84586607 A US84586607 A US 84586607A US 2009059697 A1 US2009059697 A1 US 2009059697A1
- Authority
- US
- United States
- Prior art keywords
- sram
- wordline
- write
- ring oscillator
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
Definitions
- the present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation.
- SRAM static random access memory
- U.S. Pat. No. 6,728,912 to Dawson et al. issued Apr. 27, 2004, entitled SOI Cell Stability Test Method and assigned to the present assignee discloses a method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, that uses a reset test circuit with a wordline pulse width control circuit.
- the method can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin.
- the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width.
- the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.
- a principal aspect of the present invention is to provide a method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation.
- Other important aspects of the present invention are to provide such a method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
- a SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column.
- a ring oscillator circuit coupled to the SRAM core generates wordline pulses.
- An input logic couples data to the SRAM core, and an output logic provides an oscillator signal at an output to identify a minimum wordline pulse width to write the cell.
- a state machine controls the ring oscillator circuit and write and read operations to the SRAM core for implementing SRAM cell write performance evaluation.
- an enable control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state.
- Each wordline is connected to one cell from different bitlines. In this second write operation, each wordline has a different narrow pulse width, as a result some of the cells are written and some are not written.
- the ring oscillator includes a series of wordline pulse generators creating signals with different pulse widths. The cells are read with the original wide wordline pulse width. Based on the results of the read, one of the frequency divider signals is selected for output. The selected frequency signal of the output shows the minimum wordline pulse width needed to write the cell.
- the SRAM cell write performance evaluation circuit determines the wordline pulse width required to write the cell by reading the cells and setting a select bit in an output multiplexer based upon whether the cell connected was written properly.
- the select bits from the read operation determine how many times the frequency is divided. Then, the output oscillates at the natural frequency of the oscillator divided by an identified multiple of 2.
- FIGS. 1A and 1B together provide a schematic diagram of an exemplary circuit for implementing static random access memory (SRAM) write performance evaluation in accordance with the preferred embodiment
- FIG. 2 is a schematic diagram illustrating an exemplary ring oscillator circuit of the SRAM cell write performance evaluation circuit of FIGS. 1A and 1B in accordance with the preferred embodiment
- FIG. 3 are timing diagrams illustrating the operation of the SRAM cell write performance evaluation circuit of FIGS. 1A and 1B in accordance with the preferred embodiment
- FIGS. 4 , 5 and 6 are schematic diagrams illustrating exemplary output logic of the SRAM cell write performance evaluation circuit of FIGS. 1A and 1B in accordance with the preferred embodiment
- FIG. 7 is a schematic diagram illustrating exemplary enable signal capture logic of the SRAM cell write performance evaluation circuit of FIGS. 1A and 1B in accordance with the preferred embodiment.
- a method and circuit are provided to evaluate SRAM cell write performance in hardware.
- the method and circuit provide for granularity in performance evaluation whereas prior art does not.
- SRAM cell write performance evaluation circuit 100 includes a SRAM core 102 , such as a 16 ⁇ 16 cell array where each wordline is connected to only one bit-column, a ring oscillator circuit 104 , an input logic 106 , an output logic 108 and a state machine 110 .
- SRAM core 102 is illustrated as a 16 ⁇ 16 cell array, it should be understood that this is only an example. Various array sizes can be used to implement the SRAM core 102 in accordance with the present invention.
- the ring oscillator circuit 104 is used to generate wordline pulses WL for each of the multiple, for example sixteen wordline inputs WL( 0 )-WL( 15 ) and a precharge signal PCH applied to the SRAM core 102 .
- the state machine 110 is used to control the operation of the ring oscillator circuit 104 , input logic 106 , output logic 108 for write and read operations for implementing SRAM cell write performance evaluation.
- SRAM cell write performance evaluation circuit 100 has one input labeled ENABLE applied to the state machine 110 , and one output labeled OUT of output logic 108 that oscillates.
- the frequency of oscillation for the output signal OUT when ENABLE is low, and the frequency of oscillation for OUT when ENABLE is high, are used to show the required wordline pulse width to write the SRAM cells.
- the input logic 106 provides data inputs applied to a local evaluation circuit 112 of the SRAM core 102 and local evaluation circuit 112 also receives the precharge signal PCH from ring oscillator 104 .
- the DOT output of the local evaluation circuit 112 provides respective inputs to the output logic 108 .
- a read path of the output logic 108 is illustrated and described with respect to FIGS. 4 and 5 .
- SRAM cell write performance evaluation circuit 100 is very simple to use and no special test patterns are required. The required operations for implementing SRAM cell write performance evaluation are to first simply measure the output frequency OUT with ENABLE low. Then, raise ENABLE, wait a few clock cycles, and measure the output frequency OUT again. From these two frequencies the required wordline pulse width to write the cell is identified.
- Ring oscillator circuit 104 receives inputs ACT_WL and NARROW/WIDE_B from the state machine 110 .
- the signal ACT_WL controls when wordlines and the precharge signals are generated.
- the signal NARROW/WIDE_B controls whether the wordlines and precharge signals are wide, to ensure that the data is correctly written and read, or narrow to test the write performance of the SRAM cells.
- Ring oscillator circuit 104 provides the output RINGSIG applied to the output logic 108 , and the plurality of wordline outputs WL( 0 )-WL( 15 ) and precharge signal PCH applied to the SRAM core 102 .
- Ring oscillator circuit 104 includes a chain or ring generally designated by reference character 202 including a plurality of stages or inverter pairs 204 connected in series.
- a two input NAND gate 206 includes an input connected to node NET 1 and an input connected to a positive supply rail VDD.
- the output of the two input NAND gate 206 is inverted by an inverter 208 and applied to each of a plurality of wordline pulse generator circuits generally designated by reference character 212 and providing wordline outputs WL( 0 )-WL( 15 ).
- the ring signal at node NET 1 is coupled by a first inverter pair 204 in the ring 202 and is inverted by an inverter 210 and applied to the wordline pulse generator circuit 212 providing wordline output WL( 0 ).
- Each of the wordline pulse generator circuits 212 include a pair of two input NAND gates 214 , 216 , a three input NAND gate 218 and an inverter 220 .
- the input NARROW/WIDE_B is applied to an input of the NAND gate 216 of each of the wordline pulse generator circuits 212 .
- the output of inverter 208 is applied to an input of the NAND gate 214 of each of the wordline pulse generator circuits 212 .
- the NAND gate 216 has an input connected between respective series connected inverter pairs 204 in the chain 202 .
- Each of the two input NAND gates 214 , 216 has a respective output applied to the three input NAND gate 218 , which has a third input receiving the signal ACT_WL for controlling when wordlines and the precharge signals are generated.
- Inverter 220 inverts the output of the three input NAND gate 218 .
- the respective output of inverter 220 of each of the pulse generator circuits 212 respectively provides the plurality of wordline outputs WL( 0 )-WL( 15 ) and precharge signal PCH.
- a ring output path includes a two input NAND gate 224 having an input connected between two inverter pairs 204 and an input connected to VDD.
- the NAND gate output is inverted by an inverter 226 , which provides output RINGSIG.
- a plurality of two input NAND gates 228 having an output coupled by a capacitor 230 to ground potential, has an input connected between respective series connected inverter pairs 204 in the chain 202 from ring connection for output RINGSIG to the node NET 1 .
- Timing considerations for the ring oscillator circuit 104 require that the delay through the state machine of RINGSIG rising to the correct signals switching, especially ACT_WL is less than the delay from output RINGSIG to node NET 1 in FIG. 2 . Extra delay can be added to the ring path if required.
- wordline output pulses at output WL ⁇ 0 > are very narrow and the wordline output pulses are progressively wider until WL ⁇ 15 > and the precharge signal PCH is the widest signal pulse.
- the signal NARROW/WIDE_B causes all the wordlines and precharge signals to be wide.
- ENABLE is low, the signal RINGSIG is sent to the output of the SRAM cell write performance evaluation circuit 100 . From this, delay per stage of the oscillator can be found, and the actual wordline pulse widths can also be found.
- FIG. 3 there are shown timing diagrams illustrating the operation of the SRAM cell write performance evaluation circuit 100 .
- waveforms illustrate the input signal ENABLE, oscillator output signal RINGSIG, oscillator control signal ACT_WL, input DATA, read/write control R/W_B, the ring oscillator input NARROW/WIDE_B, and a wordline output pulses at an exemplary output WL.
- SRAM cell write performance evaluation circuit 100 operates as follows. During a first time period indicated by an arrow labeled A of a first write operation, the input signal ENABLE is low. While ENABLE is low the SRAM cell write performance evaluation circuit 100 repeatedly writes 0s as illustrated at DATA with wide wordline pulses, as illustrated at output WL.
- FIGS. 4 and 5 together illustrate a read path generally designated by the reference character 400 of SRAM cell write performance evaluation circuit 100 in accordance with the preferred embodiment.
- Read path 400 includes a respective data input DOT ⁇ 0 >-DOT ⁇ 15 > applied to a read circuit XCN 402 , receiving the RINGSIG applied by a plurality of series connected inverters 406 , 408 410 , 412 at a node P 2 .
- the read circuit XCN 402 provides a respective output RD ⁇ 0 >-RD ⁇ 15 >.
- the read circuit XCN 402 includes a precharge P-channel field effect transistor (PFET) 502 connected between the data input DOT node. PFET 502 has a gate input applied by an inverter 504 having an input connected to node P 2 .
- the read circuit XCN 402 includes a pair of cross-connected two input NAND gates 506 , 508 .
- the data input DOT node is applied to NAND gate 506 with the output of NAND gate 508 applied to the other input of NAND gate 506 .
- the RINGSIG applied by the series connected inverters 406 , 408 , 410 , 412 at node P 2 is applied to NAND gate 508 with the output of NAND gate 506 applied to the other input of NAND gate 508 .
- the SRAM cell write performance evaluation circuit 100 determines the wordline pulse width required to write the cell by reading the cells and setting a select bit in an output multiplexer 602 of the output logic 108 based on whether the cell connected was written properly.
- the frequency output RINGSIG of the oscillator 104 is applied to a first one of a plurality of frequency dividers or divide by 2 circuits 604 that are connected in a chain.
- the output RINGSIG, and the respective frequency divided output of the plurality of frequency dividers 604 are applied to respective inputs of the output multiplexer 602 .
- a respective NAND gate 606 provides a select signal to the output multiplexer 602 based upon the select bits from the read.
- the select bits from the read determine how many times the frequency is divided.
- the output signal OUT oscillates at the natural frequency of the oscillator divided by the selected multiple of 2, which is provided by the selected one of the chained divide by 2 circuits 604 .
- the state machine 110 is used to step through the required states of the signals that control the read and write operations.
- Enable signal capture logic 700 includes a plurality of series connected D-latches 702 , each receiving a clock input C of the frequency output RINGSIG of the oscillator 104 .
- the respective lettered outputs A-J of the D-latches 702 are used to control the state machine 110 .
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
- The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation.
- In advanced CMOS technology, devices used in SRAM cells are different than devices used elsewhere on a chip. These differences include dopant levels, layout topologies, and channel lengths.
- A need exists for an effective method and circuit to evaluate SRAM cell write performance in hardware. It is desirable to provide such method and circuit that enables characterizing the wordline pulse width to identify a minimum wordline pulse width to write the cell. Known prior art test arrangements do not enable incrementally varying the wordline pulse width.
- For example, U.S. Pat. No. 6,728,912 to Dawson et al. issued Apr. 27, 2004, entitled SOI Cell Stability Test Method and assigned to the present assignee, discloses a method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, that uses a reset test circuit with a wordline pulse width control circuit. The method can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. During test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. During a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.
- A principal aspect of the present invention is to provide a method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation. Other important aspects of the present invention are to provide such a method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
- In brief, a method and apparatus are provided for implementing static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit coupled to the SRAM core generates wordline pulses. An input logic couples data to the SRAM core, and an output logic provides an oscillator signal at an output to identify a minimum wordline pulse width to write the cell. A state machine controls the ring oscillator circuit and write and read operations to the SRAM core for implementing SRAM cell write performance evaluation.
- In accordance with features of the invention, an enable control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. Each wordline is connected to one cell from different bitlines. In this second write operation, each wordline has a different narrow pulse width, as a result some of the cells are written and some are not written. The ring oscillator includes a series of wordline pulse generators creating signals with different pulse widths. The cells are read with the original wide wordline pulse width. Based on the results of the read, one of the frequency divider signals is selected for output. The selected frequency signal of the output shows the minimum wordline pulse width needed to write the cell.
- When the enable control signal is high, the SRAM cell write performance evaluation circuit determines the wordline pulse width required to write the cell by reading the cells and setting a select bit in an output multiplexer based upon whether the cell connected was written properly. The select bits from the read operation determine how many times the frequency is divided. Then, the output oscillates at the natural frequency of the oscillator divided by an identified multiple of 2.
- The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
-
FIGS. 1A and 1B together provide a schematic diagram of an exemplary circuit for implementing static random access memory (SRAM) write performance evaluation in accordance with the preferred embodiment; -
FIG. 2 is a schematic diagram illustrating an exemplary ring oscillator circuit of the SRAM cell write performance evaluation circuit ofFIGS. 1A and 1B in accordance with the preferred embodiment; -
FIG. 3 are timing diagrams illustrating the operation of the SRAM cell write performance evaluation circuit ofFIGS. 1A and 1B in accordance with the preferred embodiment -
FIGS. 4 , 5 and 6 are schematic diagrams illustrating exemplary output logic of the SRAM cell write performance evaluation circuit ofFIGS. 1A and 1B in accordance with the preferred embodiment; -
FIG. 7 is a schematic diagram illustrating exemplary enable signal capture logic of the SRAM cell write performance evaluation circuit ofFIGS. 1A and 1B in accordance with the preferred embodiment. - In accordance with features of the invention, a method and circuit are provided to evaluate SRAM cell write performance in hardware. The method and circuit provide for granularity in performance evaluation whereas prior art does not.
- Having reference now to the drawings, in
FIGS. 1A and 1B , there is shown an exemplary circuit for implementing static random access memory (SRAM) write performance evaluation generally designated by thereference character 100 in accordance with the preferred embodiment. SRAM cell writeperformance evaluation circuit 100 includes aSRAM core 102, such as a 16×16 cell array where each wordline is connected to only one bit-column, aring oscillator circuit 104, aninput logic 106, anoutput logic 108 and astate machine 110. - While
SRAM core 102 is illustrated as a 16×16 cell array, it should be understood that this is only an example. Various array sizes can be used to implement the SRAMcore 102 in accordance with the present invention. - The
ring oscillator circuit 104 is used to generate wordline pulses WL for each of the multiple, for example sixteen wordline inputs WL(0)-WL(15) and a precharge signal PCH applied to theSRAM core 102. Thestate machine 110 is used to control the operation of thering oscillator circuit 104,input logic 106,output logic 108 for write and read operations for implementing SRAM cell write performance evaluation. - SRAM cell write
performance evaluation circuit 100 has one input labeled ENABLE applied to thestate machine 110, and one output labeled OUT ofoutput logic 108 that oscillates. The frequency of oscillation for the output signal OUT when ENABLE is low, and the frequency of oscillation for OUT when ENABLE is high, are used to show the required wordline pulse width to write the SRAM cells. Theinput logic 106 provides data inputs applied to alocal evaluation circuit 112 of theSRAM core 102 andlocal evaluation circuit 112 also receives the precharge signal PCH fromring oscillator 104. The DOT output of thelocal evaluation circuit 112 provides respective inputs to theoutput logic 108. A read path of theoutput logic 108 is illustrated and described with respect toFIGS. 4 and 5 . - SRAM cell write
performance evaluation circuit 100 is very simple to use and no special test patterns are required. The required operations for implementing SRAM cell write performance evaluation are to first simply measure the output frequency OUT with ENABLE low. Then, raise ENABLE, wait a few clock cycles, and measure the output frequency OUT again. From these two frequencies the required wordline pulse width to write the cell is identified. - Referring now to
FIG. 2 , there is shown an exemplaryring oscillator circuit 104 of the SRAM cell writeperformance evaluation circuit 100 in accordance with the preferred embodiment.Ring oscillator circuit 104 receives inputs ACT_WL and NARROW/WIDE_B from thestate machine 110. The signal ACT_WL controls when wordlines and the precharge signals are generated. The signal NARROW/WIDE_B controls whether the wordlines and precharge signals are wide, to ensure that the data is correctly written and read, or narrow to test the write performance of the SRAM cells.Ring oscillator circuit 104 provides the output RINGSIG applied to theoutput logic 108, and the plurality of wordline outputs WL(0)-WL(15) and precharge signal PCH applied to theSRAM core 102. -
Ring oscillator circuit 104 includes a chain or ring generally designated byreference character 202 including a plurality of stages or inverter pairs 204 connected in series. At anode NET 1 of theoscillator chain 202, a twoinput NAND gate 206 includes an input connected tonode NET 1 and an input connected to a positive supply rail VDD. The output of the twoinput NAND gate 206 is inverted by an inverter 208 and applied to each of a plurality of wordline pulse generator circuits generally designated byreference character 212 and providing wordline outputs WL(0)-WL(15). The ring signal atnode NET 1 is coupled by afirst inverter pair 204 in thering 202 and is inverted by aninverter 210 and applied to the wordlinepulse generator circuit 212 providing wordline output WL(0). - Each of the wordline
pulse generator circuits 212 include a pair of twoinput NAND gates input NAND gate 218 and aninverter 220. The input NARROW/WIDE_B is applied to an input of theNAND gate 216 of each of the wordlinepulse generator circuits 212. The output of inverter 208 is applied to an input of theNAND gate 214 of each of the wordlinepulse generator circuits 212. TheNAND gate 216 has an input connected between respective series connected inverter pairs 204 in thechain 202. Each of the twoinput NAND gates input NAND gate 218, which has a third input receiving the signal ACT_WL for controlling when wordlines and the precharge signals are generated.Inverter 220 inverts the output of the threeinput NAND gate 218. The respective output ofinverter 220 of each of thepulse generator circuits 212 respectively provides the plurality of wordline outputs WL(0)-WL(15) and precharge signal PCH. - A ring output path includes a two input NAND gate 224 having an input connected between two
inverter pairs 204 and an input connected to VDD. The NAND gate output is inverted by aninverter 226, which provides output RINGSIG. A plurality of twoinput NAND gates 228 having an output coupled by acapacitor 230 to ground potential, has an input connected between respective series connected inverter pairs 204 in thechain 202 from ring connection for output RINGSIG to thenode NET 1. TheseNAND gates 228 insure that all inverter pairs 204 in thering oscillator 104 have the same capacitance loading. Timing considerations for thering oscillator circuit 104 require that the delay through the state machine of RINGSIG rising to the correct signals switching, especially ACT_WL is less than the delay from output RINGSIG tonode NET 1 inFIG. 2 . Extra delay can be added to the ring path if required. - In narrow mode of ring oscillator input NARROW/WIDE_B, wordline output pulses at output WL<0> are very narrow and the wordline output pulses are progressively wider until WL<15> and the precharge signal PCH is the widest signal pulse. In initial wide mode, the signal NARROW/WIDE_B causes all the wordlines and precharge signals to be wide. When ENABLE is low, the signal RINGSIG is sent to the output of the SRAM cell write
performance evaluation circuit 100. From this, delay per stage of the oscillator can be found, and the actual wordline pulse widths can also be found. - Referring also to
FIG. 3 , there are shown timing diagrams illustrating the operation of the SRAM cell writeperformance evaluation circuit 100. InFIG. 3 , waveforms illustrate the input signal ENABLE, oscillator output signal RINGSIG, oscillator control signal ACT_WL, input DATA, read/write control R/W_B, the ring oscillator input NARROW/WIDE_B, and a wordline output pulses at an exemplary output WL. - SRAM cell write
performance evaluation circuit 100 operates as follows. During a first time period indicated by an arrow labeled A of a first write operation, the input signal ENABLE is low. While ENABLE is low the SRAM cell writeperformance evaluation circuit 100 repeatedly writes 0s as illustrated at DATA with wide wordline pulses, as illustrated at output WL. - Then when ENABLE goes high one more set of 0s are written with wide wordline pulses during a next time period indicated by an arrow labeled B. With the wordlines disabled indicated by ACT_WL during a next time period indicated by an arrow labeled C, the control signals indicated by ring oscillator input NARROW/WIDE_B are switched to prepare to write 1s with narrow wordline pulses.
- During a next time period indicated by an arrow labeled D, 1s are written with a very narrow wordline pulse width for WL<0> and with an incrementally wider wordline pulse width until WL<15>. With the wordlines disabled, the control signals are switched to prepare to read the cells with wide wordline pulses during a next time period indicated by an arrow labeled E. Then the cells are read with wide WL pulses during a next time period indicated by an arrow labeled F.
- Then during a next time period indicated by an arrow labeled G wordlines are deactivated and the control signals are switched back to their original state. The results of the read determine how many times the RINGSIG signal is divided before it is sent to the output OUT. This output signal OUT shows the required wordline pulse width to write the cell. During a next time period indicated by an arrow labeled H, when the ENABLE goes low, the control signals are switched back to the state of continually writing 0s. When ENABLE is low, the output OUT oscillates at the natural frequency RINGSIG of the
oscillator 104. -
FIGS. 4 and 5 together illustrate a read path generally designated by thereference character 400 of SRAM cell writeperformance evaluation circuit 100 in accordance with the preferred embodiment. Readpath 400 includes a respective data input DOT<0>-DOT<15> applied to aread circuit XCN 402, receiving the RINGSIG applied by a plurality of series connectedinverters read circuit XCN 402 provides a respective output RD<0>-RD<15>. - Referring to
FIG. 5 , theread circuit XCN 402 is illustrated. Theread circuit XCN 402 includes a precharge P-channel field effect transistor (PFET) 502 connected between the data input DOT node.PFET 502 has a gate input applied by aninverter 504 having an input connected to node P2. Theread circuit XCN 402 includes a pair of cross-connected twoinput NAND gates NAND gate 506 with the output ofNAND gate 508 applied to the other input ofNAND gate 506. The RINGSIG applied by the series connectedinverters NAND gate 508 with the output ofNAND gate 506 applied to the other input ofNAND gate 508. - Referring to
FIG. 6 , there is shownexemplary output logic 108 of the SRAM cell writeperformance evaluation circuit 100. When ENABLE is high, the SRAM cell writeperformance evaluation circuit 100 determines the wordline pulse width required to write the cell by reading the cells and setting a select bit in anoutput multiplexer 602 of theoutput logic 108 based on whether the cell connected was written properly. The frequency output RINGSIG of theoscillator 104 is applied to a first one of a plurality of frequency dividers or divide by 2circuits 604 that are connected in a chain. The output RINGSIG, and the respective frequency divided output of the plurality offrequency dividers 604 are applied to respective inputs of theoutput multiplexer 602. Arespective NAND gate 606 provides a select signal to theoutput multiplexer 602 based upon the select bits from the read. The select bits from the read determine how many times the frequency is divided. Then, the output signal OUT oscillates at the natural frequency of the oscillator divided by the selected multiple of 2, which is provided by the selected one of the chained divide by 2circuits 604. Thestate machine 110 is used to step through the required states of the signals that control the read and write operations. - Referring to
FIG. 7 , there is shown an exemplary enable signal capture logic generally designated by thereference character 700 of thestate machine 110 of the SRAM cell writeperformance evaluation circuit 100. Enablesignal capture logic 700 includes a plurality of series connected D-latches 702, each receiving a clock input C of the frequency output RINGSIG of theoscillator 104. The respective lettered outputs A-J of the D-latches 702 are used to control thestate machine 110. - While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
Claims (7)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/845,866 US7505340B1 (en) | 2007-08-28 | 2007-08-28 | Method for implementing SRAM cell write performance evaluation |
US11/873,173 US7788554B2 (en) | 2007-08-28 | 2007-10-16 | Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation |
US12/351,920 US7768851B2 (en) | 2007-08-28 | 2009-01-12 | Apparatus for implementing SRAM cell write performance evaluation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/845,866 US7505340B1 (en) | 2007-08-28 | 2007-08-28 | Method for implementing SRAM cell write performance evaluation |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/873,173 Continuation-In-Part US7788554B2 (en) | 2007-08-28 | 2007-10-16 | Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation |
US12/351,920 Continuation US7768851B2 (en) | 2007-08-28 | 2009-01-12 | Apparatus for implementing SRAM cell write performance evaluation |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090059697A1 true US20090059697A1 (en) | 2009-03-05 |
US7505340B1 US7505340B1 (en) | 2009-03-17 |
Family
ID=40407241
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/845,866 Expired - Fee Related US7505340B1 (en) | 2007-08-28 | 2007-08-28 | Method for implementing SRAM cell write performance evaluation |
US11/873,173 Expired - Fee Related US7788554B2 (en) | 2007-08-28 | 2007-10-16 | Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation |
US12/351,920 Expired - Fee Related US7768851B2 (en) | 2007-08-28 | 2009-01-12 | Apparatus for implementing SRAM cell write performance evaluation |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/873,173 Expired - Fee Related US7788554B2 (en) | 2007-08-28 | 2007-10-16 | Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation |
US12/351,920 Expired - Fee Related US7768851B2 (en) | 2007-08-28 | 2009-01-12 | Apparatus for implementing SRAM cell write performance evaluation |
Country Status (1)
Country | Link |
---|---|
US (3) | US7505340B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107851453A (en) * | 2015-07-27 | 2018-03-27 | 电力荡半导体有限公司 | Using the low-power consumption SRAM bit location of resonance drive circuit |
US10867665B1 (en) * | 2017-02-16 | 2020-12-15 | Synopsys, Inc. | Reset before write architecture and method |
US10891992B1 (en) | 2017-02-16 | 2021-01-12 | Synopsys, Inc. | Bit-line repeater insertion architecture |
US11784648B2 (en) | 2021-06-02 | 2023-10-10 | Power Down Semiconductor, Inc. | Low power interconnect using resonant drive circuitry |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7505340B1 (en) * | 2007-08-28 | 2009-03-17 | International Business Machines Corporation | Method for implementing SRAM cell write performance evaluation |
US7882407B2 (en) * | 2007-12-17 | 2011-02-01 | Qualcomm Incorporated | Adapting word line pulse widths in memory systems |
US7755960B2 (en) * | 2007-12-17 | 2010-07-13 | Stmicroelectronics Sa | Memory including a performance test circuit |
US7684263B2 (en) * | 2008-01-17 | 2010-03-23 | International Business Machines Corporation | Method and circuit for implementing enhanced SRAM write and read performance ring oscillator |
US8027213B2 (en) * | 2009-06-19 | 2011-09-27 | Apple Inc. | Mechanism for measuring read current variability of SRAM cells |
US9058866B2 (en) | 2012-08-30 | 2015-06-16 | International Business Machines Corporation | SRAM local evaluation logic for column selection |
US9087563B2 (en) | 2012-09-06 | 2015-07-21 | International Business Machines Corporation | SRAM local evaluation and write logic for column selection |
US9355692B2 (en) | 2012-09-18 | 2016-05-31 | International Business Machines Corporation | High frequency write through memory device |
CN104956442A (en) | 2013-03-28 | 2015-09-30 | 惠普发展公司,有限责任合伙企业 | Apparatus and method for storage device reading |
US9343182B2 (en) | 2013-07-10 | 2016-05-17 | International Business Machines Corporation | Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability |
CN103886913B (en) * | 2014-03-31 | 2016-09-14 | 西安紫光国芯半导体有限公司 | SRAM reads time self testing circuit and method of testing |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6414535B1 (en) * | 1995-02-06 | 2002-07-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device realizing internal operational factor corresponding to an external operational factor stably regardless of fluctuation of external operational factor |
US6728912B2 (en) * | 2001-04-12 | 2004-04-27 | International Business Machines Corporation | SOI cell stability test method |
US7133320B2 (en) * | 2004-11-04 | 2006-11-07 | International Business Machines Corporation | Flood mode implementation for continuous bitline local evaluation circuit |
US7278034B2 (en) * | 2002-12-02 | 2007-10-02 | Silverbrook Research Pty Ltd | Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor |
US20080162770A1 (en) * | 2006-11-01 | 2008-07-03 | Texas Instruments Incorporated | Hardware voting mechanism for arbitrating scaling of shared voltage domain, integrated circuits, processes and systems |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7505340B1 (en) | 2007-08-28 | 2009-03-17 | International Business Machines Corporation | Method for implementing SRAM cell write performance evaluation |
-
2007
- 2007-08-28 US US11/845,866 patent/US7505340B1/en not_active Expired - Fee Related
- 2007-10-16 US US11/873,173 patent/US7788554B2/en not_active Expired - Fee Related
-
2009
- 2009-01-12 US US12/351,920 patent/US7768851B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6414535B1 (en) * | 1995-02-06 | 2002-07-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device realizing internal operational factor corresponding to an external operational factor stably regardless of fluctuation of external operational factor |
US6728912B2 (en) * | 2001-04-12 | 2004-04-27 | International Business Machines Corporation | SOI cell stability test method |
US7278034B2 (en) * | 2002-12-02 | 2007-10-02 | Silverbrook Research Pty Ltd | Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor |
US7133320B2 (en) * | 2004-11-04 | 2006-11-07 | International Business Machines Corporation | Flood mode implementation for continuous bitline local evaluation circuit |
US20080162770A1 (en) * | 2006-11-01 | 2008-07-03 | Texas Instruments Incorporated | Hardware voting mechanism for arbitrating scaling of shared voltage domain, integrated circuits, processes and systems |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107851453A (en) * | 2015-07-27 | 2018-03-27 | 电力荡半导体有限公司 | Using the low-power consumption SRAM bit location of resonance drive circuit |
EP3329490A4 (en) * | 2015-07-27 | 2019-05-22 | Power Down Semiconductor Inc | A low power sram bitcell using resonant drive circuitry |
US10510399B2 (en) | 2015-07-27 | 2019-12-17 | Power Down Semiconductor Inc. | Low power SRAM bitcell using resonant drive circuitry |
US10867665B1 (en) * | 2017-02-16 | 2020-12-15 | Synopsys, Inc. | Reset before write architecture and method |
US10891992B1 (en) | 2017-02-16 | 2021-01-12 | Synopsys, Inc. | Bit-line repeater insertion architecture |
US11784648B2 (en) | 2021-06-02 | 2023-10-10 | Power Down Semiconductor, Inc. | Low power interconnect using resonant drive circuitry |
Also Published As
Publication number | Publication date |
---|---|
US20090063912A1 (en) | 2009-03-05 |
US7788554B2 (en) | 2010-08-31 |
US7768851B2 (en) | 2010-08-03 |
US20090116298A1 (en) | 2009-05-07 |
US7505340B1 (en) | 2009-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7505340B1 (en) | Method for implementing SRAM cell write performance evaluation | |
KR100714308B1 (en) | Semiconductor memory device and refresh clock signal generator thereof | |
US11742051B2 (en) | Sensor for performance variation of memory read and write characteristics | |
US7170774B2 (en) | Global bit line restore timing scheme and circuit | |
US8295099B1 (en) | Dual port memory with write assist | |
US7609542B2 (en) | Implementing enhanced SRAM read performance sort ring oscillator (PSRO) | |
US20130003446A1 (en) | Method for Extending Word-Line Pulses | |
US6999367B2 (en) | Semiconductor memory device | |
US7684263B2 (en) | Method and circuit for implementing enhanced SRAM write and read performance ring oscillator | |
US6785173B2 (en) | Semiconductor memory device capable of performing high-frequency wafer test operation | |
KR100301645B1 (en) | Semiconductor memory device having selection circuit for arbitrarily setting a word line to selected state at high speed in test mode | |
US20100046278A1 (en) | Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage | |
JPH08227598A (en) | Semiconductor storage device and its word line selecting method | |
US5007028A (en) | Multiport memory with improved timing of word line selection | |
JP2004129254A (en) | Frequency multiplier, data output buffer of semiconductor device, semiconductor device, and multiplication method of clock frequency | |
US6490222B2 (en) | Decoding circuit for controlling activation of wordlines in a semiconductor memory device | |
US20150063010A1 (en) | Negative bias thermal instability stress testing for static random access memory (sram) | |
KR100318420B1 (en) | A pipe register in synchronous semiconductor memory device | |
US9111595B2 (en) | Memory device with tracking wordline voltage level circuit and method | |
US6999347B2 (en) | Non-volatile semiconductor memory device with expected value comparison capability | |
US5652535A (en) | Non-overlaping signal generation circuit | |
CN212724727U (en) | Wide voltage SRAM timing tracking circuit | |
KR20090016168A (en) | Semiconductor integrated circuits comprising strobe signal generating circuit | |
KR100630524B1 (en) | Word line driving circuit with improved test signal path and semiconductor memory device with the same | |
KR19980069481A (en) | Section Wordline Driven Pulse Generation Method for High Speed Memory Devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ADAMS, CHAD ALLEN;BEHRENDS, DERICK GARDNER;HEBIG, TRAVIS REYNOLD;AND OTHERS;REEL/FRAME:019755/0629 Effective date: 20070827 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20130317 |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |