US20080318354A1 - Method of fabricating thin film transistor and method of fabricating liquid crystal display - Google Patents
Method of fabricating thin film transistor and method of fabricating liquid crystal display Download PDFInfo
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- US20080318354A1 US20080318354A1 US12/204,103 US20410308A US2008318354A1 US 20080318354 A1 US20080318354 A1 US 20080318354A1 US 20410308 A US20410308 A US 20410308A US 2008318354 A1 US2008318354 A1 US 2008318354A1
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- 239000010409 thin film Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 67
- 239000000463 material Substances 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052804 chromium Inorganic materials 0.000 claims description 11
- 239000011651 chromium Substances 0.000 claims description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000872 buffer Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Definitions
- the present invention relates to a method of fabricating a thin film transistor of a thin film transistor liquid crystal display (TFT-LCD) and a method of fabricating a liquid crystal display. More particularly, the present invention relates to a method of fabricating a thin film transistor of a thin film transistor liquid crystal display (TFT-LCD) and a method of fabricating the liquid crystal display by damascene process.
- TFT-LCD thin film transistor liquid crystal display
- cathode ray tubes were one of the most important display devices in the market due to their high display quality and moderate pricing.
- energy consumption is also a very important consideration.
- TFT-LCD thin film transistor liquid crystal display
- the conventional method of fabricating a thin film transistor includes forming a gate on a substrate and then forming an insulating layer and a semiconductor layer sequentially over the substrate to cover the gate. Thereafter, a source and a drain are formed on the semiconductor layer to form a thin film transistor.
- the metallic layers In the conventional method of fabricating the thin film transistor, a photolithographic and etching process is used to pattern metallic layers for producing the gate, the source and the drain.
- the metallic layers must have a property that matches with the liquid etchant or gaseous etchant used in the etching operation. Therefore, a metal having an ideal etching property such as aluminum to form the metallic layer is selected in the prior art.
- a metal having an ideal etching property such as aluminum to form the metallic layer is selected in the prior art.
- the materials that can be used to form the electrodes of the thin film transistor are limited.
- the increase in electrical resistance as the device miniaturization will directly affect the performance of the thin film transistors.
- At least one objective of the present invention is to provide a method of fabricating a thin film transistor of a thin film transistor liquid crystal display that can increase the choice of material for forming the electrodes of the thin film transistor.
- At least a second objective of the present invention is to provide a method of fabricating a thin film transistor of a thin film transistor liquid crystal display that can improve the electrical performance of the thin film transistor.
- At least a third objective of the present invention is to provide a method of fabricating a liquid crystal display that can improve the electrical performance of the liquid crystal display.
- the invention provides a method of fabricating a thin film transistor of a thin film transistor liquid crystal display.
- a first patterned dielectric layer is formed over a substrate and then a first metallic layer is formed over the substrate to cover the first patterned dielectric layer.
- the first metallic layer is planarized until the first patterned dielectric layer is exposed.
- the remaining first metallic layer serves as a gate.
- a gate insulating layer is formed over the first patterned dielectric layer and the gate.
- a semiconductor layer is formed over the gate insulating layer above the gate.
- a source and a drain are formed over the semiconductor layer.
- the step of planarizing the metallic layer includes performing a chemical-mechanical polishing operation.
- the material constituting the first metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- the method of forming the source and the drain includes forming a second patterned dielectric layer over the gate insulating layer and then forming a second metallic layer over the second patterned dielectric layer. Thereafter, a planarization process is performed to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form the source and the drain.
- the planarization process includes a chemical-mechanical polishing operation.
- the material constituting the second metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. Furthermore, after forming the source and the drain, the second patterned dielectric layer is removed.
- before forming the first patterned dielectric layer over the substrate further comprises forming a stress-buffering layer over the substrate.
- the stress-buffering layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof.
- the semiconductor layer comprises a channel layer and an ohmic contact layer.
- the present invention also provides an alternative method of fabricating a thin film transistor of a thin film transistor liquid crystal display.
- a gate is formed over a substrate and then a gate insulating layer is formed over the substrate to cover the gate.
- a semiconductor layer is formed on the gate insulating layer above the gate.
- a patterned dielectric layer is formed over the gate insulating layer.
- a metallic layer is formed over the patterned dielectric layer and then a planarization process is performed to remove a portion of the metallic layer and a portion of the patterned dielectric layer to form a source and a drain.
- the planarization process includes a chemical-mechanical polishing operation.
- the material constituting the metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- a stress-buffering layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof.
- the semiconductor layer comprises a channel layer and an ohmic contact layer.
- the present invention also provides a method of fabricating a liquid crystal display.
- a thin film transistor array layer is formed over a first substrate.
- a second substrate is provided.
- a liquid crystal layer is formed between the first substrate and the second substrate.
- the thin film transistor array layer comprises a plurality of thin film transistors and a plurality of pixel electrodes.
- Each thin film transistor further comprises a gate, a source and a drain.
- the method of forming the gate and/or the source and drain includes forming a patterned dielectric layer over the substrate and then forming a metallic layer over the patterned dielectric layer. Thereafter, a planarization process is preformed.
- the planarization process includes a chemical-mechanical polishing operation.
- the material constituting the metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- the second substrate further comprises a color-filtering layer disposed thereon.
- a damascene process replaces the conventional photolithographic and etching process.
- the type of materials that can be chosen for forming the metallic layer is increased.
- a metallic material having a lower electrical resistance can be used.
- the thin film transistor and the liquid crystal display using such thin film transistor can have a better electrical performance.
- FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to one embodiment of the present invention.
- FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention.
- FIGS. 3A through 3F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention.
- FIG. 4 is a schematic cross-sectional view of a liquid crystal display according to one embodiment of the present invention.
- FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to one embodiment of the present invention.
- a first patterned dielectric layer 120 is formed over a substrate 100 .
- the method of forming the patterned dielectric layer 120 includes depositing a dielectric layer (not shown) and then performing a photolithographic and etching process to pattern the dielectric layer.
- a stress-buffering layer 110 might be optionally formed on the substrate 100 before forming the first patterned dielectric layer 120 .
- the stress-buffering layer 110 buffers the substrate 100 against stresses encountered during the thin film transistor fabrication process so that cracks and damages in the substrate 100 are minimized.
- the stress-buffering layer 110 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof, for example.
- a first metallic layer 130 is formed over the substrate 100 to cover the first patterned dielectric layer 120 .
- the material constituting the first metallic layer 140 is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof some, for example.
- the first metallic layer 130 is planarized until the first patterned dielectric layer 120 is exposed.
- the step of planarizing the first metallic layer 130 includes performing a chemical-mechanical polishing operation, for example. After the planarization, the remained first metallic layer 130 serves as a gate 132 .
- a gate insulating layer 140 is formed over the first patterned dielectric layer 120 and the gate 132 . Then, a semiconductor layer 150 is formed over the gate insulating layer 140 above the gate 132 .
- the semiconductor layer 150 comprises a channel layer 152 and an ohmic contact layer 154 .
- the gate insulating layer 140 is fabricated using silicon oxide, silicon nitride or silicon oxynitride, for example.
- the channel layer 152 is fabricated using amorphous silicon and the ohmic contact layer 154 is fabricated using n+ doped amorphous silicon, for example.
- a source 162 and a drain 164 are formed on the semiconductor layer 150 so that a thin film transistor 190 is formed.
- the method of forming the source 162 and the drain 164 includes performing a photolithographic and etching process, for example.
- an additional passivation layer (not shown) may be formed over the thin film transistor 190 .
- the aforementioned photolithographic and etching process for forming the source 162 and the drain 164 is only one of the embodiments in the present invention.
- the process of fabricating the source 162 and the drain 164 is not limited as such.
- anyone familiar with the fabrication process may select a more appropriate process that also uses the damascene process according to the actual processing demand.
- another embodiment that uses the damascene process for forming the source and the drain is described.
- FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention.
- FIGS. 2A ⁇ 2C the steps for forming the stress-buffering layer 120 , the first patterned dielectric layer 220 , the gate 232 , the gate insulating layer 240 and the semiconductor layer 250 are described. Since these steps are identical to the steps described in FIGS. 1A ⁇ 1C , a detailed description is omitted.
- a second patterned dielectric layer 270 is formed over the gate insulating layer 240 .
- the method of forming the second patterned dielectric layer 270 includes, for example, depositing an insulating layer (not shown) and then patterning the insulating layer by performing a photolithographic and etching process.
- the second patterned dielectric layer 270 is formed over the gate insulating layer 240 but does not cover the entire semiconductor layer 250 . A portion of the semiconductor layer 250 is exposed.
- a second metallic layer 260 is formed over the second patterned dielectric layer 270 .
- the second metallic layer 260 can be fabricated using a material identical to the metallic layer used for forming the gate in the aforementioned embodiment.
- the second metallic layer 260 is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- a planarization process is performed to the second metallic layer 260 .
- the planarization process is still performed to remove the second metallic layer 260 and the second patterned dielectric layer 270 over the semiconductor layer 250 until the second patterned dielectric layer 270 at the two sides of the resulted structure of FIG. 2F is exposed. That is, the planarization process completely removes the second metallic layer 260 above the second patterned dielectric layer 270 , and the second metallic layer 260 which does not located above the second patterned dielectric layer 270 is remained.
- the planarization process includes a chemical-mechanical polishing operation, for example.
- the remained second metallic layer 260 serves as a source 262 and a drain 264 .
- a thin film transistor 290 is formed.
- the second patterned dielectric layer 270 can be optionally removed.
- a passivation layer (not shown) is formed over the thin film transistor 290 .
- FIGS. 3A through 3F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention.
- a gate 320 is formed over a substrate 300 .
- the method of forming the gate 320 includes performing a photolithographic and etching process, for example.
- an optional stress-buffering layer 110 for buffering the substrate 100 against stress might be formed on the substrate 100 before forming the gate 320 .
- This stress-buffering layer 310 can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof, for example.
- a gate insulating layer 330 is formed over the substrate 300 to cover the gate 320 .
- a semiconductor layer 340 is formed over the gate insulating layer 330 above the gate 320 .
- the semiconductor layer 340 comprises a channel layer 342 and an ohmic contact layer 344 .
- the gate insulating layer is fabricated using silicon oxide, silicon nitride or silicon oxynitride, for example.
- the channel layer 342 is fabricated using amorphous silicon and the ohmic contact layer 344 is fabricated using n+ doped amorphous silicon, for example.
- a patterned dielectric layer 350 is formed over the semiconductor layer 340 .
- the method of forming the patterned dielectric layer 350 includes depositing a dielectric layer (not shown) and then patterning the dielectric layer (not shown) by a photolithographic and etching process to form the patterned dielectric layer 350 .
- the patterned dielectric layer 350 covers only a portion of the semiconductor layer 340 . A portion of the semiconductor layer 340 is exposed.
- a metallic layer 360 is formed over the patterned dielectric layer 350 .
- the metallic layer 360 is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof, for example.
- a planarization process is performed to the metallic layer 360 .
- the planarization process is still performed to remove the metallic layer 360 and the patterned dielectric layer 350 over the semiconductor layer 340 until the patterned dielectric layer 350 at the two sides of the resulted structure of FIG. 3F is exposed. That is, the planarization process completely removes the metallic layer 360 above the patterned dielectric layer 350 , and the metallic layer 360 which does not located above the patterned dielectric layer 350 is remained.
- the planarization process includes, for example, a chemical-mechanical polishing operation.
- the remained metallic layer constitutes a source 362 and a drain 364 .
- a thin film transistor 390 is formed.
- the patterned dielectric layer 350 is optionally removed.
- a passivation layer (not shown) is formed over the thin film transistor 390 .
- FIG. 4 is a schematic cross-sectional view of a liquid crystal display according to one embodiment of the present invention.
- the method of forming a liquid crystal display 450 according to the present invention includes forming a thin film transistor array layer 410 over a first substrate 400 .
- the thin film transistor array layer 410 comprises a plurality of thin film transistors (not shown) and a plurality of pixel electrodes (not shown).
- the thin film transistors in the thin film transistor array layer 410 is formed using the aforementioned damascene process (in FIGS. 1A ⁇ 1D or FIGS. 2A ⁇ 2F or FIGS. 3A ⁇ 3F ).
- the pixel electrodes are defined and each pixel electrode is electrically connected to a corresponding thin film transistor.
- a second substrate 440 is provided.
- the second substrate 440 has a color filter layer 430 thereon, for example.
- a liquid crystal layer 420 is formed between the first substrate 400 and the second substrate 440 to form a thin film transistor liquid crystal display 450 .
- any conventional methods can be used to form the color filter layer 430 on the second substrate 440 and the liquid crystal layer 420 between the two substrates 400 and 440 .
- the method of fabricating the thin film transistor of a thin film transistor liquid crystal display according to the present invention includes using a damascene process to form the electrodes of the transistor. Consequently, more choices of materials are available for forming the electrodes of the thin film transistors. Furthermore, if a material having a lower resistance such as copper is used as the electrode material for the thin film transistors, the electrical performance of the thin film transistor and the liquid crystal display using such thin film transistor will improve.
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Abstract
A method of fabricating a thin film transistor is provided. First, a patterned dielectric layer is formed over a substrate. A metallic layer is formed over the substrate to cover the patterned dielectric layer. Thereafter, the metallic layer is planarized until the patterned dielectric layer is exposed. The remained metallic layer serves as a gate. An insulating layer is formed over the patterned dielectric layer and the gate, and then a semiconductor layer is formed over the gate insulating layer above the gate. A source and a drain are formed over the semiconductor layer.
Description
- This is a continuation application of patent application Ser. No. 11/357,812, filed on Feb. 16, 2006, which claims the priority benefit of Taiwan patent application serial no. 94104418 and 94139059, filed on Feb. 16, 2005, and Nov. 8, 2005. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The present invention relates to a method of fabricating a thin film transistor of a thin film transistor liquid crystal display (TFT-LCD) and a method of fabricating a liquid crystal display. More particularly, the present invention relates to a method of fabricating a thin film transistor of a thin film transistor liquid crystal display (TFT-LCD) and a method of fabricating the liquid crystal display by damascene process.
- 2. Description of the Related Art
- With the rapid progress in the fabrication of semiconductor devices and man-machine interfacing devices, multimedia technologies are deployed everywhere in our society. In the past, cathode ray tubes (CRT) were one of the most important display devices in the market due to their high display quality and moderate pricing. However, in an environment where a large number of desktop operated terminals/display devices are used, energy consumption is also a very important consideration. Because a CRT wastes a lot of power and has a poor spatial utilization, other types of display devices having higher display quality, greater spatial utilization, lower power consumption and capable of radiation-free operation such as the thin film transistor liquid crystal display (TFT-LCD) gradually take over. In fact, TFT-LCD has become one of the mainstream display devices in the market.
- The conventional method of fabricating a thin film transistor includes forming a gate on a substrate and then forming an insulating layer and a semiconductor layer sequentially over the substrate to cover the gate. Thereafter, a source and a drain are formed on the semiconductor layer to form a thin film transistor.
- In the conventional method of fabricating the thin film transistor, a photolithographic and etching process is used to pattern metallic layers for producing the gate, the source and the drain. Thus, the metallic layers must have a property that matches with the liquid etchant or gaseous etchant used in the etching operation. Therefore, a metal having an ideal etching property such as aluminum to form the metallic layer is selected in the prior art. However, when this type of material is used, the materials that can be used to form the electrodes of the thin film transistor are limited. In particular, because aluminum has a higher resistance relative to other metals, the increase in electrical resistance as the device miniaturization will directly affect the performance of the thin film transistors.
- Accordingly, at least one objective of the present invention is to provide a method of fabricating a thin film transistor of a thin film transistor liquid crystal display that can increase the choice of material for forming the electrodes of the thin film transistor.
- At least a second objective of the present invention is to provide a method of fabricating a thin film transistor of a thin film transistor liquid crystal display that can improve the electrical performance of the thin film transistor.
- At least a third objective of the present invention is to provide a method of fabricating a liquid crystal display that can improve the electrical performance of the liquid crystal display.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a thin film transistor of a thin film transistor liquid crystal display. First, a first patterned dielectric layer is formed over a substrate and then a first metallic layer is formed over the substrate to cover the first patterned dielectric layer. Thereafter, the first metallic layer is planarized until the first patterned dielectric layer is exposed. The remaining first metallic layer serves as a gate. After that, a gate insulating layer is formed over the first patterned dielectric layer and the gate. A semiconductor layer is formed over the gate insulating layer above the gate. Finally, a source and a drain are formed over the semiconductor layer.
- According to the preferred embodiment of the present invention, the step of planarizing the metallic layer includes performing a chemical-mechanical polishing operation.
- According to the preferred embodiment of the present invention, the material constituting the first metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- According to the preferred embodiment of the present invention, the method of forming the source and the drain includes forming a second patterned dielectric layer over the gate insulating layer and then forming a second metallic layer over the second patterned dielectric layer. Thereafter, a planarization process is performed to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form the source and the drain. The planarization process includes a chemical-mechanical polishing operation. The material constituting the second metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. Furthermore, after forming the source and the drain, the second patterned dielectric layer is removed.
- According to the preferred embodiment of the present invention, before forming the first patterned dielectric layer over the substrate, further comprises forming a stress-buffering layer over the substrate.
- According to the preferred embodiment of the present invention, the stress-buffering layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof.
- According to the preferred embodiment of the present invention, the semiconductor layer comprises a channel layer and an ohmic contact layer.
- The present invention also provides an alternative method of fabricating a thin film transistor of a thin film transistor liquid crystal display. First, a gate is formed over a substrate and then a gate insulating layer is formed over the substrate to cover the gate. Thereafter, a semiconductor layer is formed on the gate insulating layer above the gate. A patterned dielectric layer is formed over the gate insulating layer. After that, a metallic layer is formed over the patterned dielectric layer and then a planarization process is performed to remove a portion of the metallic layer and a portion of the patterned dielectric layer to form a source and a drain.
- According to one preferred embodiment of the present invention, the planarization process includes a chemical-mechanical polishing operation.
- According to one preferred embodiment of the present invention, the material constituting the metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- According to the preferred embodiment of the present invention, before forming the gate over the substrate, further comprises forming a stress-buffering layer on the substrate. The stress-buffering layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof.
- According to the preferred embodiment of the present invention, the semiconductor layer comprises a channel layer and an ohmic contact layer.
- The present invention also provides a method of fabricating a liquid crystal display. First, a thin film transistor array layer is formed over a first substrate. A second substrate is provided. Then, a liquid crystal layer is formed between the first substrate and the second substrate. The thin film transistor array layer comprises a plurality of thin film transistors and a plurality of pixel electrodes. Each thin film transistor further comprises a gate, a source and a drain. The method of forming the gate and/or the source and drain includes forming a patterned dielectric layer over the substrate and then forming a metallic layer over the patterned dielectric layer. Thereafter, a planarization process is preformed.
- According to the preferred embodiment of the present invention, the planarization process includes a chemical-mechanical polishing operation.
- According to the preferred embodiment of the present invention, the material constituting the metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
- According to the preferred embodiment of the present invention, the second substrate further comprises a color-filtering layer disposed thereon.
- In the method of fabricating the thin film transistor of a thin film transistor liquid crystal display and the method of fabricating the liquid crystal display according to the present invention, a damascene process replaces the conventional photolithographic and etching process. Hence, the type of materials that can be chosen for forming the metallic layer is increased. Furthermore, when the thin film transistor of the thin film transistor liquid crystal display is formed by a damascene process, a metallic material having a lower electrical resistance can be used. Ultimately, the thin film transistor and the liquid crystal display using such thin film transistor can have a better electrical performance.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to one embodiment of the present invention. -
FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention. -
FIGS. 3A through 3F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention. -
FIG. 4 is a schematic cross-sectional view of a liquid crystal display according to one embodiment of the present invention. - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to one embodiment of the present invention. First, as shown inFIG. 1A , a firstpatterned dielectric layer 120 is formed over asubstrate 100. In the present embodiment, the method of forming the patterneddielectric layer 120 includes depositing a dielectric layer (not shown) and then performing a photolithographic and etching process to pattern the dielectric layer. It should be noted that a stress-buffering layer 110 might be optionally formed on thesubstrate 100 before forming the firstpatterned dielectric layer 120. The stress-buffering layer 110 buffers thesubstrate 100 against stresses encountered during the thin film transistor fabrication process so that cracks and damages in thesubstrate 100 are minimized. The stress-buffering layer 110 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof, for example. - As shown in
FIG. 1B , a firstmetallic layer 130 is formed over thesubstrate 100 to cover the firstpatterned dielectric layer 120. In one embodiment, the material constituting the firstmetallic layer 140 is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof some, for example. - As shown in
FIG. 1C , the firstmetallic layer 130 is planarized until the firstpatterned dielectric layer 120 is exposed. The step of planarizing the firstmetallic layer 130 includes performing a chemical-mechanical polishing operation, for example. After the planarization, the remained firstmetallic layer 130 serves as agate 132. - As shown in
FIG. 1D , agate insulating layer 140 is formed over the firstpatterned dielectric layer 120 and thegate 132. Then, asemiconductor layer 150 is formed over thegate insulating layer 140 above thegate 132. In the present embodiment, thesemiconductor layer 150 comprises achannel layer 152 and anohmic contact layer 154. Furthermore, thegate insulating layer 140 is fabricated using silicon oxide, silicon nitride or silicon oxynitride, for example. Thechannel layer 152 is fabricated using amorphous silicon and theohmic contact layer 154 is fabricated using n+ doped amorphous silicon, for example. Thereafter, asource 162 and adrain 164 are formed on thesemiconductor layer 150 so that athin film transistor 190 is formed. In one embodiment, the method of forming thesource 162 and thedrain 164 includes performing a photolithographic and etching process, for example. After forming thesource 162 and thedrain 164, an additional passivation layer (not shown) may be formed over thethin film transistor 190. - It should be noted that the aforementioned photolithographic and etching process for forming the
source 162 and thedrain 164 is only one of the embodiments in the present invention. The process of fabricating thesource 162 and thedrain 164 is not limited as such. Anyone familiar with the fabrication process may select a more appropriate process that also uses the damascene process according to the actual processing demand. In the following, another embodiment that uses the damascene process for forming the source and the drain is described. -
FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention. InFIGS. 2A˜2C , the steps for forming the stress-buffering layer 120, the firstpatterned dielectric layer 220, thegate 232, thegate insulating layer 240 and thesemiconductor layer 250 are described. Since these steps are identical to the steps described inFIGS. 1A˜1C , a detailed description is omitted. - As shown in
FIG. 2D , a secondpatterned dielectric layer 270 is formed over thegate insulating layer 240. The method of forming the secondpatterned dielectric layer 270 includes, for example, depositing an insulating layer (not shown) and then patterning the insulating layer by performing a photolithographic and etching process. The secondpatterned dielectric layer 270 is formed over thegate insulating layer 240 but does not cover theentire semiconductor layer 250. A portion of thesemiconductor layer 250 is exposed. - As shown in
FIG. 2E , a secondmetallic layer 260 is formed over the secondpatterned dielectric layer 270. The secondmetallic layer 260 can be fabricated using a material identical to the metallic layer used for forming the gate in the aforementioned embodiment. For example, the secondmetallic layer 260 is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof. - As shown in
FIG. 2E andFIG. 2F , a planarization process is performed to the secondmetallic layer 260. In particular, after the planarization process is carried out to expose the secondpatterned dielectric layer 270 over thesemiconductor layer 250, the planarization process is still performed to remove the secondmetallic layer 260 and the secondpatterned dielectric layer 270 over thesemiconductor layer 250 until the secondpatterned dielectric layer 270 at the two sides of the resulted structure ofFIG. 2F is exposed. That is, the planarization process completely removes the secondmetallic layer 260 above the secondpatterned dielectric layer 270, and the secondmetallic layer 260 which does not located above the secondpatterned dielectric layer 270 is remained. The planarization process includes a chemical-mechanical polishing operation, for example. After the planarization process, the remained secondmetallic layer 260 serves as asource 262 and adrain 264. Hence, athin film transistor 290 is formed. After forming thesource 262 and thedrain 264, the secondpatterned dielectric layer 270 can be optionally removed. Thereafter, a passivation layer (not shown) is formed over thethin film transistor 290. -
FIGS. 3A through 3F are schematic cross-sectional views showing the steps for fabricating a thin film transistor according to another embodiment of the present invention. First, as shown inFIG. 3A , agate 320 is formed over asubstrate 300. The method of forming thegate 320 includes performing a photolithographic and etching process, for example. It should be noted that an optional stress-buffering layer 110 for buffering thesubstrate 100 against stress might be formed on thesubstrate 100 before forming thegate 320. Thus, thesubstrate 100 is prevented from forming cracks or defects in the process of forming the thin film transistor. This stress-buffering layer 310 can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a combination thereof, for example. - As shown in
FIG. 3B , agate insulating layer 330 is formed over thesubstrate 300 to cover thegate 320. - As shown in
FIG. 3C , asemiconductor layer 340 is formed over thegate insulating layer 330 above thegate 320. Thesemiconductor layer 340 comprises achannel layer 342 and anohmic contact layer 344. In the present embodiment, the gate insulating layer is fabricated using silicon oxide, silicon nitride or silicon oxynitride, for example. Thechannel layer 342 is fabricated using amorphous silicon and theohmic contact layer 344 is fabricated using n+ doped amorphous silicon, for example. - As shown in
FIG. 3D , a patterneddielectric layer 350 is formed over thesemiconductor layer 340. In one embodiment, the method of forming the patterneddielectric layer 350 includes depositing a dielectric layer (not shown) and then patterning the dielectric layer (not shown) by a photolithographic and etching process to form the patterneddielectric layer 350. The patterneddielectric layer 350 covers only a portion of thesemiconductor layer 340. A portion of thesemiconductor layer 340 is exposed. - As shown in
FIG. 3E , ametallic layer 360 is formed over the patterneddielectric layer 350. Themetallic layer 360 is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof, for example. - As shown in
FIG. 3E andFIG. 3F , a planarization process is performed to themetallic layer 360. In particular, after the planarization process is carried out to expose the patterneddielectric layer 350 over thesemiconductor layer 340, the planarization process is still performed to remove themetallic layer 360 and the patterneddielectric layer 350 over thesemiconductor layer 340 until the patterneddielectric layer 350 at the two sides of the resulted structure ofFIG. 3F is exposed. That is, the planarization process completely removes themetallic layer 360 above the patterneddielectric layer 350, and themetallic layer 360 which does not located above the patterneddielectric layer 350 is remained. The planarization process includes, for example, a chemical-mechanical polishing operation. After the planarization, the remained metallic layer constitutes asource 362 and adrain 364. Thus, athin film transistor 390 is formed. After forming thesource 362 and thedrain 364, the patterneddielectric layer 350 is optionally removed. Thereafter, a passivation layer (not shown) is formed over thethin film transistor 390. -
FIG. 4 is a schematic cross-sectional view of a liquid crystal display according to one embodiment of the present invention. The method of forming aliquid crystal display 450 according to the present invention includes forming a thin filmtransistor array layer 410 over afirst substrate 400. The thin filmtransistor array layer 410 comprises a plurality of thin film transistors (not shown) and a plurality of pixel electrodes (not shown). The thin film transistors in the thin filmtransistor array layer 410 is formed using the aforementioned damascene process (inFIGS. 1A˜1D orFIGS. 2A˜2F orFIGS. 3A˜3F ). After forming the thin film transistors, the pixel electrodes are defined and each pixel electrode is electrically connected to a corresponding thin film transistor. - Thereafter, a
second substrate 440 is provided. Thesecond substrate 440 has acolor filter layer 430 thereon, for example. Then, aliquid crystal layer 420 is formed between thefirst substrate 400 and thesecond substrate 440 to form a thin film transistorliquid crystal display 450. Here, any conventional methods can be used to form thecolor filter layer 430 on thesecond substrate 440 and theliquid crystal layer 420 between the twosubstrates - In summary, the method of fabricating the thin film transistor of a thin film transistor liquid crystal display according to the present invention includes using a damascene process to form the electrodes of the transistor. Consequently, more choices of materials are available for forming the electrodes of the thin film transistors. Furthermore, if a material having a lower resistance such as copper is used as the electrode material for the thin film transistors, the electrical performance of the thin film transistor and the liquid crystal display using such thin film transistor will improve.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (19)
1. A method of fabricating a thin film transistor comprising the steps of:
providing a substrate;
forming a first patterned dielectric layer having at least one first opening over the substrate;
forming a first metallic layer cover the first patterned dielectric layer and the first opening;
performing a chemical-mechanical polishing operation to planarize the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate;
forming a gate insulating layer over the first patterned dielectric layer and the gate;
forming a semiconductor layer over the gate insulating layer above the gate; and
forming a source and a drain over the semiconductor layer.
2. The method of claim 1 , wherein the material constituting the first metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
3. The method of claim 1 , wherein the step of forming the source and the drain over the semiconductor layer comprises:
forming a second patterned dielectric layer over the gate insulating layer;
forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; and
performing a planarization process to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form the source and the drain in the second opening.
4. The method of claim 3 , wherein the planarization process includes a chemical-mechanical polishing operation.
5. The method of claim 3 , wherein the material constituting the second metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
6. The method of claim 3 , further comprising removing the second patterned dielectric layer after forming the source and the drain.
7. The method of claim 1 , further comprising forming a stress-buffering layer over the substrate before forming the first patterned dielectric layer over the substrate.
8. The method of claim 7 , wherein the material constituting the stress-buffering layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a combination thereof.
9. The method of claim 1 , wherein the semiconductor layer comprises a channel layer and an ohmic contact layer.
10. A method of fabricating a thin film transistor, comprising:
providing a substrate;
forming a first patterned dielectric layer having at least one first opening over the substrate;
forming a first metallic layer cover the first patterned dielectric layer and the first opening;
performing a first chemical-mechanical polishing operation to planarize the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate;
forming a gate insulating layer over the substrate to cover the gate;
forming a semiconductor layer over the gate insulating layer above the gate;
forming a second patterned dielectric layer over the gate insulating layer;
forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; and
performing a second chemical-mechanical polishing operation to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form a source and a drain in the second opening.
11. The method of claim 10 , wherein the material constituting the metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
12. The method of claim 10 , further comprising forming a stress-buffering layer over the substrate before forming the gate over the substrate.
13. The method of claim 12 , wherein the material constituting the stress-buffering layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a combination thereof.
14. The method of claim 10 , wherein the semiconductor layer comprises a channel layer and an ohmic contact layer.
15. A method of fabricating a liquid crystal display, comprising the steps of:
providing a first substrate;
forming a thin film transistor array layer over the first substrate, wherein the thin film transistor array layer comprises a plurality of thin film transistors and a plurality of pixel electrodes, each thin film transistor having a gate, a source and a drain, and the method of forming the gate comprising:
forming a first patterned dielectric layer having at least one first opening over the first substrate;
forming a first metallic layer cover the first patterned dielectric layer and the first opening;
performing a first chemical-mechanical polishing operation to planarize the first metallic layer until the first patterned dielectric layer is exposed, wherein the remained first metallic layer is formed in the first opening and serves as a gate;
providing a second substrate; and
forming a liquid crystal layer between the first substrate and the second substrate.
16. The method of claim 15 , wherein the material constituting the first metallic layer is selected from the group consisting of copper, tungsten, chromium, aluminum and a combination thereof.
17. The method of claim 15 , wherein the second substrate further comprises a color filter layer disposed thereon.
18. The method of claim 15 , wherein the method of forming the source and the drain comprises:
forming a second patterned dielectric layer over the gate insulating layer;
forming a second metallic layer over the second patterned dielectric layer having a plurality of second openings; and
performing a planarization process to remove a portion of the second metallic layer and a portion of the second patterned dielectric layer so as to form the source and the drain in the second opening.
19. The method of claim 18 , wherein the planarization process includes a chemical-mechanical polishing operation.
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US12/204,103 US20080318354A1 (en) | 2005-02-16 | 2008-09-04 | Method of fabricating thin film transistor and method of fabricating liquid crystal display |
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TW094139059A TWI326790B (en) | 2005-02-16 | 2005-11-08 | Method of fabricating a thin film transistor of a thin film transistor liquid crystal display and method of fabricating a transistor liquid crystal display |
TW94139059 | 2005-11-08 | ||
US11/357,812 US7528019B2 (en) | 2005-02-16 | 2006-02-16 | Method of fabricating thin film transistor of thin film transistor liquid crystal display and method of fabricating liquid crystal display |
US12/204,103 US20080318354A1 (en) | 2005-02-16 | 2008-09-04 | Method of fabricating thin film transistor and method of fabricating liquid crystal display |
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US11/357,812 Continuation US7528019B2 (en) | 2005-02-16 | 2006-02-16 | Method of fabricating thin film transistor of thin film transistor liquid crystal display and method of fabricating liquid crystal display |
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US12/204,103 Abandoned US20080318354A1 (en) | 2005-02-16 | 2008-09-04 | Method of fabricating thin film transistor and method of fabricating liquid crystal display |
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KR101111995B1 (en) * | 2003-12-02 | 2012-03-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Thin film transistor, display device and liquid crystal display device and method for manufacturing the same |
TWI326790B (en) * | 2005-02-16 | 2010-07-01 | Au Optronics Corp | Method of fabricating a thin film transistor of a thin film transistor liquid crystal display and method of fabricating a transistor liquid crystal display |
WO2013156085A1 (en) * | 2012-04-20 | 2013-10-24 | Hewlett-Packard Development Company, L.P. | Method of manufacturing a semiconductor device |
KR20150137214A (en) * | 2014-05-28 | 2015-12-09 | 삼성디스플레이 주식회사 | Organic light-emitting display apparatus and manufacturing the same |
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US7528019B2 (en) | 2009-05-05 |
TW200630726A (en) | 2006-09-01 |
TWI326790B (en) | 2010-07-01 |
US20060183645A1 (en) | 2006-08-17 |
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