US20080293223A1 - Method for Manufacturing Strained Silicon - Google Patents
Method for Manufacturing Strained Silicon Download PDFInfo
- Publication number
- US20080293223A1 US20080293223A1 US12/185,167 US18516708A US2008293223A1 US 20080293223 A1 US20080293223 A1 US 20080293223A1 US 18516708 A US18516708 A US 18516708A US 2008293223 A1 US2008293223 A1 US 2008293223A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- silicon
- induced
- layer
- epi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
Definitions
- This invention relates generally to semiconductor manufacturing, and more particularly to a method for manufacturing strained silicon.
- Silicon is used to manufacture a variety of semiconductors.
- the speed at which these semiconductors work ultimately depends on the rate at which the transistors in the semiconductors can switch on and off, which in turns depends on the speed at which current can flow through the transistors, and the distance the charge has to travel.
- One way of reducing this distance is to deform the lattice of the silicon used to manufacture the semiconductors, resulting in a sort of “strained silicon.”
- strained silicon By stretching the lattice of the silicon, the energies of the orbitals of the silicon in the direction of the tension are lowered, allowing electrons to flow more easily along the aligned orbitals.
- putting the silicon lattice into compression raises the energies of the aligned orbitals, allowing positive charges to flow more easily.
- the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while the silicon wafer is under the induced curvature, and releasing the silicon wafer from the induced curvature, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.
- a technical advantage of some embodiments of the present invention includes the provision of a simple and economical approach to manufacturing strained silicon. Using simple mechanical processes and traditional deposition techniques, particular embodiments may provide an efficient, high-yield method of manufacturing strained silicon.
- Another technical advantage of some embodiments of the present invention includes the ability to manufacture strained silicon without introducing an excessive number of defects to the silicon lattice of the epi-layer. Rather than growing the epi-layer in a strained state (either compressive or tensile), which could introduce defects into the lattice of the epi-layer, particular embodiments of the present invention instead mechanically introduce a stress (compressive or tensile) to the epi-layer following deposition of the epi-layer. This allows the silicon to be deposited on the wafer in an optimum state using traditional deposition techniques and may reduce the number of defects formed within the lattice of the epi-layer.
- FIG. 1A illustrates a cross-sectional view of a strained silicon manufacturing system in accordance with a particular embodiment of the present invention
- FIG. 1B illustrates later cross-sectional view of the manufacturing system shown in FIG. 1A ;
- FIG. 1C illustrates an even later cross-sectional view of the manufacturing system shown in FIGS. 1A and 1B ;
- FIG. 2A illustrates a cross-sectional view of another strained silicon manufacturing system in accordance with a particular embodiment of the present invention
- FIG. 2B illustrates a later cross-sectional view of the manufacturing system shown in FIG. 2A ;
- FIG. 2C illustrates an even later cross-sectional view of the manufacturing system shown in FIGS. 2A and 2B ;
- FIG. 3 illustrates a flowchart of a method of manufacturing strained silicon in accordance with a particular embodiment of the present invention.
- FIGS. 1A-C illustrate strained silicon manufacturing system 100 , which may be used to manufacture strained silicon by introducing a stress into a silicon wafer, depositing an epitaxial layer of silicon upon the silicon wafer, and removing the stress from the silicon wafer such that a strain is induced in the epitaxial layer.
- strained silicon manufacturing system 100 offers an economical and efficient way to manufacture strained silicon epi-wafers.
- manufacturing system 100 comprises plenum 102 and vacuum chuck 104 , which may be used induce and maintain a stress in silicon wafer 106 .
- plenum 102 is a generally cylindrical pedestal having an upper surface that is convex. Of course, other shapes of pedestals may used in accordance with the teachings of the present invention. Nevertheless, when vacuum chuck 104 holds wafer 106 against this convex upper surface, the upper surface of wafer 106 is subjected to a tensile stress. After epi-layer 108 is deposited on the upper surface of wafer 106 and wafer 106 is released by vacuum chuck 104 , the tensile stress on wafer 206 is then removed.
- a tensile stress is first induced in the upper surface of wafer 106 by forcing the wafer against the convex surface of plenum 102 using vacuum chuck 104 . This may be done by placing wafer 106 on plenum 102 and holding it in place with a vacuum or over pressure. Once the under side of wafer 106 is flush with plenum 102 , vacuum chuck 104 may be used to secure wafer 106 in this strained position, alleviating or eliminating further need for the vacuum or over pressure.
- epi-layer 108 is then deposited upon wafer 106 , as shown in FIG. 1B . So deposited, epi-layer 108 may grow in a generally unstrained state. This reduces the number of defects induced in the epi-layer, and allows traditional methods of epi-layer deposition to be used in accordance with the teachings of the present invention.
- the strained induced in wafer may be removed by releasing vacuum chuck 104 . This is shown in FIG. 1C . As vacuum chuck 104 releases wafer 106 from its tensile state, the wafer is free to return to a unstrained state. In doing so, the atoms in the lattice of epi-layer 108 are forced together as the wafer returns to its original state, placing epi-layer 108 under a uniform compressive strain.
- the amount of the compressive stress induced in the epi-layer is related to the curvature induced in the silicon wafer during the manufacturing process.
- the relationship between the stress introduced into the silicon, ⁇ , and the curvature induced into the wafer (as measured from the wafer center to the datum), ⁇ , may be determined from Stoney's Equation:
- t S is the thickness of the wafer
- t f is the thickness of the silicon film to be deposited
- (E/(1 ⁇ v)) S is the stiffness of the wafer.
- one inch of center bow may be induced in an eight-inch wafer having a standard thickness of 0.020 inch.
- other embodiments of the present invention may induce other amounts of desired stress, including that resulting from two to three inches of center bow in a similar wafer.
- the amount of curvature that may be induced in the wafer will depend on the thickness of the wafer. Generally, thicker wafers may be subjected to lesser amounts of curvature before an excessive amount of defects are induced in the wafer, while thinner wafers may be subjected to greater amounts of curvature before excessive defects develop.
- a wafer may be bent without damaging the wafer itself
- another consideration is the number of defects that are introduced into the epi-layer when the wafer is allowed to return to an unstrained state.
- greater levels of strain (compression or tension) induced in the epi-layer result in faster electron transport.
- greater levels of strain may result in defects being introduced to the lattice of the epi-layer.
- One of ordinary skill in the art should be able to recognize the tradeoffs between greater levels of strain and greater numbers of defects induced in the epi-layer, and select a suitable level of strain to induce in the silicon.
- FIGS. 1A-C illustrate a system and method for manufacturing strained silicon having a compressive strain bias
- FIGS. 2A-C illustrate a system and method for manufacturing strained silicon having a compressive strain bias
- FIGS. 2A-C illustrate a system and method for manufacturing strained silicon having a compressive strain bias
- FIGS. 2A-C illustrate strained silicon manufacturing system 200 .
- manufacturing system 200 comprises plenum 202 and vacuum chuck 204 .
- plenum 202 is a generally cylindrical pedestal having an upper surface that is concave (as opposed to the convex upper surface of plenum 102 ), although other pedestal shapes may used in accordance with the teachings of the present invention.
- vacuum chuck 204 holds wafer 206 against this concave upper surface, the upper surface of wafer 206 is subjected to a compressive stress.
- a compressive stress is first induced in wafer 206 . This is accomplished by forcing wafer 206 against the concave surface of plenum 202 using vacuum chuck 204 .
- vacuum chuck 204 In order to ensure that wafer 206 is held flush against plenum 202 , particular embodiments of the present invention employ a vacuum on the under side (plenum side) of wafer 206 to hold the wafer in place against the plenum. Similarly, an over pressure on the upper side (chuck side) of wafer 206 could also be used to hold the wafer in place against the plenum.
- vacuum chuck 204 may be used to secure wafer 206 in this strained position, alleviating or eliminating further need for the vacuum or over pressure.
- epi-layer 208 is then deposited upon wafer 206 , as shown in FIG. 2B . So deposited, epi-layer 208 may grow in a generally unstrained state. This reduces the number of defects induced in the epi-layer, and allows traditional methods of epi-layer deposition to be used in accordance with the teachings of the present invention.
- the wafer is then released by vacuum chuck 204 , as shown in FIG. 2C .
- Releasing wafer 206 allows the wafer to return to its natural, unstrained state.
- the compressive strain induced in the wafer is at least partially transferred to epi-layer 208 in the form of a tensile strain. Similar to an epi-layer under a compressive strain, this tensile strain also helps increase the rate of electron transport through the lattice of the epi-layer.
- FIG. 3 a flowchart of a method for manufacturing strained silicon in accordance with the teachings of the present invention is illustrated in FIG. 3 .
- flowchart 300 begins in block 301 .
- a strain is induced in a silicon wafer. As discussed above this may be accomplished by inducing a curvature in the wafer using a plenum and vacuum chuck or other suitable techniques.
- an epi-layer of silicon is deposited on the upper surface of the wafer in block 303 . In this stage, the epi-layer is deposited in a generally unstrained state. After the deposition of the epi-layer, however, the wafer is released in block 304 .
- the wafer may return to its natural, unstrained state.
- an opposite strain is induced in the silicon lattice of the epi-layer on the upper surface of the wafer. This strain in the epi-layer allows for faster electron transport through the lattice of the epi-layer. After this strain has been induced in the epi-layer, the process terminates in block 305 .
- particular embodiments of the present invention may offer numerous technical advantages. For example, particular embodiments of the present invention offer an simple and economical approach to manufacturing strained silicon. Using simple mechanical processes and traditional deposition techniques, particular embodiments may provide an efficient method of manufacturing strained silicon.
- Particular embodiments of the present invention may also offer the ability to manufacture strained silicon without introducing an excessive number of defects to the silicon lattice of the epi-layer.
- particular embodiments of the present invention instead mechanically introduce a stress (compressive or tensile) to the epi-layer following deposition of the epi-layer. This allows the silicon to be deposited on the wafer in an optimum state using traditional deposition techniques and may reduce the number of defects formed within the lattice of the epi-layer.
Abstract
In accordance with a particular embodiment of the present invention, a method for manufacturing strained silicon is provided. In one embodiment, the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while the silicon wafer is under the induced curvature, and releasing the silicon wafer from the induced curvature, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.
Description
- This invention relates generally to semiconductor manufacturing, and more particularly to a method for manufacturing strained silicon.
- Silicon is used to manufacture a variety of semiconductors. The speed at which these semiconductors work ultimately depends on the rate at which the transistors in the semiconductors can switch on and off, which in turns depends on the speed at which current can flow through the transistors, and the distance the charge has to travel. One way of reducing this distance is to deform the lattice of the silicon used to manufacture the semiconductors, resulting in a sort of “strained silicon.” By stretching the lattice of the silicon, the energies of the orbitals of the silicon in the direction of the tension are lowered, allowing electrons to flow more easily along the aligned orbitals. Similarly, putting the silicon lattice into compression raises the energies of the aligned orbitals, allowing positive charges to flow more easily.
- In accordance with the teachings of the present invention, a method for manufacturing strained silicon is provided. In one embodiment, the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while the silicon wafer is under the induced curvature, and releasing the silicon wafer from the induced curvature, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.
- A technical advantage of some embodiments of the present invention includes the provision of a simple and economical approach to manufacturing strained silicon. Using simple mechanical processes and traditional deposition techniques, particular embodiments may provide an efficient, high-yield method of manufacturing strained silicon.
- Another technical advantage of some embodiments of the present invention includes the ability to manufacture strained silicon without introducing an excessive number of defects to the silicon lattice of the epi-layer. Rather than growing the epi-layer in a strained state (either compressive or tensile), which could introduce defects into the lattice of the epi-layer, particular embodiments of the present invention instead mechanically introduce a stress (compressive or tensile) to the epi-layer following deposition of the epi-layer. This allows the silicon to be deposited on the wafer in an optimum state using traditional deposition techniques and may reduce the number of defects formed within the lattice of the epi-layer.
- Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims. Moreover, while specific advantages have been enumerated above, various embodiments of the present invention may include some, all, or none of the enumerated technical advantages.
- For a more complete understanding of particular embodiments of the present invention and features and advantages thereof, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:
-
FIG. 1A illustrates a cross-sectional view of a strained silicon manufacturing system in accordance with a particular embodiment of the present invention; -
FIG. 1B illustrates later cross-sectional view of the manufacturing system shown inFIG. 1A ; -
FIG. 1C illustrates an even later cross-sectional view of the manufacturing system shown inFIGS. 1A and 1B ; -
FIG. 2A illustrates a cross-sectional view of another strained silicon manufacturing system in accordance with a particular embodiment of the present invention; -
FIG. 2B illustrates a later cross-sectional view of the manufacturing system shown inFIG. 2A ; -
FIG. 2C illustrates an even later cross-sectional view of the manufacturing system shown inFIGS. 2A and 2B ; and -
FIG. 3 illustrates a flowchart of a method of manufacturing strained silicon in accordance with a particular embodiment of the present invention. - In accordance with a particular embodiment of the present invention,
FIGS. 1A-C illustrate strainedsilicon manufacturing system 100, which may be used to manufacture strained silicon by introducing a stress into a silicon wafer, depositing an epitaxial layer of silicon upon the silicon wafer, and removing the stress from the silicon wafer such that a strain is induced in the epitaxial layer. By mechanically inducing a strain in the epitaxial layer, or epi-layer, after its deposition, strainedsilicon manufacturing system 100 offers an economical and efficient way to manufacture strained silicon epi-wafers. - As shown in
FIG. 1A-C ,manufacturing system 100 comprisesplenum 102 andvacuum chuck 104, which may be used induce and maintain a stress insilicon wafer 106. As shown inFIGS. 1A-C ,plenum 102 is a generally cylindrical pedestal having an upper surface that is convex. Of course, other shapes of pedestals may used in accordance with the teachings of the present invention. Nevertheless, whenvacuum chuck 104 holdswafer 106 against this convex upper surface, the upper surface ofwafer 106 is subjected to a tensile stress. After epi-layer 108 is deposited on the upper surface ofwafer 106 andwafer 106 is released byvacuum chuck 104, the tensile stress onwafer 206 is then removed. Removing this stress allowswafer 106 to return to an unstrained state. However, aswafer 106 returns to an unstrained state, the silicon atoms of epi-layer 108 are forced closer together, placing the silicon lattice of epi-layer 108 into uniform compression. A better understanding of this process may be had by referring toFIGS. 1A-C in sequence. - In
FIG. 1A , a tensile stress is first induced in the upper surface ofwafer 106 by forcing the wafer against the convex surface ofplenum 102 usingvacuum chuck 104. This may be done by placingwafer 106 onplenum 102 and holding it in place with a vacuum or over pressure. Once the under side ofwafer 106 is flush withplenum 102,vacuum chuck 104 may be used to securewafer 106 in this strained position, alleviating or eliminating further need for the vacuum or over pressure. - With
wafer 106 securely held in a tensile state, epi-layer 108 is then deposited uponwafer 106, as shown inFIG. 1B . So deposited, epi-layer 108 may grow in a generally unstrained state. This reduces the number of defects induced in the epi-layer, and allows traditional methods of epi-layer deposition to be used in accordance with the teachings of the present invention. - After epi-
layer 108 has been deposited onwafer 106, the strained induced in wafer may be removed by releasingvacuum chuck 104. This is shown inFIG. 1C . Asvacuum chuck 104 releases wafer 106 from its tensile state, the wafer is free to return to a unstrained state. In doing so, the atoms in the lattice of epi-layer 108 are forced together as the wafer returns to its original state, placing epi-layer 108 under a uniform compressive strain. - Generally, the amount of the compressive stress induced in the epi-layer is related to the curvature induced in the silicon wafer during the manufacturing process. The relationship between the stress introduced into the silicon, σ, and the curvature induced into the wafer (as measured from the wafer center to the datum), Δδ, may be determined from Stoney's Equation:
-
- where r is the radius of the wafer, tS is the thickness of the wafer, tf is the thickness of the silicon film to be deposited, and (E/(1−v))S is the stiffness of the wafer.
- In particular embodiments of the present invention, one inch of center bow may be induced in an eight-inch wafer having a standard thickness of 0.020 inch. However, other embodiments of the present invention may induce other amounts of desired stress, including that resulting from two to three inches of center bow in a similar wafer. Of course, as would be understood by one of ordinary skill in the art, the amount of curvature that may be induced in the wafer will depend on the thickness of the wafer. Generally, thicker wafers may be subjected to lesser amounts of curvature before an excessive amount of defects are induced in the wafer, while thinner wafers may be subjected to greater amounts of curvature before excessive defects develop. Furthermore, although a wafer may be bent without damaging the wafer itself, another consideration is the number of defects that are introduced into the epi-layer when the wafer is allowed to return to an unstrained state. Generally, greater levels of strain (compression or tension) induced in the epi-layer result in faster electron transport. However, greater levels of strain may result in defects being introduced to the lattice of the epi-layer. One of ordinary skill in the art should be able to recognize the tradeoffs between greater levels of strain and greater numbers of defects induced in the epi-layer, and select a suitable level of strain to induce in the silicon.
- Although
FIGS. 1A-C illustrate a system and method for manufacturing strained silicon having a compressive strain bias, other embodiments of the present invention could also be used to produce a tensile strain bias in the resulting strained silicon. An example of such an embodiment is illustrated inFIGS. 2A-C . -
FIGS. 2A-C illustrate strainedsilicon manufacturing system 200. Similar tosystem 100 shown, inFIGS. 1A-C ,manufacturing system 200 comprisesplenum 202 andvacuum chuck 204. Unlikeplenum 102 illustrated inFIGS. 1A-C ,plenum 202 is a generally cylindrical pedestal having an upper surface that is concave (as opposed to the convex upper surface of plenum 102), although other pedestal shapes may used in accordance with the teachings of the present invention. Whenvacuum chuck 204 holdswafer 206 against this concave upper surface, the upper surface ofwafer 206 is subjected to a compressive stress. After epi-layer 208 is deposited on the upper surface ofwafer 206 andwafer 206 is released byvacuum chuck 204, the compressive stress onwafer 206 is removed. Removing this compressive stress allowswafer 206 to return to its natural, unstrained state. However, in doing so, epi-layer 208 is put into a tensile state, straining the silicon lattice of the epi-layer. A better understanding of this process is available by looking atFIGS. 2A-C in sequence. - As shown in
FIG. 2A , a compressive stress is first induced inwafer 206. This is accomplished by forcingwafer 206 against the concave surface ofplenum 202 usingvacuum chuck 204. In order to ensure thatwafer 206 is held flush againstplenum 202, particular embodiments of the present invention employ a vacuum on the under side (plenum side) ofwafer 206 to hold the wafer in place against the plenum. Similarly, an over pressure on the upper side (chuck side) ofwafer 206 could also be used to hold the wafer in place against the plenum. Once the under side ofwafer 206 is flush withplenum 202,vacuum chuck 204 may be used to securewafer 206 in this strained position, alleviating or eliminating further need for the vacuum or over pressure. - With
wafer 206 securely held in a compressive state, epi-layer 208 is then deposited uponwafer 206, as shown inFIG. 2B . So deposited, epi-layer 208 may grow in a generally unstrained state. This reduces the number of defects induced in the epi-layer, and allows traditional methods of epi-layer deposition to be used in accordance with the teachings of the present invention. - Once epi-
layer 208 has been deposited onwafer 206, the wafer is then released byvacuum chuck 204, as shown inFIG. 2C . Releasingwafer 206 allows the wafer to return to its natural, unstrained state. Aswafer 206 returns to an unstrained state, the compressive strain induced in the wafer is at least partially transferred to epi-layer 208 in the form of a tensile strain. Similar to an epi-layer under a compressive strain, this tensile strain also helps increase the rate of electron transport through the lattice of the epi-layer. - Of course, while specific structures and equipment have been described in the foregoing description, it should be understood that other structures may be used to induce a stress or curvature in a silicon wafer in accordance with the teachings of the present invention. With the benefit of the present disclosure, one of ordinary skill art should be able to select a suitable apparatus for inducing such a stress or curvature.
- With that understanding, a flowchart of a method for manufacturing strained silicon in accordance with the teachings of the present invention is illustrated in
FIG. 3 . As shown inFIG. 3 , flowchart 300 begins inblock 301. Atblock 302, a strain is induced in a silicon wafer. As discussed above this may be accomplished by inducing a curvature in the wafer using a plenum and vacuum chuck or other suitable techniques. After the wafer is secured in a strained positioned, an epi-layer of silicon is deposited on the upper surface of the wafer inblock 303. In this stage, the epi-layer is deposited in a generally unstrained state. After the deposition of the epi-layer, however, the wafer is released inblock 304. Without anything maintaining the curvature of the wafer, the wafer may return to its natural, unstrained state. As the strain is removed from the wafer, an opposite strain is induced in the silicon lattice of the epi-layer on the upper surface of the wafer. This strain in the epi-layer allows for faster electron transport through the lattice of the epi-layer. After this strain has been induced in the epi-layer, the process terminates inblock 305. - By mechanically inducing a strain in a silicon wafer prior to the deposition of an epi-layer of silicon, particular embodiments of the present invention may offer numerous technical advantages. For example, particular embodiments of the present invention offer an simple and economical approach to manufacturing strained silicon. Using simple mechanical processes and traditional deposition techniques, particular embodiments may provide an efficient method of manufacturing strained silicon.
- Particular embodiments of the present invention may also offer the ability to manufacture strained silicon without introducing an excessive number of defects to the silicon lattice of the epi-layer. Rather than growing the epi-layer in a strained state (either compressive or tensile), which could introduce defects into the lattice of the epi-layer, particular embodiments of the present invention instead mechanically introduce a stress (compressive or tensile) to the epi-layer following deposition of the epi-layer. This allows the silicon to be deposited on the wafer in an optimum state using traditional deposition techniques and may reduce the number of defects formed within the lattice of the epi-layer.
- Although particular embodiments of the method and apparatus of the present invention have been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.
Claims (15)
1-5. (canceled)
6. A method for manufacturing strained silicon, comprising:
inducing a curvature in a silicon wafer;
depositing an epitaxial layer of silicon upon an upper surface of the silicon water while the silicon wafer is under the induced curvature; and
releasing the silicon wafer from the induced curvature, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.
7. The method of claim 6 , wherein the strain is compressive.
8. The method of claim 6 , wherein the strain is tensile.
9. The method of claim 6 , wherein the strain induced in the epitaxial layer is related to the curvature induced in the silicon wafer by Stoney's Equation.
10. The method of claim 6 , wherein inducing a curvature in a silicon wafer comprises bending the silicon wafer between a plenum and a vacuum chuck.
11. The method of claim 10 , wherein the plenum has a convex upper surface.
12. The method of claim 10 , wherein the plenum has a concave upper surface.
13. A method for manufacturing strained silicon, comprising:
inducing a stress into a silicon wafer;
depositing an epitaxial layer of silicon upon an upper surface of the silicon wafer while the silicon wafer is under the induced stress; and
removing the induced stress from the silicon wafer, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.
14. The method of claim 13 , wherein the strain is compressive.
15. The method of claim 13 , wherein the strain is tensile.
16. The method of claim 13 , wherein introducing a stress comprises inducing a curvature in the silicon wafer.
17. The method of claim 16 , wherein the strain induced in the epitaxial layer is related to the curvature induced in the silicon wafer by Stoney's Equation.
18. The method of claim 16 , wherein the curvature is induced by bending the silicon wafer between a plenum and a vacuum chuck.
19-20. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/185,167 US20080293223A1 (en) | 2004-12-30 | 2008-08-04 | Method for Manufacturing Strained Silicon |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/027,512 US7410888B2 (en) | 2004-12-30 | 2004-12-30 | Method for manufacturing strained silicon |
US12/185,167 US20080293223A1 (en) | 2004-12-30 | 2008-08-04 | Method for Manufacturing Strained Silicon |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/027,512 Division US7410888B2 (en) | 2004-12-30 | 2004-12-30 | Method for manufacturing strained silicon |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080293223A1 true US20080293223A1 (en) | 2008-11-27 |
Family
ID=36641084
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/027,512 Active 2025-02-14 US7410888B2 (en) | 2004-12-30 | 2004-12-30 | Method for manufacturing strained silicon |
US12/185,167 Abandoned US20080293223A1 (en) | 2004-12-30 | 2008-08-04 | Method for Manufacturing Strained Silicon |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/027,512 Active 2025-02-14 US7410888B2 (en) | 2004-12-30 | 2004-12-30 | Method for manufacturing strained silicon |
Country Status (1)
Country | Link |
---|---|
US (2) | US7410888B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7410888B2 (en) * | 2004-12-30 | 2008-08-12 | Texas Instruments Incorporated | Method for manufacturing strained silicon |
US8691663B2 (en) * | 2009-11-06 | 2014-04-08 | Alliance For Sustainable Energy, Llc | Methods of manipulating stressed epistructures |
DE102012204853A1 (en) * | 2012-03-27 | 2013-10-02 | Siemens Aktiengesellschaft | Method for producing a thin film on a substrate |
US11894245B2 (en) * | 2020-04-29 | 2024-02-06 | Semiconductor Components Industries, Llc | Non-planar semiconductor packaging systems and related methods |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3808674A (en) * | 1972-08-10 | 1974-05-07 | Westinghouse Electric Corp | Epitaxial growth of thermically expandable films and particularly anisotropic ferro-electric films |
US4457359A (en) * | 1982-05-25 | 1984-07-03 | Varian Associates, Inc. | Apparatus for gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer |
US4548658A (en) * | 1985-01-30 | 1985-10-22 | Cook Melvin S | Growth of lattice-graded epilayers |
US4823607A (en) * | 1987-05-18 | 1989-04-25 | Massachusetts Institute Of Technology | Released film structures and method of measuring film properties |
US4830984A (en) * | 1987-08-19 | 1989-05-16 | Texas Instruments Incorporated | Method for heteroepitaxial growth using tensioning layer on rear substrate surface |
US5043044A (en) * | 1984-10-15 | 1991-08-27 | Nec Corporation | Monocrystalline silicon wafer |
US5562770A (en) * | 1994-11-22 | 1996-10-08 | International Business Machines Corporation | Semiconductor manufacturing process for low dislocation defects |
US5893760A (en) * | 1996-03-27 | 1999-04-13 | Kabushiki Kaisha Toshiba | Method of heat treating a semiconductor wafer to reduce stress |
US6054387A (en) * | 1996-09-13 | 2000-04-25 | Texas Instruments Incorporated | Method for forming a silicide region |
US6156623A (en) * | 1998-03-03 | 2000-12-05 | Advanced Technology Materials, Inc. | Stress control of thin films by mechanical deformation of wafer substrate |
US6500759B1 (en) * | 1998-10-05 | 2002-12-31 | Seiko Epson Corporation | Protective layer having compression stress on titanium layer in method of making a semiconductor device |
US20030017626A1 (en) * | 2001-07-23 | 2003-01-23 | Motorola Inc. | Method and apparatus for controlling propagation of dislocations in semiconductor structures and devices |
US20040018392A1 (en) * | 2002-07-26 | 2004-01-29 | Texas Instruments Incorporated | Method of increasing mechanical properties of semiconductor substrates |
US20040220057A1 (en) * | 2000-01-12 | 2004-11-04 | Teracomm Research, Inc. | Structures for increasing the critical temperature of superconductors |
US20050019967A1 (en) * | 2003-07-24 | 2005-01-27 | Ravi Kramadhati V. | Method of fabricating a microelectronic die |
US20050026332A1 (en) * | 2003-07-29 | 2005-02-03 | Fratti Roger A. | Techniques for curvature control in power transistor devices |
US20050035514A1 (en) * | 2003-08-11 | 2005-02-17 | Supercritical Systems, Inc. | Vacuum chuck apparatus and method for holding a wafer during high pressure processing |
US6884718B2 (en) * | 2003-03-18 | 2005-04-26 | Micron Technology, Inc. | Semiconductor manufacturing process and apparatus for modifying in-film stress of thin films, and product formed thereby |
US7410888B2 (en) * | 2004-12-30 | 2008-08-12 | Texas Instruments Incorporated | Method for manufacturing strained silicon |
-
2004
- 2004-12-30 US US11/027,512 patent/US7410888B2/en active Active
-
2008
- 2008-08-04 US US12/185,167 patent/US20080293223A1/en not_active Abandoned
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3808674A (en) * | 1972-08-10 | 1974-05-07 | Westinghouse Electric Corp | Epitaxial growth of thermically expandable films and particularly anisotropic ferro-electric films |
US4457359A (en) * | 1982-05-25 | 1984-07-03 | Varian Associates, Inc. | Apparatus for gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer |
US5043044A (en) * | 1984-10-15 | 1991-08-27 | Nec Corporation | Monocrystalline silicon wafer |
US4548658A (en) * | 1985-01-30 | 1985-10-22 | Cook Melvin S | Growth of lattice-graded epilayers |
US4823607A (en) * | 1987-05-18 | 1989-04-25 | Massachusetts Institute Of Technology | Released film structures and method of measuring film properties |
US4830984A (en) * | 1987-08-19 | 1989-05-16 | Texas Instruments Incorporated | Method for heteroepitaxial growth using tensioning layer on rear substrate surface |
US5562770A (en) * | 1994-11-22 | 1996-10-08 | International Business Machines Corporation | Semiconductor manufacturing process for low dislocation defects |
US5893760A (en) * | 1996-03-27 | 1999-04-13 | Kabushiki Kaisha Toshiba | Method of heat treating a semiconductor wafer to reduce stress |
US6054387A (en) * | 1996-09-13 | 2000-04-25 | Texas Instruments Incorporated | Method for forming a silicide region |
US6156623A (en) * | 1998-03-03 | 2000-12-05 | Advanced Technology Materials, Inc. | Stress control of thin films by mechanical deformation of wafer substrate |
US6500759B1 (en) * | 1998-10-05 | 2002-12-31 | Seiko Epson Corporation | Protective layer having compression stress on titanium layer in method of making a semiconductor device |
US20040220057A1 (en) * | 2000-01-12 | 2004-11-04 | Teracomm Research, Inc. | Structures for increasing the critical temperature of superconductors |
US20030017626A1 (en) * | 2001-07-23 | 2003-01-23 | Motorola Inc. | Method and apparatus for controlling propagation of dislocations in semiconductor structures and devices |
US20040018392A1 (en) * | 2002-07-26 | 2004-01-29 | Texas Instruments Incorporated | Method of increasing mechanical properties of semiconductor substrates |
US6884718B2 (en) * | 2003-03-18 | 2005-04-26 | Micron Technology, Inc. | Semiconductor manufacturing process and apparatus for modifying in-film stress of thin films, and product formed thereby |
US20050019967A1 (en) * | 2003-07-24 | 2005-01-27 | Ravi Kramadhati V. | Method of fabricating a microelectronic die |
US20050026332A1 (en) * | 2003-07-29 | 2005-02-03 | Fratti Roger A. | Techniques for curvature control in power transistor devices |
US20050035514A1 (en) * | 2003-08-11 | 2005-02-17 | Supercritical Systems, Inc. | Vacuum chuck apparatus and method for holding a wafer during high pressure processing |
US7410888B2 (en) * | 2004-12-30 | 2008-08-12 | Texas Instruments Incorporated | Method for manufacturing strained silicon |
Also Published As
Publication number | Publication date |
---|---|
US7410888B2 (en) | 2008-08-12 |
US20060148214A1 (en) | 2006-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7442993B2 (en) | Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer | |
KR100796832B1 (en) | Transfer of a thin layer from a wafer comprising a buffer layer | |
JP2694120B2 (en) | Pseudo substrate structure | |
US5413679A (en) | Method of producing a silicon membrane using a silicon alloy etch stop layer | |
US8187955B2 (en) | Graphene growth on a carbon-containing semiconductor layer | |
US7390724B2 (en) | Method and system for lattice space engineering | |
JP4602475B2 (en) | Method for transferring a layer of strained semiconductor material | |
US7067400B2 (en) | Method for preventing sidewall consumption during oxidation of SGOI islands | |
JP3870188B2 (en) | Method for forming strained silicon regions in a wafer | |
JP5026685B2 (en) | Method for producing wafer structure with strained silicon layer and intermediate product of this method | |
US20080296615A1 (en) | Fabrication of strained heterojunction structures | |
US7998835B2 (en) | Strain-direct-on-insulator (SDOI) substrate and method of forming | |
US7067430B2 (en) | Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction | |
KR20080040638A (en) | Method for producing dislocation-free strained crystalline films | |
US7001826B2 (en) | Wafer with a relaxed useful layer and method of forming the wafer | |
US20080293223A1 (en) | Method for Manufacturing Strained Silicon | |
US20060234479A1 (en) | Implantation-less approach to fabricating strained semiconductor on isolation wafers | |
US10396165B2 (en) | Thin low defect relaxed silicon germanium layers on bulk silicon substrates | |
US5506155A (en) | Method for manufacturing a substrate for semiconductor device using a selective gettering technique | |
JP4980049B2 (en) | Relaxation of thin layers after transition | |
US6589333B1 (en) | Method for the manufacture of a substrate, substrate manufactured in accordance with this method, carrier wafer and diamond jewel | |
US9865462B2 (en) | Strain relaxed buffer layers with virtually defect free regions | |
JP6333725B2 (en) | Process to smooth the surface by heat treatment | |
US9305781B1 (en) | Structure and method to form localized strain relaxed SiGe buffer layer | |
US7064037B2 (en) | Silicon-germanium virtual substrate and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |