US20080198669A1 - Method of operating non-volatile memory - Google Patents
Method of operating non-volatile memory Download PDFInfo
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- US20080198669A1 US20080198669A1 US12/107,774 US10777408A US2008198669A1 US 20080198669 A1 US20080198669 A1 US 20080198669A1 US 10777408 A US10777408 A US 10777408A US 2008198669 A1 US2008198669 A1 US 2008198669A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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Abstract
A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.
Description
- This application is a divisional of an application Ser. No. 11/161,398, filed on Aug. 2, 2005, now allowed, which claims the priority benefit of Taiwan application serial no. 94102849, filed on Jan. 31, 2005. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory and manufacturing and operating method thereof.
- 2. Description of the Related Art
- Among the various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used inside most personal computer systems and electronic equipment. In an EEPROM, data can be stored, read out or erased from the EEPROM numerous times and any stored data is retained even after power is cut off.
- Typically, the floating gate and the control gate of an EEPROM cell is fabricated using doped polysilicon. To prevent errors in reading data from an EEPROM due to over-erasing, a select gate is disposed on the sidewalls of the control gate and the floating gate above the substrate, thereby forming a split-gate structure.
- On the other hand, because doped polysilicon is used to fabricate the floating gates, any defects in the tunneling oxide layer under the floating gate can easily produce a leakage current and affect the reliability in the device.
- To resolve the current leakage problem in the EEPROM, a charge-trapping layer often replaces the conventional polysilicon floating gate of the memory. The charge- trapping layer is fabricated using silicon nitride, for example. In general, an oxide layer is formed both above and below the silicon nitride charge-trapping layer to form a stacked structure including an oxide-nitride-oxide (ONO) composite layer. Read-only memory having this type of stacked gate structure is often referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
- At present, an AND type memory array structure, constructed using split-gate memory cells with ONO structure, is disclosed in U.S. patent application US2004/0084714.
FIG. 1 is a schematic cross-sectional view of a conventional AND type memory cell structure. As shown inFIG. 1 , the memory cell has a triple-well structure composed of a p-type silicon substrate 16, an n-type well 15 and a p-type well 14. A plurality of n-type diffusion layers type well 14. A plurality ofassist electrodes gate oxide layer 18 is disposed betweenassist electrodes control electrode 5 is disposed on the substrate to serve as a word line. Asilicon oxide layer 19, asilicon nitride layer 17, and asilicon oxide layer 20 are sequentially laid between the control gate and the substrate and between thecontrol gate 5 and theassist electrodes silicon nitride layer 17 between theassist electrode 4 and its adjacent n-type diffusion layers trapping regions assist electrode 4, aninversion layer 1 is formed in the surface of the substrate under theassist electrode 4. - With the trend toward increasing the level of integration of integrated circuits and miniaturizing electronic devices, the size of the aforementioned AND type memory cell needs to be reduced. One way of shrinking the AND type memory cell is to reduce the length of the assist electrode and minimize the distance separating the n-
type diffusion layers assist electrodes assist electrodes type diffusion layers assist electrodes type diffusion layer type diffusion layers type diffusion layers - Accordingly, at least one objective of the present invention is to provide a non-volatile memory and manufacturing and operating method thereof. The non-volatile memory has no device isolation structure between various memory cell arrays and no contact and no doped region between various memory cells so that the overall level of integration of the device can be increased.
- At least a second objective of the present invention is to provide a non-volatile memory and manufacturing and operating method thereof that can be efficiently programmed to increase the operating speed of the device.
- At least a third objective of the present invention is to provide a non-volatile memory and manufacturing and operating method thereof that has simpler processing steps for reducing overall production cost.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a non-volatile memory. The non-volatile memory mainly includes a substrate, a plurality of select gates, a plurality of select gate dielectric layers, a composite layer, and a plurality of word lines. The substrate has a plurality of trenches arranging in parallel to each other and extending in a first direction. The select gates are disposed on the substrate between two adjacent trenches respectively. The select gate dielectric layers are disposed between the select gate and the substrate. The composite layer is disposed over the surface of the trenches, the composite layer includes a charge trapping layer. The word lines are disposed on the composite layer filling the, trench between adjacent, select gates. The word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.
- In the aforementioned non-volatile memory, a plurality of bit lines are formed in the substrate underneath the select gate when a voltage is applied to the select gate.
- In the aforementioned non-volatile memory, the composite layer not only covers the surface of the trenches, but also covers the surface of the select gates. The composite layer further includes a bottom dielectric layer and a top dielectric layer. The charge-trapping layer is fabricated using a material including silicon nitride or doped polysilicon. The bottom dielectric layer and the top dielectric layer are fabricated using a material including silicon oxide.
- In the aforementioned non-volatile memory, the composite layers and the word lines disposed thereon constitute a plurality of two-bits memory cells respectively.
- In the aforementioned non-volatile memory, the select gates and the word lines are fabricated using doped polysilicon.
- In the non-volatile memory of the present invention, the select gates, the word line located between two adjacent select gates, and the composite layer together form a plurality of memory cells. Because there is no gap and no device isolation structure and contact between various memory cells, the level of integration of the memory cell array can be increased. Furthermore, each composite layer on the two sidewalls of the trenches contains a single bit of data. In other words, a single memory cell in the non-volatile memory of the present invention can store two bits of data. Moreover, the two bits of data in the memory cell are physically isolated from each other by a trench. Hence, any interference between them is minimized. In addition, by controlling the depth of the trenches, the channel length can be adjusted to prevent abnormal electrical punch-through in the memory cell.
- The present invention also provides a method of operating a non-volatile memory, adapted for a memory array including an array of memory cells. Each memory cell array includes a plurality of select gate structures on a substrate, a composite layer, a plurality of control gates, a plurality of word lines, a plurality of select gate lines and a plurality of bit lines. Each select gate structure includes a select gate dielectric layer and a select gate sequentially stacked on the substrate and a trench in the substrate between neighboring select gates. The composite layer covers the substrate and the select gates. The composite layer includes a charge-trapping layer. The control gates are disposed on the composite layer, filling the trench between two adjacent select gates. The word lines are laid in the row direction parallel to each other and coupled to the control gates in the same row. The select gate lines are laid in the column direction parallel to each other and coupled to the select gates in the same column. The bit lines are laid in the column direction in parallel to each other. When a voltage is applied to the select gate line, a bit line is formed in the substrate underneath the select gate line. Two adjacent select gates, the control gate between two adjacent select gates, and the composite layer together form an array of memory cells. Furthermore, two neighboring memory cells share a common select gate line. The composite layer between the control gate of various memory cells and a first sidewall of various trenches contains a first bit, and the composite layer between the control gate of various memory cells and a second sidewall of the various trenches contains a second bit. The method of operating the non-volatile memory includes the following steps.
- To perform a programming operation, a first voltage is applied to a selected word line coupled to a selected memory cell; a second voltage is applied to a first selected select gate line adjacent to the selected memory cell on the first bit side; a third voltage is applied to a second selected select gate line next to the first selected select gate line on the first bit side so that a first selected bit line is formed in the substrate underneath the second selected select gate line; a fourth voltage is applied to the first selected bit line; a fifth voltage is applied to a third selected select gate line adjacent to the selected memory cell on the second bit side so that a second selected bit line is formed in the substrate underneath the third selected select gate line; a sixth voltage is applied to the second selected bit line; a seventh voltage is applied to a fourth selected select gate line next to the third selected select gate line on the second bit side, and a 0V to is applied the unselected select gate lines, wherein the second voltage is close to the threshold voltage of the select gate line, the fifth voltage and the third voltage is higher than the second voltage, the sixth voltage is higher than the fourth voltage, and the first voltage is higher than the second voltage so that the first bit is programmed through source side injection.
- In the aforementioned method of operating the non-volatile memory, the first voltage is about 10V, the second voltage is about 1V, the third voltage is about 5V, the fourth voltage is about 0V, the fifth voltage is about 8V, the sixth voltage is about 4.5V, and the seventh voltage is about 0V.
- In the aforementioned method of operating the non-volatile memory, the programming operation further includes the following steps. An eighth voltage is applied to the selected word line coupled to the selected memory cell; a ninth voltage is applied to the third selected select gate line adjacent to the selected memory cell on the second bit side; a tenth voltage is applied to the fourth selected select gate line next to the third selected select gate line on the second bit side so that a third selected bit line is formed in the substrate underneath the fourth selected select gate line; a eleventh voltage is applied to the third selected bit line; a twelfth voltage is applied to the first selected select gate line adjacent to the selected memory cell on the first bit side so that a fourth selected bit line is formed in the substrate underneath the first selected select gate line; a thirteenth voltage is applied to the first selected bit line; a fourteenth voltage is applied to the second selected select gate line next to the first selected select gate line on the first bit side, and a 0V is applied to the unselected select gate lines, wherein the ninth voltage is close to the threshold voltage of the select gate line, the twelfth voltage and the tenth voltage is higher than the ninth voltage, the thirteenth voltage is higher than the eleventh voltage, and the eighth voltage is higher than the ninth voltage, so that the second bit is programmed through source side injection.
- In the aforementioned method of operating the non-volatile memory, the eighth voltage is about 10V, the ninth voltage is about 1V, the tenth voltage is about 5V, the eleventh voltage is about 0V, the twelfth voltage is about 8V, the thirteenth voltage is about 4.5V, and the fourteenth voltage is about 0V.
- To perform an erasing operation according to the aforementioned method of operating the non-volatile memory, an eighth voltage is applied to the word lines; a ninth voltage is applied to the substrate and making the select gate floating so that the electrons stored in the composite layer are tunnelled into the substrate. Furthermore, the voltage differential between the eighth and the ninth voltage is high enough to trigger an FN (Fowler-Nordheim) tunneling.
- In the aforementioned method of operating the non-volatile memory, the voltage differential is between about −12 to -20V. The eighth voltage is about −15V and the ninth voltage is about 0V.
- To perform a reading operation according to the aforementioned method of operating the non-volatile memory, a eighth voltage is applied to the selected word line coupled to the selected memory cell; an ninth voltage is applied to the first selected select gate line adjacent to the selected memory cell on first bit side so that the third selected bit line is formed in the substrate underneath the first selected select gate line; a tenth voltage is applied to the third selected bit line; a eleventh voltage is applied to the third selected select gate line adjacent to the selected memory cell on the second bit side so that the second selected bit line is formed in the substrate underneath the third selected select gate line; a twelfth voltage is applied to the second selected bit line and reading out the first bit, wherein the ninth voltage and the eleventh voltage is higher than the twelfth voltage, the twelfth voltage is higher than the tenth voltage, and the eighth voltage is higher than the threshold voltage of the memory cells without trapped electrons but smaller than the threshold voltage of the memory cells containing trapping electrons.
- In the aforementioned method of operating the non-volatile memory, the eighth voltage is about 3V, the ninth voltage and the eleventh voltage are about 5V, the tenth voltage is about 0V and the twelfth voltage is about 1.5V.
- To perform a reading operation according to the aforementioned method of operating the non-volatile memory, a thirteenth voltage is applied to a selected word line coupled to the selected memory cell; an fourteenth voltage is applied to the third selected select gate line adjacent to the selected memory cell on the second bit side so that the second selected bit line is formed in the substrate underneath the third selected select gate line; a fifteenth voltage is applied to the second selected bit line; a sixteenth voltage is applied to the first selected select gate line adjacent to the selected memory cell on the first bit side so that the third selected bit line is formed in the substrate underneath the first selected select gate line; a seventeenth voltage is applied to the third selected bit line and reading out the second bit, wherein the fourteenth voltage and the sixteenth voltage are higher than the seventeenth voltage, the seventeenth voltage is higher than the fifteenth voltage, and the thirteenth voltage is higher than the threshold voltage of the memory cells without trapped electrons but smaller than the threshold voltage of the memory cells containing trapping electrons.
- In the aforementioned method of operating the non-volatile memory, the thirteenth voltage is about 3V, the fourteenth voltage and the sixteenth voltage are about 5V, the fifteenth voltage is about 0V, and the seventeenth voltage is about 1.5V.
- The method of operating a non-volatile memory according to the present invention utilizes source side injection (SSI) to program a single bit unit into a single memory cell and uses FN tunneling to erase the data in the memory cells. Hence, the electron injection efficiency is high so that the memory cell current appearing in a normal operation is low but the operating speed is high. Moreover, the lowered memory cell current effectively reduces overall power consumption in the chip.
- In addition, the control gates within the non-volatile memory of the present invention are buried in the trenches within the substrate. Since accelerated electrons are directly injected into the charge-trapping region on the sidewall of the trench, a high operating efficiency is attained. Furthermore, the two-bit storage regions within a single memory cell are effectively isolated from each other through the trench, thereby reducing interference from each other.
- The present invention also provides a method of manufacturing a non-volatile memory. First, a substrate is provided. Then, a plurality of stacked gate structures are formed on the substrate. Each stacked gate structure is separated from a neighboring one by a gap. Each stacked gate structure includes a gate dielectric layer, a first conductive layer, and a mask layer. Thereafter, using the mask layers to serve as an etching masks, a plurality of trenches are formed in the substrate The trenches are arranged in parallel to each other and extend in a first direction. After removing the mask layers, a composite layer is formed on the substrate covering the surface of the trenches. The composite layer includes a bottom dielectric layer, a charge-trapping layer, and a top dielectric layer. Then, a plurality of second conductive layers is formed on the composite layer. The second conductive layers fill the trenches. The conductive layers are arranged in parallel to each other and extend in a second direction and the second direction crosses over the first direction.
- In the aforementioned method of manufacturing the non-volatile memory, the step of forming the second conductive layer on the composite layer includes forming a conductive material layer over the substrate and then patterning the conductive material layer.
- In the aforementioned method of manufacturing the non-volatile memory, the charge-trapping layer is fabricated using silicon nitride or doped polysilicon, and the bottom and the top dielectric layer are fabricated using silicon oxide.
- In the aforementioned method of manufacturing the non-volatile memory, there is no device isolation structure between various memory cell arrays and there is no contact or doped region between various memory cells. Hence, the process of fabricating the memory is simplified and the level of integration of the memory arrays is increased.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1 is a schematic cross-sectional view of a conventional AND type memory cell structure. -
FIG. 2A is a top view of a non-volatile memory according to one embodiment of the present invention. -
FIG. 2B is a cross-sectional view along line A-A′ ofFIG. 2A . -
FIG. 2C is a cross-sectional view along line B-B′ ofFIG. 2A . -
FIG. 3 is a simplified circuit diagram of a memory array according to one embodiment of the present invention. -
FIG. 4A is a cross-sectional view of a non-volatile memory showing a programming operation according to one embodiment of the present invention. -
FIG. 4B is a cross-sectional view of a non-volatile memory showing a programming operation according to another embodiment of the present invention. -
FIG. 4C is a cross-sectional view of a non-volatile memory showing a reading operation according to one embodiment of the present invention. -
FIG. 4D is a cross-sectional view of a non-volatile memory showing a reading operation according to another embodiment of the present invention. -
FIG. 4E is a cross-sectional view of a non-volatile memory showing an erasing operation according to one embodiment of the present invention. -
FIGS. 5A through 5C are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention. - Reference now is made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
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FIG. 2A is a top view of a non-volatile memory according to one embodiment of the present invention.FIG. 2B is a cross-sectional view along line A-A′ ofFIG. 2A .FIG. 2C is a cross-sectional view along line B-B′ ofFIG. 2A . As shown inFIG. 2A , the non-volatile memory array of the present invention includes asubstrate 100, a plurality of memory cell arrays MR1˜MR5, a plurality of word lines WL1˜WL5, a plurality of select gate lines SG1˜SG6, and a plurality of bit lines BL1˜BL6. - The memory cell arrays MR1˜MR5 are arranged to form a memory array. The word lines WL1˜WL5 are coupled to the control gates respectively in the same row of memory cells. The word lines WL1˜WL5 are arranged in parallel to each other and extend in an X direction. The select gate lines SG1˜SG6 are coupled to the select gates respectively in the same row of memory cells. The select gate lines SG1˜SG6 are arranged in parallel to each other and extend in the Y direction. The X direction and the Y direction cross over each other. When a voltage is applied to the select gate lines SG1˜SG6, an inversion layer is formed in the
substrate 100 underneath the select gate lines SG1˜SG6. These inversion layers serve as bit lines BL1˜BL6. - In the following, the structure of the non-volatile memory cell array according to the present invention is described. Here, the memory cell array MR1 serves as an example in the illustration.
- As shown in
FIGS. 2A , 2B and 2C, the non-volatile memory structure in the present invention includes asubstrate 100, a plurality ofselect gates 102 a˜102 f, a plurality of select gatedielectric layers 104, acomposite layer 106, and a plurality ofcontrol gates 108 a˜108 e. - The
substrate 100 is a silicon substrate, for example. Thesubstrate 100 has a p-type well 110, for example. Furthermore, thesubstrate 100 has a plurality oftrenches 112 a˜112 e. Thesetrenches 112 a˜112 e are arranged in parallel to each other and extend in the Y direction. - The
select gates 102 a˜102 f are disposed on thesubstrate 100 between two neighboringtrenches 112 a˜112 e, and theselect gates 102 a˜102 f are fabricated using doped polysilicon, for example. - The select gate
dielectric layers 104 are disposed between theselect gates 102 a˜102 f and thesubstrate 100. The select gatedielectric layers 104 are fabricated using silicon oxide, for example. - The
composite layer 106 covers the surface of the trenches. For example, thecomposite layer 106 covers the upper surface of thesubstrate 100 and theselect gates 102 a˜102 f. Thecomposite layer 106 includes abottom dielectric layer 106 a, a charge-trapping layer 106 b, and atop dielectric layer 106 c, sequentially stacked on thesubstrate 100. Thebottom dielectric layer 106 a is fabricated using silicon oxide; the charge-trapping layer 106 b is fabricated using silicon nitride; and thetop dielectric layer 106 c is fabricated using silicon oxide, for example. Obviously, the charge-trapping layer 106 b can be fabricated using any material capable of trapping or holding charges, such as doped polysilicon. - The
control gates 108 a˜108 e are disposed on thecomposite layer 106 within thetrenches 112 a˜112 e between two neighboringselect gates 102 a˜102 f (as shown inFIG. 2B ). Thecontrol gates 108 a˜108 e are serially connected through the word line WL1. For example, thecontrol gates 108 a˜108 e and the word line WL1 are formed together as an integrated unit. In other words, thecontrol gates 108 a˜108 e extend into areas above theselect gates 102 a˜102 f and connect with each other to form the word line WL1. - When a voltage is applied to the
select gates 102 a˜102 f (the select gate lines SG1˜SG6),inversion layers 116 a˜116 f (bit lines BL1˜BL6) are formed respectively in thesubstrate 100 underneath theselect gates 102 a˜102 f (the select gate lines SG1˜SG6). The inversion layers 116 a˜116 f (the bit lines BL1˜BL6) are isolated by thetrenches 112 a˜112 e and located in thesubstrate 100 underneath theselect gates 102 a˜102 f. - Using the memory cell array MR1 as an example, two adjacent
select gates 102 a˜102 f, thecontrol gates 108 a˜108 e between two adjacentselect gates 102 a˜102 f, and thecomposite layer 106 together form a plurality of memory cells M1˜M5. For example, theselect gate 102 a, theselect gate 102 b, thecontrol gate 108 a, and thecomposite layer 106 together form the memory cell M1; theselect gate 102 b, theselect gate 102 c, thecontrol gate 108 b, and thecomposite layer 106 together form the memory cell M2, and likewise, theselect gate 102 e, theselect gate 102 f, thecontrol gate 108 e, and thecomposite layer 106 together form the memory cell M5. The memory cells M1˜M5 are serially connected together in the X direction (the row direction) without any gaps in between and adjacent memory cells M1˜M5 shareselect gates 102 a˜102 f and bit lines BL1˜BL6. For example, the memory cell M2 and the memory cell M1 share theselect gate 102 b, and the memory cell M2 and the memory cell M3 share theselect gate 102 c. - The
composite layer 106 between thecontrol gates 108 a˜108 e of various memory cells M1˜M5 and the two sidewalls ofvarious trenches 112 a˜112 e can store one bit of data. Using the memory cell M1 as an example, thecomposite layer 106 between thecontrol gate 108 a and the left sidewall of thetrench 112 a serves as a charge-trappingregion 114 a (a left bit), and thecomposite layer 106 between thecontrol gate 108 a and the right sidewall of thetrench 114 a serves as another charge-trappingregion 114 b (a right bit). Similarly, each of the memory cells M2˜M5 has two charge-trapping regions (a left bit and a right bit). Hence, each memory cell in the non-volatile memory of the present invention can store two bits of data. Since the structures of the memory cell arrays MR2˜MR5 coupled by the word lines WL2˜WL5 are identical to that of the memory cell array MR1, a detailed description of them is omitted. - In the aforementioned non-volatile memory, there are no gaps between the memory cells M2˜M5, and there is no device isolation structure or contact between the memory cell arrays. Therefore, the overall level of integration of the memory cell arrays can be increased. Furthermore, the
composite layer 106 on the two sidewalls of thetrenches 112 a˜112 e can serve as a left charge-trappingregion 114 a (a left bit) and a right charge-trappingregion 114 b (a right bit). In other words, a single memory cell in the non-volatile memory of the present invention can store two bits of data. Moreover, the left charge-trappingregion 114 a (the left bit) and the right charge-trappingregion 114 b (the right bit) are isolated from each other by the trench. Thus, interference between the left charge-trappingregion 114 a (the left bit) and the right charge-trappingregion 114 b is minimized. In addition, length of the channel in the memory cell can be adjusted by controlling the depth of thetrenches 112 a˜112 e to prevent any abnormal electrical punch-through in the memory cell. - In the aforementioned embodiment, a total of five memory cells M1˜M5 are serially connected together. Obviously, the number of serially connected memory cells can change according to the actual requirement. For example, 32 to 64 memory cell structures can be serially connected to the same word line.
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FIG. 3 is a simplified circuit diagram of a memory array according to one embodiment of the present invention. Here, a memory array with 16 memory cells is used as an example to describe the operating modes of the memory array in the present invention.FIG. 4A is a cross-sectional view of a non-volatile memory showing a programming operation according to one embodiment of the present invention.FIG. 4B is a cross-sectional view of a non-volatile memory showing a programming operation according to another embodiment of the present invention.FIG. 4C is a cross-sectional view of a non-volatile memory showing a reading operation according to one embodiment of the present invention.FIG. 4D is a cross-sectional view of a non-volatile memory showing a reading operation according to another embodiment of the present invention.FIG. 4E is a cross-sectional view of a non-volatile memory showing an erasing operation according to one embodiment of the present invention. - As shown in
FIG. 3 , the memory cell array includes 16 memory cells M11˜M44, a plurality of select gate lines SG1˜SG5, a plurality of word lines WL1˜WL4 and a plurality of bit lines BL1˜BL5. - Each of the memory cells M11˜M44 includes a select gate, a control gate and a charge-trapping layer. Furthermore, each pair of adjacent memory cell shares a single select gate.
- Each memory cell array includes four serially connected memory cells. For example, the memory cells M11˜M14 are serially connected together; the memory cells M21˜M24 are serially connected together; the memory cells M31˜M34 are serially connected together; and the memory cells M41˜M44 are serially connected together.
- The word lines WL1˜WL4 respectively connect with all the control gates of memory cells on the same row. For example, the word line WL1 connects the control gate of the memory cells M11˜M14 together; the word line WL2 connects the control gate of the memory cells M21˜M24 together; the word line WL3 connects the control gate of the memory cells M31˜M34 together; and, the word line WL4 connects the control gate of the memory cells M41˜M44 together.
- The select gate lines SG1˜SG5 connect the select gate of the memory cells in the same column. When a voltage is applied to the select gate lines SG1˜SG5, inversion layers are formed in the substrate underneath the select gate lines SG1˜SG5. These inversion layers serve as the bit lines BL1˜BL5.
- In the following, the method of operating the non-volatile memory according to the present invention is described with an embodiment. However, the method of operating the non-volatile memory is not limited thereto. The method of operating the non-volatile memory in the present invention includes combining four memory cells together to form a working group. For example, to operate the memory cell M23, besides the word line WL2, the select gate line SG3, the select gate line SG4, the bit line BL3 and the bit line BL4 that are directly coupled to the memory cell M23, additional lines including the select gate line SG2, the select gate line SG5, the bit line BL2, the bit line BL5 adjacent to the select gate line SG2, and the select gate line SG4 are also required. In the following, the memory cell M23 is described for exemplary purpose.
- As shown in
FIGS. 3 and 4A , to send electric charges into the charge-trapping region B1 (the left bit) of the memory cell M23 in a programming operation, for example, a voltage Vp1 is applied to the word line WL2 coupled to the selected memory cell M23. The voltage Vp1 is about 10V, for example. Another voltage Vp2 is applied to the selected select gate line SG2 on the charge-trapping region B1 (the left bit) side and adjacent to the charge-trapping region B1 (the left bit). The voltage Vp2 is close to the threshold voltage of the select gate line SG3, for example, about 1V. A voltage Vp3 is applied to the selected select gate line SG2 on the charge-trapping region B1 (the left bit) side and adjacent to the selected select gate line SG3. The voltage Vp3 is, for example, about 5V so that a bit line BL2 is formed in the substrate underneath the selected select gate line SG2. A voltage Vp4 is applied to the selected bit line BL2. The voltage Vp4 is about 0V, for example. Another voltage Vp5 is applied to the selected select gate line SG4 on the charge-trapping region B2 (the right bit) side and adjacent to the charge-trapping region B2 (the right bit). The voltage Vp5 is, for example, about 8V so that a bit line BL4 is formed in the substrate underneath the selected select gate line SG4. A voltage Vp6 is applied to the selected bit line BL4. The voltage Vp6 is about 4.5V, for example. A voltage Vp7 is applied to the selected select gate line SG5 on the charge-trapping region B2 (the right bit) side and adjacent to the selected select gate line SG4. The voltage Vp7 is about 0V, for example. A voltage of about 0V is applied to other unselected select gate lines such as SG1 so that source side injection (SSI) is utilized to inject electrons into the charge-trapping region B1 (the left bit) and hence program the left bit of the memory cell M23. In the aforementioned operation, the voltages Vp5 and Vp3 should be higher than the voltage Vp2, the voltage Vp6 should be higher than the voltage Vp4, and the voltage Vp1 should be higher than the voltage Vp2 to facilitate source side injection (SSI). Since the control gate of the non-volatile memory is buried within the trench, the accelerated electrons can be directly injected into the charge-trapping region B1 (the left bit) on the sidewall of the trench when the electrons in the bit line BL2 move toward the bit line BL4. Hence, a higher operating efficiency is achieved. Furthermore, the charge-trapping region B1 (the left bit) and the charge-trapping region B2 (the right bit) are isolated from each other through the trench so that mutual interference is minimized. - As shown in
FIGS. 3 and 4B , to send electric charges into the charge-trapping region B2 (the right bit) of the memory cell M23 in a programming operation, for example, a voltage Vp1 is applied to the word line WL2 coupled to the selected memory cell M23. The voltage Vp1 is about 10V, for example. Another voltage Vp2 is applied to the selected select gate line SG4 on the charge-trapping region B2 (the right bit) side and adjacent to the charge-trapping region B2 (the right bit). The voltage Vp2 is close to the threshold voltage of the select gate line SG4, for example, about 1V. A voltage Vp3 is applied to the selected select gate line SG4 on the charge-rapping region B2 (the right bit) side and adjacent to the selected select gate line SG4. The voltage Vp3 is, for example, about 5V so that a bit line BL5 is formed in the substrate underneath the selected select gate line SG5. A voltage Vp4 is applied to the selected bit line BL5. The voltage Vp4 is about 0V, for example. Another voltage Vp5 is applied to the selected select gate line SG3 on the charge-trapping region B1 (the left bit) side and adjacent to the charge-trapping region B1 (the left bit). The voltage Vp5 is, for example, about 8V so that a bit line BL3 is formed in the substrate underneath the selected select gate line SG3. A voltage Vp6 is applied to the selected bit line BL3. The voltage Vp6 is about 4.5V, for example. A voltage Vp7 is applied to the selected select gate line SG2 on the charge-trapping region B1 (the left bit) side and adjacent to the selected select gate line SG3. The voltage Vp7 is about 0V, for example. A voltage of about 0V is applied to other unselected select gate lines such as SG1 so that source side injection (SSI) is utilized to inject electrons into the charge-trapping region B2 (the right bit) and hence program the right bit of the memory cell M23. In the aforementioned operation, the voltages Vp5 and Vp3 should be higher than the voltage Vp2, the voltage Vp6 should be higher than the voltage Vp4, and the voltage Vp1 should be higher than the voltage Vp2 to facilitate source side injection (SSI). Similarly, since the control gate of the non-volatile memory is buried within the trench, the accelerated electrons can be directly injected into the charge-trapping region B2 (the right bit) on the sidewall of the trench when the electrons in the bit line BL5 move toward the bit line BL3. Hence, a higher operating efficiency is attained. Furthermore, the charge-trapping region B1 (the left bit) and the charge-trapping region B2 (the right bit) are isolated from each other through the trench so that interference from each other is minimized. - As shown in
FIGS. 3 and 4C , to read data from the charge-trapping region B1 (the left bit) of the memory cell M23 in a reading operation, for example, a voltage Vr1 is applied to the selected word line coupled to the selected memory cell M23. The voltage Vr1 is about 3V, for example. A voltage Vr2 is applied to the selected select gate line SG3 on the charge-trapping region B1 (the left bit) side and adjacent to the charge-trapping region B1 (the left bit). The voltage Vr2 is, for example, 5V so that a bit line BL3 is formed in the substrate underneath the selected select gate line SG3. A voltage Vr3 is applied to the selected bit line BL3. The voltage Vr3 is about 0V, for example. A voltage Vr4 is applied to the selected select gate lines SG4 on the charge-trapping region B2 (the right bit) side and adjacent to the charge-trapping region B2 (the right bit). The voltage Vr4 is, for example, about 5V so that the bit line BL4 is formed in the substrate underneath the selected select gate line SG4. A voltage Vr5 is applied to the selected bit line BL4. The voltage Vr5 is about 1.5V so that the left bit can be read from the memory cell M23. In this operation, the voltages Vr2 and Vr4 should be higher than the voltage Vr5 and the voltage Vr5 should be higher than the voltage Vr3. The voltage Vr1 should be higher than the threshold voltage of the memory cells without any trapped charges but smaller than the threshold voltage of the memory cells with electric charges. - As shown in
FIGS. 3 and 4D , to read data from the charge-trapping region B2 (the right bit) of the memory cell M23 in a reading operation, for example, a voltage Vr1 is applied to the selected word line coupled to the selected memory cell M23. The voltage Vr1 is about 3V, for example. A voltage Vr2 is applied to the selected select gate line SG4 on the charge-trapping region B2 (the right bit) side and adjacent to the charge-trapping region B2 (the right bit). The voltage Vr2 is, for example, 5V so that a bit line BL4 is formed in the substrate underneath the selected select gate line SG4. A voltage Vr3 is applied to the selected bit line BL4. The voltage Vr3 is about 0V, for example. A voltage Vr4 is applied to the selected select gate lines SG3 on the charge-trapping region B1 (the left bit) side and adjacent to the charge-trapping region B1 (the left bit). The voltage Vr4 is, for example, about 5V so that the bit line BL3 is formed in the substrate underneath the selected select gate line SG3. A voltage Vr5 is applied to the selected bit line BL3. The voltage Vr5 is about 1.5V so that the right bit can be read from the memory cell M23. In this operation, the voltages Vr2 and Vr4 should be higher than the voltage Vr5, and the voltage Vr5 should be higher than the voltage Vr3. The voltage Vr1 should be higher than the threshold voltage of the memory cells without any trapped charges but smaller than the threshold voltage of the memory cells with electric charges. Because the channel is closed with a small current when the total charge inside the charge-trapping layer is negative and because the channel is opened with a large current when the total charge inside the charge-trapping layer is positive, the open-close/current size in the channel can be used to determine whether a ‘1’ or ‘0’ bit data is stored inside the memory cell. - As shown in
FIGS. 3 and 4E , in an erasing operation, a voltage Ve1 is applied to the selected word line and a voltage Ve2 is applied to the substrate so that the select gate lines SG1˜SG5 are in a floating state and the electrons trapped inside the composite layer are tunnelled into the substrate. Hence, the data inside the memory cell is erased. The voltage differential between the voltage Ve1 and the voltage Ve2 triggers the FN tunneling effect. The voltage differential between the voltage Ve1 and the voltage Ve2 is between −12V to −20V, for example. For example, the voltage Ve1 is about −15V and the voltage Ve2 is about 0V. - The aforementioned method of operating the non-volatile memory of the present invention utilizes source side injection (SSI) to program a single bit in a unit memory cell and utilizes FN tunneling to erase the data within the memory cells so that the electron injection efficiency is high. Therefore, memory cell current can be reduced and operating speed can be increased. Moreover, with a small current loss, the power loss from the chip is effectively reduced.
- Because the control gates are buried inside the trenches of the substrate in the non-volatile memory, the accelerated electrons are directly injected into the charge-trapping regions on the sidewalls of the trenches. Therefore, the operating efficiency is high. Furthermore, the two charge-trapping regions (the left bit and the right bit) inside a single memory cell are effectively isolated from each other through the trench. Hence, interference between the two areas is significantly minimized.
-
FIGS. 5A through 5C are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention. In fact,FIGS. 5A through 5C are a series of cross-sectional views at different processing stages along line A-A′ ofFIG. 2A . First, as shown inFIG. 5A , asubstrate 300 such as a silicon substrate is provided. Then, a well 302 is formed in thesubstrate 300. The well 302 is a p-type well, for example. Thereafter, a plurality of stacked gate structure including adielectric layer 304, aconductive layer 306, and amask layer 308 sequentially stacked on thesubstrate 300 are formed. To form the stacked gate structures, a layer of dielectric material, conductive material, and insulating material are sequentially deposited over the substrate, and then a photolithographic and etching process is applied to pattern the layers. The dielectric layer is a silicon oxide layer formed, for example, by performing a thermal oxidation process. The conductive layer is a doped polysilicon layer, for example. The method of forming the conductive layer includes depositing a layer of undoped polysilicon material in a chemical vapor deposition process and then performing an ion implantation process thereafter or performing an in-situ doping in a chemical vapor deposition process, for example. The insulating layer is a silicon nitride layer formed, for example, by performing a chemical vapor deposition process. Theconductive layer 306 serves as the select gate and thedielectric layer 304 serves as a select gate dielectric layer. - As shown in
FIG. 5B , a portion of thesubstrate 300 is removed using themask layer 308 as a mask to form a plurality oftrenches 310 in thesubstrate 300. The method of removing a portion of thesubstrate 300 includes performing a dry etching operation such as a reactive ion etching operation. After removing themask layer 308, a composite layer 312 is formed on thesubstrate 300. Themask layer 308 is removed by performing a wet etching operation, for example. The composite layer 312 includes abottom dielectric layer 312 a, a charge-trapping layer 312 b, and atop dielectric layer 312 c. The bottom dielectric layer 321 a is fabricated using silicon oxide, the charge-trapping layer 312 b is fabricated using silicon nitride, and the top dielectric layer 321 c is fabricated using silicon oxide, for example. The method of forming the composite layer 312 includes forming adielectric layer 312 a, a charge-trapping layer 312 b, and atop dielectric layer 312 c, sequentially over thesubstrate 300 in a chemical vapor deposition process. Obviously, the composite layer 312 can be formed by performing a thermal oxidation process to form thebottom dielectric layer 312 a and then performing a chemical vapor deposition process to form the charge-trapping layer 312 b and the top dielectric layer 321 c. - As shown in
FIG. 5C , a plurality ofconductive layers 314 are formed over thesubstrate 300. Theconductive layers 314 fill up the gaps between theconductive layers 306 and thetrenches 310 within thesubstrate 300. Furthermore, theconductive layers 314 are arranged in parallel to each other and extend in a direction that crosses over the extension direction of the conductive layers 306 (the select gates). Theconductive layers 314 serve as word lines. The conductive layers 314 (the word lines) are formed using the following steps. First, a conductive material layer is formed over thesubstrate 300. Thereafter, a chemical-mechanical polishing operation or a back etching operation is performed to planarize the conductive material layer. Finally, the conductive material layer is patterned to form a plurality of linear conductive layers 314 (word lines). Theconductive layers 314 are doped polysilicon layers formed, for example, by depositing undoped polysilicon in a chemical vapor deposition process and then performing an ion implantation on the undoped polysilicon layer thereafter. Alternatively, theconductive layers 314 are formed by performing an in-situ doping process in a chemical vapor deposition process. After that, other steps necessary for fabricating a complete memory array are performed. Since these steps should be familiar to people skilled in the art of semiconductor manufacturing, a detailed description is omitted. - In the aforementioned embodiment, there is no device isolation structure between various memory cell arrays, and there is no contact and doped polysilicon between various memory cells. Hence, the process of fabricating the memory cell array is simple and the overall level of integration of the memory array is increased.
- Although the example in the aforementioned embodiment uses five memory cell structures altogether, there is no particular restriction on the number of memory cell structures that can be used. Obviously, the number of memory cells chained together may depend on the actual requirement. For example, a total of 32 to 64 memory cell structures can be serially connected through a word line. Furthermore, the method for fabricating the memory cell array in the present invention is actually applied to form an integrative memory array.
- It is apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (11)
1. A method of operating a non-volatile memory array having a plurality of memory cell arrays, each memory cell array comprising: a plurality of select gate structures disposed on a substrate, each select gate structure comprising a select gate dielectric layer and a select gate formed on the substrate and a trench in the substrate between two adjacent select gates; a composite layer covering the substrate and the select gates and comprising a charge-trapping layer; a plurality of control gates disposed on the composite layer and filling the trench between adjacent select gates; a plurality of word lines arranged in a row direction and coupled to the control gates in the same row; a plurality of select gate lines arranged in parallel in the column direction and coupled to the select gates on the same column; a plurality of bit lines arranged in parallel in the column direction such that the bit lines are formed in the substrate underneath the select gate lines when a voltage is applied to the select gate lines; a pair of adjacent select gates, wherein the control gate between two adjacent select gates and the composite layer together form a plurality of memory cells and each pair of neighboring memory cells share a common select gate line; and the composite layer between the control gate of each memory cell and a first sidewall of a corresponding trench constituting a first bit storage and the composite layer between the control gate of each memory cell and a second sidewall of a corresponding trench constituting a second bit storage, the method comprising:
performing a programming operation by applying a first voltage to a selected word line coupled to a selected memory cell; applying a second voltage to a first selected select gate line adjacent to the selected memory cell on the first bit side; applying a third voltage to a second selected select gate line next to the first selected select gate line on the first bit side so that a first selected bit line is formed in the substrate underneath the second selected select gate line; applying a fourth voltage to the first selected bit line; applying a fifth voltage to a third selected select gate line adjacent to the selected memory cell on the second bit side so that a second selected bit line is formed in the substrate underneath the third selected select gate line; applying a sixth voltage to the second selected bit line; applying a seventh voltage to a fourth selected select gate line next to the third selected select gate line on the second bit side, and applying a 0V to the unselected select gate lines, wherein the second voltage is close to the threshold voltage of the select gate line, the fifth voltage and the third voltage is higher than the second voltage, the sixth voltage is higher than the fourth voltage, and the first voltage is higher than the second voltage so that the first bit is programmed through source side injection.
2. The method of claim 1 , wherein the first voltage is about 10V, the second voltage is about 1V, the third voltage is about 5V, the fourth voltage is about 0V, the fifth voltage is about 8V, the sixth voltage is about 4.5V, and the seventh voltage is about 0V.
3. The method of claim 1 , farther comprising:
performing a programming operation by applying a eighth voltage to the selected word line coupled to the selected memory cell; applying a ninth voltage to the third selected select gate line adjacent to the selected memory cell on the second bit side; applying a tenth voltage to the fourth selected select gate line next to the third selected select gate line on the second bit side so that a third selected bit line is formed in the substrate underneath the fourth selected select gate line; applying a eleventh voltage to the third selected bit line; applying a twelfth voltage to the first selected select gate line adjacent to the selected memory cell on the first bit side so that a fourth selected bit line is formed in the substrate underneath the first selected select gate line; applying a thirteenth voltage to the fourth selected bit line; applying a fourteenth voltage to the second selected select gate line next to the first selected select gate line on the first bit side, and applying 0V to the unselected select gate lines, wherein the ninth voltage is close to the threshold voltage of the select gate line, the twelfth voltage and the tenth voltage is higher than the ninth voltage, the thirteenth voltage is higher than the eleventh voltage, and the eighth voltage is higher than the ninth voltage, so that the second bit is programmed through source side injection.
4. The method of claim 3 , wherein the eighth voltage is about 10V, the ninth voltage is about 1V, the tenth voltage is about 5V, the eleventh voltage is about 0V, the twelfth voltage is about 8V, the thirteenth voltage is about 4.5V, and the fourteenth voltage is about 0V.
5. The method of claim 1 , further comprising:
performing an erasing operation by applying an eighth voltage to the word lines and applying a ninth voltage to the substrate, and making the select gate lines floating so that the electrons stored within the composite layers are tunnelled into the substrate, wherein the voltage differential between the eighth voltage and the ninth voltage triggers FN tunneling effect.
6. The method of claim 5 , wherein the voltage differential is between about −12V to −20V.
7. The method of claim 6 , wherein the eighth voltage is about −15V and the ninth voltage is about 0V.
8. The method of claim 1 , further comprising:
performing a reading operation by applying a eighth voltage to the selected word line coupled to the selected memory cell; applying an ninth voltage to the first selected select gate line adjacent to the selected memory cell on first bit side so that a third selected bit line is formed in the substrate underneath the first selected select gate line; applying a tenth voltage to a third selected bit line; applying a eleventh voltage to the third selected select gate line adjacent to the selected memory cell on the second bit side so that the second selected bit line is formed in the substrate underneath the third selected select gate line; applying a twelfth voltage to the second selected bit line and reading out the first bit, wherein the ninth voltage and the eleventh voltage is higher than the twelfth voltage, the twelfth voltage is higher than the tenth voltage, and the eighth voltage is higher than the threshold voltage of the memory cells without trapping electrons but smaller than the threshold voltage of the memory cells containing trapped electrons.
9. The method of claim 8 , wherein the eighth voltage is about 3V, the ninth voltage and the eleventh voltage are about 5V, the tenth voltage is about 0V and the twelfth voltage is about 1.5V.
10. The method of claim 8 , further comprising:
performing a reading operation by applying a thirteenth voltage to a selected word line coupled to the selected memory cell; applying a fourteenth voltage to the third selected select gate line adjacent to the selected memory cell on the second bit side so that the second selected bit line is formed in the substrate underneath the third selected select gate line; applying a fifteenth voltage to the second selected bit line; applying a sixteenth voltage to the first selected select gate line adjacent to the selected memory cell on the first bit side so that the third selected bit line is formed in the substrate underneath the first selected select gate line; applying a seventeenth voltage to the third selected bit line and reading out the second bit, wherein the fourteenth voltage and the sixteenth voltage are higher than the seventeenth voltage, the seventeenth voltage is higher than the fifteenth voltage, and the thirteenth voltage is higher than the threshold voltage of the memory cells without trapping electrons but smaller than the threshold voltage of the memory cells containing trapped electrons.
11. The method of claim 10 , wherein the thirteenth voltage is about 3V, the fourteenth voltage and the sixteenth voltage are about 5V, the fifteenth voltage is about 0V, and the seventeenth voltage is about 1.5V.
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US11/161,398 US7391078B2 (en) | 2005-01-31 | 2005-08-02 | Non-volatile memory and manufacturing and operating method thereof |
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US12/107,775 Abandoned US20080227282A1 (en) | 2005-01-31 | 2008-04-23 | Method of manufacturing non-volatile memory |
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI270199B (en) * | 2005-01-31 | 2007-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
US7593264B2 (en) * | 2006-01-09 | 2009-09-22 | Macronix International Co., Ltd. | Method and apparatus for programming nonvolatile memory |
US7838920B2 (en) * | 2006-12-04 | 2010-11-23 | Micron Technology, Inc. | Trench memory structures and operation |
KR101291667B1 (en) * | 2007-08-20 | 2013-08-01 | 삼성전자주식회사 | Non-volatile memory device and reading method of the same |
KR101572482B1 (en) * | 2008-12-30 | 2015-11-27 | 주식회사 동부하이텍 | Method Manufactruing of Flash Memory Device |
CN102364675B (en) * | 2011-10-28 | 2015-07-08 | 上海华虹宏力半导体制造有限公司 | Method for forming flash memory |
TWI498908B (en) * | 2012-03-29 | 2015-09-01 | Ememory Technology Inc | Operating method for memory unit |
FR3000838B1 (en) * | 2013-01-07 | 2015-01-02 | St Microelectronics Rousset | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY |
JP6833873B2 (en) | 2016-05-17 | 2021-02-24 | シリコン ストーリッジ テクノロージー インコーポレイテッドSilicon Storage Technology, Inc. | Deep learning neural network classifier using non-volatile memory array |
US10311958B2 (en) * | 2016-05-17 | 2019-06-04 | Silicon Storage Technology, Inc. | Array of three-gate flash memory cells with individual memory cell read, program and erase |
US10269440B2 (en) | 2016-05-17 | 2019-04-23 | Silicon Storage Technology, Inc. | Flash memory array with individual memory cell read, program and erase |
US10580492B2 (en) | 2017-09-15 | 2020-03-03 | Silicon Storage Technology, Inc. | System and method for implementing configurable convoluted neural networks with flash memories |
US11087207B2 (en) | 2018-03-14 | 2021-08-10 | Silicon Storage Technology, Inc. | Decoders for analog neural memory in deep learning artificial neural network |
US10748630B2 (en) | 2017-11-29 | 2020-08-18 | Silicon Storage Technology, Inc. | High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks |
US10803943B2 (en) | 2017-11-29 | 2020-10-13 | Silicon Storage Technology, Inc. | Neural network classifier using array of four-gate non-volatile memory cells |
US11409352B2 (en) | 2019-01-18 | 2022-08-09 | Silicon Storage Technology, Inc. | Power management for an analog neural memory in a deep learning artificial neural network |
US11270763B2 (en) | 2019-01-18 | 2022-03-08 | Silicon Storage Technology, Inc. | Neural network classifier using array of three-gate non-volatile memory cells |
US11023559B2 (en) | 2019-01-25 | 2021-06-01 | Microsemi Soc Corp. | Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit |
US10720217B1 (en) | 2019-01-29 | 2020-07-21 | Silicon Storage Technology, Inc. | Memory device and method for varying program state separation based upon frequency of use |
US11423979B2 (en) | 2019-04-29 | 2022-08-23 | Silicon Storage Technology, Inc. | Decoding system and physical layout for analog neural memory in deep learning artificial neural network |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6804149B2 (en) * | 1999-10-12 | 2004-10-12 | New Halo, Inc. | Nonvolatile memory cell, operating method of the same and nonvolatile memory array |
US6885060B2 (en) * | 2001-03-19 | 2005-04-26 | Sony Corporation | Non-volatile semiconductor memory device and process for fabricating the same |
US6891221B2 (en) * | 1999-11-24 | 2005-05-10 | Aplus Flash Technology, Inc. | Array architecture and process flow of nonvolatile memory devices for mass storage applications |
US7020018B2 (en) * | 2004-04-22 | 2006-03-28 | Solid State System Co., Ltd. | Nonvolatile memory device and method for fabricating the same |
US7049652B2 (en) * | 2003-12-10 | 2006-05-23 | Sandisk Corporation | Pillar cell flash memory technology |
US7391078B2 (en) * | 2005-01-31 | 2008-06-24 | Powerchip Semiconductor Corp. | Non-volatile memory and manufacturing and operating method thereof |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6897520B2 (en) * | 1996-05-29 | 2005-05-24 | Madhukar B. Vora | Vertically integrated flash EEPROM for greater density and lower cost |
US6025626A (en) * | 1996-09-23 | 2000-02-15 | Siemens, Aktiengesellschaft | Nonvolatile memory cell |
EP1307920A2 (en) * | 2000-08-11 | 2003-05-07 | Infineon Technologies AG | Memory cell, memory cell device and method for the production thereof |
EP1243918A3 (en) * | 2001-03-23 | 2004-10-06 | Instrumentarium Corporation | An improved chemiluminescent gas analyzer |
US6936887B2 (en) * | 2001-05-18 | 2005-08-30 | Sandisk Corporation | Non-volatile memory cells utilizing substrate trenches |
JP4496514B2 (en) * | 2001-07-06 | 2010-07-07 | 株式会社デンソー | Discharge lamp equipment |
JP4027656B2 (en) * | 2001-12-10 | 2007-12-26 | シャープ株式会社 | Nonvolatile semiconductor memory device and operation method thereof |
US6720611B2 (en) * | 2002-01-28 | 2004-04-13 | Winbond Electronics Corporation | Fabrication method for flash memory |
JP2003332469A (en) * | 2002-05-10 | 2003-11-21 | Fujitsu Ltd | Non-volatile semiconductor memory device and method of manufacturing the same |
US6894930B2 (en) * | 2002-06-19 | 2005-05-17 | Sandisk Corporation | Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND |
US20030235076A1 (en) * | 2002-06-21 | 2003-12-25 | Micron Technology, Inc. | Multistate NROM having a storage density much greater than 1 Bit per 1F2 |
US6888755B2 (en) * | 2002-10-28 | 2005-05-03 | Sandisk Corporation | Flash memory cell arrays having dual control gates per memory cell charge storage element |
TW583755B (en) * | 2002-11-18 | 2004-04-11 | Nanya Technology Corp | Method for fabricating a vertical nitride read-only memory (NROM) cell |
US7332850B2 (en) * | 2003-02-10 | 2008-02-19 | Siemens Medical Solutions Usa, Inc. | Microfabricated ultrasonic transducers with curvature and method for making the same |
JP3873908B2 (en) * | 2003-02-28 | 2007-01-31 | セイコーエプソン株式会社 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US6951782B2 (en) * | 2003-07-30 | 2005-10-04 | Promos Technologies, Inc. | Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions |
TW200514256A (en) * | 2003-10-15 | 2005-04-16 | Powerchip Semiconductor Corp | Non-volatile memory device and method of manufacturing the same |
US6972260B2 (en) * | 2004-05-07 | 2005-12-06 | Powerchip Semiconductor Corp. | Method of fabricating flash memory cell |
JP4477422B2 (en) * | 2004-06-07 | 2010-06-09 | 株式会社ルネサステクノロジ | Method for manufacturing nonvolatile semiconductor memory device |
US7138681B2 (en) * | 2004-07-27 | 2006-11-21 | Micron Technology, Inc. | High density stepped, non-planar nitride read only memory |
-
2005
- 2005-01-31 TW TW094102849A patent/TWI270199B/en not_active IP Right Cessation
- 2005-08-02 US US11/161,398 patent/US7391078B2/en active Active
-
2008
- 2008-04-23 US US12/107,775 patent/US20080227282A1/en not_active Abandoned
- 2008-04-23 US US12/107,774 patent/US20080198669A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6804149B2 (en) * | 1999-10-12 | 2004-10-12 | New Halo, Inc. | Nonvolatile memory cell, operating method of the same and nonvolatile memory array |
US6891221B2 (en) * | 1999-11-24 | 2005-05-10 | Aplus Flash Technology, Inc. | Array architecture and process flow of nonvolatile memory devices for mass storage applications |
US6885060B2 (en) * | 2001-03-19 | 2005-04-26 | Sony Corporation | Non-volatile semiconductor memory device and process for fabricating the same |
US7049652B2 (en) * | 2003-12-10 | 2006-05-23 | Sandisk Corporation | Pillar cell flash memory technology |
US7253055B2 (en) * | 2003-12-10 | 2007-08-07 | Sandisk Corporation | Pillar cell flash memory technology |
US7020018B2 (en) * | 2004-04-22 | 2006-03-28 | Solid State System Co., Ltd. | Nonvolatile memory device and method for fabricating the same |
US7391078B2 (en) * | 2005-01-31 | 2008-06-24 | Powerchip Semiconductor Corp. | Non-volatile memory and manufacturing and operating method thereof |
US20080227282A1 (en) * | 2005-01-31 | 2008-09-18 | Powerchip Semiconductor Corp. | Method of manufacturing non-volatile memory |
Also Published As
Publication number | Publication date |
---|---|
US20060170038A1 (en) | 2006-08-03 |
TWI270199B (en) | 2007-01-01 |
US20080227282A1 (en) | 2008-09-18 |
US7391078B2 (en) | 2008-06-24 |
TW200627631A (en) | 2006-08-01 |
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