US20080160767A1 - Semiconductor Device And Method For Forming Pattern In The Same - Google Patents
Semiconductor Device And Method For Forming Pattern In The Same Download PDFInfo
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- US20080160767A1 US20080160767A1 US11/760,090 US76009007A US2008160767A1 US 20080160767 A1 US20080160767 A1 US 20080160767A1 US 76009007 A US76009007 A US 76009007A US 2008160767 A1 US2008160767 A1 US 2008160767A1
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- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 6
- 238000007687 exposure technique Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3146—Carbon layers, e.g. diamond-like layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Materials For Photolithography (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
- The present application claims priority to Korean patent application number 10-2006-0137008, filed on Dec. 28, 2006, which is incorporated by reference in its entirety.
- The present invention relates to a memory device. More particularly, the present invention relates to a method for forming a pattern in a semiconductor device by employing a self-aligned double exposure technology.
- In general, a semiconductor device such as dynamic random access memory (“DRAM”) includes numerous fine patterns. Such patterns are formed through a photolithography process. In order to form a pattern by a photolithography process, a photoresist (“PR”) film is coated over a target layer to be patterned. Next, an exposure process is performed to change solubility in a given potion of the PR film. Subsequently, a developing process is performed to form a PR pattern exposing the target layer. That is, the PR pattern is formed by removing the portion of which the solubility is changed, or by removing the portion of which the solubility is not changed. Later, the exposed target layer is etched using the PR pattern, and then the PR pattern is stripped to form a target layer pattern.
- In the photolithography process, resolution and depth of focus (“DOF”) are two important issues. Resolution (R) can be expressed by Equation 1 below.
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- wherein k1 is a constant determined by a kind and thicknesses of PR film, λ is a wavelength of light source, and NA stands for a numerical aperture of exposure equipment.
- According to the above Equation 1, the shorter the wavelength (λ) of a light source is and the larger the NA of exposure equipment is, the finer is a pattern formed over a wafer. However, λ of a light source being used and the NA of exposure equipment have not kept abreast of recently rapid advances in integration of a semiconductor device. Therefore, resolution enhancement technology (“RET”) for improving resolution and DOF is being applied by incorporating diverse methods. For example, the RET technology includes phase shift mask (“PSM”), off-axis illumination (“OAI”), optical proximity correction (“OPC”) and the like. Besides, there is a technology called double exposure technique (“DET”) capable of forming a fine pattern over a wafer. Critical Dimension (CD) uniformity in the DET depends on overall overlay accuracy of a first exposure mask and a second exposure mask.
- However, it is difficult to control the overlay of the first and second exposure masks to fall within the error range. Moreover, technical difficulties make it hard to achieve improvement of exposure equipment.
- Embodiments of the present invention are directed to an improved method for forming a pattern in a semiconductor device. According to one embodiment of the present invention, the improved method for forming a pattern in a semiconductor device utilizes a self-aligned double exposure technology.
- According to an embodiment of the present invention, a method for forming a pattern in a semiconductor device includes: forming a stacked structure of a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, wherein a line width of an upper part of the second hard mask layer pattern is narrower than that of its lower part, forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a third hard mask layer pattern over a fourth hard mask layer pattern, removing the insulating film and the third hard mask layer pattern, and patterning the semiconductor substrate by using the fourth hard mask layer pattern as an etching mask to form a fine pattern.
- According to another embodiment, a semiconductor device has fine patterns that are formed according to the method for forming a pattern described herein.
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FIGS. 1 a to 1 k are cross-sectional views illustrating a method for forming a pattern in a semiconductor device according to an embodiment of the present invention. - The present invention relates to a semiconductor device with fine patterns that are formed on the basis of a self-aligned double exposure technique. The fine patterns are realized with one exposure mask by using a modified stacked structure of hard mask layers and an isotropic etching method. Such fine patterns are uniformly formed to improve the degree of the integration and yield of semiconductor devices. According to the improved method for forming a fine pattern, the fabrication process of a semiconductor device is also simplified to reduce processing costs.
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FIGS. 1 a to 1 k are cross-sectional views illustrating a method for forming a pattern in a semiconductor device according to an embodiment of the present invention. A firsthard mask layer 120, a secondhard mask layer 130, a thirdhard mask layer 140, and a fourthhard mask layer 150 are formed over asemiconductor substrate 110 having an etch-target layer (not shown). A photoresist film (not shown) is formed over the fourthhard mask layer 150. The photoresist film is exposed and developed using a line/space mask (not shown) to form aphotoresist pattern 160. The fourthhard mask layer 150 and the thirdhard mask layer 140 are selectively etched using thephotoresist pattern 160 as an etching mask to form a fourth hardmask layer pattern 152 and a third hardmask layer pattern 142. - According to one embodiment of the invention, the first
hard mask layer 120 is formed of an amorphous carbon film; the secondhard mask layer 130 is formed of a silicon oxynitride (SiON) film; the thirdhard mask layer 140 is formed of a polysilicon layer or a silicon nitride (Si3N4) film; and the fourthhard mask layer 150 is formed of a silicon oxide (SiO2) film. In another embodiment, a ratio of theline width 160 a of thephotoresist pattern 160 to the width of thespace 160 b defined between the neighboringphotoresist patterns 160 is in a range of about 2.5:1.5 to about 3.5:0.5. In addition, the ratio of theline width 160 a to the width of thespace 160 a is preferably substantially about 3:1. In another embodiment of the present invention, the process of selectively etching the fourthhard mask layer 150 and the thirdhard mask layer 140 is performed by an anisotropic dry etching method. - Referring to
FIGS. 1 c through 1 f, the fourth hardmask layer pattern 152 is selectively etched by using thephotoresist pattern 160 as an etching mask to form a fifth hardmask layer pattern 154. Thephotoresist pattern 160 is then removed. Aninsulating film 170 is formed over thesemiconductor substrate 110 to fill the third hardmask layer pattern 142 and the fifth hardmask layer pattern 154. Theinsulating film 170 is etched until the top surface of the fifth hardmask layer pattern 154 is exposed (FIG. 1 f). - According to one embodiment of the present invention, the fifth hard
mask layer pattern 154 is formed by an isotropic wet etching method. In addition, the isotropic etching method may be adjusted so that alatitudinal line width 154 a of an upper part (for example 154 b) of the fifth hardmask layer pattern 154 is substantially equal to that of thespace 160 b defined between the neighboringphotoresist patterns 160 shown inFIG. 1 b (see alsoFIG. 1 d). In another embodiment of the present invention, a ratio of theline width 154 a of the upper part (for example 154 b) of the fifth hardmask layer pattern 154 to thewidth 154 c of the lower part (for example 154 d) is in a range of about 1.5:2.5 to about 0.5:3.5. In addition, the ratio of theline width 154 a to thewidth 154 c is substantially about 1:3. In another embodiment of the present invention, theinsulating film 170 is formed of a spin-on-carbon (“SOC”) film so that the fifth hardmask layer pattern 154 which upper part is etched wider than its lower part is filled. In addition, the etching process of etching theinsulating film 170 preferably is performed by an etch-back method using a gas including O2. - Referring to
FIGS. 1 g to 1 i, the exposed fifth hardmask layer pattern 154 and its underlying third hardmask layer pattern 142 are selectively etched using theinsulating film 170 as an etching mask to form a seventh hardmask layer pattern 156 and a sixth hardmask layer pattern 144, which exposes the second hard mask layer 130 (FIG. 1 h). Theinsulating film 170 is removed. The seventh hardmask layer pattern 156 is removed (FIG. 1 i). - According to one embodiment of the present invention, the process of etching the fifth hard
mask layer pattern 154 and the third hardmask layer pattern 142 is performed by an anisotropic dry etching method. The process of removing theinsulating film 170 preferably is performed by a plasma etching method using a gas including O2. In addition, the second hardmask layer pattern 130 formed of a silicon oxynitride (SiON) film can serve as an etch stop film during a plasma etching method to prevent the firsthard mask layer 120 from being etched. - In another embodiment of the present invention, the process of removing the seventh hard
mask layer pattern 156 is performed by a wet etching method using a buffer oxide etchant (“BOE”) solution. In the wet etching method using the BOE solution, the sixth hardmask layer pattern 144 and the secondhard mask layer 130 are not etched so that a seventh hardmask layer pattern 156 that is formed of a silicon oxide (SiO2) film can be selectively removed. In another embodiment of the present invention, a ratio of a latitudinal line width 144 a of the sixth hardmask layer pattern 144 to the width 144 b of the space 144 b defined between the neighboring sixth hardmask layer patterns 144 is substantially about 1:1 (SeeFIG. 1 i). For example, the line width of each of two pattern elements will be about equal to the width of the space between them. - Referring to
FIGS. 1 j and 1 k, the secondhard mask layer 130 is etched using the sixth hardmask layer pattern 144 as an etching mask to form a eighth hardmask layer pattern 132. The firsthard mask layer 120 is etched using the eighth hardmask layer pattern 132 to form a ninth hardmask layer pattern 122. The etch target layer is patterned using the ninth hardmask layer pattern 122 to form a fine pattern. Accordingly, a fine pattern can be formed in a semiconductor device based on the self-aligned double exposure technology having one mask process. - As described above, according to the semiconductor device and the pattern formation method for the same, it becomes possible to form a fine pattern having uniform critical dimension, irrespective of the overlay accuracy of exposure equipment. Accordingly, the integration and yield of semiconductor devices are improved. Moreover, since the double exposure technique uses one exposure mask, the overall fine pattern formation process is simplified to reduce processing costs.
- The above embodiments of the present invention are illustrative and not limitative. Throughout the specification, where methods and compositions are described as including steps or materials, it is contemplated that the methods and compositions can also consist essentially of, or consist of, any combination of the recited steps or materials, unless described otherwise. Although processes have been described with reference to particular embodiments, a person of ordinary skill in the art will readily appreciate that various alternatives and equivalents are possible. Other additions, subtractions, or modifications will be obvious to a person of ordinary skill in the art in view of the present disclosure and are intended to fall within the scope of the appended claims. The invention is not limited by the lithography steps or materials described herein, nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. The order of steps may be changed without departing from the scope or spirit of the method, unless described otherwise. In addition, individual steps may be combined, omitted, or further subdivided into additional steps, and intervening steps may be applicable.
Claims (22)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2006-0137008 | 2006-12-28 | ||
KR1020060137008A KR100827534B1 (en) | 2006-12-28 | 2006-12-28 | Semiconductor device and method for forming fine pattern of the same |
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US20080160767A1 true US20080160767A1 (en) | 2008-07-03 |
US7550384B2 US7550384B2 (en) | 2009-06-23 |
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US11/760,090 Active US7550384B2 (en) | 2006-12-28 | 2007-06-08 | Semiconductor device and method for forming pattern in the same |
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US (1) | US7550384B2 (en) |
JP (1) | JP5017570B2 (en) |
KR (1) | KR100827534B1 (en) |
CN (1) | CN100595888C (en) |
TW (1) | TWI345262B (en) |
Cited By (1)
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CN112967986A (en) * | 2020-10-19 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Transfer component, preparation method thereof and transfer head |
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KR100866723B1 (en) * | 2006-12-28 | 2008-11-05 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming fine pattern of the same |
JP4946625B2 (en) * | 2007-05-21 | 2012-06-06 | 日本電産株式会社 | motor |
JP2009295745A (en) * | 2008-06-04 | 2009-12-17 | Toshiba Corp | Method for manufacturing semiconductor device |
CN102446704B (en) * | 2010-10-14 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
KR20120120729A (en) * | 2011-04-25 | 2012-11-02 | 에스케이하이닉스 주식회사 | Method for manufacturing metal pattern in semiconductor device |
CN103426809B (en) * | 2012-05-18 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor making method based on self-aligned double patterning case |
US9054158B2 (en) * | 2013-02-08 | 2015-06-09 | Texas Instruments Incorporated | Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening |
CN104157564B (en) * | 2013-05-15 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Improve the method for critical dimension uniformity after etching |
CN104241099B (en) * | 2013-06-09 | 2017-09-29 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned double patterning shape technique |
US9012330B2 (en) * | 2013-08-22 | 2015-04-21 | Nanya Technology Corp. | Method for semiconductor cross pitch doubled patterning process |
CN106229255B (en) * | 2016-07-27 | 2020-02-21 | 上海华虹宏力半导体制造有限公司 | Method of self-aligned double exposure development process and semiconductor device |
Citations (4)
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US20020096490A1 (en) * | 2001-01-20 | 2002-07-25 | Chia-Chieh Yu | Photolithographic and etching method |
US20060068547A1 (en) * | 2004-07-12 | 2006-03-30 | Sang-Hoon Lee | Methods of forming self-aligned floating gates using multi-etching |
US20070077748A1 (en) * | 2005-09-30 | 2007-04-05 | Dominik Olligs | Method for forming a semiconductor product and semiconductor product |
US20080017889A1 (en) * | 2006-07-18 | 2008-01-24 | Young-Ho Koh | Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device |
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JPH03270227A (en) * | 1990-03-20 | 1991-12-02 | Mitsubishi Electric Corp | Formation of fine pattern |
KR960004291B1 (en) | 1993-12-31 | 1996-03-30 | 엘지전선주식회사 | Cable cutter |
KR0144232B1 (en) * | 1995-05-09 | 1998-08-17 | 김주용 | Formation method of fine pattern in semiconductor device |
KR0144489B1 (en) * | 1995-10-04 | 1998-07-01 | 김주용 | Process defect inspection method of semiconductor device |
KR20040019652A (en) * | 2002-08-28 | 2004-03-06 | 삼성전자주식회사 | Method for forming conductive pattern of semiconductor device |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020096490A1 (en) * | 2001-01-20 | 2002-07-25 | Chia-Chieh Yu | Photolithographic and etching method |
US20060068547A1 (en) * | 2004-07-12 | 2006-03-30 | Sang-Hoon Lee | Methods of forming self-aligned floating gates using multi-etching |
US20070077748A1 (en) * | 2005-09-30 | 2007-04-05 | Dominik Olligs | Method for forming a semiconductor product and semiconductor product |
US20080017889A1 (en) * | 2006-07-18 | 2008-01-24 | Young-Ho Koh | Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device |
Cited By (1)
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CN112967986A (en) * | 2020-10-19 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Transfer component, preparation method thereof and transfer head |
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JP5017570B2 (en) | 2012-09-05 |
US7550384B2 (en) | 2009-06-23 |
CN101211761A (en) | 2008-07-02 |
TWI345262B (en) | 2011-07-11 |
CN100595888C (en) | 2010-03-24 |
JP2008166693A (en) | 2008-07-17 |
KR100827534B1 (en) | 2008-05-06 |
TW200828406A (en) | 2008-07-01 |
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