US20080150090A1 - DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL - Google Patents

DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL Download PDF

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US20080150090A1
US20080150090A1 US12/021,728 US2172808A US2008150090A1 US 20080150090 A1 US20080150090 A1 US 20080150090A1 US 2172808 A US2172808 A US 2172808A US 2008150090 A1 US2008150090 A1 US 2008150090A1
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gate
polysilicon
metal
dielectric
profile
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Hong Lin
Wai Lo
Sey-Shing Sun
Richard Carter
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Bell Semiconductor LLC
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LSI Logic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al

Definitions

  • the present invention generally relates to damascene metal gate processes, and more specifically relates to a damascene metal gate process which uses Si 1-x Ge x as a sacrificial member.
  • MOS metal oxide semiconductor
  • a major challenge to the introduction of metal electrodes is addressing the issue of how to integrate the material into conventional transistor processing.
  • two metal types will be needed, one with an n-type work function and one with a p-type work function.
  • a single metal with a mid-gap work function can be used.
  • the integration question is still open.
  • Many candidate metals will not sustain a standard source/drain activation anneal due to either reaction with the gate dielectric or the low melting temperature of many metal materials.
  • a replacement gate approach is very appealing.
  • FIGS. 1-5 A replacement gate approach using a damascene scheme has been proposed previously, and is illustrated in FIGS. 1-5 .
  • the approach provides that polysilicon dummy gates 10 are fabricated using standard polysilicon gate CMOS process flow until the formation source/drain (wherein the source is identified with reference numeral 12 in FIG. 1 and the drain is identified with reference numeral 14 in FIG. 1 ).
  • pre-metal dielectric 16 is deposited on the silicon wafer 18 and a dielectric CMP planarization process is performed (as represented by arrows 20 in FIG. 2 ).
  • the dummy polysilicon 10 and gate oxide 22 are then removed by reactive ion etching (RIE) and/or wet chemical etching to form a gate groove 24 as shown in FIG. 3 .
  • RIE reactive ion etching
  • a new gate dielectric (SiO 2 or high-k dielectric) 26 and metal gate 28 are grown and/or deposited on the wafer and, as shown in FIG. 5 , a CMP step is performed (represented by arrows 30 in FIG. 5 ) to finally form the metal gate electrode 32 .
  • the main advantage of using a damascene process is that it avoids the thermal and plasma damages to the gate dielectric and metal electrode stacks during source/drain ion implantation, activation annealing and gate RIE.
  • a major problem of the existing damascene replacement scheme for metal gates is associated with the dummy polysilicon profile.
  • the standard CMOS polysilicon gate etch process in general can only achieve a tapered polysilicon profile 40 with an angle of 87-89 degrees as shown in FIG. 6 (i.e., the polysilicon will have an actual profile such as that which is shown in FIG. 6 , as opposed to the theoretical profile depicted in FIG. 1 ) causing a re-entrant gate groove 42 as shown in FIG. 7 (i.e., the gate groove will have an actual profile such as that which is shown in FIG. 7 as opposed to the theoretical profile depicted in FIG. 3 ).
  • An object of an embodiment of the present invention is to provide a method of forming a metal gate in a wafer which does not result in polysilicon residue being left in a groove before the groove is filled with metal.
  • Another object of an embodiment of the present invention is to provide a method of forming a metal gate in a wafer wherein a tapered groove is formed that tapers from an opening at its top to the bottom of the groove.
  • Yet another object of an embodiment of the present invention is to provide a metal gate in a wafer, where there is a groove which has a tapered profile which converges from an opening to a base, and there is metal in the groove, thereby providing the metal gate.
  • an embodiment of the present invention provides a method of forming a metal gate in a wafer wherein PolySi 1-x Ge x is used as a sacrificial member to form a tapered groove. Specifically, gate oxide, PolySi 1-x Ge x , and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi 1-x Ge x , and gate oxide is removed to provide a tapered profile.
  • the resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi 1-x Ge x , and gate oxide.
  • a dielectric is deposited, and a portion is removed thereby exposing the polysilicon.
  • the polysilicon, PolySi 1-x Ge x , and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
  • FIGS. 1-7 are views which relate to a prior art damascene metal gate process
  • FIG. 8 is a flow chart which illustrates a damascene metal gate process which is in accordance with an embodiment of the present invention.
  • FIGS. 9-14 are views which relate to the process illustrated in FIG. 8 .
  • the present invention aims to improve the dummy gate profile, eliminate the re-entrant profile of gate grooves, and extend the damascene replacement scheme to future technology nodes.
  • FIG. 8 illustrates the process on a step-and-step basis, and the progression of FIGS. 9 through 14 show the process being performed.
  • a gate oxide 50 is deposited oil a silicon wafer 52 , and then polysilicon 54 and PolySi 1-x Ge x 56 films are deposited.
  • the Ge composition in the PolySi 1-x Ge x may be anywhere from 15 to 50 percent depending on the application.
  • a resist 58 is patterned on the polysilicon 54 .
  • the wafer 52 is then processed through dummy gate etching (i.e., portions of the polysilicon 54 , PolySi 1-x Ge x 56 , and gate oxide 50 are etched away) and the resist 58 is stripped and cleaned, thereby providing that which is shown in FIG. 10 .
  • a dielectric liner 60 e.g. oxide or nitride, such as SiO2, Si3N4, or some other High-K dielectric
  • FIG. 11 is followed by an anisotropic plasma etch to remove the dielectric on top of the polysilicon and active areas, thereby leaving the structure as shown in FIG.
  • the dielectric liner 60 is left intact along the side wall 64 of the polysilicon 54 , PolySi 1-x Ge x 56 , and gate oxide 50 .
  • the dielectric liner 60 on the side wall 64 prevents Si 1-x Ge x 56 from further oxidizing and wet etching, thus preserving the dummy gate profile and gate electrode dimension throughout the subsequent processes.
  • the following steps are performed: LDD implantation and anneal, LTO oxide and Si3N4 deposition and etch to form spacer, SD implantation and anneal, salicide formation; depositing a pre-metal dielectric (such as a standard ILD oxide layer such as HDP oxide, FSG, or BPSG) on the polysilicon; and CMP removing a portion of the dielectric thereby exposing the polysilicon.
  • a pre-metal dielectric such as a standard ILD oxide layer such as HDP oxide, FSG, or BPSG
  • CMP CMP removing a portion of the dielectric thereby exposing the polysilicon.
  • the polysilicon 54 , PolySi 1-x Ge x 56 , and gate oxide 50 are removed from inside the dielectric liner 60 , thereby leaving a tapered gate groove 66 as shown in FIG. 13 .
  • the groove 66 is wider at an opening 68 at its top 70 than at its bottom 72 , proximate the silicon wafer 52 .
  • a gate dielectric 74 such as SiO2, SiON, or a high-K dielectric is deposited.
  • metal 76 is deposited into the groove 66 , and is etched to provide the final structure shown in FIG. 14 .
  • a re-entrant PolySi 1-x Ge x profile can be achieved (as shown in FIGS. 10-12 ), wherein the PolySi 1-x Ge x 56 is wider at its top 78 , proximate the polysilicon 54 , than it is at its bottom 80 , proximate the gate oxide 50 .
  • This re-entrant dummy gate profile then yields a tapered gate groove 66 as shown in FIG. 13 after processing through source/drain formation and dummy gate removal. This tapered profile thus can achieve much smaller gate length, improve gate dielectric and metal gate electrode gap fill.
  • the capability of the manipulation of Si 1-x Ge x resides in the fact that the Si 1 Ge x has higher oxidation rate than silicon, and germanium oxide is a volatile compound.
  • the present method involves the use of F/Cl2 based chemistries for plasma etching of polysilicon portion as well as the use of Cl2/HBr/O2 based chemistries for etching the PolySi 1-x Ge x portion of the film stack.
  • the profile of Si 1-x Ge x can be further manipulated by using a wet chemistry (such as SCl) that includes an oxidizing agent (such as H2O2 or O3) and an acid or base, such as NH4OH, to dissolve the oxidized surface.
  • a wet chemistry such as SCl
  • an oxidizing agent such as H2O2 or O3
  • an acid or base such as NH4OH

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Abstract

A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Description

    RELATED APPLICATION (PRIORITY CLAIM)
  • This patent application is a divisional of U.S. patent application Ser. No. 10/889,901, filed on Jul. 13, 2004.
    • BACKGROUND
  • The present invention generally relates to damascene metal gate processes, and more specifically relates to a damascene metal gate process which uses Si1-xGex as a sacrificial member.
  • The aggressive scaling of metal oxide semiconductor (MOS) devices is quickly reaching the fundamental limits of SiO2 as the gate dielectric. Scaling requirements can no longer be achieved with SiO2 or nitrided-SiO2 gate dielectrics due to the presence of excessive leakage currents arising from direct tunneling and the lack of manufacturability of sub-1 nm oxides. Moreover, poly-Si depletion and threshold voltage shifts due to boron penetration into the channel region severely degrade device performance. Replacement of SiO2-based gate dielectrics with a high dielectric constant (high-k) material provides a means to address scaling issues. A high-k material allows for a physically thicker film to meet the required gate capacitance, while reducing the leakage current due to direct tunneling and improving manufacturability.
  • The issue of poly-Si depletion is still not overcome when using a high-k material, since the 3-6A contribution to EOT due to poly-Si depletion is still about 30-50% of the target EOT. As a result, the semiconductor industry began investigating metal gate electrodes. Replacement of poly-Si with a metal electrode solves both the boron penetration and poly-Si depletion issues. Moreover, the introduction of metal gates can prolong the use of SiO2 for one or two technology generations for high performance applications before requiring a switch to high-k dielectrics.
  • A major challenge to the introduction of metal electrodes is addressing the issue of how to integrate the material into conventional transistor processing. In the case of CMOS and partially depleted SOI, two metal types will be needed, one with an n-type work function and one with a p-type work function. In the case of fully depleted SOI, a single metal with a mid-gap work function can be used. Whether one type or two types of metals are used, the integration question is still open. Many candidate metals will not sustain a standard source/drain activation anneal due to either reaction with the gate dielectric or the low melting temperature of many metal materials. In order to increase the number of candidate metal materials, a replacement gate approach is very appealing.
  • A replacement gate approach using a damascene scheme has been proposed previously, and is illustrated in FIGS. 1-5. As shown in FIG. 1, the approach provides that polysilicon dummy gates 10 are fabricated using standard polysilicon gate CMOS process flow until the formation source/drain (wherein the source is identified with reference numeral 12 in FIG. 1 and the drain is identified with reference numeral 14 in FIG. 1). Then, as shown in FIG. 2, pre-metal dielectric 16 is deposited on the silicon wafer 18 and a dielectric CMP planarization process is performed (as represented by arrows 20 in FIG. 2). The dummy polysilicon 10 and gate oxide 22 are then removed by reactive ion etching (RIE) and/or wet chemical etching to form a gate groove 24 as shown in FIG. 3. As shown in FIG. 4, a new gate dielectric (SiO2 or high-k dielectric) 26 and metal gate 28 are grown and/or deposited on the wafer and, as shown in FIG. 5, a CMP step is performed (represented by arrows 30 in FIG. 5) to finally form the metal gate electrode 32. The main advantage of using a damascene process is that it avoids the thermal and plasma damages to the gate dielectric and metal electrode stacks during source/drain ion implantation, activation annealing and gate RIE.
  • A major problem of the existing damascene replacement scheme for metal gates is associated with the dummy polysilicon profile. The standard CMOS polysilicon gate etch process in general can only achieve a tapered polysilicon profile 40 with an angle of 87-89 degrees as shown in FIG. 6 (i.e., the polysilicon will have an actual profile such as that which is shown in FIG. 6, as opposed to the theoretical profile depicted in FIG. 1) causing a re-entrant gate groove 42 as shown in FIG. 7 (i.e., the gate groove will have an actual profile such as that which is shown in FIG. 7 as opposed to the theoretical profile depicted in FIG. 3). This leads to the following disadvantages of the scheme:
      • (a). Dummy polysilicon residue 44 as illustrated in FIG. 7: Incomplete removal of dummy polysilicon the sidewall, especially when a RIE is used to remove the dummy polysilicon.
      • (b). Incomplete dummy gate dielectric removal or undercut beneath residue polysilicon.
      • (c). Difficulty of groove filling with new gate dielectric and metal electrode. Voids could be formed due to the lack of gap filling capability for the gate dielectric and metal electrode inside these narrow and high aspect ratio grooves, which will in turn limit the scalability of this scheme for the future technology nodes.
    OBJECTS AND SUMMARY
  • An object of an embodiment of the present invention is to provide a method of forming a metal gate in a wafer which does not result in polysilicon residue being left in a groove before the groove is filled with metal.
  • Another object of an embodiment of the present invention is to provide a method of forming a metal gate in a wafer wherein a tapered groove is formed that tapers from an opening at its top to the bottom of the groove.
  • Yet another object of an embodiment of the present invention is to provide a metal gate in a wafer, where there is a groove which has a tapered profile which converges from an opening to a base, and there is metal in the groove, thereby providing the metal gate.
  • Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a method of forming a metal gate in a wafer wherein PolySi1-xGex is used as a sacrificial member to form a tapered groove. Specifically, gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The organization and manner of the structure and operation of the invention, together with further objects and advantages thereof, may best be understood by reference to the following description, taken in connection with the accompanying drawings, wherein:
  • FIGS. 1-7 are views which relate to a prior art damascene metal gate process;
  • FIG. 8 is a flow chart which illustrates a damascene metal gate process which is in accordance with an embodiment of the present invention; and
  • FIGS. 9-14 are views which relate to the process illustrated in FIG. 8.
    •  DESCRIPTION
  • While the invention may be susceptible to embodiment in different forms, there are shown in the drawings, and herein will be described in detail, specific embodiments of the invention. The present disclosure is to be considered an example of the principles of the invention, and is not intended to limit the invention to that which is illustrated and described herein.
  • The present invention aims to improve the dummy gate profile, eliminate the re-entrant profile of gate grooves, and extend the damascene replacement scheme to future technology nodes.
  • Instead of using pure polysilicon as dummy gate, the new method involves the use of a polysilicon/PolySi1-xGex film stacks as a dummy gate. FIG. 8 illustrates the process on a step-and-step basis, and the progression of FIGS. 9 through 14 show the process being performed. Initially, as shown in FIG. 9, a gate oxide 50 is deposited oil a silicon wafer 52, and then polysilicon 54 and PolySi1-xGex 56 films are deposited. The Ge composition in the PolySi1-xGex may be anywhere from 15 to 50 percent depending on the application. Then, a resist 58 is patterned on the polysilicon 54. The wafer 52 is then processed through dummy gate etching (i.e., portions of the polysilicon 54, PolySi1-xGex 56, and gate oxide 50 are etched away) and the resist 58 is stripped and cleaned, thereby providing that which is shown in FIG. 10. After the desired degree of re-entrant profile has been achieved, a dielectric liner 60 (e.g. oxide or nitride, such as SiO2, Si3N4, or some other High-K dielectric) is deposited as shown in FIG. 11, which is followed by an anisotropic plasma etch to remove the dielectric on top of the polysilicon and active areas, thereby leaving the structure as shown in FIG. 12, wherein the top 62 of the polysilicon 54 is exposed, but the dielectric liner 60 is left intact along the side wall 64 of the polysilicon 54, PolySi1-xGex 56, and gate oxide 50. The dielectric liner 60 on the side wall 64 prevents Si1-xGex 56 from further oxidizing and wet etching, thus preserving the dummy gate profile and gate electrode dimension throughout the subsequent processes. Subsequently, the following steps are performed: LDD implantation and anneal, LTO oxide and Si3N4 deposition and etch to form spacer, SD implantation and anneal, salicide formation; depositing a pre-metal dielectric (such as a standard ILD oxide layer such as HDP oxide, FSG, or BPSG) on the polysilicon; and CMP removing a portion of the dielectric thereby exposing the polysilicon. Subsequently, the polysilicon 54, PolySi1-xGex 56, and gate oxide 50 are removed from inside the dielectric liner 60, thereby leaving a tapered gate groove 66 as shown in FIG. 13. As shown, the groove 66 is wider at an opening 68 at its top 70 than at its bottom 72, proximate the silicon wafer 52. Then, a gate dielectric 74 such as SiO2, SiON, or a high-K dielectric is deposited. Finally, metal 76 is deposited into the groove 66, and is etched to provide the final structure shown in FIG. 14.
  • By manipulating the Ge composition in the PolySi1-xGex, the plasma etching chemistries of Si1-xGex, oxidation, and oxide wet etching, a re-entrant PolySi1-xGex profile can be achieved (as shown in FIGS. 10-12), wherein the PolySi1-xGex 56 is wider at its top 78, proximate the polysilicon 54, than it is at its bottom 80, proximate the gate oxide 50. This re-entrant dummy gate profile then yields a tapered gate groove 66 as shown in FIG. 13 after processing through source/drain formation and dummy gate removal. This tapered profile thus can achieve much smaller gate length, improve gate dielectric and metal gate electrode gap fill.
  • The capability of the manipulation of Si1-xGex resides in the fact that the Si1 Gex has higher oxidation rate than silicon, and germanium oxide is a volatile compound. The present method involves the use of F/Cl2 based chemistries for plasma etching of polysilicon portion as well as the use of Cl2/HBr/O2 based chemistries for etching the PolySi1-xGex portion of the film stack. The inclusion of O2 in the etch chemistry results in a diminished Si1-xGex dimension with respect to the polysilicon (LsiGe/LSi=0.8 with LsiGe and Lsi being the dimensions of the PolySi1-xGex and silicon, respectively).
  • The profile of Si1-xGex can be further manipulated by using a wet chemistry (such as SCl) that includes an oxidizing agent (such as H2O2 or O3) and an acid or base, such as NH4OH, to dissolve the oxidized surface. The film thickness of polysilicon/Poly Si1-xGex, and the composition of Ge in the Si1-xGex alloy can also be adjusted to fit the requirements of the final profile and CDs.
  • Hence, the process has the following features:
      • (a). Deposition of polysilicon/Poly Si1-xGex film stacks as damascene replacement dummy gate materials.
      • (b). Manipulation of the plasma etch chemistries, Ge composition, film stack thickness, and wet clean chemistries to achieve a desired re-entrant dummy gate profile.
      • (c). Dielectric liner deposition and plasma etching to provide a dielectric sidewall for preserving the gate groove profile.
      • (d). A unique gate profile.
      • (e). Scalability: can be used to achieve small gate length without the need of small line print.
      • (f). Prevention of the incomplete polysilicon strip and undercut after dummy gate dielectric removal.
      • (g). Improved subsequent new gate dielectric and metal gate electrode gap fill capability.
  • While embodiments of the present invention are shown and described, it is envisioned that those skilled in the art may devise various modifications of the present invention without departing from the spirit and scope of the appended claims.

Claims (3)

1. A metal gate in a wafer comprising: a groove which has a tapered profile which converges from an opening to a base; metal in the groove, thereby providing said metal gate.
2. A metal gate as recited in claim 1, further comprising a dielectric liner on a side of said groove.
3. A metal gate as recited in claim 2, further comprising a dielectric layer, said dielectric liner being disposed between said dielectric layer and said metal.
US12/021,728 2004-07-13 2008-01-29 DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL Abandoned US20080150090A1 (en)

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