US20080110759A1 - Self Terminating Overburden Free Plating (STOP) Of Metals On Patterned Wafers - Google Patents

Self Terminating Overburden Free Plating (STOP) Of Metals On Patterned Wafers Download PDF

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US20080110759A1
US20080110759A1 US11/559,480 US55948006A US2008110759A1 US 20080110759 A1 US20080110759 A1 US 20080110759A1 US 55948006 A US55948006 A US 55948006A US 2008110759 A1 US2008110759 A1 US 2008110759A1
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patterned
dielectric layer
copper
rate
plating
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US11/559,480
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David Sarosvetsky
Nina Sezin
Yair Ein-Eli
Mark Kovler
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Tower Semiconductor Ltd
Technion Research and Development Foundation Ltd
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Tower Semiconductor Ltd
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Publication of US20080110759A1 publication Critical patent/US20080110759A1/en
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Definitions

  • the present invention relates to electrochemical metal deposition during fabrication of an integrated circuit. More specifically, the present invention relates to controlling the deposition rate of electrochemical metal deposition in different regions of an integrated circuit chip.
  • Electrochemical metal deposition is used in semiconductor manufacture for on-chip wiring of integrated circuits.
  • electrochemical deposition of copper can be used to fill and/or coat different patterned features of an integrated circuit, including trenches and/or vias formed in dielectric layers on the wafer surface.
  • FIG. 1 is a schematic drawing of an electrochemical deposition system 100 , wherein a patterned dielectric layer 102 is formed over a surface of wafer 101 .
  • Patterned dielectric layer 102 includes patterned features (vias/trenches) 111 - 113 , and open areas 121 - 123 .
  • Copper layer 103 is formed over patterned dielectric layer 102 by conventional electrochemical deposition. Note that patterned dielectric layer 102 is initially covered by barrier and copper seed layers 106 .
  • the electrochemical deposition process uses a specially formulated electrolyte 104 , which typically contains both chloride ions and organic additives. These organic additives can perform the functions of suppressing metal deposition (suppressor), leveling the deposited metal (leveler), or accelerating the metal deposition (accelerator).
  • the organic additives are typically selected to achieve void-free upper-filling or bottom-up filling of patterned features having sub-micrometer sizes.
  • the electrochemical deposition is performed by applying a voltage (V) between wafer 101 (cathode) and copper electrode 105 (anode).
  • V a voltage
  • This applied voltage determines the required potential value relative to a reference electrode (e.g. saturated calomel electrode, SCE), which is kept constant during a desired time of deposition.
  • SCE saturated calomel electrode
  • an excessive amount of copper must be formed over open areas 121 - 123 to ensure that patterned features 111 - 113 are properly filled.
  • the excessive copper deposited over open areas 121 - 123 is commonly referred to as ‘overburden’.
  • This overburden is typically removed by chemical mechanical polishing (CMP), thereby leaving only the copper formed in patterned features 111 - 113 .
  • CMP represents an additional process step that is required in view of conventional electrochemical deposition technology. It would therefore be desirable to have an ECM process which eliminates the need for a chemical mechanical polishing step.
  • the present invention provides a method of performing electrochemical deposition, wherein overburden is minimized.
  • electrochemical deposition is performed using a constant plating voltage (and a variable plating current) in an electrolyte that contains both suppressor molecules and accelerator molecules.
  • the constant plating voltage is selected such that the suppressor molecules in the electrolyte are predominantly active on the flat upper surface areas of the patterned dielectric layer, and the accelerator molecules in the electrolyte are predominantly active within the patterned features of the patterned dielectric layer.
  • metal is deposited at a relatively high rate within the patterned features, and at a relatively low rate on the flat upper surface areas of the patterned dielectric layer. Consequently, the patterned features are filled with metal before significant overburden can be formed over the flat upper surface areas of the patterned dielectric layer.
  • FIG. 1 is a schematic diagram of a conventional electrochemical deposition system.
  • FIG. 2 is a schematic diagram of an electrochemical deposition system in accordance with one embodiment of the present invention.
  • FIG. 3 is a graph illustrating the polarization curves that result when the potential of the copper electrode in the system of FIG. 2 is varied in the negative and positive directions.
  • FIG. 4 is a schematic diagram illustrating the relative adsorption rates of suppressor and accelerator molecules on advancing concave and convex surfaces.
  • FIG. 5A illustrates a dielectric layer that exhibits a relatively large pattern density.
  • FIG. 5B illustrates a dielectric layer that exhibits a relatively small pattern density.
  • FIG. 2 is a schematic diagram of an electrochemical deposition system 200 in accordance with one embodiment of the present invention.
  • ECD system 200 includes semiconductor wafer structure 201 having an overlying patterned dielectric layer 202 .
  • Patterned dielectric layer 202 includes patterned features (openings) 211 - 213 and dielectric regions 221 - 224 . The upper surfaces of dielectric regions 221 - 224 are substantially flat.
  • Wafer structure 201 and patterned dielectric layer 202 are immersed in electrolyte 204 , along with metal electrode 205 .
  • electrolyte 204 is an aqueous solution, which includes metal ions (e.g., copper), and both suppressor and accelerator molecules.
  • electrolyte 204 is highly acidic with a low copper content. In alternate embodiments, electrolyte 204 may have low or medium acidity and a high copper content. In yet other embodiments, electrolyte 204 may include ions of gold or silver or nickel or combinations of gold and/or silver and/or nickel ions instead of copper ions. In a particular embodiment, electrolyte 204 includes sulfuric acid having concentrations in the range of about 10 to 320 g/L, and cupric concentrations in the range of about 10 to 60 g/L. The suppressor molecules in electrolyte 204 may include, for example, polyethylene glycol (PEG) or polypropylene glycol (PPG).
  • PEG polyethylene glycol
  • PPG polypropylene glycol
  • the accelerator molecules in electrolyte 204 may include, for example, Na 2 [SO 3 (CH 2 ) 3 S] 2 sodium bis(3-sulfopropyl)disulfide (SPS), available from Rasching GmbH, Germany; H 2 [SO 3 (CH 2 ) 3 S] 2 ; (SPS), also available from Rasching GmbH, Germany; SO 3 H(CH 2 ) 3 SH; 3-mercaptopropylsulfonic acid (MPS), a monomer of SPS; Enthone ViaForm accelerator DF-74; and/or thyol sulfonate H 2 [SO 3 (CH 2 ) 3 SO] 2 (3-mercapto-propanesulfonate) (MPSA).
  • anode 205 is copper. However, other metals, such as gold, silver, and nickel can be used in other embodiments.
  • wafer structure 201 is grounded, and copper electrode 205 is held at a constant plating voltage V P .
  • a variable plating current I PV flows through the electrolyte 204 , thereby causing copper layer 203 to be deposited over patterned dielectric layer 202 .
  • the constant plating voltage V P is selected such that the overburden of copper layer 203 is minimized over the upper surfaces of dielectric regions 221 - 224 , while properly filling patterned features 211 - 213 with metal.
  • the constant plating voltage V P is selected in view of the characteristics of the metal being plated and the characteristics of electrolyte 204 , including the suppressor and accelerator used.
  • the deposition of copper layer 203 in electrolyte 204 is accompanied by the competitive adsorption of the suppressor and accelerator on the surface of copper electrode 205 .
  • a thin film of the suppressor molecules rapidly forms on the surface of this electrode 205 .
  • This thin film of suppressor molecules initially inhibits the deposition of copper layer 203 .
  • the accelerator molecules present in electrolyte 204 replace the thin film of suppressor molecules initially present on copper electrode 205 .
  • the variable plating current I PV is relatively low.
  • the variable plating current I PV increases, thereby increasing the deposition rate of copper layer 203 .
  • FIG. 3 is a graph 300 illustrating the polarization curves 301 and 302 that result when the potential of copper electrode 205 is swept in the negative direction.
  • the interplay of the competitive adsorption between the suppressor molecules and the accelerator molecules is shown by the hysteresis of the polarization curves 301 and 302 .
  • the variable plating current I PV i.e., copper deposition rate
  • the variable plating current I PV i.e., copper deposition rate
  • the variable plating current I PV i.e., copper deposition rate
  • the adsorption characteristics of the accelerator molecules strongly depend on the potential applied to copper electrode 205 , wherein the copper deposition rate increases rapidly as the potential of copper electrode 205 becomes more negative.
  • the rate at which the suppressor molecules are replaced with accelerator molecules also increases as the potential of copper electrode 205 becomes more negative.
  • FIG. 4 is a schematic diagram illustrating the relative adsorption rates of suppressor and accelerator molecules on advancing concave surfaces 401 - 402 and advancing convex surfaces 403 - 404 .
  • FIG. 5A illustrates a patterned dielectric layer 501 that exhibits a relatively high pattern density
  • FIG. 5B illustrates a patterned dielectric layer 502 that exhibits a relatively low pattern density.
  • patterned dielectric layers having a higher pattern density will have patterned features with a greater aspect ratio (i.e., greater height/width ratio).
  • the patterned features in dielectric layer 501 can be approximated by a first concave pattern 511
  • the patterned features in dielectric layer 502 can be approximated by a second concave pattern 512 .
  • the flat (i.e., less concave) upper surface areas of dielectric layer 501 are rapidly covered by a suppressor film, thereby inhibiting the deposition of copper.
  • These conditions may be represented by the polarization curves of FIG. 3 , wherein polarization curve 301 represents the relatively slow deposition rate of copper on the flat upper surface areas of dielectric layer 501 , and polarization curve 302 represents the relatively rapid deposition rate of copper in the high aspect ratio patterned features of dielectric layer 501 .
  • the constant plating voltage V P is applied to copper electrode 205 .
  • the constant plating voltage V P is selected in view of the polarization curves 301 and 302 of FIG. 3 . More specifically, the constant plating voltage V P is selected such that there is a significant difference between the plating currents associated with polarization curves 301 and 302 at the selected plating voltage V P .
  • the plating voltage V P is selected to be a negative voltage selected from the range that is greater than or equal to about ⁇ 0.2 Volts.
  • the plating voltage V P is selected to be a negative voltage selected from the range of about ⁇ 0.18 Volts to about ⁇ 0.05 Volts. In another embodiment, the plating voltage V P is selected to have a voltage of about ⁇ 0.15 Volts.
  • the current difference between polarization curves 301 and 302 is about 19.9 mA/cm 2 (2 ⁇ 10 ⁇ 2 ⁇ 1 ⁇ 10 ⁇ 4 A/cm 2 ).
  • the plating voltage V P is selected to achieve the maximum difference in the plating currents associated with polarization curves 301 and 302 .
  • copper layer 203 will be deposited in the following manner.
  • the accelerator molecules prevail within the ‘concave’ patterned features 211 - 213 .
  • copper is rapidly deposited to fill these patterned features 211 - 213 .
  • the copper deposition rate within patterned features 211 - 213 is proportional to the current density corresponding with the plating voltage V P on polarization curve 302 of FIG. 3 .
  • the copper deposition rate within patterned features 211 - 213 is proportional to 2 ⁇ 10 ⁇ 2 A/cm 2 .
  • the suppressor molecules prevail and strongly passivate the flat (non-concave) upper surfaces of the patterned dielectric regions 221 - 224 . That is, the suppressor molecules protect the flat upper surfaces of patterned dielectric regions 221 - 224 from copper deposition.
  • the copper deposition rate at the flat upper surfaces of dielectric regions 221 - 224 is proportional to the current density corresponding with the plating voltage V P on polarization curve 301 of FIG. 3 .
  • the copper deposition rate on the flat upper surfaces of dielectric regions 221 - 224 is proportional to 1 ⁇ 10 ⁇ 4 A/cm 2 .
  • the ratio of the copper deposition rate within patterned features 211 - 213 to the ratio of the copper deposition rate on dielectric regions 221 - 224 is about 200:1 (i.e., 2 ⁇ 10 ⁇ 2 :1 ⁇ 10 ⁇ 4 ).
  • patterned features 211 - 213 are filled, while the amount of overburden in copper layer 203 is advantageously minimized.
  • the overburden in copper layer 203 is reduced by a factor of at least about ten with respect to the prior art.
  • the minimized overburden still needs to be removed, typically by a CMP process.
  • the time (cost) of the CMP process is significantly reduced due to the relatively small thickness of the overburden.
  • the short CMP process creates an end structure having fewer surface defects.

Abstract

A method of performing electrochemical deposition is provided to minimize overburden. A constant plating voltage (and a variable plating current) is applied across a semiconductor structure (e.g., patterned dielectric layer) and a metal electrode, which are both submerged in an electrolyte that contains both suppressor and accelerator molecules. The constant plating voltage is selected such that the suppressor molecules are predominantly active on the flat upper surface of the patterned dielectric layer, and the accelerator molecules are predominantly active within the patterned features of the patterned dielectric layer. As a result, metal is deposited at a relatively high rate within the patterned features, and at a relatively low rate on the flat upper surface areas of the patterned dielectric layer. Consequently, the patterned features are filled with metal before significant overburden can be formed over the flat upper surface areas of the patterned dielectric layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to electrochemical metal deposition during fabrication of an integrated circuit. More specifically, the present invention relates to controlling the deposition rate of electrochemical metal deposition in different regions of an integrated circuit chip.
    • RELATED ART
  • Electrochemical metal deposition is used in semiconductor manufacture for on-chip wiring of integrated circuits. For example, electrochemical deposition of copper can be used to fill and/or coat different patterned features of an integrated circuit, including trenches and/or vias formed in dielectric layers on the wafer surface.
  • FIG. 1 is a schematic drawing of an electrochemical deposition system 100, wherein a patterned dielectric layer 102 is formed over a surface of wafer 101. Patterned dielectric layer 102 includes patterned features (vias/trenches) 111-113, and open areas 121-123. Copper layer 103 is formed over patterned dielectric layer 102 by conventional electrochemical deposition. Note that patterned dielectric layer 102 is initially covered by barrier and copper seed layers 106.
  • The electrochemical deposition process uses a specially formulated electrolyte 104, which typically contains both chloride ions and organic additives. These organic additives can perform the functions of suppressing metal deposition (suppressor), leveling the deposited metal (leveler), or accelerating the metal deposition (accelerator). The organic additives are typically selected to achieve void-free upper-filling or bottom-up filling of patterned features having sub-micrometer sizes.
  • The electrochemical deposition is performed by applying a voltage (V) between wafer 101 (cathode) and copper electrode 105 (anode). This applied voltage determines the required potential value relative to a reference electrode (e.g. saturated calomel electrode, SCE), which is kept constant during a desired time of deposition. As a result, a constant plating current IP flows between wafer 101 and copper electrode 105.
  • When Using Conventional Electrochemical deposition, an excessive amount of copper must be formed over open areas 121-123 to ensure that patterned features 111-113 are properly filled. The excessive copper deposited over open areas 121-123 is commonly referred to as ‘overburden’. This overburden is typically removed by chemical mechanical polishing (CMP), thereby leaving only the copper formed in patterned features 111-113. The CMP represents an additional process step that is required in view of conventional electrochemical deposition technology. It would therefore be desirable to have an ECM process which eliminates the need for a chemical mechanical polishing step.
    • SUMMARY
  • Accordingly, the present invention provides a method of performing electrochemical deposition, wherein overburden is minimized. In one embodiment, electrochemical deposition is performed using a constant plating voltage (and a variable plating current) in an electrolyte that contains both suppressor molecules and accelerator molecules. The constant plating voltage is selected such that the suppressor molecules in the electrolyte are predominantly active on the flat upper surface areas of the patterned dielectric layer, and the accelerator molecules in the electrolyte are predominantly active within the patterned features of the patterned dielectric layer. As a result, metal is deposited at a relatively high rate within the patterned features, and at a relatively low rate on the flat upper surface areas of the patterned dielectric layer. Consequently, the patterned features are filled with metal before significant overburden can be formed over the flat upper surface areas of the patterned dielectric layer.
  • The present invention will be more fully understood in view of the following description and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of a conventional electrochemical deposition system.
  • FIG. 2 is a schematic diagram of an electrochemical deposition system in accordance with one embodiment of the present invention.
  • FIG. 3 is a graph illustrating the polarization curves that result when the potential of the copper electrode in the system of FIG. 2 is varied in the negative and positive directions.
  • FIG. 4 is a schematic diagram illustrating the relative adsorption rates of suppressor and accelerator molecules on advancing concave and convex surfaces.
  • FIG. 5A illustrates a dielectric layer that exhibits a relatively large pattern density.
  • FIG. 5B illustrates a dielectric layer that exhibits a relatively small pattern density.
    •  DETAILED DESCRIPTION
  • FIG. 2 is a schematic diagram of an electrochemical deposition system 200 in accordance with one embodiment of the present invention. ECD system 200 includes semiconductor wafer structure 201 having an overlying patterned dielectric layer 202. Patterned dielectric layer 202 includes patterned features (openings) 211-213 and dielectric regions 221-224. The upper surfaces of dielectric regions 221-224 are substantially flat. Wafer structure 201 and patterned dielectric layer 202 are immersed in electrolyte 204, along with metal electrode 205. In general, electrolyte 204 is an aqueous solution, which includes metal ions (e.g., copper), and both suppressor and accelerator molecules. In one embodiment, electrolyte 204 is highly acidic with a low copper content. In alternate embodiments, electrolyte 204 may have low or medium acidity and a high copper content. In yet other embodiments, electrolyte 204 may include ions of gold or silver or nickel or combinations of gold and/or silver and/or nickel ions instead of copper ions. In a particular embodiment, electrolyte 204 includes sulfuric acid having concentrations in the range of about 10 to 320 g/L, and cupric concentrations in the range of about 10 to 60 g/L. The suppressor molecules in electrolyte 204 may include, for example, polyethylene glycol (PEG) or polypropylene glycol (PPG). The accelerator molecules in electrolyte 204 may include, for example, Na2 [SO3 (CH2)3S]2 sodium bis(3-sulfopropyl)disulfide (SPS), available from Rasching GmbH, Germany; H2 [SO3 (CH2)3S]2; (SPS), also available from Rasching GmbH, Germany; SO3H(CH2)3SH; 3-mercaptopropylsulfonic acid (MPS), a monomer of SPS; Enthone ViaForm accelerator DF-74; and/or thyol sulfonate H2 [SO3 (CH2)3SO]2 (3-mercapto-propanesulfonate) (MPSA). In the described embodiments, anode 205 is copper. However, other metals, such as gold, silver, and nickel can be used in other embodiments.
  • In accordance with one embodiment of the present invention, wafer structure 201 is grounded, and copper electrode 205 is held at a constant plating voltage VP. Under these conditions, a variable plating current IPV flows through the electrolyte 204, thereby causing copper layer 203 to be deposited over patterned dielectric layer 202. As described in more detail below, the constant plating voltage VP is selected such that the overburden of copper layer 203 is minimized over the upper surfaces of dielectric regions 221-224, while properly filling patterned features 211-213 with metal. The constant plating voltage VP is selected in view of the characteristics of the metal being plated and the characteristics of electrolyte 204, including the suppressor and accelerator used.
  • The deposition of copper layer 203 in electrolyte 204 is accompanied by the competitive adsorption of the suppressor and accelerator on the surface of copper electrode 205. When copper electrode 205 is immersed in electrolyte 204, a thin film of the suppressor molecules rapidly forms on the surface of this electrode 205. This thin film of suppressor molecules initially inhibits the deposition of copper layer 203. Under catholic polarization (i.e., applying a negative voltage to copper electrode 205 relative to wafer 201), the accelerator molecules present in electrolyte 204 replace the thin film of suppressor molecules initially present on copper electrode 205. At this time, the variable plating current IPV is relatively low. As the accelerator molecules cover an increasing surface area of copper electrode 205, the variable plating current IPV increases, thereby increasing the deposition rate of copper layer 203.
  • FIG. 3 is a graph 300 illustrating the polarization curves 301 and 302 that result when the potential of copper electrode 205 is swept in the negative direction. The interplay of the competitive adsorption between the suppressor molecules and the accelerator molecules is shown by the hysteresis of the polarization curves 301 and 302. When the thin film of suppressor molecules are initially present on copper electrode 205 (i.e., the suppressor molecules are dominant), the variable plating current IPV (i.e., copper deposition rate) through the electrolyte 204 follows polarization curve 301. However, when the thin film of suppressor molecules on copper electrode 205 have been replaced by accelerator molecules (i.e., the accelerator molecules are dominant), the variable plating current IPV (i.e., copper deposition rate) follows polarization curve 302.
  • The adsorption characteristics of the accelerator molecules strongly depend on the potential applied to copper electrode 205, wherein the copper deposition rate increases rapidly as the potential of copper electrode 205 becomes more negative. The rate at which the suppressor molecules are replaced with accelerator molecules also increases as the potential of copper electrode 205 becomes more negative.
  • The adsorption of suppressor and accelerator molecules also strongly depends on the type and parameters of the local surface area curvature on different sites of patterned dielectric layer 202. For example, the adsorption of accelerator molecules increases on advancing concave sites, and decreases on advancing convex sites. In contrast, the adsorption of suppressor molecules decreases on advancing concave sites, and increases on advancing convex sites. FIG. 4 is a schematic diagram illustrating the relative adsorption rates of suppressor and accelerator molecules on advancing concave surfaces 401-402 and advancing convex surfaces 403-404.
  • Note that wafers that exhibit dielectric layers with different pattern densities can be viewed as presenting advancing concave surfaces of differing sizes. For example, FIG. 5A illustrates a patterned dielectric layer 501 that exhibits a relatively high pattern density and FIG. 5B illustrates a patterned dielectric layer 502 that exhibits a relatively low pattern density. In general, patterned dielectric layers having a higher pattern density will have patterned features with a greater aspect ratio (i.e., greater height/width ratio). The patterned features in dielectric layer 501 can be approximated by a first concave pattern 511, and the patterned features in dielectric layer 502 can be approximated by a second concave pattern 512.
  • Using the same electrochemical deposition parameters, copper will be deposited more rapidly in the patterned features of patterned dielectric layer 501 than in the patterned features of patterned dielectric layer 502. This is because the patterned features of patterned dielectric layer 501 present a more concave advancing pattern than the patterned features of patterned dielectric layer 502 (i.e., pattern 511 is more concave than pattern 512). Thus, more accelerator molecules (and fewer suppressor molecules) will affect the metal deposition within the patterned features of patterned dielectric layer 501. In general, the reaction kinetics result in high deposition rates and bottom-up filling inside high aspect ratio patterned features (e.g., aspect ratios greater than three). The flat (i.e., less concave) upper surface areas of dielectric layer 501 are rapidly covered by a suppressor film, thereby inhibiting the deposition of copper. These conditions may be represented by the polarization curves of FIG. 3, wherein polarization curve 301 represents the relatively slow deposition rate of copper on the flat upper surface areas of dielectric layer 501, and polarization curve 302 represents the relatively rapid deposition rate of copper in the high aspect ratio patterned features of dielectric layer 501.
  • Returning now to FIG. 2, at the beginning of the electrochemical deposition process (i.e., before copper layer 203 is formed) the constant plating voltage VP is applied to copper electrode 205. The constant plating voltage VP is selected in view of the polarization curves 301 and 302 of FIG. 3. More specifically, the constant plating voltage VP is selected such that there is a significant difference between the plating currents associated with polarization curves 301 and 302 at the selected plating voltage VP. In accordance with one embodiment of the present invention, the plating voltage VP is selected to be a negative voltage selected from the range that is greater than or equal to about −0.2 Volts. In an alternate embodiment, the plating voltage VP is selected to be a negative voltage selected from the range of about −0.18 Volts to about −0.05 Volts. In another embodiment, the plating voltage VP is selected to have a voltage of about −0.15 Volts.
  • As illustrated in FIG. 3, there is a significant difference between the polarization curves 301 and 302 within the above-described ranges. For example, at a plating voltage VP of about −0.15 Volts, the current difference between polarization curves 301 and 302 is about 19.9 mA/cm2 (2×10−2−1×10−4 A/cm2). In one embodiment, the plating voltage VP is selected to achieve the maximum difference in the plating currents associated with polarization curves 301 and 302.
  • Having selected the plating voltage VP in the above-described manner, copper layer 203 will be deposited in the following manner. At the selected plating voltage VP, the accelerator molecules prevail within the ‘concave’ patterned features 211-213. As a result, copper is rapidly deposited to fill these patterned features 211-213. The copper deposition rate within patterned features 211-213 is proportional to the current density corresponding with the plating voltage VP on polarization curve 302 of FIG. 3. Thus, the copper deposition rate within patterned features 211-213 is proportional to 2×10−2 A/cm2.
  • Conversely, at the selected plating voltage VP, the suppressor molecules prevail and strongly passivate the flat (non-concave) upper surfaces of the patterned dielectric regions 221-224. That is, the suppressor molecules protect the flat upper surfaces of patterned dielectric regions 221-224 from copper deposition. The copper deposition rate at the flat upper surfaces of dielectric regions 221-224 is proportional to the current density corresponding with the plating voltage VP on polarization curve 301 of FIG. 3. Thus, the copper deposition rate on the flat upper surfaces of dielectric regions 221-224 is proportional to 1×10−4 A/cm2.
  • In the described example, the ratio of the copper deposition rate within patterned features 211-213 to the ratio of the copper deposition rate on dielectric regions 221-224 is about 200:1 (i.e., 2×10−2:1×10−4). As a result, patterned features 211-213 are filled, while the amount of overburden in copper layer 203 is advantageously minimized. In accordance with one embodiment, the overburden in copper layer 203 is reduced by a factor of at least about ten with respect to the prior art. The minimized overburden still needs to be removed, typically by a CMP process. However, the time (cost) of the CMP process is significantly reduced due to the relatively small thickness of the overburden. Moreover, the short CMP process creates an end structure having fewer surface defects.
  • Note that if the constant plating voltage VP is more negative than −0.2 Volts, the predominant role of the suppressor versus accelerator on the flat upper surfaces of dielectric regions 221-224 diminishes, as does the surface passivation. That is, polarization curves 301 and 302 approach one another, thereby leading to an increase in the overburden of copper layer 203.
  • Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. For example, although the present invention was described in connection with specific materials (i.e., copper, gold, silver, or their alloys), it is understood that other materials can be used to implement other embodiments in accordance with the teachings provided herein. Thus, the invention is limited only by the following claims.

Claims (11)

1. An electrochemical deposition method comprising:
immersing a semiconductor structure in a plating solution containing an accelerator and a suppressor, wherein the semiconductor structure includes an upper surface having one or more flat regions and one or more patterned features;
immersing a metal electrode in the plating solution; and
applying a plating voltage across the semiconductor structure and the metal electrode, wherein the plating voltage is selected such that metal is deposited in the one or more patterned features at a first rate, and deposited on the one or more flat regions at a second rate, wherein the first rate is substantially greater than the second rate.
2. The method of claim 1, further comprising selecting the plating voltage such that the first rate is at least about 10 times greater than the second rate.
3. The method of claim 1, wherein the plating voltage is constant.
4. The method of claim 1, wherein the plating voltage is applied by grounding the semiconductor structure and applying a negative voltage to the metal electrode.
5. The method of claim 1, wherein the negative voltage is greater than or equal to about −0.2 Volts.
6. The method of claim 1, wherein the metal electrode comprises copper.
7. The method of claim 1, wherein the plating solution comprises sulfuric acid and copper.
8. The method of claim 1, wherein the semiconductor structure comprises a wafer and a patterned dielectric layer, wherein the patterned features are located in the patterned dielectric layer.
9. The method of claim 1, wherein the one or more patterned features have an aspect ratio greater than three.
10. The method of claim 1, wherein the one or more patterned features are concave.
11. The method of claim 1, wherein the plating voltage is selected to maximize the difference between the first rate and the second rate.
US11/559,480 2006-11-14 2006-11-14 Self Terminating Overburden Free Plating (STOP) Of Metals On Patterned Wafers Abandoned US20080110759A1 (en)

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Citations (6)

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Publication number Priority date Publication date Assignee Title
US4619749A (en) * 1985-03-25 1986-10-28 Nusbaum Ronald C System for extracting silver from liquid solutions
US6551483B1 (en) * 2000-02-29 2003-04-22 Novellus Systems, Inc. Method for potential controlled electroplating of fine patterns on semiconductor wafers
US20040045832A1 (en) * 1999-10-14 2004-03-11 Nicholas Martyak Electrolytic copper plating solutions
US6793796B2 (en) * 1998-10-26 2004-09-21 Novellus Systems, Inc. Electroplating process for avoiding defects in metal features of integrated circuit devices
US20060081477A1 (en) * 2000-12-18 2006-04-20 Basol Bulent M Method and apparatus for establishing additive differential on surfaces for preferential plating
US20060252254A1 (en) * 2005-05-06 2006-11-09 Basol Bulent M Filling deep and wide openings with defect-free conductor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4619749A (en) * 1985-03-25 1986-10-28 Nusbaum Ronald C System for extracting silver from liquid solutions
US6793796B2 (en) * 1998-10-26 2004-09-21 Novellus Systems, Inc. Electroplating process for avoiding defects in metal features of integrated circuit devices
US20040045832A1 (en) * 1999-10-14 2004-03-11 Nicholas Martyak Electrolytic copper plating solutions
US6551483B1 (en) * 2000-02-29 2003-04-22 Novellus Systems, Inc. Method for potential controlled electroplating of fine patterns on semiconductor wafers
US20060081477A1 (en) * 2000-12-18 2006-04-20 Basol Bulent M Method and apparatus for establishing additive differential on surfaces for preferential plating
US20060252254A1 (en) * 2005-05-06 2006-11-09 Basol Bulent M Filling deep and wide openings with defect-free conductor

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