US20080105919A1 - Non-volatile memory device having separate charge trap patterns and method of fabricating the same - Google Patents
Non-volatile memory device having separate charge trap patterns and method of fabricating the same Download PDFInfo
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- US20080105919A1 US20080105919A1 US11/819,850 US81985007A US2008105919A1 US 20080105919 A1 US20080105919 A1 US 20080105919A1 US 81985007 A US81985007 A US 81985007A US 2008105919 A1 US2008105919 A1 US 2008105919A1
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.
Description
- 1. Field of the Invention
- Embodiments of the present invention relate to a non-volatile semiconductor device and a method of fabricating the same. More particularly, embodiments of the present invention relate to a non-volatile memory device having separate charge trap patterns and a method of fabricating the same.
- 2. Description of the Related Art
- Semiconductor memory devices storing data may be classified into volatile memory devices and non-volatile memory devices. While the volatile memory devices lose stored data when a power supply is interrupted, the non-volatile memory devices retain the stored data even when the power supply is interrupted. Accordingly, non-volatile memory devices, e.g., flash memory devices, find wide applications in portable storage devices or mobile telecommunication systems.
- Meanwhile, as electronic systems gradually become smaller and require low-power consumption components, the flash memory devices may have to be highly integrated. Therefore, the size of a gate constituting a unit cell of the flash memory device may also have to be scaled down.
- Recently, to scale down the size of the gate, a technology of fabricating the flash memory cell by forming a charge trap layer and a control gate on an active region having a fin structure has been developed. Also, a technology employing an insulating layer, e.g., a silicon nitride layer, as the charge trap layer may be considered. NAND-type flash memory devices may be especially amenable to high integration because a number of cells share one contact.
-
FIG. 1 illustrates a cross-sectional view taken along a word line direction of unit cells of a related art NAND-type flash memory device having a charge trap layer. - Referring to
FIG. 1 , first andsecond fins semiconductor substrate 11 by sinking anisolation trench 13T. Anisolation layer 13 may partially fill theisolation trench 13T. The first andsecond fins isolation layer 13. - A
charge trap layer 17 may be applied along a surface of theisolation layer 13, and surfaces of the first andsecond fins isolation layer 13. Thecharge trap layer 17 may be, e.g., a silicon nitride layer. A first tunnel dielectric layer 15A may be between thecharge trap layer 17 and thefirst fin 12A, and a second tunneldielectric layer 15B may be between thecharge trap layer 17 and thesecond fin 12B. - A
control gate electrode 21 may cross over the first andsecond fins control gate electrode 21 may serve as a word line. A controldielectric layer 19 may be between thecontrol gate electrode 21 and thecharge trap layer 17. - Flash memory cells C1 and C2 may be provided at crossing points of the
control gate electrode 21 and thefins control gate electrode 21 and thefirst fin 12A, and the second flash memory cell C2 may be provided at the crossing point of thecontrol gate electrode 21 and thesecond fin 12B. - Electrons may be injected into the
charge trap layer 17 by a program operation of the memory cells C1 and C2. The electrons may be injected into thecharge trap layer 17 between thefirst fin 12A and thecontrol gate electrode 21 by the program operation of the first flash memory cell C1. The electrons may also be similarly injected into thecharge trap layer 17 between thesecond fin 12B and thecontrol gate electrode 21 by the program operation of the second flash memory cell C2. - However, the
charge trap layers 17 of the first and second flash memory cells C1 and C2 may have a connected structure. The connected structure of thecharge trap layers 17 may provide a path for spreading charges. That is, the electrons injected into thecharge trap layer 17 may be spread to an adjacent region due to the connected structure of thecharge trap layers 17, as indicated by the arrows inFIG. 1 . The charge spreading may lead to bad data retention of the memory cells C1 and C2 and malfunction of adjacent memory cells. - The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
- Embodiments of the present invention are therefore directed to non-volatile memory device, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
- It is therefore a feature of an embodiment of the present invention to provide a non-volatile memory device having separate charge trap patterns in order to prevent charge spreading.
- It is therefore another feature of an embodiment of the present invention to provide a method of fabricating a non-volatile memory device having separate charge trap patterns in order to prevent charge spreading.
- At least one of the above and other features and advantages of the present invention may be realized by providing a non-volatile memory device that may include an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.
- The first and second charge trap patterns may each be an insulating layer. The first and second charge trap patterns may be each be a nitride layer. The first and second charge trap patterns may cover parts of the first and second fins projecting from the isolation layer. A distance between the first and second charge trap patterns may be smaller than a resolution limit of a photolithography process. A tunnel dielectric layer may be between the first and second charge trap patterns, and the first and second fins. The control gate electrode may cover parts of the first and second fins projecting from the isolation layer. A control dielectric layer may be at a lower part of the control gate electrode. The control dielectric layer may be between the first and second charge trap patterns and the control gate electrode, and the control dielectric layer may extend to be in contact with the isolation layer between the first and second charge trap patterns.
- At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating a non-volatile memory device, which may include forming an isolation trench in a semiconductor substrate, the isolation trench defining first and second fins, forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.
- The charge trap patterns may each be an insulating layer. The charge trap patterns may each be a nitride layer. Forming the first and second charge trap patterns may include forming a charge trap layer along a surface of the isolation layer and surfaces of the fins projecting from the isolation layer, forming sacrificial patterns covering the charge trap layer on the fins and exposing the charge trap layer on the isolation layer, and removing the exposed charge trap layer. The sacrificial patterns may be formed of a material having an etch selectivity with respect to the charge trap layer. Forming the sacrificial patterns may include forming a sacrificial layer on the charge trap layer, forming a capping pattern partially filling a gap between the first and second fins, the sacrificial layer on the isolation layer being covered by the capping pattern and the sacrificial layer projecting from the capping pattern being exposed, oxidizing the exposed sacrificial layer, and removing the capping pattern and the sacrificial layer remaining under the capping pattern. The sacrificial layer may be formed from a material having an etch selectivity with respect to the charge trap layer. The sacrificial layer may be formed from silicon. Forming the capping pattern may include forming a capping layer filling a gap between the first and second fins, and etching-back the capping layer. The capping pattern may be formed of a material layer having an etch selectivity with respect to the sacrificial layer. The capping pattern may be formed from nitride.
- The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
-
FIG. 1 illustrates a cross-sectional view of a related art non-volatile memory device having a charge trap layer; -
FIG. 2 illustrates a plan view of a cell array region of a non-volatile memory device according to an exemplary embodiment of the present invention; -
FIG. 3 illustrates a cross-sectional view of a non-volatile memory device according to an exemplary embodiment of the present invention; and -
FIGS. 4 to 12 illustrate cross-sectional views of stages of a method of fabricating a non-volatile memory device according to an exemplary embodiment of the present invention. - In
FIGS. 3 to 12 , section “1” is a cross-sectional view taken along line I-I′ ofFIG. 2 , and section “2” is a cross-sectional view taken along line II-II′ ofFIG. 2 . - Korean Patent Application No. 10-2006-0109534, filed on Nov. 7, 2006, in the Korean Intellectual Property Office, and entitled: “Non-Volatile Memory Device Having Separate Charge Trap Patterns and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.
- The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
- In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
- According to the present invention, a non-volatile memory device may include a first charge trap pattern on a first fin, and a second charge trap pattern on a second fin. The first and second charge trap patterns may be spaced apart from each other. The first and second charge trap patterns may be formed of an insulating layer, e.g., a nitride layer. The charge trap patterns may be insulated from adjacent charge trap patterns by a tunnel dielectric layer and a control dielectric layer, respectively. Thus, spreading of electrons injected into the charge trap patterns may be prevented. The non-volatile memory device may thus prevent charge spreading.
-
FIG. 2 illustrates a plan view of a cell array region of a NAND-type flash memory device according to an exemplary embodiment of the present invention, andFIG. 3 illustrates a cross-sectional view of a NAND-type flash memory device according to an exemplary embodiment of the present invention. InFIG. 3 , section “1” is a cross-sectional view taken along line I-I′ ofFIG. 2 , and section “2” is a cross-sectional view taken along line II-II′ ofFIG. 2 . - Referring to
FIGS. 2 and 3 , first tofourth fins isolation trenches 53T in asemiconductor substrate 51. Thesemiconductor substrate 51 may be, e.g., a silicon wafer, a silicon-on-insulator (SOI) wafer, etc. Anisolation layer 53 may partially fill theisolation trenches 53T between the first tofourth fins fourth fins isolation layer 53. Theisolation layer 53 may include an insulating layer, e.g., a silicon oxide layer. - A string selection line SSL and a ground selection line GSL may cross over the first to
fourth fins FIG. 2 , the first tofourth fins - Multiple
control gate electrodes 75 may be provided between the string selection line SSL and the ground selection line GSL. Thecontrol gate electrodes 75 may cross over the first tofourth fins control gate electrodes 75 may be substantially parallel to each other in a row direction. Thecontrol gate electrodes 75 may extend to fill gap regions between the first tofourth fins control gate electrodes 75 may serve as word lines. - The
control gate electrodes 75 may each include a firstconductive layer 71, a secondconductive layer 72 and a thirdconductive layer 73, which may be sequentially stacked. The string and ground selection lines SSL and GSL may also include the first to thirdconductive layers 71 to 73. The firstconductive layer 71 may be, e.g., a tantalum nitride (TaN) layer, the secondconductive layer 72 may be, e.g., a tungsten nitride (WN) layer, and the thirdconductive layer 73 may be, e.g., a tungsten (W) layer. -
Charge trap patterns control gate electrodes 75 and the first tofourth fins charge trap patterns charge trap patterns - The
charge trap patterns charge trap pattern 59A and a secondcharge trap pattern 59B. The firstcharge trap pattern 59A may cover a part of thefirst fin 55A projecting from theisolation layer 53. The secondcharge trap pattern 59B may cover a part of thesecond fin 55B projecting from theisolation layer 53. - As illustrated in the region shown in dotted line S of
FIG. 3 , the first and secondcharge trap patterns distance 59W between the first and secondcharge trap patterns charge trap patterns - A first
tunnel dielectric layer 57A may be between the firstcharge trap pattern 59A and thefirst fin 55A. A part of thefirst fin 55A projecting from theisolation layer 53 may be covered by the firsttunnel dielectric layer 57A. A secondtunnel dielectric layer 57B may be between the secondcharge trap pattern 59B and thesecond fin 55B. That is, the part of thesecond fin 55B projecting from theisolation layer 53 may also be covered by the secondtunnel dielectric layer 57B. - The
tunnel dielectric layers charge trap patterns fins tunnel dielectric layers - A
control dielectric layer 69 may be under thecontrol gate electrodes 75. Thecontrol dielectric layer 69 may be a different material layer from thecharge trap patterns control dielectric layer 69 may be, e.g., a silicon oxide layer, a high-k dielectric layer, etc. Thecharge trap patterns control gate electrodes 75 by thecontrol dielectric layer 69. Thecontrol dielectric layer 69 may be in contact with theisolation layer 53 between the first and secondcharge trap patterns -
Spacers 85 may be on sidewalls of thecontrol gate electrodes 75, the string selection line SSL, and the ground selection line GSL. Thespacers 85 may be formed of an insulating layer, e.g., a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. - Source and
drain regions fourth fins control gate electrodes 75, the string selection line SSL, and the ground selection line GSL. The source and drainregions - The
semiconductor substrate 51 having thecontrol gate electrodes 75, the string selection line SSL and the ground selection line GSL may be covered by aninterlayer insulating layer 91. The interlayer insulatinglayer 91 may be, e.g., a silicon oxide layer. - Bit lines BL may be on the
interlayer insulating layer 91. The bit lines BL may be parallel to each other in a column direction. The bit lines BL may be electrically connected to the source and drainregions 83, which may be adjacent to the string selection line SSL and opposite to the ground selection line GSL, by bit plugs 93 passing through the interlayer insulatinglayer 91. The bit lines BL and the bit plugs 93 may be formed of, e.g., a conductive layer. - According to the exemplary embodiment of the present invention described above, the first
charge trap pattern 59A may be insulated from the secondcharge trap pattern 59B by the firsttunnel dielectric layer 57A and thecontrol dielectric layer 69. The secondcharge trap pattern 59B may be insulated from the firstcharge trap pattern 59A by the secondtunnel dielectric layer 57B and thecontrol dielectric layer 69. That is, each of thecharge trap patterns tunnel dielectric layers control dielectric layer 69. - In the NAND-type flash memory device according to the exemplary embodiment of the present invention, electrons may be injected into the
charge trap patterns charge trap patterns tunnel dielectric layers control dielectric layer 69. Accordingly, data retention characteristics of thecharge trap patterns -
FIGS. 4 to 12 illustrate cross-sectional views of a method of fabricating a NAND-type flash memory device according to an exemplary embodiment of the present invention. ThroughoutFIGS. 4 to 12 , section “1” is a cross-sectional view taken along line I-I′ ofFIG. 2 . - Referring to
FIGS. 2 and 4 , first tofourth fins isolation trenches 53T in thesemiconductor substrate 51. Thefins first fin 55A, thesecond fin 55B, thethird fin 55C and thefourth fin 55D, which may be formed parallel to one another in a column direction. Theisolation trenches 53T may be formed by, e.g., a well-known patterning technique. - An insulating layer filling the
isolation trench 53T and covering a top surface of thesemiconductor substrate 51 may be formed. The insulating layer may be recessed to form anisolation layer 53, which may partially fill theisolation trench 53T. Theisolation layer 53 may remain at a lower region in theisolation trench 53T. Recessing the insulating layer may be performed by, e.g., an etch-back process, a chemical mechanical polishing (CMP) process, a combination thereof, etc. As a result, the first tofourth fins isolation layer 53. Also, the parts of the first tofourth fins isolation layer 53, may be exposed. - The
isolation layer 53 may be an insulating layer formed from, e.g., silicon oxide. Theisolation layer 53 may have a sidewall oxide layer (not illustrated) and a nitride layer liner (not illustrated), which may be formed along sidewalls of the first tofourth fins - Referring to
FIGS. 2 to 5 ,tunnel dielectric layers fourth fins tunnel dielectric layers isolation layer 53. Thus, the firsttunnel dielectric layer 57A may be formed along the surface of thefirst fin 55A, which may project from theisolation layer 53. The secondtunnel dielectric layer 57B may similarly be formed along the surface of thesecond fin 55B, which may project from theisolation layer 53. - Alternatively, the first and second
tunnel dielectric layers tunnel dielectric layers tunnel dielectric layers isolation layer 53. The following description will assume that thetunnel dielectric layers - A
charge trap layer 59 may be formed on thesemiconductor substrate 51 having thetunnel dielectric layers charge trap layer 59 may be formed from a material layer that is different from thetunnel dielectric layers charge trap layer 59 may be, e.g., a nitride layer, a silicon nitride layer, etc. For example, the silicon nitride layer may be formed employing, e.g., a low pressure chemical vapor deposition (LPCVD) apparatus, an ALD apparatus, etc. - The
charge trap layer 59 may be formed along the surfaces of thetunnel dielectric layers isolation layer 53. That is, thecharge trap layer 59 may cover thetunnel dielectric layers charge trap layer 59 may cover the top surface of theisolation layer 53. As a result, thecharge trap layer 59 formed on thefirst fin 55A and thecharge trap layer 59 formed on thesecond fin 55B may be connected to each other by thecharge trap layer 59 covering the top surface of theisolation layer 53. - Referring to
FIGS. 2 and 6 , asacrificial layer 61 may be formed along a surface of thecharge trap layer 59. Thesacrificial layer 61 may be a material layer having an etch selectivity with respect to thecharge trap layer 59. Thesacrificial layer 61 may also be a material layer having a high surface oxidation rate. Thesacrificial layer 61 may be, e.g., a silicon layer. The silicon layer may be formed employing, e.g., an LPCVD apparatus, an ALD apparatus, etc. - A
capping layer 63 may be formed on thesemiconductor substrate 51 having thesacrificial layer 61. Thecapping layer 63 may be a material layer with an etch selectivity with respect to thesacrificial layer 61. By “etch selectivity,” different etch rates under the same conditions may be observed for thecapping layer 63 and thesacrificial layer 61. Thecapping layer 63 may also be a material layer having a lower surface oxidation rate than thesacrificial layer 61. Thecapping layer 63 may be, e.g., a silicon nitride layer. Thecapping layer 63 may fill gap regions between the first tofourth fins capping layer 63 may be formed using, e.g., an LPCVD apparatus, a plasma-enhanced chemical vapor deposition (PECVD) apparatus, etc. - Referring to
FIGS. 2 and 7 , thecapping layer 63 may be etched-back, thereby forming acapping pattern 63′. The etch-back of thecapping layer 63 may be performed by a wet process employing, e.g., a phosphoric acid (H3PO4) solution. A dry etching process may also be used. Thecapping pattern 63′ may cover thesacrificial layer 61 on theisolation layer 53. Thecapping pattern 63′ may remain at lower parts in the gap regions between the first tofourth fins sacrificial layer 61 covering the part projecting from thecapping pattern 63′ may be exposed. -
Sacrificial patterns semiconductor substrate 51 having the partially exposedsacrificial layer 61 by employing, e.g., an oxidation process. The oxidation process may include, e.g., a thermal oxidation process, a plasma oxidation process, etc. When thesacrificial layer 61 is, e.g., a silicon layer, thesacrificial patterns charge trap layer 59 projecting from thecapping pattern 63′ may be covered by the first and secondsacrificial patterns sacrificial pattern 65A may cover a top surface of thefirst fin 55A, and the secondsacrificial pattern 65B may cover a top surface of thesecond fin 55B. - In this case, the
sacrificial layer 61 may remain under thecapping pattern 63′. The remainingsacrificial layer 61′ may cover thecharge trap layer 59 on theisolation layer 53. - During the oxidation process, formation of an oxidation layer on a surface of the
capping pattern 63′ may be prevented. If an oxidation layer, which may be very thin, is formed on the surface of thecapping pattern 63′, a surface of thecapping pattern 63′ may be exposed by employing a cleaning or etching process. The cleaning or etching process may employ a solution containing, e.g., hydrofluoric acid. - Referring to
FIGS. 2 and 8 , thecapping pattern 63′ may be removed to expose the remainingsacrificial layer 61′. The removal of thecapping pattern 63′ may be performed by, e.g., a wet process using phosphoric acid (H3PO4) solution. - Referring to
FIGS. 2 and 9 , the remainingsacrificial layer 61′ may be removed to expose thecharge trap layer 59 on theisolation layer 53. A sufficient etch selectivity may be obtained between thesacrificial patterns sacrificial layer 61′. Accordingly, the removal of the remainingsacrificial layer 61′ may be performed by either a dry or wet process. - The exposed
charge trap layer 59 may be removed to form first and secondcharge trap patterns charge trap layer 59 may be performed by an anisotropic etching process. Reactive ion etch (RIE) may be used as the anisotropic etching process. Alternatively, the removal of the exposedcharge trap layer 59 may be performed by an isotropic etching process. Thedistance 59W between the first and secondcharge trap patterns sacrificial patterns - As described above, the first and second
charge trap patterns charge trap patterns second fins distance 59W may be smaller than the resolution limit of the photolithography process. That is, the first and secondcharge trap patterns - Referring to
FIGS. 2 and 10 , thesacrificial patterns charge trap patterns sacrificial patterns - Consequently, the first
charge trap pattern 59A may cover the part of thefirst fin 55A projecting from theisolation layer 53, and the secondcharge trap pattern 59B may cover the part of thesecond fin 55B projecting from theisolation layer 53. Also, the firstcharge trap pattern 59A may be insulated from thefirst fin 55A by the firsttunnel dielectric layer 57A. The secondcharge trap pattern 59B may also be insulated from thesecond fin 55B by the secondtunnel dielectric layer 57B. - Referring to
FIGS. 2 and 11 , acontrol dielectric layer 69 may be formed on thesemiconductor substrate 51 having thecharge trap patterns control dielectric layer 69 may be, e.g., a silicon oxide layer, a high-k dielectric layer, etc. For example, thecontrol dielectric layer 69 may be, e.g., an aluminum oxide layer. - The
control dielectric layer 69 may be formed along the surfaces of thecharge trap patterns isolation layer 53. Between the first andsecond fins control dielectric layer 69 may be in contact with theisolation layer 53. -
Control gate electrodes 75 crossing over the first tofourth fins semiconductor substrate 51 having thecontrol dielectric layer 69. Thecontrol gate electrodes 75 may be formed by sequentially depositing and patterning a firstconductive layer 71, a secondconductive layer 72, and a thirdconductive layer 73. The firstconductive layer 71 may be, e.g., a TaN layer, the secondconductive layer 72 may be, e.g., a WN layer, and the thirdconductive layer 73 may be, e.g., a W layer. - While forming the
control gate electrodes 75, thecontrol dielectric layer 69 may also be patterned. In this case, thecontrol dielectric layer 69 may remain under thecontrol gate electrodes 75. Thecontrol gate electrodes 75 may also be formed to fill gap regions between the first tofourth fins charge trap patterns control gate electrodes 75 by thecontrol dielectric layer 69. - Referring to
FIGS. 2 and 12 , theinterlayer insulating layer 91 may be formed on thesemiconductor substrate 51 having thecontrol gate electrodes 75. The interlayer insulatinglayer 91 may be an insulating layer, e.g., a silicon oxide layer. Bit lines BL may be on theinterlayer insulating layer 91. The bit lines BL may be, e.g., a conductive layer. - Referring again to
FIGS. 2 and 3 , while forming thecontrol gate electrodes 75, the string selection line SSL and the ground selection line GSL may be formed. For example, the string selection line SSL may be formed of the first to thirdconductive layers 71 to 73, which may be sequentially stacked. - Then, source and drain
regions fourth fins control gate electrodes 75, the string selection line SSL, and the ground selection line GSL. The source and drainregions - The
spacers 85 may be formed on sidewalls of thecontrol gate electrodes 75, the string selection line SSL, and the ground selection line GSL. Thespacers 85 may be formed of an insulating layer, e.g., a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a combination thereof, etc. - Bit contact holes BC may pass through the interlayer insulating
layer 91, and the bit plugs 93 may fill the bit contact holes BC. The bit lines BL may be electrically connected to the source and drainregions 83, which may be adjacent to the string selection line SSL and opposite to the ground selection line GSL, by the bit plugs 93. The bit plugs 93 may be formed of, e.g., a conductive material. - Exemplary embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only, not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. For example, the present invention may also be applied to a NOR type non-volatile memory device and a method of fabricating the same.
Claims (20)
1. A non-volatile memory device, comprising:
an isolation trench in a semiconductor substrate;
an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench;
a control gate electrode crossing the first and second fins;
a first charge trap pattern between the first fin and the control gate electrode; and
a second charge trap pattern between the second fin and the control gate electrode.
2. The device as claimed in claim 1 , wherein the first and second charge trap patterns are each an insulating layer.
3. The device as claimed in claim 2 , wherein the first and second charge trap patterns are each a nitride layer.
4. The device as claimed in claim 1 , wherein the first and second charge trap patterns cover parts of the first and second fins projecting from the isolation layer.
5. The device as claimed in claim 1 , wherein a distance between the first and second charge trap patterns is smaller than a resolution limit of a photolithography process.
6. The device as claimed in claim 1 , further comprising a tunnel dielectric layer between the first and second charge trap patterns, and the first and second fins.
7. The device as claimed in claim 1 , wherein the control gate electrode covers parts of the first and second fins projecting from the isolation layer.
8. The device as claimed in claim 1 , further comprising a control dielectric layer at a lower part of the control gate electrode.
9. The device as claimed in claim 8 , wherein the control dielectric layer is between the first and second charge trap patterns and the control gate electrode, and the control dielectric layer extends to be in contact with the isolation layer between the first and second charge trap patterns.
10. A method of fabricating a non-volatile memory device, comprising:
forming an isolation trench in a semiconductor substrate, the isolation trench defining first and second fins;
forming an isolation layer partially filling the isolation trench;
forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer; and
forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.
11. The method as claimed in claim 10 , wherein the charge trap patterns are each an insulating layer.
12. The method as claimed in claim 10 , wherein the charge trap patterns are each a nitride layer.
13. The method as claimed in claim 10 , wherein forming the first and second charge trap patterns comprises:
forming a charge trap layer along a surface of the isolation layer and surfaces of the fins projecting from the isolation layer;
forming sacrificial patterns covering the charge trap layer on the fins and exposing the charge trap layer on the isolation layer; and
removing the exposed charge trap layer.
14. The method as claimed in claim 13 , wherein the sacrificial patterns are formed of a material having an etch selectivity with respect to the charge trap layer.
15. The method as claimed in claim 13 , wherein forming the sacrificial patterns comprises:
forming a sacrificial layer on the charge trap layer;
forming a capping pattern partially filling a gap between the first and second fins, the sacrificial layer on the isolation layer being covered by the capping pattern and the sacrificial layer projecting from the capping pattern being exposed;
oxidizing the exposed sacrificial layer; and
removing the capping pattern and the sacrificial layer remaining under the capping pattern.
16. The method as claimed in claim 15 , wherein the sacrificial layer is formed from a material having an etch selectivity with respect to the charge trap layer.
17. The method as claimed in claim 15 , wherein the sacrificial layer comprises silicon.
18. The method as claimed in claim 15 , wherein forming the capping pattern comprises:
forming a capping layer filling a gap between the first and second fins; and
etching-back the capping layer.
19. The method as claimed in claim 15 , wherein the capping pattern is formed of a material layer having an etch selectivity with respect to the sacrificial layer.
20. The method as claimed in claim 15 , wherein the capping pattern comprises nitride.
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KR1020060109534A KR100773356B1 (en) | 2006-11-07 | 2006-11-07 | Non-volatile memory device having separate charge trap patterns and method of fabricating the same |
KR10-2006-0109534 | 2006-11-07 |
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Also Published As
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US7951671B2 (en) | 2011-05-31 |
US20090221140A1 (en) | 2009-09-03 |
KR100773356B1 (en) | 2007-11-05 |
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