US20080064139A1 - Reliable printed wiring board assembly employing packages with solder joints and related assembly technique - Google Patents

Reliable printed wiring board assembly employing packages with solder joints and related assembly technique Download PDF

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Publication number
US20080064139A1
US20080064139A1 US11/938,727 US93872707A US2008064139A1 US 20080064139 A1 US20080064139 A1 US 20080064139A1 US 93872707 A US93872707 A US 93872707A US 2008064139 A1 US2008064139 A1 US 2008064139A1
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Prior art keywords
package
wiring board
printed wiring
pwb
solder balls
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US11/938,727
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Mumtaz Bora
Charles Girardot
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Kyocera Corp
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Kyocera Wireless Corp
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Priority to US11/938,727 priority Critical patent/US20080064139A1/en
Assigned to KYOCERA WIRELESS CORP. reassignment KYOCERA WIRELESS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BORA, MUMTAZ Y., GIRARDOT II, CHARLES E.
Publication of US20080064139A1 publication Critical patent/US20080064139A1/en
Assigned to KYOCERA CORPORATION reassignment KYOCERA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KYOCERA WIRELESS CORP.
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to semiconductor package assembly. More specifically, the invention relates to printed wiring board assembly techniques involving packages having solder bumps and other solder joints.
  • BGAs ball grid arrays
  • CSPs chip-scale packages
  • BGAs have a series of solder bumps (or “balls”) typically arranged on the bottom of the package.
  • the solder balls are used to attach the BGA package to a printed wiring board (“PWB”) using a reflow technique. During the reflow process, the solder balls are melted, and upon melting, the solder balls electrically and mechanically join various of the BGA package traces to various of the system PCB traces.
  • a PWB generally exhibits some degree of flexibility depending on its structural composition and its operating environment, whereas the packages mounted on the PWB remain relatively rigid by comparison. This difference can result in significant mechanical stresses being asserted between the PWB and the package, causing the physical connection between the package and the PWB to fail.
  • An example of a severe failure is when the solder ball is disconnected from a corresponding contact on the PWB, resulting in an interruption of the connection between appropriate contacts of the package and the PWB.
  • Such failures are typically remedied by way of expensive and time-consuming tear down and reassemble of the package and PWB, resulting in undesirable expense and inconvenience to both manufacturer and consumer.
  • an exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package.
  • An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in the anchor via is connected to or integral with a respective solder joint of the package.
  • the solder joint connected to the conductive material in the anchor via is situated proximate a periphery or corner of the package.
  • FIG. 1 illustrates an exemplary assembly employing a package with solder balls according to one embodiment of the present invention.
  • FIG. 2 illustrates a sectional view of the exemplary assembly of FIG. 1 .
  • FIGS. 3A through 3D illustrate exemplary assembly arrangements according to various stages of assembly according to one embodiment of the present invention.
  • FIG. 4 illustrates an exemplary assembly employing a package with solder balls according to another embodiment of the present invention.
  • PWB 102 comprises a multi-layer wiring board.
  • PWB 102 may comprise a plurality of conductive layers, typically metal, each conductive layer being separated by a dielectric layer, typically epoxy.
  • Package 104 is mounted on surface 103 of PWB 102 .
  • PWB 102 is capable of receiving a plurality of packages, e.g., two or more packages on the same surface or one package on a top surface and a second package on a bottom surface.
  • Package 104 may be any package having a plurality of solder joints, such as solder balls, for attaching to PWB 102 .
  • solder joints When mounted on PWB 102 , the solder joints provide an electrical connection and a conductive path between elements of package 104 and elements attached to PWB 102 , such as a supply voltage or a reference voltage, for example.
  • the solder joints mechanically attach package 104 to PWB 102 .
  • package 104 is typically attached to PWB 102 using a reflow process, whereby the solder balls are melted, and upon melting, the solder balls are mechanically and electrically attached to corresponding bump attach sites on PWB 102 .
  • bump attach sites 106 a through 106 e , and 121 are depicted and referenced in FIG. 1 .
  • bump attach sites comprise a metal layer formed and patterned on surface 103 of PWB 102 .
  • Certain bump attach sites are also connected to electrical traces formed on surface 103 for routing electrical signals to other elements (not shown).
  • bump attach site 106 d is connected to electrical trace 107 .
  • bump attach sites such as bump attach site 106 c and 121 are electrically connected to intermediate metal layers of PWB 103 or other metal layers on a surface (such as an opposite surface to surface 103 , for example) of PWB 102 .
  • bump attach site 106 c and 121 may be connected to an intermediate metal layer by way of interconnect vias 120 and 122 , respectively.
  • Interconnect vias 120 and 122 are generally formed by drilling through bump attach site 106 c and 121 , respectively, and through a dielectric layer below bump attach sites 106 c and 121 to the intermediate metal layer. Interconnect vias 120 and 122 are subsequently filled or plated with conductive material for providing an electrical connection between bump attach sites 106 c and 121 and their respective intermediate metal layer. The respective intermediate metal layers are then electrically connected to respective elements, typically through other traces and other metal interconnects.
  • PWB 102 further includes one or more anchor vias, such as anchor vias 116 and 118 .
  • Anchor vias 116 and 118 are also filled (whether partially or completely) with conductive material.
  • the conductive material filling anchor vias 116 and 118 comprises a portion of the solder ball attached to bump attach sites 106 a and 106 e , respectively.
  • anchor vias 116 and 118 are filled with conductive material prior to the process for attaching package to PWB 102 .
  • the conductive material in anchor vias 116 and 118 secure respective solder balls, and, thus, package 104 to PWB 102 , as described below.
  • Anchor vias 116 and 118 are distinguished from interconnect vias 120 and 122 , which function to provide an electrical connection between package 104 and a corresponding element attached to PWB 102 .
  • anchor vias 116 and 118 and any conductive material therein are “isolated” conductors. That is, anchor vias and any conductive material therein do not directly provide an electrical connection or a conductive path to an element attached to PWB 102 . Instead, as discussed above, anchor vias 116 and 118 and provide a cavity for conductive material situated therein to secure package 104 to PWB 102 .
  • electrical connections if any, to package 104 by way of solder bumps attached to bump attach sites 106 a and 106 e corresponding to anchor vias 116 and 118 , respectively, are provided by another electrical path, i.e., a path other than the conductive material in anchor vias 116 and 118 .
  • a separate conductive path such as a trace on surface 103 , may be provided for providing the requisite electrical connection.
  • assembly 200 shows a sectional view of assembly 100 of FIG. 1 taken at line 2 - 2 .
  • PWB 202 , surface 203 , package 204 , bump attach sites 206 a , 206 b , 206 c , 206 d and 206 e , anchor vias 216 and 218 , and interconnect via 220 correspond to PWB 102 , surface 103 , package 104 , bump attach sites 106 a , 106 b , 106 c , 106 d and 106 e , anchor vias 116 and 118 , and interconnect via 120 , respectively, in FIG. 1 .
  • PWB 202 comprises a multi-layer wiring board including metal layers separated by dielectric layers.
  • bump attach sites 206 a , 206 b , 206 c , 206 d and 206 e are formed from a first metal layer situated on surface 203 of PWB 202 .
  • dielectric layer 208 is situated below surface 203
  • intermediate metal layer 210 is situated below dielectric layer 208
  • dielectric layer 212 is situated below intermediate metal layer 210
  • intermediate metal layer 232 is situated below dielectric layer 212 .
  • Additional layers may be situated below intermediate metal layer 232 .
  • Package 204 is attached to PWB 202 by way solder balls attached to corresponding bump attach sites.
  • solder balls 214 a , 214 b , 214 c , 214 d and 214 e are connected to bump attach sites 206 a , 206 b , 206 c , 206 d and 206 e , respectively.
  • PWB 202 further comprises anchor vias 216 and 218 and interconnect via 220 .
  • Anchor vias 216 and 218 are filled (whether partially or completely) with conductive material, such as with a metal.
  • the conductive material in anchor vias 216 and 218 comprise a portion of solder balls 214 a and 214 e , respectively, as a result of the reflow process used to mount package 204 to PWB 202 .
  • anchor vias 216 and 218 extend from bump attach sites 206 a and 206 e , respectively, through dielectric layer 208 and to intermediate metal layer segments 217 and 219 , respectively. As shown in FIG.
  • anchor vias 216 and 218 extend through dielectric layer 208 to intermediate metal layer segments 217 and 219 , respectively.
  • anchor vias 216 and 218 and the conducive material therein and intermediate metal layer segments 217 and 219 comprise isolated conductors.
  • intermediate metal layer segments 217 and 219 are isolated metal layer segments.
  • intermediate metal layer segments 217 and 219 are directly electrically connected only to the conductive material in anchor vias 216 and 218 , respectively.
  • anchor vias 216 and 218 and the conducive material therein and intermediate metal layer segments 217 and 219 do not directly provide electrical connectivity to other components attached to PWB 202 .
  • anchor vias 216 and 218 and the conducive material therein and intermediate metal layer segments 217 and 219 are arranged to mechanically secure package 204 to PWB 202 .
  • any electrical connections required to be made to package 204 by way of solder bumps 214 a and 214 e are made by way through a separate conductive path, e.g., by way of separate electrical traces connected to bump attach sites 206 a and 206 e.
  • interconnect via 220 provides a direct electrical path to a component (not shown) attached to PWB 202 .
  • interconnect via 220 electrically connects solder ball 214 c and bump attach site 206 c to metal segment 227 by way of conductive material in interconnect via 220 , metal segment 223 and conductive material in interconnect via 225 .
  • Metal segment 227 then provides an electrical path to a corresponding component by way other conductive traces or interconnects.
  • anchor vias 216 and 218 and intermediate metal segments 217 and 219 are isolated.
  • any electrical connections required to be made to package 204 by way of solder bumps 214 a and 214 e are made by way through a separate conductive path.
  • FIGS. 1 and 2 result in significantly improving the reliability of assemblies 100 and 200 .
  • the reason is that anchor vias 216 and 218 and the conductive material therein, which are attached to or integral with solder balls 214 a and 214 e , more securely attach package 204 to PWB 202 .
  • interior walls defining anchor vias 216 and 218 and metal segments 217 and 219 along with the surface area of bump attach sites 206 a and 206 e provide significantly greater mounting surface for securing solder balls 214 a and 216 e to PWB 202 .
  • FIGS. 3A through 3D show cross-sectional views of some of the features of an assembly incorporating anchor vias in intermediate stages of assembly, formed in accordance with an exemplary embodiment of the invention. The steps for forming interconnect vias are not described for simplicity.
  • intermediate assembly 350 comprises PWB 302 .
  • Bump attach sites 306 a , 306 b , 306 c , 306 d and 306 e are formed from a first metal layer situated on one surface of PWB 302 .
  • Dielectric layer 308 is situated below bump attach sites 306 a , 306 b , 306 c , 306 d and 306 e .
  • Intermediate metal layer 310 is situated below dielectric layer 308
  • dielectric layer 312 is situated below intermediate metal layer 310 . Additional layers (not shown for simplicity) may be situated below dielectric layer 312 .
  • intermediate assembly 352 is shown according to another stage of assembly.
  • anchor vias 324 and 326 have been formed through bump attach sites 306 a , 306 b , 306 c , 306 d and 306 e , dielectric layer 308 , and a portion of intermediate metal segments 317 and 319 .
  • anchor vias 324 and 326 can be formed by drilling through bump attach sites 306 a , 306 b , 306 c , 306 d and 306 e , dielectric layer 308 , and a portion of intermediate metal segments 317 and 319 .
  • intermediate assembly 354 is shown according to another stage of assembly.
  • package 304 including a plurality of solder balls has been arranged over PWB 302 .
  • solder balls 314 a , 314 b , 314 c , 314 d and 314 e are interfaced with bump attach sites 306 a , 306 b , 306 c , 306 d and 306 e , respectively.
  • intermediate assembly 356 is shown according to another stage of assembly after a reflow process.
  • the solder balls of package 304 are melted, and upon melting, mechanically and electrically connect package 304 to PWB 302 .
  • a portion of solder balls 314 a and 314 e fill (partially or completely) vias 316 and 318 , respectively.
  • this particular arrangement more securely anchors package 304 to PWB 302 , thereby forming a significantly more reliable assembly.
  • very little expense is added to the assembly process, since the technique for forming anchor vias is similar to that used to form interconnect vias, and the technique used for filling anchor vias is similar to that used to fill interconnect vias.
  • FIG. 4 illustrates assembly 458 according to another embodiment of the invention.
  • PWB 402 , package 404 , bump attach sites 406 a , 406 b , 406 c , 406 d and 406 e , dielectric layer 408 , intermediate metal layer 410 , dielectric layer 412 , and solder balls 414 a , 414 b , 414 c , 414 d and 414 e correspond to PWB 202 , package 204 , bump attach sites 206 a , 206 b , 206 c , 206 d and 206 e , dielectric layer 208 , intermediate metal layer 210 , dielectric layer 212 , and solder balls 214 a , 214 b , 214 c , 214 d and 214 e in FIG. 2 .
  • anchor vias 428 and 430 of assembly 458 do not extend to intermediate metal layer 410 .
  • the conductive material in anchor vias 428 and 430 more clearly illustrates that the conductive material is “isolated” and does not provide a direct electrical connection or conductive path to another component (such as a supply voltage or a reference voltage, for example) attached to PWB 402 .
  • Any electrical connection required to be made to package 404 by way of solder bumps 414 a and 414 e and bump attach sites 406 a and 406 e are by way of a separate electrical connection. Referring back to FIG.
  • solder bumps such as BGAs and CSPs
  • present invention also could be applied to benefit other types of assemblies with packages employing other types of solder joint configurations.
  • certain non-solder ball packages employ “flat” joints. When such packages are connected to an anchor via in a printed wiring board, and solder flows in the anchor via during assembly, a similar improvement in the assembly reliability can be achieved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in the anchor via is connected to or integral with a respective solder joint of the package.

Description

    CROSS-REFERENCE AND PRIORITY CLAIM TO RELATED APPLICATION
  • This application is a division of, claims priority to, and wholly incorporates by reference U.S. patent application Ser. No. 10/956,405 filed Sep. 30, 2004.
  • FIELD OF THE INVENTION
  • The present invention relates to semiconductor package assembly. More specifically, the invention relates to printed wiring board assembly techniques involving packages having solder bumps and other solder joints.
  • BACKGROUND OF THE INVENTION
  • Packaging arrangements employing solder bumps are known. Examples include ball grid arrays (“BGAs”) and chip-scale packages (“CSPs”). By way of illustration, BGAs have a series of solder bumps (or “balls”) typically arranged on the bottom of the package. The solder balls are used to attach the BGA package to a printed wiring board (“PWB”) using a reflow technique. During the reflow process, the solder balls are melted, and upon melting, the solder balls electrically and mechanically join various of the BGA package traces to various of the system PCB traces.
  • A PWB generally exhibits some degree of flexibility depending on its structural composition and its operating environment, whereas the packages mounted on the PWB remain relatively rigid by comparison. This difference can result in significant mechanical stresses being asserted between the PWB and the package, causing the physical connection between the package and the PWB to fail. An example of a severe failure is when the solder ball is disconnected from a corresponding contact on the PWB, resulting in an interruption of the connection between appropriate contacts of the package and the PWB. Such failures are typically remedied by way of expensive and time-consuming tear down and reassemble of the package and PWB, resulting in undesirable expense and inconvenience to both manufacturer and consumer.
  • Existing approaches for resolving this problem have a number of drawbacks. For example, the use of expensive rigid boards significantly raises costs. In addition, such rigid boards typically employ insulating layers comprising epoxy and glass, which, among other problems, are difficult to drill, e.g., for forming vias. Consequently, assembly productivity is reduced. Another approach is to increase the size of the solder balls used to connect packages and PWBs. However, increasing the volume of the solder balls between the surface of the package and the PWB can result in bridging adjacent solder balls, thereby undesirably shorting contacts, which can result in malfunctions and/or damage.
  • Accordingly, there remains a strong need in the art to provide a cost effective and reliable assembly for printed wiring board and packages employing solder joints.
  • SUMMARY OF THE INVENTION
  • An assembly for printed wiring boards and packages employing solder joints and related assembly technique are disclosed which address and resolve one or more of the disadvantages associated with conventional assembly arrangements, as discussed above.
  • By way of illustration, an exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in the anchor via is connected to or integral with a respective solder joint of the package. In one embodiment, the solder joint connected to the conductive material in the anchor via is situated proximate a periphery or corner of the package. As discussed below, the particular arrangement of this assembly significantly improves reliability.
  • Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates an exemplary assembly employing a package with solder balls according to one embodiment of the present invention.
  • FIG. 2 illustrates a sectional view of the exemplary assembly of FIG. 1.
  • FIGS. 3A through 3D illustrate exemplary assembly arrangements according to various stages of assembly according to one embodiment of the present invention.
  • FIG. 4 illustrates an exemplary assembly employing a package with solder balls according to another embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The drawings and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention which use the principles of the present invention are not specifically described herein and are not specifically illustrated by the present drawings. It is noted that, for ease of illustration, the various elements shown in the drawings are not drawn to scale.
  • Referring first to FIG. 1, there is shown a top view of exemplary assembly 100 including PWB 102 and package 104 according to one embodiment of the invention. PWB 102 comprises a multi-layer wiring board. For example, PWB 102 may comprise a plurality of conductive layers, typically metal, each conductive layer being separated by a dielectric layer, typically epoxy. Package 104 is mounted on surface 103 of PWB 102. In certain embodiments, PWB 102 is capable of receiving a plurality of packages, e.g., two or more packages on the same surface or one package on a top surface and a second package on a bottom surface.
  • Package 104 may be any package having a plurality of solder joints, such as solder balls, for attaching to PWB 102. When mounted on PWB 102, the solder joints provide an electrical connection and a conductive path between elements of package 104 and elements attached to PWB 102, such as a supply voltage or a reference voltage, for example. In addition, the solder joints mechanically attach package 104 to PWB 102.
  • In an example embodiment where package 104 employs solder balls, package 104 is typically attached to PWB 102 using a reflow process, whereby the solder balls are melted, and upon melting, the solder balls are mechanically and electrically attached to corresponding bump attach sites on PWB 102. By way of illustration, bump attach sites 106 a through 106 e, and 121 are depicted and referenced in FIG. 1. Generally, bump attach sites comprise a metal layer formed and patterned on surface 103 of PWB 102. Certain bump attach sites are also connected to electrical traces formed on surface 103 for routing electrical signals to other elements (not shown). For example, bump attach site 106 d is connected to electrical trace 107. Other bump attach sites, such as bump attach site 106 c and 121 are electrically connected to intermediate metal layers of PWB 103 or other metal layers on a surface (such as an opposite surface to surface 103, for example) of PWB 102. For example, bump attach site 106 c and 121 may be connected to an intermediate metal layer by way of interconnect vias 120 and 122, respectively.
  • Interconnect vias 120 and 122 are generally formed by drilling through bump attach site 106 c and 121, respectively, and through a dielectric layer below bump attach sties 106 c and 121 to the intermediate metal layer. Interconnect vias 120 and 122 are subsequently filled or plated with conductive material for providing an electrical connection between bump attach sites 106 c and 121 and their respective intermediate metal layer. The respective intermediate metal layers are then electrically connected to respective elements, typically through other traces and other metal interconnects.
  • Continuing with FIG. 1, PWB 102 further includes one or more anchor vias, such as anchor vias 116 and 118. Anchor vias 116 and 118 are also filled (whether partially or completely) with conductive material. Typically, the conductive material filling anchor vias 116 and 118 comprises a portion of the solder ball attached to bump attach sites 106 a and 106 e, respectively. In other embodiments, anchor vias 116 and 118 are filled with conductive material prior to the process for attaching package to PWB 102. In assembly 100, the conductive material in anchor vias 116 and 118 secure respective solder balls, and, thus, package 104 to PWB 102, as described below.
  • Anchor vias 116 and 118 are distinguished from interconnect vias 120 and 122, which function to provide an electrical connection between package 104 and a corresponding element attached to PWB 102. In contrast, anchor vias 116 and 118 and any conductive material therein are “isolated” conductors. That is, anchor vias and any conductive material therein do not directly provide an electrical connection or a conductive path to an element attached to PWB 102. Instead, as discussed above, anchor vias 116 and 118 and provide a cavity for conductive material situated therein to secure package 104 to PWB 102. Thus, electrical connections, if any, to package 104 by way of solder bumps attached to bump attach sites 106 a and 106 e corresponding to anchor vias 116 and 118, respectively, are provided by another electrical path, i.e., a path other than the conductive material in anchor vias 116 and 118. By way of illustration, a separate conductive path, such as a trace on surface 103, may be provided for providing the requisite electrical connection.
  • Referring to FIG. 2, assembly 200 shows a sectional view of assembly 100 of FIG. 1 taken at line 2-2. In FIG. 2, PWB 202, surface 203, package 204, bump attach sites 206 a, 206 b, 206 c, 206 d and 206 e, anchor vias 216 and 218, and interconnect via 220 correspond to PWB 102, surface 103, package 104, bump attach sites 106 a, 106 b, 106 c, 106 d and 106 e, anchor vias 116 and 118, and interconnect via 120, respectively, in FIG. 1.
  • In the example embodiment shown in FIG. 2, PWB 202 comprises a multi-layer wiring board including metal layers separated by dielectric layers. Typically, bump attach sites 206 a, 206 b, 206 c, 206 d and 206 e are formed from a first metal layer situated on surface 203 of PWB 202. As shown in FIG. 2, dielectric layer 208 is situated below surface 203, intermediate metal layer 210 is situated below dielectric layer 208, dielectric layer 212 is situated below intermediate metal layer 210, and intermediate metal layer 232 is situated below dielectric layer 212. Additional layers (not shown for simplicity) may be situated below intermediate metal layer 232. Package 204 is attached to PWB 202 by way solder balls attached to corresponding bump attach sites. For example, solder balls 214 a, 214 b, 214 c, 214 d and 214 e are connected to bump attach sites 206 a, 206 b, 206 c, 206 d and 206 e, respectively.
  • Continuing with FIG. 2, PWB 202 further comprises anchor vias 216 and 218 and interconnect via 220. Anchor vias 216 and 218 are filled (whether partially or completely) with conductive material, such as with a metal. In one embodiment, the conductive material in anchor vias 216 and 218 comprise a portion of solder balls 214 a and 214 e, respectively, as a result of the reflow process used to mount package 204 to PWB 202. In the particular embodiment shown in FIG. 2, anchor vias 216 and 218 extend from bump attach sites 206 a and 206 e, respectively, through dielectric layer 208 and to intermediate metal layer segments 217 and 219, respectively. As shown in FIG. 2, the conductive material in anchor vias 216 and 218 extend through dielectric layer 208 to intermediate metal layer segments 217 and 219, respectively. It is noted that anchor vias 216 and 218 and the conducive material therein and intermediate metal layer segments 217 and 219 comprise isolated conductors. Specifically, intermediate metal layer segments 217 and 219 are isolated metal layer segments. Thus, intermediate metal layer segments 217 and 219 are directly electrically connected only to the conductive material in anchor vias 216 and 218, respectively. As such, anchor vias 216 and 218 and the conducive material therein and intermediate metal layer segments 217 and 219 do not directly provide electrical connectivity to other components attached to PWB 202. Instead, anchor vias 216 and 218 and the conducive material therein and intermediate metal layer segments 217 and 219 are arranged to mechanically secure package 204 to PWB 202. Thus, any electrical connections required to be made to package 204 by way of solder bumps 214 a and 214 e are made by way through a separate conductive path, e.g., by way of separate electrical traces connected to bump attach sites 206 a and 206 e.
  • By way of contrast, interconnect via 220 provides a direct electrical path to a component (not shown) attached to PWB 202. With reference to FIG. 2, interconnect via 220 electrically connects solder ball 214 c and bump attach site 206 c to metal segment 227 by way of conductive material in interconnect via 220, metal segment 223 and conductive material in interconnect via 225. Metal segment 227 then provides an electrical path to a corresponding component by way other conductive traces or interconnects. In contrast, anchor vias 216 and 218 and intermediate metal segments 217 and 219, respectively, are isolated. As pointed out above, any electrical connections required to be made to package 204 by way of solder bumps 214 a and 214 e are made by way through a separate conductive path.
  • The particular arrangements depicted in FIGS. 1 and 2 result in significantly improving the reliability of assemblies 100 and 200. The reason is that anchor vias 216 and 218 and the conductive material therein, which are attached to or integral with solder balls 214 a and 214 e, more securely attach package 204 to PWB 202. Instead of a relatively small point of contact on the surface of bump attach sites 206 a and 206 e, interior walls defining anchor vias 216 and 218 and metal segments 217 and 219 along with the surface area of bump attach sites 206 a and 206 e provide significantly greater mounting surface for securing solder balls 214 a and 216 e to PWB 202. Thus, despite the flexibility of PWB 202, the likelihood for solder balls 214 a and 214 e to be dislodged from PWB 202 is greatly reduced. It has been found that arranging one or more anchor vias to the periphery of the package significantly improves assembly reliability. For example, employing anchor vias corresponding to solder balls proximate to the corner or periphery of package 204 and 104 enhances connectivity and reliability of assemblies 200 and 100, respectively.
  • FIGS. 3A through 3D show cross-sectional views of some of the features of an assembly incorporating anchor vias in intermediate stages of assembly, formed in accordance with an exemplary embodiment of the invention. The steps for forming interconnect vias are not described for simplicity.
  • Referring to FIG. 3A, intermediate assembly 350 comprises PWB 302. Bump attach sites 306 a, 306 b, 306 c, 306 d and 306 e are formed from a first metal layer situated on one surface of PWB 302. Dielectric layer 308 is situated below bump attach sites 306 a, 306 b, 306 c, 306 d and 306 e. Intermediate metal layer 310 is situated below dielectric layer 308, and dielectric layer 312 is situated below intermediate metal layer 310. Additional layers (not shown for simplicity) may be situated below dielectric layer 312.
  • Referring to FIG. 3B, intermediate assembly 352 is shown according to another stage of assembly. In assembly 352, anchor vias 324 and 326 have been formed through bump attach sites 306 a, 306 b, 306 c, 306 d and 306 e, dielectric layer 308, and a portion of intermediate metal segments 317 and 319. For example, anchor vias 324 and 326 can be formed by drilling through bump attach sites 306 a, 306 b, 306 c, 306 d and 306 e, dielectric layer 308, and a portion of intermediate metal segments 317 and 319.
  • Referring to FIG. 3C, intermediate assembly 354 is shown according to another stage of assembly. In assembly 354, package 304 including a plurality of solder balls has been arranged over PWB 302. Specifically, solder balls 314 a, 314 b, 314 c, 314 d and 314 e are interfaced with bump attach sites 306 a, 306 b, 306 c, 306 d and 306 e, respectively.
  • Referring to FIG. 3D, intermediate assembly 356 is shown according to another stage of assembly after a reflow process. During the reflow process, the solder balls of package 304 are melted, and upon melting, mechanically and electrically connect package 304 to PWB 302. In addition, a portion of solder balls 314 a and 314 e fill (partially or completely) vias 316 and 318, respectively. As discussed above, this particular arrangement more securely anchors package 304 to PWB 302, thereby forming a significantly more reliable assembly. Moreover, very little expense is added to the assembly process, since the technique for forming anchor vias is similar to that used to form interconnect vias, and the technique used for filling anchor vias is similar to that used to fill interconnect vias.
  • As discussed above, an anchor via is distinct from a traditional interconnect via in that the conductor in an anchor via is an isolated conductor. To further illustrate this concept, reference to FIG. 4 is now made. FIG. 4 illustrates assembly 458 according to another embodiment of the invention. In FIG. 4, PWB 402, package 404, bump attach sites 406 a, 406 b, 406 c, 406 d and 406 e, dielectric layer 408, intermediate metal layer 410, dielectric layer 412, and solder balls 414 a, 414 b, 414 c, 414 d and 414 e correspond to PWB 202, package 204, bump attach sites 206 a, 206 b, 206 c, 206 d and 206 e, dielectric layer 208, intermediate metal layer 210, dielectric layer 212, and solder balls 214 a, 214 b, 214 c, 214 d and 214 e in FIG. 2.
  • However, in contrast to assembly 200 of FIG. 2, anchor vias 428 and 430 of assembly 458 do not extend to intermediate metal layer 410. The conductive material in anchor vias 428 and 430 more clearly illustrates that the conductive material is “isolated” and does not provide a direct electrical connection or conductive path to another component (such as a supply voltage or a reference voltage, for example) attached to PWB 402. Any electrical connection required to be made to package 404 by way of solder bumps 414 a and 414 e and bump attach sites 406 a and 406 e are by way of a separate electrical connection. Referring back to FIG. 2, even though the conductive material in anchor vias 216 and 218 are connected to intermediate metal segments 217 and 219, the conductive material in anchor vias 216 and 218 along with intermediate metal segments 217 and 219 are also “isolated” conductors, similar to assembly 458 in FIG. 4. The reason is that conductive material in anchor vias 216 and 218 and intermediate metal segments 217 and 219 do not provide a direct conducive path to a component in the manner that interconnect vias do, as discussed above.
  • While the description set forth above has been illustrated with packages employing solder bumps, such as BGAs and CSPs, it is noted that the present invention also could be applied to benefit other types of assemblies with packages employing other types of solder joint configurations. For example, certain non-solder ball packages employ “flat” joints. When such packages are connected to an anchor via in a printed wiring board, and solder flows in the anchor via during assembly, a similar improvement in the assembly reliability can be achieved.
  • From the above description of exemplary embodiments of the invention, it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes could be made in form and detail without departing from the spirit and the scope of the invention. For example, the specific layout arrangement on a printed wiring board could be modified from that discussed above without departing from the scope of the invention. The described exemplary embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular exemplary embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Claims (8)

1. A method for assembling a package to a printed wiring board, the printed wiring board having a first surface, the package including a plurality of solder balls on at least one surface of the package, the method comprising:
forming an anchor via through the first surface of the printed wiring board;
mounting the package on the printed wiring board such that at least one of the plurality of solder balls contact an opening of the anchor via;
melting the that at least one of the plurality of solder balls so that a portion of the at least one of the plurality of solder balls fills at least a portion of the anchor via.
2. The method of claim 1, wherein the at least one of the plurality of solder balls is situated proximate a periphery of the at least one surface of the package.
3. The method of claim 1, wherein the at least one of the plurality of solder balls is situated proximate a corner of the at least one surface of the package.
4. The method of claim 1, wherein the portion of the at least one of the plurality of solder balls situated within the anchor via comprises an isolated conductor.
5. The method of claim 1, wherein the anchor via extends through the printed wiring board to an intermediate metal layer segment of the printed wiring board, the intermediate metal layer segment comprising an isolated metal layer segment.
6. The method of claim 1, wherein the forming the anchor via step comprises drilling through the first surface of the printed wiring board.
7. The method of claim 1, wherein the melting step comprises a reflow process.
8. The method of claim 1, wherein the forming the anchor via step comprises drilling through the first surface of the printed wiring board without drilling to an intermediate metal layer of the printed wiring board.
US11/938,727 2004-09-30 2007-11-12 Reliable printed wiring board assembly employing packages with solder joints and related assembly technique Abandoned US20080064139A1 (en)

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JP4812130B2 (en) 2011-11-09
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WO2006039246A1 (en) 2006-04-13
JP2008512878A (en) 2008-04-24

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