US20080006899A1 - Schottky diode and method of fabricating the same - Google Patents

Schottky diode and method of fabricating the same Download PDF

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US20080006899A1
US20080006899A1 US11/797,560 US79756007A US2008006899A1 US 20080006899 A1 US20080006899 A1 US 20080006899A1 US 79756007 A US79756007 A US 79756007A US 2008006899 A1 US2008006899 A1 US 2008006899A1
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junction
schottky
well
electrode
formed
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US11/797,560
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Dae-Shik Kim
Oh-Kyum Kwon
Myung-Hee Kim
Yong-Chan Kim
Hye-young Park
Joon-Suk Oh
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to KR1020060062838A priority Critical patent/KR100763848B1/en
Priority to KR10-2006-0062838 priority
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, DAE-SHIK, KIM, MYUNG-HEE, KIM, YONG-CHAN, KWON, OH-KYUM, OH, JOON-SUK, PARK, HYE-YOUNG
Publication of US20080006899A1 publication Critical patent/US20080006899A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes

Abstract

A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.

Description

    PRIORITY STATEMENT
  • This U.S. non-provisional application claims the benefit of priority from Korean Patent Application No. 10-2006-0062838, filed on Jul. 5, 2006, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference.
  • BACKGROUND
  • 1. Field
  • Example embodiments relate to a semiconductor device and a method for fabricating the same, for example, a schottky diode and a method for fabricating the same.
  • 2. Description of the Related Art
  • A schottky diode is a semiconductor device including a schottky junction between a semiconductor and a metal. Because the schottky barrier may predominantly emit majority carriers and may have little or no recombination or storage of minority carriers to limit switching speed, the schottky diode may exhibit a faster switching characteristic. Because the semiconductor device is driven in a tunneling method using the schottky junction between a semiconductor and a metal, a voltage drop characteristic in an ON state may be obtained that is lower than may be obtained in a P—N diode.
  • Thus, schottky diodes may be widely used as a core device in the applied fields of communications and portable apparatuses, which may require a lower loss characteristic. However, Schottky diodes may be external type schottky diodes which may require additional fabrication. Thus, additional costs and time may be needed for the fabrication.
  • SUMMARY
  • Example embodiments may provide a schottky diode which may be formed on the same semiconductor substrate where an NMOS, PMOS, or CMOS transistor is located, without deterioration of the characteristics thereof.
  • Example embodiments may provide a method for fabricating a schottky diode which may be formed on the same semiconductor substrate where an NMOS, PMOS, or CMOS transistor is located, without deterioration of the characteristics thereof.
  • In an example embodiment, a schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first conductive well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.
  • According to an example embodiment, the first device isolation region and the first electrode may be spaced apart from each other.
  • According to an example embodiment, at least a portion of the well guard may be formed under an outer perimeter portion of the schottky junction.
  • According to an example embodiment, the well guard may be formed in the shape of a ring having one of a square shape, a rectangular shape, a circular shape, and an elliptical shape.
  • According to an example embodiment, each of the first and second electrodes may include a silicide.
  • According to an example embodiment, the first and second electrodes may include a same silicide or different silicides.
  • According to an example embodiment, the first and second electrodes may include cobalt silicide.
  • According to an example embodiment, the first electrode may include titanium silicide and the second electrode may include cobalt silicide.
  • According to an example embodiment, a second ohmic junction may be formed to induce a leakage current to flow from the first well to the semiconductor substrate. A second device isolation region may separate the first ohmic junction and the second ohmic junction.
  • According to an example embodiment, the second ohmic junction may include a second junction region formed in the well and a third electrode contacting the second junction region. The second junction region may have a higher concentration of the second conductivity type than a concentration of the second conductivity type in the well guard.
  • In an example embodiment, a method for fabricating a schottky diode may include forming a well having a first conductivity type in a semiconductor substrate; forming a first device isolation region in the well to separate a schottky junction region from a first ohmic junction region; forming a well guard having a second conductivity type opposite to the first conductivity type in the well, at least a portion of the well guard formed in a portion of the schottky junction region; forming a first junction region in the first ohmic junction region, the first junction region having a higher concentration of the first conductivity type than the well; and forming an electrode over the first ohmic junction region contacting the first junction region.
  • According to an example embodiment, the method may further include forming an electrode over the schottky junction region simultaneously with forming the electrode over the ohmic junction region.
  • According to an example embodiment, each of the electrode of the ohmic junction and the electrode of the schottky junction may include a silicide.
  • According to an example embodiment, the electrode of the ohmic junction and the electrode of the schottky junction may include cobalt silicide.
  • According to an example embodiment, the method may further include forming an interlayer insulation film on the semiconductor substrate; forming a contact hole in the interlayer insulation film exposing at least a portion of the schottky junction region; and forming an electrode in the schottky junction region by forming a barrier metal film covering the interlayer insulation film and the schottky junction region and applying a heat treatment to the barrier metal film to form a silicide in the schottky junction region.
  • According to an example embodiment, each of the electrode of the ohmic junction and the electrode of the schottky junction may include a silicide.
  • According to an example embodiment, the electrode of the ohmic junction may include cobalt silicide and the electrode of the schottky junction may include titanium silicide.
  • According to an example embodiment, the method may further include forming a second ohmic junction in the semiconductor substrate; and forming a second device isolation region separating the first ohmic junction and the second ohmic junction. The second ohmic junction may induce a leakage current to flow from the well to the semiconductor substrate.
  • According to an example embodiment, forming the second ohmic junction may include forming a second junction region in the semiconductor substrate and forming a third electrode contacting the second junction region. The second junction region may have a higher concentration of the second conductivity type than the well guard.
  • According to an example embodiment, the internal schottky diode may be fabricated simultaneously with an NMOS transistor, a PMOS transistor, or a CMOS transistor which is formed on the same semiconductor substrate where the internal schottky diode is formed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Example embodiments will be described with reference to the accompanying drawings.
  • FIG. 1 is a plan view of a schottky diode according to an example embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1.
  • FIG. 3 is a graph showing the relationship between the concentration of impurities and the contact resistance of a semiconductor.
  • FIG. 4 is a plan view of a schottky diode according to another example embodiment.
  • FIG. 5 is a cross-sectional view taken along line V-V′ of FIG. 4.
  • FIG. 6 is a plan view of a schottky diode according to yet another example embodiment.
  • FIG. 7 is a cross-sectional view taken along line VII-VII′ of FIG. 6.
  • FIG. 8 is a plan view of a schottky diode according to yet further another example embodiment.
  • FIG. 9 is a cross-sectional view taken along line IX-IX′ of FIG. 8.
  • FIGS. 10 and 11 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to an example embodiment.
  • FIGS. 12 and 13 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to another example embodiment.
  • FIGS. 14 and 15 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to yet another example embodiment.
  • FIGS. 16 and 17 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to yet further another example embodiment.
  • FIGS. 18 and 19 are graphs showing the electrical characteristic of the schottky diode according to example embodiments.
  • DESCRIPTION OF EXAMPLE EMBODIMENTS
  • Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. In some example embodiments, well-known processes, well-known device structure, and well-known technologies are not described in detail to avoid the unclear interpretation of the example embodiments. Throughout the specification, like reference numerals in the drawings denote like elements.
  • It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it may be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
  • Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
  • Example embodiments may be described herein with reference to cross-section illustrations that may be schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the example embodiments.
  • Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
  • Furthermore, the words of the “first conductive type” and the “second conductive type” indicate conductive types opposite to each other, for example, P-type or N-type.
  • FIG. 1 is a plan view of a schottky diode according to an example embodiment. FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1.
  • A schottky diode 100 may include a schottky junction 13 including a first conductive well 11 formed in a semiconductor substrate 10 and a first electrode 12 contacting the first conductive well 11. Further included is an ohmic junction 16 including a first conductive higher concentration junction region 14 located in the first conductive well 11 and a second electrode 15 contacting the first conductive higher concentration junction region 14. A first device isolation region 17 may be formed in the first conductive well 11 separating the schottky junction 13 and the ohmic junction 16. A second conductive type well guard 18 may be formed in the first conductive well 11 having at least a portion thereof formed under the outer perimeter of the schottky junction 13. A second device isolation region 19 may be formed in the semiconductor substrate 10 and/or the first conductive well 11, outside of the outer perimeter of the ohmic junction 16. “TNP” and “TNM” respectively denote ports that may be connected to the schottky junction 13 and the ohmic junction 16. The electric potential of the TNP may correspond to the electric potential at a metal side of the schottky junction 13, while the electric potential of the TNM may correspond to a semiconductor side of the schottky junction 13.
  • In example embodiments disclosed in the present specification, the first conductive type may be an N-type and the second conductive type may be a P-type. However, example embodiments are not limited thereto.
  • FIG. 3 is a graph showing the relationship between the concentration of impurities and the contact resistance of a semiconductor. Referring to FIG. 3, for example, a semiconductor-metal junction having a doner impurity concentration of 1017 cm−3 may become a schottky junction while a semiconductor-metal junction having a higher doner impurity concentration of 1019 cm−3 or more may become an ohmic junction. Thus, the schottky junction 13 may be formed in a portion where the N-type well 11 having a lower impurity concentration and the first electrode 12 contact each other. The ohmic junction may be formed in a portion where the N-type higher concentration junction region 14 having a higher impurity concentration and the second electrode 15 contact each other.
  • Although it is not shown, if a P-type semiconductor where acceptor impurity is added and a metal contact each other, a boundary surface between a P-type well region having a lower impurity concentration and a metal electrode may form a schottky junction while a boundary surface between a P-type higher concentration junction region having a higher impurity concentration and a metal electrode may form an ohmic junction.
  • The first and second electrodes 12 and 15 of the schottky junction 13 and the ohmic junction 16 may include a silicide. The first electrode 12 of the schottky junction 13 and the second electrode 15 of the ohmic junction 16 may include the same silicide. For example, each of the first and second metal electrodes 12 and 15 may include one of titanium (Ti) silicide, tungsten (W) silicide, molybdenum (Mo) silicide, tantalum (Ta) silicide, cobalt (Co) silicide, nickel (Ni) silicide, or etc.
  • The schottky junction 13 and the ohmic junction 16 may be electrically separated by the first device isolation region 17 formed in the semiconductor substrate 10. The first device isolation region 17 may be, for example, a shallow trench isolation (STI). The first electrode 12 of the schottky junction 13 and the first device isolation region 17 may be spaced apart from each other, the reason for which will be discussed below in describing a method for fabricating a schottky diode according to an example embodiment.
  • The well guard 18 may be provided to reduce the concentration of an electric field and improve a breakdown voltage (BV) characteristic during a reverse bias so that the electric potential of the TNM may be set higher than the TNP. The well guard 18 may be provided so that at least a portion thereof is formed under the outer perimeter of the schottky junction 13. The well guard 18 may be formed the shape of a ring, for example, in a square shaped ring, a rectangular shaped ring, a circular shaped ring, an elliptical shaped ring, or etc. The well guard 18 may be of a well type, and a variety of well-type guards 18 may be applied according to the BV characteristic needed for the schottky diode 100. For example, the well guard 18 may be a pocket P-type well (PPwell) type that may be used as a source/drain of a higher voltage (HV) PMOS transistor or a P-type field interdiffused multilayer process (IMP) well type that may be used as a well of a lower voltage (LV) NMOS transistor.
  • The schottky diode 100 may be located on the same semiconductor substrate 10 where an NMOS transistor, a PMOS transistor, or a CMOS transistor may be located.
  • FIG. 4 is a plan view of a schottky diode according to another example embodiment. FIG. 5 is a cross-sectional view taken along line V-V′ of FIG. 4.
  • Referring to FIGS. 4 and 5, a schottky diode 200 according to an example embodiment may be substantially the same as the schottky diode 100 shown in the example embodiment of FIG. 1, except that the schottky diode 200 may include a second ohmic junction 23, which may induce a leakage current flowing from the well 11 toward the semiconductor substrate 10. Thus, the schottky diode 200 will be described regarding the difference from the schottky diode 100 shown in FIG. 1.
  • The second ohmic junction 23 may include a P-type higher concentration junction region 21 located in the semiconductor substrate 10 and a third electrode 22 contacting the P-type higher concentration junction region 21. The third electrode 22 may include a silicide. For example, the third electrode 22 may include one of titanium (Ti) silicide, tungsten (W) silicide, molybdenum (Mo) silicide, tantalum (Ta) silicide, cobalt (Co) silicide, nickel (Ni) silicide, or etc.
  • The second ohmic junction 23 may induce current to leak from the well 11 toward the semiconductor substrate 10, as indicated by a dotted line, during forward bias to set the electric potential of the TNP higher than that of the TNM. The induced leakage may prevent a defect in the schottky diode, which may occur if the leakage current flows arbitrarily. The second ohmic junction 23 may be electrically separated from the first ohmic junction 16 located in the well 11 by the second device isolation region 19.
  • FIG. 6 is a plan view of a schottky diode according to yet another example embodiment. FIG. 7 is a cross-sectional view taken along line VII-VII′ of FIG. 6.
  • Referring to FIGS. 6 and 7, a schottky diode 300 according to yet another example embodiment may be substantially the same as the schottky diode 100 shown in the example embodiment of FIG. 1, except that the first electrode 42 of the schottky junction 13′ and the second electrode 15 of the ohmic junction 16 may include silicides that may be different from each other. Thus, the schottky diode 300 will be described mainly regarding the difference from the schottky diode 100 shown in FIG. 1.
  • In the schottky diode 300, the first and second electrodes 42 and 15 included in the schottky junction 13′ and the ohmic junction 16, respectively, may include silicides which are different from each other. For example, each of the first and second electrodes 42 and 15 may be a different one of titanium (Ti) silicide, tungsten (W) silicide, molybdenum (Mo) silicide, tantalum (Ta) silicide, cobalt (Co) silicide, or nickel (Ni) silicide, or etc. For example, the first electrode 42 of the schottky junction 13′ may be titanium (Ti) silicide while the second electrode 15 of the ohmic junction 16 may be cobalt (Co) silicide.
  • The schottky diode 300 may include an interlayer insulation film 30 formed on the surface of the substrate 10. A first contact hole 31 may be formed in the interlayer insulation film 30 to expose at least a portion of the second electrode 15 of the ohmic junction 16. A second contact hole 32 may be formed in the interlayer insulation film 30 to expose at least a portion of the first electrode 42 of the schottky junction 13′. A barrier metal film 41 may be formed on the interlayer insulation film 30 . The barrier metal film 41 may prevent inter-diffusion of heterogeneous materials between a metal wiring (not shown) and the semiconductor substrate 10, and may be formed of, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc.
  • FIG. 8 is a plan view of a schottky diode according to yet further another example embodiment. FIG. 9 is a cross-sectional view taken along line IX-IX′ of FIG. 8.
  • Referring to FIGS. 8 and 9, a schottky diode 400 according to yet further another example embodiment may be substantially the same as the schottky diode 200 shown in the example embodiment of FIG. 4, except that the first electrode 42 of the schottky junction 13′ and the second electrode 15 of the ohmic junction 16 may include silicides that may be different from each other. Thus, the schottky diode 400 will be described mainly regarding the difference from the schottky diode 200 as shown in FIG. 4.
  • In the schottky diode 400, the first and second electrodes 42 and 15 in the schottky junction 13′ and the ohmic junction 16, respectively, may include silicides, which may be different from each other. For example, each of the first and second electrodes 42 and 15 may be a different one of titanium (Ti) silicide, tungsten (W) silicide, molybdenum (Mo) silicide, tantalum (Ta) silicide, cobalt (Co) silicide, nickel (Ni) silicide, or etc. For example, the first electrode 42 of the schottky junction 13′ may be titanium (Ti) silicide while the second electrode 15 of the ohmic junction 16 may be cobalt (Co) silicide.
  • The third electrode 22 of the second ohmic junction 23 may be formed of a silicide different from that of the first electrode 42 of the schottky junction 13′ or the same silicide as that of the first electrode 42. For example, if the first electrode 42 of the schottky junction 13′ is titanium silicide, the third electrode 22 of the ohmic junction 13 may be cobalt silicide or titanium silicide.
  • The schottky diode 400 may include an interlayer insulation film 30 formed on the surface of the substrate 10. A first contact hole 31 may be formed in the interlayer insulation film 30 that may expose at least a portion of the second electrode 15 of the first ohmic junction 16. A second contact hole 32 may be formed in the interlayer insulation film 30 that may expose at least a portion of the first electrode 42 of the schottky junction 13′. A third contact hole 33 may be formed in the interlayer insulation film 30 that may expose at least a portion of the third electrode 22 of the second ohmic junction 23. A barrier metal film 41 may be formed on the interlayer insulation film 30. The barrier metal film 41 may prevent inter-diffusion of heterogeneous materials between a metal wiring (not shown) and the semiconductor substrate 10, and may be formed of, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc.
  • FIGS. 10 and 11 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to an example embodiment.
  • Referring to FIG. 10, a P-type semiconductor substrate 10 may include an N-type well 11, first and second device isolation regions 17 and 19 separating a schottky junction region SJ and an ohmic junction region OJ, and a P-type well guard 18 located in the N-type well 11. The N-type well 11 may be formed in the P-type semiconductor substrate 10. The N-type well 11 may be simultaneously formed during the formation of an N-type well of a PMOS transistor or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed. For example, if the MOS transistor formed on the semiconductor substrate 10 is, for example, an HV PMOS transistor or an MV PMOS transistor, the N-type well may be an HV N-type well.
  • The first and second device isolation regions 17 and 19 may be formed in the semiconductor substrate to separate the schottky junction region SJ and the ohmic junction region OJ. The first and second device isolation regions 17 and 19 may be, for example, an STI. The first and second device isolation regions 17 and 19 may be simultaneously formed during the formation of the device isolation region of an NMOS transistor, PMOS transistor, or CMOS transistor which may be formed on the same semiconductor substrate 10 where the schottky diode may be formed.
  • The P-type well guard 18 may be formed having at least a portion thereof formed under the ohmic junction region OJ. The well guard 18 may be formed in the shape of a ring, for example, a square shaped ring, a rectangular shaped ring, a circular shaped ring, an elliptical shaped ring, or etc. The well guard 18 may be a variety of well types according to the breakdown voltage characteristic needed for the schottky diode 100. For example, the well guard 18 may be formed as a pocket P-type well used as a source/drain of an HV PMOS transistor or a P-type field IMP well type used as a well of an MV NMOS transistor or LV NMOS transistor.
  • The well guard 18 may be simultaneously formed during the formation of a P-type well of an NMOS transistor or CMOS transistor device, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed. Although the well guard 18 may be formed after the first and second device isolation regions 17 and 19 are formed, the order of formation of the first and second device isolation regions 17 and 19 and the well guard 18 may be changed according to the type of the semiconductor device that is formed with the schottky diode.
  • Referring to FIG. 11, the N-type higher concentration junction region 14 may be formed in the ohmic junction region OJ. The N-type higher concentration junction region 14 may be simultaneously formed during the formation of the source/drain region of an NMOS transistor or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • Referring to FIG. 2, the first and second electrodes 12 and 15 may be formed in the schottky junction region SJ and the ohmic junction region OJ of FIG. 11, respectively, to complete the schottky junction 13 and the ohmic junction 16. The first and second electrodes 12 and 15 may be formed by depositing metal, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc. in the schottky junction region SJ and the ohmic junction region OJ of FIG. 11 and applying a heat treatment to the deposited metal to form a silicide. For example, the silicide may be formed using cobalt to reduce the resistance of the first and second electrodes 12 and 15.
  • Because the first electrode 12 may be formed in the schottky junction region SJ of FIG. 11 at a desired (or, alternatively, a predetermined) interval from the first device isolation region 17, a defect in forming the silicide that may occur at an end portion of the schottky junction region SJ of FIG. 11 may be prevented. Thus, deterioration of the schottky diode characteristic may be prevented.
  • The first and second electrodes 12 and 15 may be simultaneously formed during the formation of a metal region constituting a contact area of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed. Thereafter, the schottky diode may be completed using a typical conventional diode fabrication method.
  • FIGS. 12 and 13 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to another example embodiment.
  • The method for fabricating a schottky diode according to another example embodiment may be substantially the same as the method for fabricating a schottky diode according to the example embodiment as shown in FIGS. 10 and 11, except that an ohmic junction 23 that may induce a leakage current to flow in the semiconductor substrate 10 may be formed in the semiconductor substrate 10. Thus, the method for fabricating a schottky diode according to another example embodiment will be described mainly regarding the difference from the method for fabricating a schottky diode according to the example embodiment as shown in FIGS. 10 and 11.
  • Referring to FIG. 12, a P-type semiconductor substrate 10 may include an N-type well 11, first and second device isolation regions 17 and 19 separating schottky junction region SJ and first and second ohmic junction regions OJ1 and OJ2, and a P-type well guard 18 located in the N-type well 11.
  • Referring to FIG. 13, an N-type higher concentration junction region 14 may be formed in the ohmic junction region OJ1. A P-type higher concentration junction region 21 that may induce a leakage current may be formed in the ohmic junction region OJ2. The N-type higher concentration junction region 14 and the P-type higher concentration junction region 21 may be simultaneously formed during the formation of the source/drain region of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • Referring to FIG. 5, the first, second, and third electrodes 12, 15, and 22 may be formed in the schottky junction region SJ and the first and second ohmic junction regions OJ1 and OJ2 of the FIG. 12, respectively, to complete the schottky junction 13 and the first and second ohmic junctions 16 and 23. The first, second, and third electrodes 12, 15, and 22 may be formed by depositing metal, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc. in the schottky junction region SJ and the first and second ohmic junction regions OJ1 and OJ2 of FIG. 12 and applying a heat treatment to the deposited metal to form a silicide. For example, the silicide may be formed using cobalt to reduce the resistance of the first, second, and third electrodes 12, 15, and 22.
  • Because the first electrode 12 may be formed in the schottky junction region SJ of FIG. 12 at a desired (or, alternatively, a predetermined) interval from the first device isolation region 17, a defect in forming the silicide that may occur at an end portion of the schottky junction region SJ may be prevented. Thus, deterioration of the schottky diode characteristic may be prevented.
  • The first, second, and third electrodes 12, 15, and 22 may be simultaneously formed during the formation of a metal region constituting a contact area of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed. Thereafter, the schottky diode may be completed using a conventional schottky diode fabrication method.
  • FIGS. 14 and 15 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to yet another example embodiment.
  • The method for fabricating a schottky diode according to yet another example embodiment may be substantially the same as the method for fabricating a schottky diode according to the example embodiment as shown in FIGS. 12 and 13, except that the first electrode of the schottky junction and the second electrode of the ohmic junction may be fabricated to include silicides different from each other. Thus, the method for fabricating a schottky diode will be described mainly regarding the difference from the method for fabricating a schottky diode according to the example embodiment as shown in FIGS. 10 and 11.
  • Referring to FIG. 10, the semiconductor substrate 10 may include an N-type well 11, first and second device isolation regions 17 and 19 separating the schottky junction region SJ and the ohmic junction region OJ, and a P-type well guard 18 located in the N-type well 11.
  • Referring to FIG. 14, the second electrode 15 may be formed in the N-type higher concentration junction region 14 of the ohmic junction region OJ, thus completing the ohmic junction 16. The second electrode 15 may be formed by depositing metal, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc. in the ohmic junction region OJ and applying a heat treatment to the deposited metal to form a silicide. For example, the silicide may be formed using cobalt to reduce the resistance of the electrode 15.
  • The second electrode 15 may be simultaneously formed during the formation of a metal region constituting a contact area of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • Referring to FIG.15, an interlayer insulation film 30 may be formed on the semiconductor substrate 10. A first contact hole 31 that may expose at least a portion of the second electrode 15 of the ohmic junction 16 and a second contact hole 32 that may expose at least a portion of the schottky junction region SJ may be formed on the interlayer insulation film 30. The second contact hole 32 may also expose at least a part of the well guard 18.
  • Referring to FIG. 7, a barrier metal film 41 may be formed that may cover the entire surface of the interlayer insulation film 30 and the exposed portions of the ohmic junction 16, schottky junction region SJ, and well guard 18. The barrier metal film 41 may prevent inter-diffusion of heterogeneous materials between a metal wiring (not shown) and the semiconductor substrate 10 and may be formed of, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc.
  • The barrier metal film 41 may be simultaneously formed during the formation of the barrier metal film of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • The first electrode 42 may be formed in the schottky junction region SJ exposed through the second contact hole 32 so that the schottky junction 13′ may be complete. The first electrode 42 in the schottky junction region SJ is formed by applying a heat treatment to a barrier metal film 41 in the schottky junction region SJ. In other words, the first electrode 42 is formed by reacting with the barrier metal film 41 and a semiconductor substrate 10 in the schottky junction region SJ to form a silicide. Because the second contact hole 32 may expose only a portion of the schottky junction region SJ of FIG. 14, the first electrode 42 of the schottky junction 13′ may be separated from the first device isolation region 17.
  • The schottky diode may be completed using a conventional schottky diode fabrication method.
  • FIGS. 16 and 17 are cross-sectional views of the intermediate structures formed during a method for fabricating a schottky diode according to yet further another example embodiment.
  • The method for fabricating a schottky diode may be substantially the same as the method for fabricating a schottky diode according to the example embodiment as shown in FIGS. 12 and 13, except that the first electrode of the schottky junction and the second electrode of the first and second ohmic junctions may be fabricated to include silicides different from each other. Thus, the method for fabricating a schottky diode will be described mainly regarding the difference from the method for fabricating a schottky diode according to the example embodiment as shown in FIGS. 12 and 13.
  • Referring to FIG. 12, the semiconductor substrate 10 may include an N-type well 11, first and second device isolation regions 17 and 19 separating schottky junction region SJ and the first and second ohmic junction regions OJ1 and OJ2, and a P-type well guard 18 located in the N-type well 11.
  • Referring to FIG. 13, an N-type higher concentration junction region 14 may be formed in the ohmic junction region OJ1. The P-type higher concentration junction region 21 may be formed in the ohmic junction region OJ2 to induce a leakage current. The N-type higher concentration junction region 14 and the P-type higher concentration junction region 21 may be simultaneously formed during the formation of the source/drain region of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • Referring to FIG. 16, the second and third electrodes 15 and 22 may be formed in the ohmic junction regions OJ1 and OJ2 to complete the first and second ohmic junctions 16 and 23. The second and third electrodes 15 and 22 may be formed by depositing metal, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc., in the first and second ohmic junction regions OJ1 and OJ2, respectively, and applying a heat treatment to the deposited metal to form a silicide. For example, the silicide may be formed using cobalt to reduce the resistance of the electrodes 15 and 22.
  • The second and third electrodes 15 and 22 may be simultaneously formed during the formation of a metal region constituting a contact area of an NMOS transistor, PMOS transistor, or CMOS transistor, which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • Referring to FIG. 17, an interlayer insulation film 30 may be formed on the semiconductor substrate 10 where the second and third electrodes 15 and 22 of the first and second ohmic junctions 16 and 23 are formed. First and third contact holes 31 and 33 may be formed in the interlayer insulation film 30 that may expose at least a portion of the first and second ohmic junctions 16 and 23. A second contact hole 32 may be formed in the interlayer insulation film 30 that may expose at least a portion of the schottky junction region SJ. The second contact hole 32 may also expose at least a portion of the well guard 18.
  • Referring to FIG. 9, a barrier metal film 41 may be formed that may cover the entire surface of the interlayer insulation film 30 and the exposed portions of the first and second ohmic junctions 16 and 23, the schottky junction region SJ, and the well guard 18. The barrier metal film 41 may be formed of, for example, titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or etc.
  • The barrier metal film 41 may be simultaneously formed during the formation of the barrier metal film of an NMOS transistor, PMOS transistor, or CMOS transistor which may be formed on the same semiconductor substrate 10 where the schottky diode is formed.
  • The first electrode 42 may be formed in the schottky junction region SJ through the second contact hole 32 so that the schottky junction 13′ may be complete. The first electrode 42 in the schottky junction region SJ is formed by applying a heat treatment to a barrier metal film 41 in the schottky junction region SJ. In other words, the first electrode 42 is formed by reacting with the barrier metal film 41 and a semiconductor substrate 10 in the schottky junction region SJ to form a silicide. Because the second contact hole 32 may expose only a portion of the schottky junction region SJ of FIG. 16, the first electrode 42 of the schottky junction 13′ may be separated from the first device isolation region 17.
  • The schottky diode may be completed using a conventional schottky diode fabrication method.
  • FIGS. 18 and 19 are graphs comparing the electrical characteristics of schottky diodes fabricated according to example embodiments. Referring to FIGS. 18 and 19, comparison of the electrical characteristic of the schottky diode fabricated according to example embodiments, for example, between the electrodes of the schottky junction formed of cobalt silicide (CoSi2) and titanium silicide (TiSi2), shows the turn-on voltage may be about 0.3 V (FIG. 17) and the reverse breakdown voltage may be about 34 V, which may satisfy the basic schottky diode characteristic.
  • Example embodiments may provide a schottky diode that may be fabricated without deterioration of the schottky diode characteristic.
  • Example embodiments may provide a schottky diode that may be formed on the same semiconductor substrate with a PMOS transistor, NMOS transistor, or CMOS transistor, thus an additional process to fabricate the schottky diode may not be required.
  • Example embodiments may provide a method for fabricating a schottky diode that may improve the efficiency of production of semiconductor devices.
  • While this invention has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims (20)

1. A schottky diode comprising:
a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the well, the well having a first conductivity type;
a first ohmic junction including a first junction region formed in the well and a second electrode contacting the first junction region, the first junction region having a higher concentration of the first conductivity type than the well;
a first device isolation region formed in the semiconductor substrate separating the schottky junction and the first ohmic junction; and
a well guard having a second conductivity type opposite to the first conductivity type formed in the well, at least a portion of the well guard formed under a portion of the schottky junction.
2. The schottky diode of claim 1, wherein the first device isolation region and the first electrode are spaced apart from each other.
3. The schottky diode of claim 1, wherein at least a portion of the well guard is formed under an outer perimeter portion of the schottky junction.
4. The schottky diode of claim 1, wherein the well guard is formed in the shape of a ring having one of a square shape, a rectangular shape, a circular shape, arid an elliptical shape.
5. The schottky diode of claim 1, wherein each of the first and second electrodes include a silicide.
6. The schottky diode of claim 5, wherein the first and second electrodes include a same silicide or different silicides.
7. The schottky diode of claim 6, wherein the first and second electrodes include cobalt silicide.
8. The schottky diode of claim 6, wherein the first electrode includes titanium silicide and the second electrode includes cobalt silicide.
9. The schottky diode of claim 1, further comprising:
a second ohmic junction formed to induce a leakage current to flow from the well to the semiconductor substrate; and
a second device isolation region separating the first ohmic junction and the second ohmic junction.
10. The schottky diode of claim 9, wherein the second ohmic junction includes a second junction region formed in the well and a third electrode contacting the second junction region, the second junction region having a higher concentration of the second conductivity type than a concentration of the second conductivity type in the well guard.
11. A method for fabricating a schottky diode, the method comprising:
forming a well having a first conductivity type in a semiconductor substrate;
forming a first device isolation region in the well to separate a schottky junction region from a first ohmic junction region;
forming a well guard having a second conductivity type opposite to the first conductivity type in the well, at least a portion of the well guard formed in a portion of the schottky junction region;
forming a first junction region in the first ohmic junction region, the first junction region having a higher concentration of the first conductivity type than the well; and
forming an electrode over the first ohmic junction region contacting the first junction region.
12. The method of claim 11, further comprising forming an electrode over the schottky junction region simultaneously with forming the electrode over the first ohmic junction region.
13. The method of claim 12, wherein each of the electrode of the ohmic junction and the electrode of the schottky junction include a silicide.
14. The method of claim 13, wherein the electrode of the ohmic junction and the electrode of the schottky junction include cobalt silicide.
15. The method of claim 11, further comprising:
forming an interlayer insulation film on the semiconductor substrate;
forming a contact hole in the interlayer insulation film exposing at least a portion of the schottky junction region; and
forming an electrode in the schottky junction region by forming a barrier metal film covering the interlayer insulation film and the schottky junction region and applying a heat treatment to the barrier metal film to form a suicide in the schottky junction region.
16. The method of claim 15, wherein each of the electrode of the ohmic junction and the electrode of the schottky junction include a silicide.
17. The method of claim 16, wherein the electrode of the ohmic junction includes cobalt silicide and the electrode of the schottky junction includes titanium silicide.
18. The method of claim 11, further comprising:
forming a second ohmic junction in the semiconductor substrate; and
forming a second device isolation region separating the first ohmic junction and the second ohmic junction,
wherein the second ohmic junction induces a leakage current to flow from the well to the semiconductor substrate.
19. The method of claim 18, wherein forming the second ohmic junction includes forming a second junction region in the semiconductor substrate and forming an electrode contacting the second junction region, the second junction region having a higher concentration of the second conductivity type than the well guard.
20. The method of claim 11, wherein the schottky diode is fabricated simultaneously with an NMOS transistor, a PMOS transistor, or a CMOS transistor which is formed on the same semiconductor substrate where the schottky diode is formed.
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