US20070263472A1 - Process environment variation evaluation - Google Patents

Process environment variation evaluation Download PDF

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Publication number
US20070263472A1
US20070263472A1 US11/382,722 US38272206A US2007263472A1 US 20070263472 A1 US20070263472 A1 US 20070263472A1 US 38272206 A US38272206 A US 38272206A US 2007263472 A1 US2007263472 A1 US 2007263472A1
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Prior art keywords
fet
polarity
pad
polarity fet
coupled
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Abandoned
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US11/382,722
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English (en)
Inventor
Brent Anderson
Edward Nowak
Noah Zamdmer
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International Business Machines Corp
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International Business Machines Corp
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Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/382,722 priority Critical patent/US20070263472A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NOWAK, EDWARD J., ZAMDMER, NOAH D., ANDERSON, BRENT A.
Priority to CN200710089833.XA priority patent/CN101071813B/zh
Publication of US20070263472A1 publication Critical patent/US20070263472A1/en
Priority to US12/870,373 priority patent/US8932884B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates generally to microelectronics fabrication, and more particularly, to structures and methods for evaluating the effect of process environment variations across a chip.
  • Vt threshold voltage
  • FETs field effect transistors
  • a pattern density of various material stacks can modulate the rapid thermal anneal (RTA) temperature locally and may cause as much as 100 mV variation in threshold voltage (Vt) within a chip.
  • RTA rapid thermal anneal
  • Vt threshold voltage
  • One approach to this problem is to measure an electrical property of two transistors and then to characterize across chip variation based on those measurements. This approach, however, can require a very large sample size of transistors to provide adequate data for variations over many length scales. For example, the characterization does not enable an evaluation of a direction of the process environment variation on the chip.
  • a structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures.
  • the plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads.
  • the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
  • a first aspect of the invention provides a structure comprising: a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in a vicinity of the plurality of electrical structures.
  • a second aspect of the invention provides a structure comprising: a first polarity field effect transistor (FET) coupled to a second polarity FET, each of the first polarity FET and the second polarity FET coupled to a first pad and a second pad; and wherein the structure provides for independent measurement of the first polarity FET and the second polarity FET using only the first pad and the second pad.
  • FET field effect transistor
  • a third aspect of the invention provides a method of determining a gradient field of a process environment variation, the method comprising: providing a plurality of electrical structures arranged in a non-collinear fashion in a substrate; performing a process on the substrate; measuring an electrical property of each of the electrical structures; and determining a magnitude and a direction of the process environment variation in the vicinity of the plurality of electrical structures based on the measurements.
  • a fourth aspect of the invention provides a method of independently evaluating transistors, the method comprising: forming a first polarity field effect transistor (FET) coupled to a second polarity FET, each of the first polarity FET and the second polarity FET coupled to a first pad and a second pad; and independently measuring the first polarity FET and the second polarity FET using only the first pad and the second pad.
  • FET field effect transistor
  • FIG. 1 shows one embodiment of a structure for evaluating process environment variation according the invention.
  • FIG. 2A shows a first embodiment of an electrical structure used in the structure of FIG. 1 including resistors.
  • FIG. 2B shows a second embodiment of an electrical structure used in the structure of FIG. 1 including diodes.
  • FIG. 2C shows a third embodiment of an electrical structure used in the structure of FIG. 1 including ring oscillators.
  • FIG. 3 shows a fourth embodiment of an electrical structure used in the structure of FIG. 1 including transistors.
  • FIG. 4 shows the fourth embodiment of the electrical structure of FIG. 3 implemented in the layout of FIGS. 2A-2B .
  • FIG. 5 shows an alternative fourth embodiment of an electrical structure used in the structure of FIG. 1 including transistors.
  • FIG. 6 shows the alternative fourth embodiment of the electrical structure of FIG. 5 implemented in the layout of FIG. 2A -B.
  • FIG. 1 shows one embodiment of a structure 100 for evaluating the effect of a process environment variation across a chip 102 .
  • Structure 100 includes a plurality of electrical structures 104 arranged in a non-collinear fashion for determining a magnitude and a direction of a process environment variation in the vicinity of plurality of electrical structures 104 .
  • the process environment variation may include practically any environmental characteristic that varies during a particular fabrication process, e.g., etching, annealing, material deposition, ion implanting, etc.
  • a process environment variation may include a spacer etch variation, a photolithography exposure variation, a gate length variation, a variation in film deposition, and an anneal temperature gradient.
  • Electrical structures 104 A-C are interconnected, via interconnects 110 , to a plurality of probe pads (or simply “pads”) 106 . As illustrated, electrical structures 104 A-C are interconnected by four pads 106 A-D, but more may be employed where more electrical structures 104 are used.
  • Electrical structures 104 may take the form of a variety of different electrical devices.
  • electrical structures may each include a resistor, a diode or a ring oscillator.
  • each end (input or output) of the aforementioned devices are coupled as indicated in FIG. 1 .
  • FIG. 2A shows one embodiment employing doped polysilicon resistors 120 A-C.
  • resistors 122 A-C are interconnected to pads 106 A-D.
  • FIG. 2B shows another embodiment employing diodes 122 A- 122 C.
  • diodes 120 A-C are interconnected to pads 106 A-D.
  • FIG. 2C shows another embodiment employing ring oscillators 124 A-C.
  • ring oscillators 124 A-C are interconnected to pads 106 A-D, and output signals of each ring oscillator 124 A-C are connected to a signal probe pad 126 .
  • each electrical structure 104 may include a plurality of transistors. In FIGS. 3 and 5 , two transistors 130 A-B are shown, respectively. However, it is understood that any number of transistors 130 A-B greater than or equal to two may be used.
  • each electrical structure 104 may include a first polarity field effect transistor (FET), e.g., a NFET 130 A, 230 A, coupled to a second polarity FET, e.g., a PFET 130 B, 230 B. It is understood that the position of each type FET may be switched from what is illustrated.
  • FET first polarity field effect transistor
  • first polarity FET 130 A, 230 A and second polarity FET 130 B, 230 B are each coupled to a first pad 206 A, 306 A and a second pad 206 B, 2306 B.
  • first polarity FET 130 A, 230 A and second polarity FET 130 B, 230 B are each coupled to a first pad 206 A, 306 A and a second pad 206 B, 2306 B.
  • independent measurement of first polarity FET 130 A, 230 A and second polarity FET 130 B, 230 B using only first pad 206 A, 306 A and second pad 206 B, 306 B is made possible.
  • the electrical property measured may be varied depending on the particular structure provided.
  • each electrical structure 104 employs measurement of a threshold voltage (Vt).
  • FIG. 4 shows the transistor embodiment of electrical structure 104 of FIG. 3 implemented in the layout of FIGS. 2 A-B. Referring to FIGS. 3 and 4 , to measure NFET 130 A Vt, positive voltage is supplied to pad 206 A to which the gates are connected with reference to ground on pad 206 B.
  • the voltage applied is adjusted until the current drawn achieves a preset condition defining threshold voltage (typically 40 to 400 nA times the width of the FET and divided by the length of the FET).
  • PFET 130 B Vt can be measured by providing negative voltage to pad 206 A to which the gates are connected with reference to ground on pad 206 B.
  • the voltage applied is adjusted until the current drawn achieves a preset condition defining threshold voltage (typically 40 to 400 nA times the width of the FET and divided by the length of the FET).
  • a source 244 A of a first polarity FET 230 A (e.g., an NFET) is coupled to first pad 306 A
  • a gate 240 A and a drain 242 A of first polarity FET 230 A are coupled to a source 244 B of second polarity FET 230 B (e.g., a PFET)
  • a gate 240 B and a drain 242 B of second polarity FET 230 B are coupled to a second pad 306 B.
  • electrical structure 104 measures an off current (I off ).
  • FIG. 6 shows the transistor embodiment of electrical structure 104 of FIG. 5 implemented in the layout of FIGS. 2 A-B. Referring to FIGS. 5 and 6 , the off-current of NFET 230 A is measured by providing a positive voltage (greater than Vt) on pad 306 A to which only a drain is electrically connected to ground on pad 306 B.
  • the current measured in this state is the off-current (Ioff) of NFET 230 A.
  • the off-current of PFET 230 B is obtained by providing a negative voltage (greater than Vt) on pad 306 A to which only a drain is electrically connected to ground on pad 306 B.
  • the current measured in this state is off-current (Ioff) of PFET 230 B.
  • each electrical structure 104 is substantially identical in design to the others used therewith to provide accurate gradient measurements. However, some variation may be allowed in some cases.
  • the above-described structure 100 may be employed to measure the effect of a process environment variation across a chip 102 ( FIG. 1 ).
  • one of the above-described embodiments of electrical structures 104 is provided. That is, a plurality of electrical structures 104 are arranged in a non-collinear fashion in a substrate 150 ( FIG. 1 ) used to fabricate a chip 102 .
  • a process is performed on substrate 102 .
  • the process may include any now known or later developed semiconductor fabrication process, e.g., an etch, an anneal, material deposition, ion implanting, etc.
  • An electrical property e.g., threshold voltage (Vt), resistance (R), off current (Ioff), etc.
  • the particular type of electrical property measured varies depending on the type of electrical structure 104 used. For example, resistance is measured if resistors are used, threshold voltage (Vt) or off current (Ioff) is measured if transistors are used, a reverse bias leakage or forward bias voltage may be measured if diodes are used, and a speed or delay using fixed voltages may be measured if ring oscillators are used.
  • a magnitude and a direction of the process environment variation in the vicinity of the plurality of electrical structures 104 can be determined.
  • electrical structures 104 shown in FIG. 1 are transistor structures as shown in FIG. 3
  • electrical structure 104 A having a higher threshold voltage (Vt) compared to electrical structures 104 B, 104 C may indicate a pattern density of various material stacks at the location, i.e., X1, Y1, of electrical structure 104 A has altered the rapid thermal anneal (RTA) temperature locally.
  • RTA rapid thermal anneal
  • electrical structures 104 may include doped polysilicon resistors, which are sensitive to annealing temperatures.
  • resistance measurements can be used to determine the anneal temperature at the location of each electrical structure 104 (e.g., using empirical data) or the effect of the annealing at the location of each electrical structure 104 .
  • the non-collinear location of electrical structures 104 allows an evaluation in two dimensions, i.e., based on location, such that a direction of the effect can be determined.
  • the local magnitude and direction of change can be calculated from the data obtained from the three structures 104 as follows. Let Z 1 , Z 2 , and Z 3 represent the electrical measurements obtained from structures 104 A, 104 B, and 104 C, respectively.
  • dZ/dY [( X 2 ⁇ X 1)( Z 3 ⁇ Z 1) ⁇ ( Z 2 ⁇ Z 1)( X 3 ⁇ X 1)]/[( X 2 ⁇ X 1)( Y 3 ⁇ Y 1) ⁇ ( Y 2 ⁇ Y 1)( X 3 ⁇ X 1)] (Eq. 1)
  • dZ/dY [( Y 3 ⁇ Y 1)( Z 2 ⁇ Z 1) ⁇ ( Z 3 ⁇ Z 1)( Y 2 ⁇ Y 1)]/[( X 2 ⁇ X 1)( Y 3 ⁇ Y 1) ⁇ ( Y 2 ⁇ Y 1)( X 3 ⁇ X 1)] (Eq. 2).
  • a method of independently evaluating transistors may be employed using the structure of FIG. 3 or 5 alone, or as part of the above-described embodiment for evaluating the effect of a process environment variation.
  • the structure used can be selected from any of the above-described versions of the transistor embodiment, i.e., FIGS. 3 and 5 .
  • first polarity FET 130 A is coupled to second polarity FET 130 B with each first polarity FET 130 A and second polarity FET 130 B coupled to first pad 206 A and second pad 206 B.
  • transistors 130 A, 130 B are provided, various processes are performed on first polarity FET 130 A and second polarity FET 130 B.
  • first polarity FET 130 A and second polarity FET 130 B using only first pad 206 A and second pad 206 B may then occur to evaluate transistors 130 A, 130 B and, hence, the processes used to create them.
  • the type of electrical property measured will vary depending the structure used. For example, referring to FIG. 3 , the measuring may include: applying a positive voltage ramp to one pad 206 A with respect to the other pad 206 B to maintain PFET 130 B in an off-state and measuring NFET 130 A, i.e., measuring a threshold voltage thereof.
  • a negative voltage ramp may be applied to pad 206 B with respect to the other pad 206 A to maintain NFET 130 A in an off-state and measure PFET 130 B, i.e., measuring a threshold voltage thereof.
  • One example may include: applying a positive ramp on pad 206 B with an ammeter to ground on the other pad 206 A. This situation will turn NFET 130 A on when the threshold voltage (Vt) is reached, while PFET 130 B remains off. Hence, the situation will force a positive current, e.g., approximately 300 nA ⁇ W/L, resulting in the value of the threshold voltage (Vt) of NFET 130 A to be communicated from pad 206 B to pad 206 A.
  • CMOS complementary metal-oxide semiconductors
  • bodies may continue to be left to ‘float’ or, the bodies may be explicitly connected in a number of ways.
  • One such connection is illustrated in FIG. 3 with dashed lines connecting bodies 146 A, 146 B to sources 144 .
  • bodies 146 A, 146 B can be wired to other probe pads.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
US11/382,722 2006-05-11 2006-05-11 Process environment variation evaluation Abandoned US20070263472A1 (en)

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US11/382,722 US20070263472A1 (en) 2006-05-11 2006-05-11 Process environment variation evaluation
CN200710089833.XA CN101071813B (zh) 2006-05-11 2007-04-05 确定工艺环境变化的梯度场的结构及方法
US12/870,373 US8932884B2 (en) 2006-05-11 2010-08-27 Process environment variation evaluation

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Cited By (1)

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US7487487B1 (en) 2008-04-01 2009-02-03 International Business Machines Corporation Design structure for monitoring cross chip delay variation on a semiconductor device

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US8754412B2 (en) 2012-01-03 2014-06-17 International Business Machines Corporation Intra die variation monitor using through-silicon via
US8966431B2 (en) 2012-11-21 2015-02-24 International Business Machines Corporation Semiconductor timing improvement
US9508618B2 (en) * 2014-04-11 2016-11-29 Globalfoundries Inc. Staggered electrical frame structures for frame area reduction

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CN101071813A (zh) 2007-11-14
US20100323462A1 (en) 2010-12-23
US8932884B2 (en) 2015-01-13
CN101071813B (zh) 2011-01-19

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