US20070247130A1 - Adaptive current reversal comparator - Google Patents
Adaptive current reversal comparator Download PDFInfo
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- US20070247130A1 US20070247130A1 US11/408,749 US40874906A US2007247130A1 US 20070247130 A1 US20070247130 A1 US 20070247130A1 US 40874906 A US40874906 A US 40874906A US 2007247130 A1 US2007247130 A1 US 2007247130A1
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- transistor
- inductor
- comparison circuit
- synchronous
- switching regulator
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Definitions
- This invention relates to voltage regulators. More specifically this invention relates to switching regulators with synchronous rectification.
- a synchronous switching regulator typically includes a first transistor that is ON during a first portion of a switching cycle and a second transistor that is ON during a second portion of the switching cycle.
- the first transistor conducts between a power supply and an inductor.
- the second transistor is typically OFF during the first portion of the cycle.
- power is transmitted from the power supply through the first transistor to the inductor (which in turn is typically coupled to a load and/or load capacitor).
- the second transistor which may be referred to herein as the synchronous transistor, turns ON and couples ground (or some other suitable reference voltage) to the end of the inductor that is not coupled to the load.
- both transistors may be OFF and the end of the inductor not coupled to the load may, in fact, be floating.
- Switching regulators with synchronous rectification preferably require a comparator, or for the purposes of this application other suitable comparison circuit, that monitors current reversal across the synchronous transistor.
- An ideal comparator with zero propagation delay would simply trip—i.e., change from a first output state to a second output state—when a sign reversal is detected across the synchronous transistor.
- the output of the comparator is used to control the operation of the second transistor.
- the synchronous switching regulator includes a power supply, a main transistor that typically operates as a switch, a synchronous transistor, and an inductor having one side coupled to the load.
- the method preferably includes turning ON a first transistor during a first portion of a switching cycle.
- the first transistor is preferably coupled to a second side of the inductor, the first transistor that conducts between the power supply and the inductor during the first portion of the switching cycle.
- the method also preferably includes turning ON a second transistor that is ON during a second portion of the switching cycle and that is OFF during the remainder of the switching cycle, the second transistor that is also coupled to the second side of the inductor. The second transistor conducts between ground and the inductor during the second portion of the switching cycle.
- the method also includes detecting a trip point at which the voltage at the second side of the inductor is about zero, the detecting using a comparison circuit, determining a time differential between the trip point and an end of the second portion of the switching cycle, and, finally adjusting an offset of the comparison circuit in response to the time differential.
- FIG. 1 is a synchronous switching regulator according to the invention
- FIG. 2 is a group of signal traces based on the circuit shown in FIG. 1 ;
- FIG. 3 is a second group of signal traces based on the circuit in FIG. 1 ;
- FIG. 4 is a second synchronous switching regulator according to the invention.
- FIG. 5 is a group of signal traces based on the circuit in FIG. 4 ;
- FIG. 6 is a second group of signal traces based on the circuit shown in FIG. 4 ;
- FIG. 7 is a delay circuit
- FIG. 8 is a group of signal traces based on the circuit shown in FIG. 7 .
- the offset of the current reversal comparator is preferably automatically adjusted for any suitable output voltage and inductor value.
- the adaptive current reversal comparator ensures the synchronous transistor is substantially always turned OFF at about zero inductor current—i.e., about the point of current reversal in the secondary switch.
- the current reversal comparator is active preferably only in discontinuous conduction mode (DCM).
- DCM discontinuous conduction mode
- the current reversal comparator prevents inductor current reversal by turning OFF the synchronous transistor thereby mimicking a rectifying diode to prevent the backflow of current through the inductor.
- CCM continuous conduction mode
- the current reversal comparator is inactive, since the inductor current, by definition, does not reverse.
- the synchronous transistor can either turn OFF too early or turn OFF too late.
- the stored energy left in the inductor pulls the SW pin 114 below ground, until the internal body diode of the synchronous transistor conducts the necessary current and clamps the transistor pin at ⁇ 0.7 volts.
- conducting through the body diode results in a reduction of efficiency because it is more efficient to conduct through the channel of the synchronous transistor than it is to conduct through the body diode of the synchronous transistor.
- the reverse stored energy in the inductor pushes SW pin 114 HIGH right after the synchronous transistor is turned OFF.
- the adaptive current reversal comparator takes advantage of these differences and servos its offset voltage such that the synchronous transistor is preferably turned OFF within a predetermined window of the discharge point of the inductor (wherein the inductor is substantially completely discharged)—i.e., the point of current reversal in the synchronous transistor.
- the offset voltage of the adaptive current reversal comparator which controls where the comparator actually trips as opposed to where it should trip, is served such that the comparator (which responds to the discharge point of the inductor) substantially always trips within a certain predetermined time of the tripping of the synchronous transistor.
- FIG. 1 shows the circuit implementation 100 of the adaptive current reversal comparator (RCMP) 101 .
- the offset of RCMP 101 is developed by a current dropped across resistor 102 (which is the offset resistor coupled to the gate of transistor 135 and which receives a constant current from current source 106 .) This current is modulated by transistor 104 to servo the offset voltage as needed.
- Transistor 104 is adapted to steer current away from a constant current source 106 as necessary.
- the offset voltage can range from zero volts to a maximum of the current through source 106 ⁇ the resistance of resistor 102 .
- Transistor 103 preferably provides level shifting to allow the current steering to be implemented.
- Charging and discharging capacitor 108 modulates the RCMP offset voltage. To increase the offset voltage, capacitor 108 is discharged, and conversely to decrease the offset voltage, capacitor 108 is charged.
- the implementation of the comparator offset servo loop could just as well be implemented with a digital counter (not shown) or a digital-to-analog converter (DAC) (also not shown) instead of using capacitor 108 .
- DAC digital-to-analog converter
- TDR 107 is typically controlled by an input from an oscillator.
- BDR is controlled by the output of current reversal comparator 101 .
- the RCMP offset voltage should preferably be decreased.
- trace 202 representing IL
- the current through the inductor trace 204 which represents the SW pin 114 that is coupled to inductor 112
- trace 206 which represents BDR 109 input
- trace 208 which represents RESETB which is input to latches 117 and 119
- trace 210 PG which shows implementation of the decrease of the offset voltage.
- the stored energy left in inductor 112 pushes SW pin 114 (which is located at the second end of the inductor) below ground right after BDR 109 goes LOW.
- NOR gate 116 and NAND gate 118 preferably latch (which are implemented via logic 117 and 119 , respectively, and that have outputs that are inverted using inverters 133 and 132 , respectively), and drive PG 120 (coupled to the gate of transistor 122 , transistor 122 having a source coupled to constant current source 138 ) LOW, thereby charging capacitor 108 (see trace 210 in FIG. 2 ).
- Block 121 preferably provides a delay of some predetermined amount—e.g., 70 nanoseconds—to allow transistor 104 to charge up sufficiently so as to be able to influence the operation of current reversal comparator 101 .
- Trace 212 does not oscillate in FIG. 2 but its equivalent trace 312 in FIG. 3 does oscillate.
- Trace 312 NG implements the increase of the offset voltage (see FIG. 3 ) wherein the BDR trace 306 shows BDR 109 forcing transistor 110 LOW after inductor 112 , carrying IL 202 , has fully discharged and reversed polarity.
- FIG. 3 includes trace 302 representing IL, the current through the inductor, trace 304 which represents the pin voltage at SW pin 114 , trace 306 which represents BDR 109 input, trace 308 which represents RESETB which is input to latches 117 and 119 , trace 309 PG (which is flat under the conditions shown in FIG. 3 ), and trace 310 which shows NG implementing the increase of the offset voltage.
- circuitry may be needed to recognize and/or distinguish the situation where the regulator is running in CCM at relatively HIGH output load current, and CCM at relatively LOW output load current.
- CCM at HIGH output load current the traces for which are shown in FIG. 5
- the inductor current does not reverse—i.e., the inductor current is typically above a certain threshold value.
- circuitry is preferably only needed to prevent capacitor 108 from charging or discharging—i.e., circuitry that maintains capacitor 108 at a preferably predetermined independent value.
- the regulator may be running in forced continuous mode and the inductor current may reverse. In this case, capacitor 108 needs to discharge to raise the RCMP offset voltage.
- FIG. 4 shows additional circuitry.
- This additional circuitry preferably distinguishes CCM at HIGH output load current from CCM at LOW output load current (and, preferably, both conditions from DCM mode).
- NICMP comparison circuit 450 is used to detect whether SW pin 114 dips below ground or not. In the case of CCM at HIGH output load current, SW pin 114 dips below ground immediately following the falling edge of BDR 109 and circuit 450 goes HIGH. (See FIG.
- trace 502 shows the inductor current IL 112
- trace 504 shows SW pin 114
- trace 506 shows BDR 109
- trace 508 shows TDR 107
- trace 510 shows circuit 450 .
- circuit 450 resets latch 452 , which also is coupled to receive an input from TDR 107 , allows TDR 107 through latch 454 and gate 456 to pull RESETB LOW (see trace 512 ), keeping both PG 120 HIGH and NG 123 LOW (see traces 514 and 516 ). Keeping PG 120 HIGH and NG 123 LOW maintains the offset voltage independent of oscillation of IL 502 at preferably more than a predetermined threshold.
- capacitor 108 is allowed to charge or discharge—i.e., is flexible—as needed to prevent the inductor current from reversing.
- Inverter 481 and 482 invert the signals at the outputs of TDR 107 and 450 resectively.
Abstract
Description
- This invention relates to voltage regulators. More specifically this invention relates to switching regulators with synchronous rectification.
- A synchronous switching regulator typically includes a first transistor that is ON during a first portion of a switching cycle and a second transistor that is ON during a second portion of the switching cycle. During the first portion of the switching cycle, the first transistor conducts between a power supply and an inductor. The second transistor is typically OFF during the first portion of the cycle. In the first portion of the cycle, power is transmitted from the power supply through the first transistor to the inductor (which in turn is typically coupled to a load and/or load capacitor). During a second portion of the cycle, the second transistor, which may be referred to herein as the synchronous transistor, turns ON and couples ground (or some other suitable reference voltage) to the end of the inductor that is not coupled to the load. In certain parts of the switching cycle, both transistors may be OFF and the end of the inductor not coupled to the load may, in fact, be floating.
- Switching regulators with synchronous rectification preferably require a comparator, or for the purposes of this application other suitable comparison circuit, that monitors current reversal across the synchronous transistor. An ideal comparator with zero propagation delay would simply trip—i.e., change from a first output state to a second output state—when a sign reversal is detected across the synchronous transistor. The output of the comparator is used to control the operation of the second transistor.
- However, real comparators must offset the trip point to compensate for the propagation delays associated with the current reversal in the output inductor. The offset required depends on the propagation delay of the comparator and the time the inductor current takes to reach zero from the trip point. These two factors typically depend on the output voltage of the regulator and the inductor value used, both of which are typically beyond the IC (integrated circuit) designer's control. The current state of the art is to select the most likely output voltage and its corresponding inductor value, and then calculate the offset voltage the comparator needs. This approach works reasonably well for many applications. But for some applications the comparator either trips too early or too late, resulting in lowered efficiency.
- It would be desirable to provide current reversal comparison circuits and methods that automatically adjusts for any suitable output voltage and/or inductor value.
- It is an object of the invention to provide current reversal comparison circuits and methods that are automatically adjustable for any suitable output voltage and/or inductor value.
- A method of providing power to a load using a synchronous switching regulator according to one embodiment of the invention is provided. The synchronous switching regulator includes a power supply, a main transistor that typically operates as a switch, a synchronous transistor, and an inductor having one side coupled to the load.
- The method preferably includes turning ON a first transistor during a first portion of a switching cycle. The first transistor is preferably coupled to a second side of the inductor, the first transistor that conducts between the power supply and the inductor during the first portion of the switching cycle. The method also preferably includes turning ON a second transistor that is ON during a second portion of the switching cycle and that is OFF during the remainder of the switching cycle, the second transistor that is also coupled to the second side of the inductor. The second transistor conducts between ground and the inductor during the second portion of the switching cycle.
- The method also includes detecting a trip point at which the voltage at the second side of the inductor is about zero, the detecting using a comparison circuit, determining a time differential between the trip point and an end of the second portion of the switching cycle, and, finally adjusting an offset of the comparison circuit in response to the time differential.
- The following detailed description of the embodiments of the present disclosure can best be understood when read in conjunction with the following drawings, in which the features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features, wherein
-
FIG. 1 is a synchronous switching regulator according to the invention; -
FIG. 2 is a group of signal traces based on the circuit shown inFIG. 1 ; -
FIG. 3 is a second group of signal traces based on the circuit inFIG. 1 ; -
FIG. 4 is a second synchronous switching regulator according to the invention; -
FIG. 5 is a group of signal traces based on the circuit inFIG. 4 ; -
FIG. 6 is a second group of signal traces based on the circuit shown inFIG. 4 ; -
FIG. 7 is a delay circuit; and -
FIG. 8 is a group of signal traces based on the circuit shown inFIG. 7 . - In the present invention, the offset of the current reversal comparator is preferably automatically adjusted for any suitable output voltage and inductor value. The adaptive current reversal comparator ensures the synchronous transistor is substantially always turned OFF at about zero inductor current—i.e., about the point of current reversal in the secondary switch.
- In synchronous regulators, the current reversal comparator is active preferably only in discontinuous conduction mode (DCM). The current reversal comparator prevents inductor current reversal by turning OFF the synchronous transistor thereby mimicking a rectifying diode to prevent the backflow of current through the inductor. In continuous conduction mode (CCM), the current reversal comparator is inactive, since the inductor current, by definition, does not reverse.
- In convention implementations of DCM circuitry, the synchronous transistor can either turn OFF too early or turn OFF too late. When it turns OFF too early, the stored energy left in the inductor pulls the
SW pin 114 below ground, until the internal body diode of the synchronous transistor conducts the necessary current and clamps the transistor pin at −0.7 volts. Typically, conducting through the body diode results in a reduction of efficiency because it is more efficient to conduct through the channel of the synchronous transistor than it is to conduct through the body diode of the synchronous transistor. When the synchronous transistor turns OFF too late, the reverse stored energy in the inductor pushesSW pin 114 HIGH right after the synchronous transistor is turned OFF. - The adaptive current reversal comparator according to the invention takes advantage of these differences and servos its offset voltage such that the synchronous transistor is preferably turned OFF within a predetermined window of the discharge point of the inductor (wherein the inductor is substantially completely discharged)—i.e., the point of current reversal in the synchronous transistor. In other words, the offset voltage of the adaptive current reversal comparator, which controls where the comparator actually trips as opposed to where it should trip, is served such that the comparator (which responds to the discharge point of the inductor) substantially always trips within a certain predetermined time of the tripping of the synchronous transistor.
- Circuit Implementation
-
FIG. 1 shows thecircuit implementation 100 of the adaptive current reversal comparator (RCMP) 101. The offset of RCMP 101 is developed by a current dropped across resistor 102 (which is the offset resistor coupled to the gate oftransistor 135 and which receives a constant current fromcurrent source 106.) This current is modulated bytransistor 104 to servo the offset voltage as needed.Transistor 104 is adapted to steer current away from a constantcurrent source 106 as necessary. Thus, the offset voltage can range from zero volts to a maximum of the current throughsource 106× the resistance ofresistor 102.Transistor 103 preferably provides level shifting to allow the current steering to be implemented. - Charging and discharging
capacitor 108 modulates the RCMP offset voltage. To increase the offset voltage,capacitor 108 is discharged, and conversely to decrease the offset voltage,capacitor 108 is charged. - Alternatively, the implementation of the comparator offset servo loop could just as well be implemented with a digital counter (not shown) or a digital-to-analog converter (DAC) (also not shown) instead of using
capacitor 108. - TDR 107 is typically controlled by an input from an oscillator. In DCM, BDR is controlled by the output of current
reversal comparator 101. - In the case when the synchronous FET (NFET),
transistor 110, is turned OFF too early byBDR 109, the RCMP offset voltage should preferably be decreased. (SeeFIG. 2 , which includestrace 202 representing IL, the current through the inductor,trace 204 which represents theSW pin 114 that is coupled toinductor 112,trace 206 which representsBDR 109 input,trace 208 which represents RESETB which is input tolatches trace 210 PG, which shows implementation of the decrease of the offset voltage.1 The stored energy left ininductor 112 pushes SW pin 114 (which is located at the second end of the inductor) below ground right after BDR 109 goes LOW. Some time after the inductor current has dischargedSW pin 114 swings HIGH and settles to the output voltage (VOUT). The time it takes BDR 109 (which responds to current reversal intransistor 110 as stated above) to go LOW andSW 114 to go HIGH is compared against a 20 nanoseconds delayed BDR signal 115 (which is coupled to receive an input from BDR 109). If the time differential betweenBDR 109 going LOW andSW 114 going HIGH is greater than 20 nanoseconds, NORgate 116 andNAND gate 118 preferably latch (which are implemented vialogic inverters transistor 122,transistor 122 having a source coupled to constant current source 138) LOW, thereby charging capacitor 108 (seetrace 210 inFIG. 2 ).Block 121 preferably provides a delay of some predetermined amount—e.g., 70 nanoseconds—to allowtransistor 104 to charge up sufficiently so as to be able to influence the operation ofcurrent reversal comparator 101.
1Trace 212 does not oscillate inFIG. 2 but its equivalent trace 312 inFIG. 3 does oscillate. Trace 312 NG implements the increase of the offset voltage (seeFIG. 3 ) wherein theBDR trace 306 showsBDR 109 forcingtransistor 110 LOW afterinductor 112, carryingIL 202, has fully discharged and reversed polarity.
- In the situation when
transistor 110 is turned OFF too late, SW pin 114 swings HIGH immediately afterBDR 109 goes LOW. In thiscase gate 116 andgate 118 latch in the opposite state, and drive NG 123 (which is coupled to the gate oftransistor 124 which itself is preferably coupled to constant current sink 136) is HIGH thereby discharging capacitor 108 (seetrace 310 inFIG. 3 ).FIG. 3 includestrace 302 representing IL, the current through the inductor,trace 304 which represents the pin voltage atSW pin 114,trace 306 which representsBDR 109 input,trace 308 which represents RESETB which is input to latches 117 and 119,trace 309 PG (which is flat under the conditions shown inFIG. 3 ), and trace 310 which shows NG implementing the increase of the offset voltage. - CCM at High Load and CCM at Low Load
- Additional circuitry may be needed to recognize and/or distinguish the situation where the regulator is running in CCM at relatively HIGH output load current, and CCM at relatively LOW output load current. In CCM at HIGH output load current (the traces for which are shown in
FIG. 5 ), the inductor current does not reverse—i.e., the inductor current is typically above a certain threshold value. Thus, circuitry is preferably only needed to preventcapacitor 108 from charging or discharging—i.e., circuitry that maintainscapacitor 108 at a preferably predetermined independent value. - In CCM at LOW output load current (the traces for which are shown in
FIG. 6 ), the regulator may be running in forced continuous mode and the inductor current may reverse. In this case,capacitor 108 needs to discharge to raise the RCMP offset voltage. -
FIG. 4 shows additional circuitry. This additional circuitry preferably distinguishes CCM at HIGH output load current from CCM at LOW output load current (and, preferably, both conditions from DCM mode). To distinguish CCM at HIGH output load current from CCM at LOW output load current,NICMP comparison circuit 450 is used to detect whether SW pin 114 dips below ground or not. In the case of CCM at HIGH output load current,SW pin 114 dips below ground immediately following the falling edge ofBDR 109 andcircuit 450 goes HIGH. (SeeFIG. 5 whereintrace 502 shows the inductorcurrent IL 112,trace 504 showsSW pin 114,trace 506 showsBDR 109,trace 508 showsTDR 107, and trace 510 showscircuit 450.) In CCM at HIGH output load current,circuit 450 resetslatch 452, which also is coupled to receive an input fromTDR 107, allowsTDR 107 throughlatch 454 andgate 456 to pull RESETB LOW (see trace 512), keeping bothPG 120 HIGH andNG 123 LOW (seetraces 514 and 516). KeepingPG 120 HIGH andNG 123 LOW maintains the offset voltage independent of oscillation ofIL 502 at preferably more than a predetermined threshold. - In the case of CCM at LOW output load current,
SW pin 114 does not dip below ground immediately following the falling edge ofBDR 109 andcircuit 450 stays LOW. (SeeFIG. 6 whereintrace 602 shows inductor current 112,trace 604 showsSW pin 114,trace 606 showsBDR 109,trace 608 showsTDR 107,trace 609 shows NICMP, trace 610 shows RESETB, trace 612 showsNG 123, and trace 614 showsPG 120.) In this situation, latch 452 preferably does not reset which preventsTDR 107 from going throughlatch 454. This results in a circuit that behaves substantially identically to the circuit inFIG. 1 .capacitor 108 is allowed to charge or discharge—i.e., is flexible—as needed to prevent the inductor current from reversing.Inverter TDR - The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.
Claims (19)
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US11/408,749 US7279877B1 (en) | 2006-04-21 | 2006-04-21 | Adaptive current reversal comparator |
TW095136795A TWI396958B (en) | 2006-04-21 | 2006-10-03 | Method for adjusting the offset of a synchronous switching regulator comparison circuit, switching regulator comparison circuit, synchronous switching regulator comparison circuit, synchronous switching regulator, and method of providing power to a load |
KR1020060116141A KR101304178B1 (en) | 2006-04-21 | 2006-11-23 | Adaptive current reversal comparator |
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US11/408,749 US7279877B1 (en) | 2006-04-21 | 2006-04-21 | Adaptive current reversal comparator |
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KR101658783B1 (en) * | 2010-05-26 | 2016-09-23 | 삼성전자주식회사 | Power converter having a zero-current detecting circuit and method of converting power |
Also Published As
Publication number | Publication date |
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TWI396958B (en) | 2013-05-21 |
KR20070104200A (en) | 2007-10-25 |
KR101304178B1 (en) | 2013-09-09 |
US7279877B1 (en) | 2007-10-09 |
TW200741407A (en) | 2007-11-01 |
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