TWI470933B - Zero-current detecting circuit and operating method thereof - Google Patents

Description

Zero current detection circuit and operation method thereof

The present invention relates to error correction of an amplifier, and more particularly to an error correction circuit for a zero current comparator in a power conversion circuit.

In recent years, power supply circuits have been widely used in various electronic products, such as portable electronic products and computer products. The power supply circuit can provide voltage or current conversion or provide power with a fixed voltage or current for use in electronic products. In the power supply circuit, a power integrated circuit (Power IC) is one of the necessary active components. Therefore, in order to obtain better power conversion efficiency, the power supply integrated circuit needs to be more accurately controlled.

In the power integrated circuit, many internal circuits use components such as an amplifier or a comparator, such as an error amplifier, a current sensor, and the like. In an amplifier or comparator, a small amount of noise can affect the result of the operation. For example, due to component mismatch caused by process factors, the amplifier or comparator will be offset, thus affecting the output of its output.

A zero current detection circuit is typically used in a DC-to-DC controller or a driver associated with it to detect when the current on the output inductor is below zero in order to control the lower bridge switch to turn off. However, the zero current detection circuit usually uses a comparator for comparison, and the comparator still has an offset.

Therefore, the present invention proposes a zero current detecting circuit and an operating method thereof to solve the above problems encountered in the prior art.

One aspect of the invention is to propose a zero current detection circuit. In a preferred embodiment, the zero current detection circuit is suitable for use in a power conversion circuit. The power conversion circuit includes a control unit and a power switch, and has a normal operation mode and a zero current operation mode. The control unit is coupled to the power switch. The zero current detection circuit includes a zero current comparison unit coupled to the control unit for detecting an output current of the power conversion circuit. When the zero current comparison unit performs the self error correction procedure, if the output current is less than zero, the zero current comparison unit controls the control unit such that the power conversion circuit maintains the normal operation mode to normally turn the power switch on or off. When the zero current comparison unit ends the self-correction routine, if the output current is less than zero, the zero current comparison unit controls the control unit such that the power conversion circuit is in the zero current operation mode to turn off the power switch.

In an embodiment, the power switch is a lower bridge switch.

In an embodiment, the control unit includes a pulse width modulation controller and a driver.

In an embodiment, the control unit is a pulse width modulation controller and is coupled to the power switch through a driver.

In one embodiment, the zero current detecting circuit further includes a first offset canceling unit coupled to one of the zero current comparing unit inputs to provide a first offset. To zero current comparison unit.

In an embodiment, when the zero current comparison unit performs the self error correction procedure, the pulse width modulation controller unit provides a control signal to the first offset cancellation unit to adjust the first offset.

In one embodiment, the zero current detecting circuit further includes a first offset canceling unit coupled to one of the zero current comparing unit inputs to provide a first offset to zero current. Comparison unit.

In an embodiment, the zero current comparison unit performs a self error correction procedure The control unit provides a control signal to the first offset cancellation unit to adjust the first offset.

In one embodiment, the first input signal and the second input signal received by the zero current comparison unit are a specific voltage corresponding to the DC operating point of the zero current comparison unit, and the zero current comparison unit is based on the first input signal and The second input signal generates an output signal having a first voltage level.

In one embodiment, when the output signal of the zero current comparison unit is changed from the first voltage level to a second voltage level, the control unit provides a control signal to the first offset cancellation unit to reduce the first offset.

In an embodiment, the first offset canceling unit gradually increases the first offset according to the control signal until the output signal of the zero current comparing unit changes from the first voltage level to a second voltage level. As far as possible.

In one embodiment, the zero current detection circuit further includes a second offset cancellation unit coupled to the other input of the zero current comparison unit to provide a second offset to zero. Current comparison unit.

Another aspect of the present invention is to provide a method of operating a zero current detecting circuit. In one embodiment, the zero current detection circuit operation method is applicable to a power conversion circuit. The method comprises the steps of: (a) detecting an output current of one of the power conversion circuits; (b) performing a self-error correction procedure by the zero current detection circuit; (c) when the zero current detection circuit performs a self error correction procedure, If the output current detected in the step (a) is less than zero, the control control unit causes the power conversion circuit to maintain the normal operation mode to normally turn the power switch on or off; (d) when the zero current detection circuit ends the self error correction procedure, If the output current detected in step (a) is less than zero, the control control unit causes the power conversion circuit to operate in a zero current mode of operation to turn off the power switch.

Compared with the prior art, the zero current detecting circuit and the operator thereof according to the present invention After each system is turned on, the zero current comparison unit starts self-error correction until the zero current comparison unit completes the self error correction, and then allows the power conversion circuit to operate in the zero current operation mode to turn off the power conversion circuit. Under the bridge switch. Since the zero current comparison unit of the present invention performs the self error correction period, even if the zero current comparison unit detects that the output current of the power conversion circuit is less than zero, the zero current comparison unit controls the control unit, so that the power conversion circuit is maintained in normal operation. In the mode, the output current does not turn off the lower bridge switch, so that the zero current comparison unit can have sufficient time to complete the self-error correction operation, thereby effectively avoiding the system error situation of the power conversion circuit in the prior art, and also The correction of the error of the zero current comparison unit itself can be completed to improve the working efficiency.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

A preferred embodiment of the invention is a zero current detection circuit. In fact, the zero current detection circuit proposed by the present invention is applied to a power conversion circuit. When the zero current comparison unit of the zero current detection circuit performs self error correction, the zero current comparison unit controls the control unit to enable power conversion. The circuit is maintained in the normal operation mode without turning off the lower bridge switch, so that the zero current comparison unit can have sufficient time to complete the self-error correction operation, thereby effectively avoiding the system error situation of the power conversion circuit as in the prior art. .

Please refer to FIG. 1. FIG. 1 is a circuit diagram showing the circuit structure of the zero current detecting circuit of this embodiment. As shown in FIG. 1 , the zero current detecting circuit 10 is applied to the power conversion circuit 1 , but is not limited thereto. The power conversion circuit 1 includes a pulse width modulation controller 12 and a driver 2. The power conversion circuit 1 has a normal operation mode and a zero current operation mode. In practical applications, the pulse width modulation controller 12 and the driver 2 can be defined as control units, but not limited thereto. The zero current detecting circuit 10 and the pulse width modulation controller 12 are respectively coupled to the driver 2, and the driver 2 is coupled to the output stage 3 and the output inductor L. The output stage 3 includes a first switch US and a second switch (power switch) LS, wherein the first switch US is an upper bridge switch and the second switch LS is a lower bridge switch. One end of the first switch US is coupled to one end of the second switch LS, and the other end of the first switch US and the other end of the second switch LS are coupled to the ground end G. The current flowing through the output inductor L is defined as the output current I _L of the power conversion circuit 1. One end of the output capacitor C is coupled to the ground terminal G, and the other end is coupled to the junction K between the output inductor L and the output terminal E. The pulse width modulation controller 12 is also coupled between the output terminal E and the contact point K.

In this embodiment, the zero current detecting circuit 10 includes a zero current comparing unit 100, a logic control unit 102, a selecting unit 104, a timing unit 106, a starting unit 108, a first offset eliminating unit ofs, and N second offsets. Remove the units ofs1~ofsN. The zero current comparison unit 100 has a first input terminal +, a second output terminal - and an output terminal N. The first offset cancellation unit of is coupled to the first input terminal + of the zero current comparison unit 100 and used to provide the first offset to the zero current comparison unit 100. The N second offset cancellation units ofs1~ofsN are coupled to the second output terminal of the zero current comparison unit 100 through the selection unit 104 and used to provide the second offset to the zero current comparison unit 100.

The input signals input to the zero current detecting circuit 10 include Vp and Vn. The input signal Vp is corrected by a first offset (for example, a set of natural correction values) of the first offset canceling unit ofs, and then input to the zero current comparing unit 100 through the first input terminal +, and the selecting unit 104 is removed from the N second offsets. One or more sets of balance correction values are selected as the second offset of the N sets of balance correction values of the shift cancellation units ofs1 to fs, and are corrected by the input signal Vn and then input to the zero current comparison unit 100 through the second output terminal. The output terminal N of the zero current comparison unit 100 is used to provide an output signal to the next stage circuit NS and the logic control unit 102. The logic control unit 102 is respectively coupled to the output terminal N of the zero current comparison unit 100, the selection unit 104, and the timing list. Yuan 106. The timing unit 106 is coupled to the activation unit 108 and the driver 2, respectively. The startup unit 108 is coupled to the driver 2 and the pulse width modulation controller 12, respectively.

Please refer to FIG. 2. FIG. 2 is a timing diagram showing the operation of the zero current detecting circuit 10. As shown in FIG. 2, when the starting unit 108 in the zero current detecting circuit 10 receives power from the outside, the starting unit 108 provides the starting signal EN to the timing unit 106 and other internal circuits to indicate the power integrated circuit 1 The power is applied and the zero current comparison unit 100 will begin the self error correction procedure. After a period of time ΔT, the zero current comparison unit 100 has completed the self error correction procedure, and the startup unit 108 will start to provide the zero current detection start signal ZCEN to the timing unit 106 and other internal circuits to indicate the self error correction procedure. completed.

It should be noted that when the startup unit 108 provides the startup signal EN to indicate that the power supply integrated circuit 1 is powered on, the pulse width modulation signal PWM is generated according to a fixed frequency, and the control signal UG and the pulse width of the first switch US are used. The modulation signal PWM is the same, and during the period ΔT during which the zero current comparison unit 100 performs the self error correction procedure, the control signal LG of the second switch LS is opposite to the control signal UG of the first switch US, that is, when the first switch When the US is turned on, the second switch LS is turned off, or when the second switch LS is turned on, the first switch US is turned off.

This is because during the period ΔT during which the zero current comparison unit 100 performs the self error correction procedure, the startup unit 108 of the zero current detection circuit 10 has not provided the zero current detection start signal ZCEN to the timing unit 106 and other internal circuits, representing the self. The error correction procedure has not been completed, so even at the first time t ₁ and the second time t ₂ , the output current I _L flowing through the output inductor L drops to zero, but since the zero current detecting circuit 10 is not allowed to be controlled The driver 2 performs a zero current detection operation on the output current I _L flowing through the output inductor L. Therefore, the driver 2 does not provide the notification signal ZCDET detecting the zero current to the driver 2, and of course does not control the driver 2 to turn off the second. Switch LS, but keep the second switch LS in the on state.

Until the start unit 108 provides the zero current detection start signal ZCEN to indicate that the self error correction procedure has been completed, the driver 2 is allowed to perform the zero current detection action on the output current I _L flowing through the output inductor L, thus At the third time t ₃ and the fourth time t ₄ , the output current I _L flowing through the output inductor L drops to zero, and the driver 2 provides the notification signal ZCDET detecting the zero current to the driver 2 to control the driver 2 to be turned off. The second switch LS is as shown by the control signal LG of the second switch LS in FIG. It should be noted that the shaded portion shown in FIG. 2 represents the energy loss caused by the negative output current I _L .

It should be particularly noted that during the period ΔT during which the zero current comparison unit 100 performs the self error correction program, the zero current comparison unit 100 will control the driver 2 so that the power conversion circuit 1 is maintained in the normal operation mode, and the driver 2 receives even if The zero current detection enable signal to the outside does not perform the zero current detection action on the output current I _L flowing through the output inductor L. That is, when the zero current comparison unit 100 performs the self error correction procedure, the driver 2 is not allowed to perform the zero current detection action. Therefore, during the period ΔT during which the zero current comparison unit 100 performs the self error correction process, even if the output current I _L flowing through the output inductor L is less than zero, the pulse width modulation controller 12 does not control the driver 2 to turn off the second switch. LS, but the control driver 2 maintains the second switch LS in an on state.

When the zero current comparison unit 100 completes the self error correction procedure, the zero current comparison unit 100 will control the driver 2 such that the power conversion circuit 1 operates in the zero current operation mode, and the driver 2 is allowed to output current through the output inductor L. I _L performs the action of zero current detection. Once the driver 2 detects that the output current flowing through the output inductor L is less than zero, the pulse width modulation controller 12 controls the driver 2 to turn off the second switch LS. Since the driver 2 is allowed to perform the zero current detection action after the zero current comparison unit 100 completes the self error correction process, it does not close the second time during the self current error correction process by the zero current comparison unit 100. The switch LS allows the zero current comparison unit 100 to have sufficient time to perform the self-error correction operation, so that the system error of the power integrated circuit as in the prior art can be effectively avoided.

In addition, during the self-error correction process performed by the zero current comparison unit 100, the pulse width modulation controller 12 can provide the control signal to the first offset cancellation unit ofs and the second offset cancellation unit ofs1~ofsN respectively to adjust the first Offset and second offset.

The manner in which the first offset and the second offset are adjusted is increased or decreased, which may vary depending on actual needs. For example, when the output signal changes from the first voltage level to the second voltage level, the pulse width modulation controller 12 provides the control signal to the first offset cancellation unit ofs (or the second offset cancellation unit ofs1~). ofsN) to lower the first offset (or second offset). In addition, the pulse width modulation controller 12 can also gradually increase the first offset (or the second offset) according to the control signal until the output signal changes from the first voltage level to the second voltage level.

Another embodiment of the present invention is a method of operating a zero current detecting circuit. In this embodiment, the zero current detection circuit operation method is applicable to a power conversion circuit for operating a zero current detection circuit. The power conversion circuit includes a control unit and a power switch, and the control unit is coupled to the power switch, and the power conversion circuit has a normal operation mode and a zero current operation mode. Please refer to FIG. 3. FIG. 3 is a flow chart showing the operation method of the zero current detecting circuit. As shown in FIG. 3, in step S10, the method detects an output current of one of the power conversion circuits.

Next, in step S12, the zero current detecting circuit performs a self error correction procedure. In practical applications, the zero current detection circuit includes a zero current comparison unit, and the zero current comparison unit includes a first input terminal, a second output terminal, and an output terminal. For example, in the self-error correction program, an input signal can be corrected by a set of natural correction values before being input to the first input of the zero-current comparison unit; the other input signal can be balanced by the N-group first. One or more groups selected in the correction value The correction value is corrected and then input to the second output of the zero current comparison unit. Then, the zero current comparison unit generates an output signal according to the corrected two input signals and outputs the output signal to complete the self error correction procedure.

The above self-error correction program can be applied to each stage of the amplifier/comparator in addition to being applied to the input of an amplifier/comparator (for example, a zero current comparison unit) to eliminate the offset. limit.

In particular, during the self-error correction process of the zero current detection circuit, the driver will not perform any zero current detection on the output current flowing through the output inductor even if it receives an external zero current detection enable signal. The action. Since the driver does not perform the zero current detection operation, the method does not control the driver even if the output current flowing through the output inductor is less than zero during the self-error correction process of the zero current detection circuit. Turn off the second switch.

When the zero current detecting circuit performs the self error correcting process (step S12), if the output current detected in step S10 is less than zero, the method will execute step S14, and the control control unit maintains the power converting circuit in the normal operating mode. To turn the power switch on or off normally.

When the zero current detecting circuit ends the self error correcting process (step S12), if the output current detected in step S10 is less than zero, the method will execute step S16, and the control control unit causes the power converting circuit to operate in the zero current operating mode. Next, to turn off the power switch.

In fact, as shown in FIG. 4, the above step S12 may include sub-steps S120-S128. In the step S120, the first input end and the second output end of the zero current comparison unit respectively receive the first input signal and the second input signal and output the output signal by the output end of the zero current comparison unit. The first input signal and the second input signal are a specific voltage corresponding to the DC operating point of the zero current comparison unit, and the zero current comparison unit generates the first according to the first input signal and the second input signal. A voltage level output signal.

In step S122, the method provides a first offset to zero current comparison unit. Next, during the self error correction procedure, the method adjusts the first offset (step S124).

Similarly, the method may also perform step S126 to provide a second offset to zero current comparison unit. Next, during the self error correction procedure, the method adjusts the second offset (step S128).

As for the manner in which the method adjusts the first offset and the second offset in steps S124 and S128, the manner of increasing or decreasing may be different depending on actual needs. For example, the method reduces the first offset (second offset) when the output signal changes from the first voltage level to the second voltage level. In addition, the zero current comparison unit may gradually increase the first offset (second offset) until the output signal changes from the first voltage level to the second voltage level, without particular limitation.

Compared with the prior art, the zero current detecting circuit and the operating method thereof according to the present invention are such that after each power-on, the zero current comparison unit starts self-error correction until the zero current comparison unit completes the self error correction. The power conversion circuit is allowed to operate in a zero current mode of operation to turn off the lower bridge switch in the power conversion circuit. Since the zero current comparison unit of the present invention performs the self error correction period, even if the zero current comparison unit detects that the output current of the power conversion circuit is less than zero, the zero current comparison unit controls the control unit, so that the power conversion circuit is maintained in normal operation. In the mode, the lower bridge switch is not turned off, so that the zero current comparison unit can have sufficient time to complete the self-error correction operation, so that the system error situation of the power conversion circuit as in the prior art can be effectively avoided, and the system can also be completed. The zero current comparison unit corrects the error of the unit itself to improve its working efficiency.

The features and spirit of the present invention are more clearly described in the above detailed description of the preferred embodiments. The scope of the invention is limited. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

S10~S128‧‧‧ Process steps

1‧‧‧Power conversion circuit

10‧‧‧zero current detection circuit

12‧‧‧ Pulse width modulation controller

2‧‧‧ Drive

3‧‧‧Output level

L‧‧‧Output inductor

C‧‧‧ output capacitor

G‧‧‧ Grounding terminal

E‧‧‧ output

K‧‧‧Contact

US‧‧‧first switch

LS‧‧‧second switch

100‧‧‧Zero current comparison unit

102‧‧‧Logical Control Unit

104‧‧‧Selection unit

106‧‧‧Time unit

108‧‧‧Starting unit

Ofs1~ofsN‧‧‧Second offset elimination unit

Ofs‧‧‧First offset elimination unit

+‧‧‧first input

-‧‧‧second output

N‧‧‧ output

Vp, Vn‧‧‧ input signal

NS‧‧‧Next level circuit

Vout‧‧‧ output voltage

EN‧‧‧ start signal

ZCEN‧‧‧Zero current detection start signal

PWM‧‧‧ pulse width modulation signal

I _L ‧‧‧Output current

UG‧‧‧ control signal of the first switch

LG‧‧‧ control signal of the second switch

ZCDET‧‧‧ detected zero current notification signal

1 is a schematic diagram of a zero current detecting circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the zero current detecting circuit of FIG. 1.

3 is a flow chart showing a method of operating a zero current detecting circuit according to another embodiment of the present invention.

FIG. 4 is a flow chart showing sub-steps S120-S128 of step S12 in FIG.

1‧‧‧Power conversion circuit

10‧‧‧zero current detection circuit

12‧‧‧ Pulse width modulation controller

2‧‧‧ Drive

3‧‧‧Output level

L‧‧‧Output inductor

C‧‧‧ output capacitor

G‧‧‧ Grounding terminal

E‧‧‧ output

K‧‧‧Contact

US‧‧‧first switch

LS‧‧‧second switch

100‧‧‧Zero current comparison unit

102‧‧‧Logical Control Unit

104‧‧‧Selection unit

106‧‧‧Time unit

108‧‧‧Starting unit

Ofs‧‧‧First offset elimination unit

Ofs1~ofsN‧‧‧Second offset elimination unit

+‧‧‧first input

-‧‧‧second output

N‧‧‧ output

Vp, Vn‧‧‧ input signal

NS‧‧‧Next level circuit

Vout‧‧‧ output voltage

Claims (17)

A zero current detecting circuit is applicable to a power conversion circuit. The power conversion circuit includes a control unit and a power switch. The control unit is coupled to the power switch. The power conversion circuit has a normal operation mode and a zero current operation. a mode, the zero current detecting circuit includes: a zero current comparing unit coupled to the control unit, and detecting an output current of the power converting circuit, wherein when the zero current comparing unit performs a self error correction program, The output current is less than zero, and the zero current comparison unit controls the control unit such that the power conversion circuit is maintained in the normal operation mode to normally turn the power switch on or off, wherein the zero current comparison unit ends the self error correction In the program, if the output current is less than zero, the zero current comparison unit controls the control unit such that the power conversion circuit operates in the zero current operation mode to turn off the power switch. The zero current detecting circuit of claim 1, wherein the power switch is a lower bridge switch. The zero current detecting circuit of claim 1, wherein the control unit comprises a pulse width modulation controller and a driver. The zero current detecting circuit of claim 1, wherein the control unit is a pulse width modulation controller, and the power switch is coupled through a driver. The zero current detecting circuit further includes a first offset canceling unit coupled to the zero current detecting circuit according to claim 1 The zero current comparison unit is coupled to one of the inputs to provide a first offset to the zero current comparison unit. The zero current detecting circuit of claim 5, wherein when the zero current comparing unit performs the self error correcting process, the control unit provides a control signal to the first offset canceling unit to adjust the The first offset. The zero current detecting circuit of claim 6, wherein the first input signal and the second input signal received by the zero current comparing unit are one corresponding to a DC operating point of the zero current comparing unit. a specific voltage, and the zero current comparison unit generates an output signal having a first voltage level according to the first input signal and the second input signal. The zero current detecting circuit of claim 7, wherein the control unit provides the control signal when the output signal of the zero current comparing unit changes from the first voltage level to a second voltage level Up to the first offset cancellation unit to reduce the first offset. The zero current detecting circuit of claim 7, wherein the first offset eliminating unit gradually increases the first offset according to the control signal until the output signal of the zero current comparing unit is The first voltage level changes to a second voltage level. The zero current detecting circuit further includes a second offset canceling unit coupled to the other of the zero current comparing units, as described in claim 5 The input terminal provides a second offset to the zero current comparison unit. A zero current detection circuit operation method, suitable for a power conversion circuit, the electricity The source switching circuit includes a control unit and a power switch. The control unit is coupled to the power switch. The power conversion circuit has a normal operation mode and a zero current operation mode. The operation method includes the following steps: (a) detecting the One of the power conversion circuits outputs a current; (b) the zero current detection circuit performs a self error correction process; (c) when the zero current detection circuit performs the self error correction process, if step (a) detects The output current is less than zero, the control unit is controlled to maintain the power conversion circuit in the normal operation mode to normally turn the power switch on or off; and (d) when the zero current detection circuit ends the self error correction procedure When the output current detected in the step (a) is less than zero, the control unit is controlled such that the power conversion circuit operates in the zero current operation mode to turn off the power switch. The method of operating a zero current detecting circuit according to claim 11, wherein the power switch is a lower bridge switch. The method for operating a zero current detecting circuit according to claim 11, further comprising the steps of: providing a first offset to the zero current detecting circuit; and when the zero current detecting circuit performs the self error The first offset provided to the zero current detecting circuit is adjusted during the calibration process. The zero current detecting circuit operating method of claim 13, wherein the first current input signal and the second input signal received by the zero current detecting circuit are DC corresponding to the zero current detecting circuit A specific voltage of the operating point, and the zero current detecting circuit generates an output signal having a first voltage level according to the first input signal and the second input signal. The method for operating a zero current detecting circuit according to claim 14, further comprising the step of: providing a zero current detection when the output signal is changed from the first voltage level to a second voltage level The first offset of the circuit is measured. The method for operating a zero current detecting circuit according to claim 14, further comprising the steps of: gradually increasing the first offset provided to the zero current detecting circuit until the output signal is from the first voltage The level changes to a second voltage level. The method for operating a zero current detecting circuit according to claim 13 , further comprising the steps of: providing a second offset to the zero current detecting circuit; and when the zero current detecting circuit performs the self error When the program is corrected, the second offset provided to the zero current detecting circuit is adjusted.