US20070241792A1 - Apparatus for hysteresis based process compensation for cmos receiver circuits - Google Patents

Apparatus for hysteresis based process compensation for cmos receiver circuits Download PDF

Info

Publication number
US20070241792A1
US20070241792A1 US11/279,658 US27965806A US2007241792A1 US 20070241792 A1 US20070241792 A1 US 20070241792A1 US 27965806 A US27965806 A US 27965806A US 2007241792 A1 US2007241792 A1 US 2007241792A1
Authority
US
United States
Prior art keywords
stage
output
nfet
pfet
nand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/279,658
Other versions
US7282961B1 (en
Inventor
Darin Daudelin
Michael Lencioni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/279,658 priority Critical patent/US7282961B1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LENCIONI, MICHAEL J., DAUDELIN, DARIN
Application granted granted Critical
Publication of US7282961B1 publication Critical patent/US7282961B1/en
Publication of US20070241792A1 publication Critical patent/US20070241792A1/en
Assigned to GOOGLE INC. reassignment GOOGLE INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GOOGLE LLC reassignment GOOGLE LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: GOOGLE INC.
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

Definitions

  • the present invention relates generally to digital receiver circuits and, more particularly, to an apparatus for hysteresis based process compensation for CMOS receiver circuits.
  • CMOS Complementary Metal Oxide Semiconductor
  • NAND-INVERTER 100 One common type of CMOS receiver is what is referred to as a NAND-INVERTER 100 , shown in FIG. 1 .
  • This receiver 100 includes a first NAND gate stage 102 and a second inverter stage 104 , and has a pair of inputs thereto.
  • a first input (PAD) represents the actual data that is input to the receiver, while a second input (ENABLE) is used to selectively pass the input signal received at the data input (PAD). Otherwise, the output (OUT) of the receiver 100 is driven to logic 0 regardless of the value of the input signal.
  • the data input PAD is connected to the gates of PFET P 1 and NFET N 1 .
  • the ENABLE input is connected to the gates of PFET P 1 and NFET N 1 .
  • the PFETs P 1 and P 2 are connected in parallel, while the NFETs N 1 and N 2 are connected in series, thereby forming a NAND gate 102 of conventional design.
  • the output of the NAND gate 102 defines an intermediate node 106 , which is connected to the gates of PFET P 3 and NFET N 3 (arranged as a conventional inverter 104 ), the output of which is the output of the receiver 100 .
  • the input NAND stage 102 operates at the off-chip voltage (V DD2 ) while the output inverter stage 104 operates at the internal chip voltage (V DD )
  • FIG. 1 further illustrates the use of hysteresis through a pair of inverter stages 108 , 110 , configured as a latch that reinforces the value of the intermediate node 106 .
  • This arrangement is intended to create a higher input voltage threshold value (V TH ) when the output transitions from low to high, and a lower input voltage threshold value (V TL ) when the output transitions from high to low. Thereby, an input noise margin of V TH ⁇ V TL is provided.
  • a process compensation circuit for an inverting element of a CMOS device including a duplicate inverting element connected in parallel with the inverting element of the CMOS device.
  • An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device.
  • the upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.
  • a process compensation device for a CMOS receiver having a NAND stage and an inverter stage includes a duplicate NAND gate stage connected in parallel with the NAND gate stage of the CMOS receiver.
  • An upside-down inverter stage has an input connected to the output of the duplicate NAND gate stage, and an output connected to the output of the NAND stage of the CMOS receiver.
  • the upside-down inverter stage is configured to counteract a delayed logic transition of the output of the NAND gate stage of the CMOS device in the event of a process skew between NFET and PFET devices.
  • a CMOS receiver device in still another embodiment, includes an input NAND stage operating at a first voltage level, the input NAND stage having a data input and an enable input connected thereto.
  • An output inverter stage operates at a second voltage level, the output inverter stage having an input connected to an output of the input NAND stage, which defines an intermediate node.
  • a hysteresis latch is coupled to the intermediate node, the hysteresis latch including a pair of inverter stages.
  • a process compensation circuit is coupled in parallel with the input NAND stage, the process compensation circuit further including a duplicate NAND stage receiving the data input and the enable input.
  • An upside-down inverter stage has an input coupled to an output of the duplicate NAND stage and an output connected to the intermediate node. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of said input NAND stage in the event of a process skew between NFET and PFET devices.
  • FIG. 1 is a schematic diagram of an existing CMOS receiver circuit 100 with hysteresis compensation
  • FIG. 2 is a schematic diagram of a CMOS receiver circuit with hysteresis based process compensation, in accordance with an embodiment of the invention.
  • FIG. 2 there is shown a schematic diagram of a CMOS receiver circuit 200 with hysteresis based process compensation, in accordance with an embodiment of the invention.
  • process compensation is implemented through the addition of a duplicate NAND stage 202 that is in turn coupled to an upside-down inverter stage 204 , the output of which is coupled to the intermediate node 106 of the receiver.
  • the term “upside-down inverter” describes a CMOS device in which the NFET device N 4 is coupled to the logic high supply rail (e.g., V DD2 ) while the PFET device P 4 is coupled to the logic low supply rail (e.g., ground), which is the opposite polarity configuration with respect to a conventional CMOS inverter.
  • the upside-down inverter stage 204 will act to compensate for a relative weakness in either the PFET devices or the NFET devices.
  • the receiver 100 of FIG. 1 suffers from a process skew such that the NFET devices are disproportionately weak with respect to the PFET devices.
  • the transition of the intermediate node 106 from logic 1 to logic 0 (corresponding to a transfer of the input signal on PAD from a 0 to a 1, and assuming ENABLE is at 1) is longer due to the weakness of N 1 and N 2 .
  • this relative weakness is exploited in order to pull down the intermediate node faster than would be the case for the receiver of FIG. 1 .
  • the duplicate NAND stage 202 generates the same slow, high to low transition output signal as NAND stage 202 .
  • the relatively stronger PFET P 4 (coupled in this case to ground) assists the intermediate node 106 to transition to low.
  • PFET devices do not strongly couple to ground potential and even though NFET devices do not strongly couple to V DD potential, the fact that P 4 is disproportionately strong with respect to N 4 provides enough of a difference to assist bringing intermediate node 106 to ground.
  • the transition of the intermediate node 106 from logic 0 to logic 1 (corresponding to a transfer of the input signal on PAD from a 1 to a 0, and assuming ENABLE is at 1) is longer due to the weakness of P 1 .
  • the duplicate NAND stage 202 generates the same slow, low to high transition output signal as NAND stage 202 .
  • the relatively stronger NFET N 4 (coupled in this case to V DD2 ) now assists the intermediate node 106 to transition to high.
  • the upside-down inverter stage 204 has essentially no effect on the transitioning of the intermediate node 106 .
  • the NFET and PFET devices of the compensation device are relatively small compared to the input NAND gate devices (e.g., on the order of about 1/10th the width), thereby making the relative area impact as a result of the added devices negligible. Accordingly, by providing the above described process compensation circuit, accurate hysteresis over wide process ranges is attainable, and without significant overhead.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

Description

    BACKGROUND
  • The present invention relates generally to digital receiver circuits and, more particularly, to an apparatus for hysteresis based process compensation for CMOS receiver circuits.
  • It is well known in the art to use CMOS (Complementary Metal Oxide Semiconductor) receivers to interface with input signals from off-chip, signals that typically operate at a different voltage with respect to the internal, on-clip devices. One common type of CMOS receiver is what is referred to as a NAND-INVERTER 100, shown in FIG. 1. This receiver 100 includes a first NAND gate stage 102 and a second inverter stage 104, and has a pair of inputs thereto. A first input (PAD) represents the actual data that is input to the receiver, while a second input (ENABLE) is used to selectively pass the input signal received at the data input (PAD). Otherwise, the output (OUT) of the receiver 100 is driven to logic 0 regardless of the value of the input signal.
  • As particularly shown in the insert portions of FIG. 1 (which depict the transistor arrangement of the NAND and inverter stages), the data input PAD is connected to the gates of PFET P1 and NFET N1. Similarly, the ENABLE input is connected to the gates of PFET P1 and NFET N1. The PFETs P1 and P2 are connected in parallel, while the NFETs N1 and N2 are connected in series, thereby forming a NAND gate 102 of conventional design. The output of the NAND gate 102 defines an intermediate node 106, which is connected to the gates of PFET P3 and NFET N3 (arranged as a conventional inverter 104), the output of which is the output of the receiver 100. For such an off-chip receiver, the input NAND stage 102 operates at the off-chip voltage (VDD2) while the output inverter stage 104 operates at the internal chip voltage (VDD)
  • Depending on process variations, among other things, the input voltage at which the output of a CMOS inverter switches can vary by as much as 700 or 800 mV. Due to this variation, the switch point of the CMOS inverter tends to be unstable and susceptible to noise. Consequently, the use of hysteresis effects enables suppression of output noise by adjusting the threshold voltages of the pull up and pull down devices in a CMOS receiver, depending on the present state of the output. For example, FIG. 1 further illustrates the use of hysteresis through a pair of inverter stages 108, 110, configured as a latch that reinforces the value of the intermediate node 106.
  • This arrangement is intended to create a higher input voltage threshold value (VTH) when the output transitions from low to high, and a lower input voltage threshold value (VTL) when the output transitions from high to low. Thereby, an input noise margin of VTH−VTL is provided.
  • However, as secondary input/output supply voltages have become lower and lower over time, the effects of PFET to NFET mistracking have become a larger percent of the total hysteresis range. This has, in turn, caused the hysteresis effects to approach or move outside of specifications under certain process conditions that have NFET to PFET skew. Accordingly, it would be desirable to be able to compensate for such devices that fall within design specifications but that do not produce acceptable yield results due to process skew.
    • SUMMARY
  • The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.
  • In another embodiment, a process compensation device for a CMOS receiver having a NAND stage and an inverter stage includes a duplicate NAND gate stage connected in parallel with the NAND gate stage of the CMOS receiver. An upside-down inverter stage has an input connected to the output of the duplicate NAND gate stage, and an output connected to the output of the NAND stage of the CMOS receiver. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the NAND gate stage of the CMOS device in the event of a process skew between NFET and PFET devices.
  • In still another embodiment, a CMOS receiver device includes an input NAND stage operating at a first voltage level, the input NAND stage having a data input and an enable input connected thereto. An output inverter stage operates at a second voltage level, the output inverter stage having an input connected to an output of the input NAND stage, which defines an intermediate node. A hysteresis latch is coupled to the intermediate node, the hysteresis latch including a pair of inverter stages. A process compensation circuit is coupled in parallel with the input NAND stage, the process compensation circuit further including a duplicate NAND stage receiving the data input and the enable input. An upside-down inverter stage has an input coupled to an output of the duplicate NAND stage and an output connected to the intermediate node. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of said input NAND stage in the event of a process skew between NFET and PFET devices.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
  • FIG. 1 is a schematic diagram of an existing CMOS receiver circuit 100 with hysteresis compensation; and
  • FIG. 2 is a schematic diagram of a CMOS receiver circuit with hysteresis based process compensation, in accordance with an embodiment of the invention.
    • DETAILED DESCRIPTION
  • Referring now to FIG. 2, there is shown a schematic diagram of a CMOS receiver circuit 200 with hysteresis based process compensation, in accordance with an embodiment of the invention. As is shown, process compensation is implemented through the addition of a duplicate NAND stage 202 that is in turn coupled to an upside-down inverter stage 204, the output of which is coupled to the intermediate node 106 of the receiver. As used herein, the term “upside-down inverter” describes a CMOS device in which the NFET device N4 is coupled to the logic high supply rail (e.g., VDD2) while the PFET device P4 is coupled to the logic low supply rail (e.g., ground), which is the opposite polarity configuration with respect to a conventional CMOS inverter.
  • In the event of a process skew, the upside-down inverter stage 204 will act to compensate for a relative weakness in either the PFET devices or the NFET devices. By way of example, it is first assumed that the receiver 100 of FIG. 1 suffers from a process skew such that the NFET devices are disproportionately weak with respect to the PFET devices. In this case, the transition of the intermediate node 106 from logic 1 to logic 0 (corresponding to a transfer of the input signal on PAD from a 0 to a 1, and assuming ENABLE is at 1) is longer due to the weakness of N1 and N2. However, through the compensation device provided in FIG. 2, this relative weakness is exploited in order to pull down the intermediate node faster than would be the case for the receiver of FIG. 1.
  • More specifically, the duplicate NAND stage 202 generates the same slow, high to low transition output signal as NAND stage 202. In the case of a weak NFET process, the relatively stronger PFET P4 (coupled in this case to ground) assists the intermediate node 106 to transition to low. Even though PFET devices do not strongly couple to ground potential and even though NFET devices do not strongly couple to VDD potential, the fact that P4 is disproportionately strong with respect to N4 provides enough of a difference to assist bringing intermediate node 106 to ground.
  • Conversely, for a process condition where the PFET devices are disproportionately weak with respect to the NFET devices, the transition of the intermediate node 106 from logic 0 to logic 1 (corresponding to a transfer of the input signal on PAD from a 1 to a 0, and assuming ENABLE is at 1) is longer due to the weakness of P1. In this case, therefore, the duplicate NAND stage 202 generates the same slow, low to high transition output signal as NAND stage 202. In the case of a weak PFET process, the relatively stronger NFET N4 (coupled in this case to VDD2) now assists the intermediate node 106 to transition to high. Finally, where no appreciable process skew exists, the upside-down inverter stage 204 has essentially no effect on the transitioning of the intermediate node 106.
  • The NFET and PFET devices of the compensation device are relatively small compared to the input NAND gate devices (e.g., on the order of about 1/10th the width), thereby making the relative area impact as a result of the added devices negligible. Accordingly, by providing the above described process compensation circuit, accurate hysteresis over wide process ranges is attainable, and without significant overhead.
  • While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (9)

1. A process compensation circuit for an inverting element of a CMOS device, comprising:
a duplicate inverting element connected in parallel with the inverting element of the CMOS device; and
an upside-down inverter stage having an input thereto connected to the output of said duplicate inverting element, and an output thereof connected to the output of said inverting element of the CMOS device;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.
2. The process compensation circuit of claim 1, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate inverting element, said NFET having a source coupled to a logic high voltage supply terminal of the CMOS device;
a PFET having a gate coupled to the output of said duplicate inverting element, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS device; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
3. The process compensation circuit of claim 2, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of the inverting element of the CMOS device.
4. A process compensation device for a CMOS receiver having a NAND stage and an inverter stage; comprising:
a duplicate NAND gate stage connected in parallel with the NAND gate stage of the CMOS receiver; and
an upside-down inverter stage having an input connected to the output of said duplicate NAND gate stage, and an output connected to the output of said NAND stage of the CMOS receiver;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of the output of the NAND gate stage of the CMOS device receiver in the event of a process skew between NFET and PFET devices.
5. The process compensation device of claim 4, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate NAND stage, said NFET having a source coupled to a first logic high voltage supply terminal of the CMOS receiver;
a PFET having a gate coupled to the output of said duplicate NAND stage, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS receiver; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
6. The compensation circuit of claim 5, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of the NAND stage of the CMOS receiver.
7. A CMOS receiver device, comprising:
an input NAND stage operating at a first voltage level, said input NAND stage having a data input and an enable input connected thereto;
an output inverter stage operating at a second voltage level, said output inverter stage having an input connected to an output of said input NAND stage, which defines an intermediate node;
a hysteresis latch coupled to said intermediate node, said hysteresis latch comprising a pair of inverter stages; and
a process compensation circuit coupled in parallel with said input NAND stage, said process compensation circuit further comprising a duplicate NAND stage receiving said data input and said enable input, and an upside-down inverter stage having an input coupled to an output of said duplicate NAND stage and an output connected to said intermediate node;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of said output of said input NAND stage in the event of a process skew between NFET and PFET devices.
8. The CMOS receiver device of claim 7, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate NAND stage, said NFET having a source coupled to a logic high voltage supply terminal of the CMOS receiver corresponding to said first voltage level;
a PFET having a gate coupled to the output of said duplicate NAND stage, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS receiver; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
9. The CMOS receiver device of claim 8, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of said input NAND stage.
US11/279,658 2006-04-13 2006-04-13 Apparatus for hysteresis based process compensation for CMOS receiver circuits Expired - Fee Related US7282961B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/279,658 US7282961B1 (en) 2006-04-13 2006-04-13 Apparatus for hysteresis based process compensation for CMOS receiver circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/279,658 US7282961B1 (en) 2006-04-13 2006-04-13 Apparatus for hysteresis based process compensation for CMOS receiver circuits

Publications (2)

Publication Number Publication Date
US7282961B1 US7282961B1 (en) 2007-10-16
US20070241792A1 true US20070241792A1 (en) 2007-10-18

Family

ID=38577785

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/279,658 Expired - Fee Related US7282961B1 (en) 2006-04-13 2006-04-13 Apparatus for hysteresis based process compensation for CMOS receiver circuits

Country Status (1)

Country Link
US (1) US7282961B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4158787B2 (en) * 2005-06-14 2008-10-01 セイコーエプソン株式会社 Semiconductor integrated circuit
US8476948B2 (en) * 2009-08-21 2013-07-02 Stmicroelectronics International N.V. Reduced area schmitt trigger circuit

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4256974A (en) * 1978-09-29 1981-03-17 Rockwell International Corporation Metal oxide semiconductor (MOS) input circuit with hysteresis
US5057711A (en) * 1989-05-31 1991-10-15 Hyundai Electronics Industries Co., Ltd. Noise reducing output buffer circuit for an integrated circuit
US5111081A (en) * 1990-12-20 1992-05-05 International Business Machines Corporation Process compensated input switching threshold of a CMOS receiver
US5315173A (en) * 1991-07-19 1994-05-24 Samsung Electronics Co., Ltd. Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion
US5319258A (en) * 1991-07-16 1994-06-07 Samsung Semiconductor, Inc. Programmable output drive circuit
US5506528A (en) * 1994-10-31 1996-04-09 International Business Machines Corporation High speed off-chip CMOS receiver
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
US6184704B1 (en) * 1999-02-08 2001-02-06 Tritech Microelectronics Design method for compensation of process variation in CMOS digital input circuits
US20010010476A1 (en) * 2000-02-01 2001-08-02 Chih-Hsien Weng Protecting apparatus for protecting the isolation circuit between different power domains
US6275094B1 (en) * 1999-06-22 2001-08-14 International Business Machines Corporation CMOS device and circuit and method of operation dynamically controlling threshold voltage
US6429710B1 (en) * 1996-09-09 2002-08-06 Etron Technology, Inc. Input buffer with compensation for process variation
US6545521B2 (en) * 2001-06-29 2003-04-08 International Business Machines Corporation Low skew, power sequence independent CMOS receiver device
US6717445B1 (en) * 2000-06-30 2004-04-06 Intel Corporation Symmetric voltage follower buffer
US6750677B2 (en) * 2001-06-04 2004-06-15 Matsushita Electric Industrial Co., Ltd. Dynamic semiconductor integrated circuit
US6879198B2 (en) * 2002-12-18 2005-04-12 Stmicroelectronics Pvt. Ltd. Differential input receiver with hysteresis
US6992518B2 (en) * 2003-04-28 2006-01-31 Via Technologies, Inc. Input receiver with hysteresis
US20070063738A1 (en) * 2005-09-16 2007-03-22 Fischer Timothy C CMOS logic circuitry

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123827A (en) 1985-11-25 1987-06-05 Hitachi Ltd Output circuit in semiconductor integrated circuit

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4256974A (en) * 1978-09-29 1981-03-17 Rockwell International Corporation Metal oxide semiconductor (MOS) input circuit with hysteresis
US5057711A (en) * 1989-05-31 1991-10-15 Hyundai Electronics Industries Co., Ltd. Noise reducing output buffer circuit for an integrated circuit
US5111081A (en) * 1990-12-20 1992-05-05 International Business Machines Corporation Process compensated input switching threshold of a CMOS receiver
US5319258A (en) * 1991-07-16 1994-06-07 Samsung Semiconductor, Inc. Programmable output drive circuit
US5315173A (en) * 1991-07-19 1994-05-24 Samsung Electronics Co., Ltd. Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion
US5506528A (en) * 1994-10-31 1996-04-09 International Business Machines Corporation High speed off-chip CMOS receiver
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
US6429710B1 (en) * 1996-09-09 2002-08-06 Etron Technology, Inc. Input buffer with compensation for process variation
US6184704B1 (en) * 1999-02-08 2001-02-06 Tritech Microelectronics Design method for compensation of process variation in CMOS digital input circuits
US6275094B1 (en) * 1999-06-22 2001-08-14 International Business Machines Corporation CMOS device and circuit and method of operation dynamically controlling threshold voltage
US20010010476A1 (en) * 2000-02-01 2001-08-02 Chih-Hsien Weng Protecting apparatus for protecting the isolation circuit between different power domains
US6717445B1 (en) * 2000-06-30 2004-04-06 Intel Corporation Symmetric voltage follower buffer
US6750677B2 (en) * 2001-06-04 2004-06-15 Matsushita Electric Industrial Co., Ltd. Dynamic semiconductor integrated circuit
US6545521B2 (en) * 2001-06-29 2003-04-08 International Business Machines Corporation Low skew, power sequence independent CMOS receiver device
US6879198B2 (en) * 2002-12-18 2005-04-12 Stmicroelectronics Pvt. Ltd. Differential input receiver with hysteresis
US6992518B2 (en) * 2003-04-28 2006-01-31 Via Technologies, Inc. Input receiver with hysteresis
US20070063738A1 (en) * 2005-09-16 2007-03-22 Fischer Timothy C CMOS logic circuitry

Also Published As

Publication number Publication date
US7282961B1 (en) 2007-10-16

Similar Documents

Publication Publication Date Title
US7495483B2 (en) Input buffer for CMOS integrated circuits
JP4768300B2 (en) Voltage level conversion circuit and semiconductor integrated circuit device
US6963226B2 (en) Low-to-high level shifter
US9966955B2 (en) Overdrive receiver circuitry
US5073727A (en) Cmos inverter with noise reduction feedback means
US20050270079A1 (en) Input buffer structure with single gate oxide
US6744284B2 (en) Receiver circuit of semiconductor integrated circuit
US20090108871A1 (en) Methods, devices, and systems for a high voltage tolerant buffer
US10050625B2 (en) Techniques and devices for level-shifting a signal
US9054700B2 (en) Apparatus and methods of driving signal for reducing the leakage current
US6879198B2 (en) Differential input receiver with hysteresis
US10560084B2 (en) Level shift circuit
US6384682B2 (en) Differential amplifier circuit and pull up-type differential driver
US6777985B2 (en) Input/output buffer having reduced skew and methods of operation
US6624678B1 (en) Schmitt trigger device with disable
US7282961B1 (en) Apparatus for hysteresis based process compensation for CMOS receiver circuits
US10447269B1 (en) Level shifter
US20070063738A1 (en) CMOS logic circuitry
JP3730963B2 (en) Semiconductor integrated circuit
US5563542A (en) Output circuit for gunning transceiver logic
KR101622827B1 (en) Logig gate using schmitt trigger circuit
US20020113621A1 (en) Open drain driver having enhanced immunity to I/O ground noise
JPH04154207A (en) Schmitt trigger circuit
US5939900A (en) Input buffer
JP2002217707A (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DAUDELIN, DARIN;LENCIONI, MICHAEL J.;REEL/FRAME:017470/0350;SIGNING DATES FROM 20060412 TO 20060413

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
AS Assignment

Owner name: GOOGLE INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:026664/0866

Effective date: 20110503

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: GOOGLE LLC, CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:GOOGLE INC.;REEL/FRAME:044127/0735

Effective date: 20170929

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20191016