US20070203661A1 - Trimming for accurate reference voltage - Google Patents
Trimming for accurate reference voltage Download PDFInfo
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- US20070203661A1 US20070203661A1 US11/364,741 US36474106A US2007203661A1 US 20070203661 A1 US20070203661 A1 US 20070203661A1 US 36474106 A US36474106 A US 36474106A US 2007203661 A1 US2007203661 A1 US 2007203661A1
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- reference voltage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Definitions
- This invention relates to integrated circuits, and more specifically to a trimming methodology that can be employed to achieve an accurate bandgap voltage.
- a reference voltage In circuits having higher performance requirements, a temperature stable reference voltage is required.
- a typical bandgap circuit relies on two groups of transistors running at different emitter current densities.
- a rich transistor for instance, will typically operate at a current density that is much (e.g., about ten times) greater than the current density of a leaner transistor.
- the difference in current densities will further cause a difference between the base-emitter voltages of the two transistor groups, referred to as a delta base-emitter voltages ( ⁇ V be ).
- the ⁇ V be is usually amplified by a factor (e.g., about 10) and added to a V be voltage of a transistor. The sum of these two voltages adds up to about 1.2 volts, which is approximately the bandgap of silicon.
- the bandgap reference can be trimmed to a desired target voltage.
- the bandgap reference voltage may be required to provide a voltage within a predefined range of a desired voltage, which can be specified in terms of a percentage of variation of the bandgap reference.
- the specified voltage can vary according to the application of the IC.
- the bandgap voltage can remain untrimmed.
- bandgap reference voltages may play a pivotal role in establishing the accuracy and performance of many integrated circuits and the systems in which they are implemented, various trimming techniques and algorithms have been developed to compensate for process variations, temperature, and complex second-order and third-order effects.
- the trimming process typically is performed during late stages of IC fabrication and includes a scan of the trim codes to meet a desired target bandgap reference voltage. As a common example, the trimming can be performed on individual die on the wafer.
- the present invention relates generally to a trimming approach that can be employed to achieve an accurate reference voltage for an integrated circuit chip.
- the trim methodology can be applied during production, such as on a die-by-die basis, or post-production, such as on a chip-by-chip basis.
- the trimming methodology operates to compensate for voltage offset that is usually introduced by transistor mismatches in one or more circuits in reference voltage circuitry.
- the trimming method also can compensate for process variations that are inherent in the manufacturing process
- One aspect of the present invention provides a method for trimming reference voltage circuitry.
- the method includes defining a desired target bandgap reference voltage for a set of at least one die. At least two bandgap reference voltages are measured for at least two different bandgap trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured bandgap voltages. A trim setting associated with the bandgap reference voltage circuitry of the given die is set according to the modified target bandgap reference voltage so as to compensate for an offset voltage and substantially achieve the desired target bandgap reference voltage.
- Another aspect of the present invention provides a system for trimming bandgap circuitry to provide a desired bandgap reference voltage for a given die.
- the system includes means for measuring at least two bandgap voltages for at least two different trim settings of the given die.
- the system also includes means for determining a modified target bandgap reference voltage for the given die based on the at least two measured bandgap reference voltages.
- the system also includes means for programming at least one trim setting of the bandgap voltage reference circuitry associated with the given die according to the modified target bandgap reference voltage.
- FIG. 1 depicts a system for trimming bandgap voltage reference circuitry according to an aspect of the present invention.
- FIG. 2 depicts a system for trimming bandgap voltage reference circuitry according to another aspect of the present invention.
- FIG. 3 is a graph depicting buffered reference voltages for a plurality of die having been trimmed according to an existing trim methodology.
- FIG. 4 is graph depicting buffered reference voltages for the same plurality of die as in FIG. 3 having been trimmed according to an aspect of the present invention.
- FIG. 5 depicts a schematic example of a bandgap reference voltage circuit and trimming system that can be implemented according to an aspect of the present invention.
- FIG. 6 depicts a flow diagram of a method for trimming bandgap reference voltage circuitry according to an aspect of the present invention.
- the present invention relates generally to a system and method for trimming bandgap reference voltage circuitry to allow a more accurate bandgap reference voltage relative to conventional approaches.
- the approach described herein reduces the effect of mismatch, such as is induced by offset in the bandgap circuitry, including offset in the bandgap core as well as an associated output circuitry.
- bandgap reference voltages are measured for at least two different trim codes to determine an amount of offset associated with the bandgap circuitry in a given die.
- a modified target trim voltage can be determined for the die based on the offset. Scanning of trim codes can be performed to set the bandgap reference voltage for the die to the modified target trim voltage.
- a second scan of the output trim can then be used to compensate for the modification in target trim to yield the desired reference voltage.
- the process can be performed for each die on a wafer to establish high accuracy bandgap voltage references.
- the methodology can be employed to provide highly accurate reference voltages (e.g., better than 1.5%) in digital deep-sub-micron and other technologies.
- FIG. 1 depicts an example of a system 10 that can be utilized for trimming bandgap reference voltage circuitry 12 of an IC die 14 according to an aspect of the present invention.
- a single IC die 14 on a wafer 16 is depicted in the example of FIG. 1 .
- the wafer 16 typically will include a plurality (e.g., hundreds or thousands) of IC die formed as part of an IC fabrication process.
- the bandgap voltage reference circuitry 12 provides a reference voltage for use by the IC chip that is to be formed from the IC die 14 . Because different associated circuitry may require reference voltages different from the core bandgap reference voltage, the reference voltage circuitry 12 includes programmable or configurable networks that can be trimmed to set the reference voltage for the chip that comprises the IC die. For instance, ratios of resistor networks can be set to adjust the reference voltage above or below a core bandgap voltage provided by the bandgap reference voltage circuitry 12 .
- the reference voltage circuitry 12 provides the trimmed reference voltage to a buffer 18 , such as a unity gain amplifier.
- the buffer 18 provides a buffered reference voltage for use by other circuitry 20 on the IC die 14 .
- the buffer 18 may provide the buffered reference voltage to a pad (or bus) 22 that distributes the bandgap reference to the rest of the chip.
- the buffer 18 thus provides desired isolation between the reference voltage circuitry 12 and the other circuitry 20 that is coupled to the pad (or bus) 22 for utilizing the reference voltage. It is to be understood that some circuitry on the IC die (not shown) may not require a bandgap voltage reference, but instead may utilize other internal or external power supplies.
- the system 10 can also include a test system 24 that is programmed and/or configured to test and program (e.g. trim) the IC die 14 on the wafer 16 .
- a test system 24 that is programmed and/or configured to test and program (e.g. trim) the IC die 14 on the wafer 16 .
- ATE automated test equipment
- the test system 24 can include a plurality of different components that cooperate to perform measurements and testing of the parameters of the IC die 14 for programming the bandgap voltage reference circuitry 12 on the IC die 14 according to an aspect of the present invention.
- the test system 24 can also include wafer handling subsystem (e.g., part of the ATE or a separate system) that positions the wafer 16 and one or more probes of the test system for accessing appropriate pads on the IC die 14 (e.g., including the output pad 22 ).
- the test system 24 thus can position the wafer 16 to enable desired contact between one or more probe tips and the pads 22 on the IC die 14 .
- the test system 24 can provide appropriate signals and power to the IC die 14 under test (which may include one or more IC die at a time). For example, the test system 24 can provide one or more test signals to test and measure circuit parameters of the IC die 14 .
- the test system 24 can also provide control signals that may operate to set one or more circuit parameters, including trimming circuitry as part of a reference voltage trimming operation.
- the trimming operation may include setting a ratio of appropriate resistors in the bandgap reference voltage circuitry 12 to trim the bandgap reference voltage to a specified voltage.
- the test system may program memory (e.g., EEPROM, FLASH or other non-volatile memory) with appropriate control data that establishes the desired parameters (e.g., by setting trim codes) of the reference voltage circuitry 12 for providing a desired reference voltage.
- the desired reference voltage can vary according to the other circuitry 20 in the IC die 14 and voltage requirements of the IC chip being fabricated.
- the test system 24 includes a measurement system 26 .
- the measurement system can include one or more probes that contact one or more pads, including the pad 22 for measuring the buffered reference voltage of the IC die 14 .
- the reference voltage provided by the buffer and the pad 22 will include mismatch induced offset associated with the bandgap reference voltage circuitry 12 .
- the offset can include a core offset as well as an output offset, such as may be due (at least in part) due to process variations associated with the fabrication process. For instance, as the gate lengths of transistor devices decrease, as occurs in deep submicron technologies, the mismatch between transistors increases.
- the core offset can statistically vary for each die across a substrate (e.g., a wafer).
- the transistor mismatch further causes offsets in associated circuits in the IC. Therefore, the test system 24 is programmed and/or configured to determine the mismatch induced offsets in the reference voltage circuitry and perform trimming that compensates for such offset to provide more accurate bandgap reference voltage.
- the measurement system 26 provides the measurement of the buffered reference voltage to an associated evaluation system 28 to increase the accuracy of trimming, as described herein.
- the evaluation system 28 can be implemented in a variety of ways, such as including hardware, software or a combination of hardware and software configured to perform the functions described herein.
- the evaluation system can be implemented as a personal computer or workstation or other types of test equipment having computer-executable instructions for performing the evaluation and control functions described herein based on the measurement data from the measurement system 26 .
- the evaluation system 28 includes a calculator 30 that is programmed to calculate a compensated target bandgap reference voltage based on the measurements made by the measurement system 26 .
- the measurement system 26 can measure the buffered bandgap reference voltage for a plurality (e.g., two or more) of bandgap trim code settings. For instance, the measurement system can obtain measurements of the bandgap reference voltage at the pad 22 for a lowest trim code setting and for a highest trim code setting. By obtaining measurements for different trim code settings, a suitable level of variation between bandgap reference voltages is provided from which the calculator 30 can compute an appropriate offset value.
- the calculator 30 can compute a core offset value that is stored in memory, indicated as data 32 .
- the data 32 can also include the measured buffered reference voltage values, the corresponding trim code settings associated with such data, as well as other circuit parameters.
- the calculator 30 can also compute a new, modified target bandgap reference voltage as a function of the computed core offset. After the calculator 30 determines the modified target bandgap reference voltage, the new target can be utilized to trim the reference voltage circuitry 12 .
- the evaluation system 28 employs the measurements provided by the measurement system 26 to determine if the target voltage is met.
- the evaluation system 28 also includes trim control 34 that is operative to control and scan the trim code settings of the bandgap voltage reference circuitry 12 according to the computed modified target bandgap reference voltage.
- the trim control 34 can start a scan at an initial trim code setting and sequentially increment the trim codes until the measurement system measures a buffered bandgap value that is substantially equal to the computed modified target bandgap reference voltage.
- the measurement system 26 provides an indication of the measured voltage at the pad 22 for each of the respective trim codes, as set by the trim control 34 .
- the trim code that causes the reference voltage at the pad 22 to best match the target trim code can be utilized as the trim code for establishing the bandgap reference voltage of the IC die 14 .
- the trim control can implement a trim process that includes two phases: a first phase, as described above, for trimming core bandgap portion (not shown) of the bandgap circuitry, and a second phase for trimming an output stage (not shown in FIG. 1 ) of the bandgap circuitry.
- the calculator 30 can also be programmed to determine another target bandgap voltage corresponding to a compensated voltage for trimming back to the original target bandgap voltage for the IC die 14 .
- the trim control 34 thus can perform a scan of the output trim codes of the bandgap reference voltage circuitry 12 to set the output trim code so that the reference voltage at the pad 22 is substantially equal to the compensated target reference voltage, thereby further compensating for the offset in the reference voltage circuitry 12 .
- FIG. 2 depicts another example of a test system 50 that can be implemented according to an aspect of the present invention.
- the test system 50 can be implemented in a computer having computer executable instructions to perform the various functions described herein. Additionally or alternatively, the system 50 can be implemented as one or more units of test equipment configured to perform the functions for trimming the voltage reference to a desired target voltage, which compensates for transistor offset in the core bandgap circuit 54 .
- the test system 50 can be implemented as part of a wafer sort process, such as may be implemented at the end of wafer fabrication for testing, for setting the voltage reference of each die on an associated wafer.
- the test system 50 can be performed on a fabricated and packaged integrated circuit chip.
- the test system 50 can be coupled to an IC die 52 , such as via one or more probes that are coupled to electrically conductive pads on the IC die (e.g., the IC die being part of a wafer including a plurality of die).
- the IC die 52 includes a core bandgap circuit 54 and an associated output circuit 56 , which collectively form bandgap circuitry 55 for the IC die.
- the core bandgap voltage reference circuit 54 can be trimmed (e.g., by setting a ratio of resistors in the bandgap circuit) to adjust the core bandgap reference voltage.
- the bandgap circuit 54 provides the core bandgap reference voltage to the output circuit 56 , which is configured to adjust the core bandgap reference voltage (e.g., up or down) to achieve a target bandgap reference voltage, which can be specified for the IC that is formed from the die 52 .
- the test system 50 thus is programmed and/or configured to implement trimming by providing corresponding trim codes to the bandgap voltage reference circuitry 55 so as to compensate for mismatch induced offset in the bandgap circuitry 55 .
- the trim codes provided to the voltage reference circuit 54 are referred to herein as core trim codes and the trim codes to the output circuit 56 are referred to as output trim codes.
- the core trim codes and output trim codes can be referred to as the bandgap trim codes.
- Each of the trim codes can correspond to a digital value (e.g., one or more bits) that is employed to set a ratio of resistors for adjusting the bandgap reference voltage that is provided by the voltage reference circuitry 55 .
- the trim codes can be stored in memory (e.g., EEPROM, FLASH, registers, etc.) which can be employed to control switching in and out resistors in an associated resistor network to establish a corresponding resistor ratio for each of the circuits 54 and 56 .
- memory e.g., EEPROM, FLASH, registers, etc.
- the test system 50 also includes a measurement system 58 that is coupled to the IC die 52 for measuring the bandgap voltage reference voltage of the IC die 52 .
- the bandgap reference voltage measured by the measurement system 52 can vary based upon trim code settings for the bandgap circuit 54 and the output circuit 56 .
- the measurement system 58 provides an indication of the measured bandgap reference voltage and stores it as measurement data, indicated at 60 .
- the measurement data 60 can include data corresponding to the respective bandgap voltage reference measurements in conjunction with the trim codes associated with each respective measurement.
- the measurement data 60 can be stored in memory of a computer or workstation that is used to implement at least a portion of the test system 50 .
- the test system 50 includes an offset calculator 62 that is programmed to ascertain an offset voltage for the core of the bandgap circuit 54 .
- the offset results substantially from transistor mismatches in the bandgap circuitry 55 .
- the offset calculator 62 can compute offset voltage V O—CORE as a function of the measured bandgap reference voltage, such as for two (or more) different trim code settings.
- the trim code can correspond to a lowest core trim code and highest core trim code for the bandgap voltage reference to provide sufficient variation between the bandgap voltages measured by the measurement system 58 .
- V O—CORE V BG ⁇ ⁇ 1 - V BG ⁇ ⁇ 0 R OUT_NOM ⁇ ( R CORE ⁇ ⁇ 1 - R CORE ⁇ ⁇ 0 ) - ⁇ ⁇ ⁇ V BE Eq . ⁇ 1
- R CORE1 resistor ratio for a first core trim setting (e.g., core trim code set to all 0's);
- the test system 50 also includes a bandgap target calculator 64 that computes a target bandgap reference voltage that compensates for the mismatch induced offset, such as computed by the offset calculator 62 . That is, the bandgap target calculator 64 can compute a modified target bandgap voltage for the IC die 52 as a function of the computed core offset voltage V O—CORE .
- V BG—ORIGINAL original bandgap reference voltage for the IC die not taking into account statistical mismatches
- the approach described above results in a bandgap target trim voltage V BG—TGT at room temperature that compensates for the particular offset for the given die 52 .
- the offset for each die can be computed individually for each die based upon the respective measurements of the bandgap voltage references for the two or more trim codes (see, e.g., Eqs. 2 and 3) for that die.
- the adjusted bandgap target trim voltage V BG—TGT may be different for each die on a wafer, thereby allowing optimum temperature performance.
- the test system 50 also includes a bandgap trim control 66 that is programmed and/or configured to set core trim codes for the core bandgap circuit 54 .
- the bandgap trim control 66 can scan the corresponding trim codes until the measurement system 58 measures a bandgap reference voltage from the die 52 that best approximates the bandgap target trim voltage V BG—TGT computed by the bandgap target calculator 64 .
- the bandgap trim control 66 can set the trim code for the bandgap circuit 54 when the measured bandgap reference voltage substantially equals adjusted bandgap target trim voltage V BG—TGT , such as according to Eq. 4.
- the test system 50 can also be utilized to set the trim code for the output circuit 56 to trim back to get the desired ideal target voltage at the output of the output circuitry.
- the test system 50 thus includes a buffered bandgap target calculator 68 that computes a buffered target reference voltage V BG—BUF .
- the buffered bandgap target calculator 68 can compute the buffered bandgap target reference voltage to achieve the desired target reference voltage as a function of the bandgap target trim voltage V BG—TGT and a resistor ratio R OUT—NEW in the output circuit 56 .
- V BG—BUF buffered bandgap target reference voltage
- the buffered bandgap target calculator 68 provides an indication of the buffered target reference voltage to an output trim control 70 .
- the output trim control 70 is coupled to set the output trim code for the output circuit 56 .
- the output trim control 70 can perform a scan of trim codes (e.g., by setting R OUT—NEW to different values) until the bandgap reference voltage measured by the measurement system 58 approximates the desired buffered bandgap target reference voltage V BG—BUF computed by the calculator 68 . This corresponds to trimming back to the desired reference voltage (specified for use by associated circuitry on the IC die) after the modified target voltage has been set in the core bandgap circuit 54 .
- the output trim control 70 can set the corresponding output trim code in the output circuit such that the voltage reference is set to mitigate the effects of mismatch induced offset for the IC die 52 .
- the test system 50 can implement similar functions for each of the die on a respective wafer. As mentioned above, it will be appreciated that the target bandgap reference voltage V BG—TGT can vary for each die since the respective core offset voltage for each die on wafer may also vary. Additionally, those skilled in the art will further appreciate that the test system 50 can implement the trim methodology, such as described herein, with only minor additional cost relative to many known trimming methodologies.
- FIGS. 3 and 4 depict a comparison of buffered bandgap voltages for a plurality of IC die.
- the data represented in each of FIGS. 3 and 4 are for the same die, but trimmed using different trim methods.
- FIG. 3 illustrates a graph 80 of bandgap voltages from die trimmed by an existing trim methodology
- FIG. 4 illustrates a graph 82 of bandgap voltages from the same die trimmed in accordance with an aspect of the present invention.
- a first level of performance can be ascertained with reference to a pair of lines 84 , such as corresponds to +/ ⁇ 2% variation relative to a specified target bandgap reference voltage at room temperature (e.g., at about 25 Deg. C.).
- a second level of performance is denoted by reference line pair 86 , which corresponds to +/ ⁇ 1% variation relative to a specified target bandgap reference voltage at room temperature.
- FIG. 3 it is demonstrated that the bandgap voltages for three die, indicated at curves 88 , 90 and 92 (having been trimmed by an existing method), fail to meet the 1% variation.
- the curves 88 and 92 also fail the more relaxed 2% performance criteria.
- all die in the example of FIG. 4 (having been trimmed according to the present invention) meet the more stringent 1% variation.
- the comparison of FIGS. 3 and 4 demonstrates the efficacy of implementing a trim methodology in accordance with an aspect of the present invention.
- the benefits of more accurate bandgap reference voltage for the IC die will translate to the accuracy of all components on the die (e.g., including power supply circuitry, analog-to-digital converters, current references, etc.).
- FIG. 5 depicts an example of a trim control system 100 that is coupled to set trim codes for associated bandgap circuitry 102 .
- the bandgap circuitry includes a core bandgap voltage reference circuit 104 and an output circuit 106 .
- the bandgap output circuit 106 provides a bandgap reference voltage to buffer 108 , which is coupled to an output node of the output circuit.
- the buffer 108 provides a corresponding buffered bandgap reference voltage, indicated at V BG—BUF .
- the buffer 108 can be implemented at a unity gain amplifier that is driven by an output of the output circuit 106 .
- the trim control system 100 further includes a core trim control component 110 and an output trim control component 112 .
- the core trim control component 110 is operative to set a corresponding resistor ratio in the core bandgap circuit 104 .
- the core bandgap circuit 104 includes a variable resistance 114 coupled in series with a resistance 116 , which represents a ⁇ V BE associated with a V BE block 118 .
- the ⁇ V BE can be a predetermined parameter for the bandgap reference voltage circuitry 102 , which is fixed for a given temperature.
- the V BE block 118 further corresponds to the base-emitter voltage of a transistor that is utilized for generating the bandgap reference voltage.
- the base-emitter voltage is summed with the voltage drop across the ⁇ V BE resistance 116 to provide the core bandgap voltage.
- the core trim control component 110 sets the variable resistor 114 to set a corresponding resistor trim ratio (e.g., R CORE ) intended to compensate for the core offset represented by the resistor 116 , such as described herein.
- the output trim control component 112 is utilized to set another resistor ratio, namely, a resistor ratio of the output circuit 106 of the bandgap reference voltage circuitry 102 .
- the output circuit 106 is depicted as including a resistor 120 connected in series with a variable resistance 122 between the output of the core bandgap circuit 104 and electrical ground.
- the node between the resistances 120 and 122 is an output of the bandgap reference voltage circuitry 102 that provides a corresponding trimmed bandgap reference voltage to the buffer 108 , such as to the non-inverting input of the unity gain amplifier.
- the output trim control 112 is utilized to set the resistance ratio between the respective resistors 120 and 122 so as to achieve a desired target bandgap reference, as described herein.
- the output trim control component 112 can set the output trim code to a nominal output trim code during a first phase of a trim procedure when trimming of the core bandgap circuit 104 .
- the output trim control component 112 can scan the output trim codes during a second phase of the trim procedure to trim the resistance ratio in the output circuit 106 .
- the second phase compensates for the shift in target trim voltage in the first phase allowing recalibration to the desired reference voltage to the output buffer 108 . This represents one possible configuration for the output trim.
- FIG. 6 In view of the foregoing structural and functional features described above, certain methods will be better appreciated with reference to FIG. 6 . It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions from that shown in FIG. 6 . Moreover, not all illustrated features may be required to implement a method according to an aspect of the present invention. It is to be further understood that the methodology of FIG. 6 can be implemented in hardware (e.g., a computer, a computer network, or test equipment), software (e.g., as executable instructions running on one or more computer systems and/or test equipment), or any combination of hardware and software.
- hardware e.g., a computer, a computer network, or test equipment
- software e.g., as executable instructions running on one or more computer systems and/or test equipment
- the method begins at 200 in which starting parameters and desired parameters are set.
- the starting parameters can include, for example, a predetermined V OPT value.
- Trim codes and their corresponding resistor ratios can also be defined (e.g., each trim code corresponds to a predetermined resistor ratio).
- the predetermined V OPT value can be ascertained from initial measurements on a plurality of die (e.g., several a couple hundred dies), initial die produced in a wafer fab. This value of V OPT can then be utilized for trimming subsequent dies produced in the same fab, such that the procedure does not need be repeated on the remaining die. Based upon this optimum target voltage V OPT , a nominal ratio of trim resistors can be determined and stored as a fixed parameter associated with the initial target optimum voltage.
- the bandgap reference voltage is measured for at least two predetermined trim codes.
- the predetermined trim codes can correspond to a minimum and maximum trim code to provide a sufficient variation in the bandgap reference voltages that are generated by the bandgap reference voltage circuitry.
- the measurements at 220 are not limited to the minimum and maximum trim codes as other trim code settings can be utilized to measure respective reference voltages.
- a compensated target bandgap voltage (V BG—TGT ) is determined.
- the compensated bandgap reference voltage can be determined, for example, as set forth above in Eq. 4.
- the compensated target bandgap voltage can be determined as a function of core offset voltage in the bandgap circuitry.
- the core offset can be determined as a function of the measurements and the other known parameters associated with the bandgap circuitry (see, e.g., Eq. 1).
- the method proceeds to 240 .
- the bandgap voltage is initialized according to a starting bandgap trim code.
- V BG measured bandgap reference voltage
- V BG—TGT target compensated bandgap reference voltage
- the method proceeds to 260 .
- the bandgap trim code is changed to the next value (may use many search algorithms including binary search). From 260 , the method returns to 250 in which another determination is made.
- the method proceeds from 250 to 270 .
- This corresponds to setting the trim code of the core bandgap circuit to the trim code that resulted in the measured bandgap reference substantially equaling the target bandgap reference voltage, as determined at 230 .
- another scan can be performed, namely, to set the output trim code for the output circuit of the bandgap circuitry.
- the output reference voltage is initialized according to a starting output trim code.
- a determination is made as to whether the measured output bandgap reference (V BG ) is substantially equal to (or approximates) a new target reference voltage (V BG—BUF ), such as determined by Eq. 5. This essentially corresponds to trimming back to the original specified reference voltage after trimming the core bandgap circuit. If the output reference V BG does not substantially equal the target reference voltage V BG—BUF (NO), the method proceeds from 280 to 290 .
- the output trim code setting is changed and the method returns to 280 .
- the method can loop between 280 and 290 as part of a scan process until the determination at 280 indicates that the measured output voltage V BG is substantially equal to the target bandgap reference voltage V BG—BUF (YES), and the method proceeds to 300 .
- the trim method is complete for the die and the output trim code is set to the trim code setting that provided for the condition in which the output reference is equal to the target reference voltage.
- the method of FIG. 4 can be repeated for each die on a wafer for setting the respective trim codes of the associated bandgap circuitry in each die.
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Abstract
Description
- This invention relates to integrated circuits, and more specifically to a trimming methodology that can be employed to achieve an accurate bandgap voltage.
- With the continuing trend of increased device densities in integrated circuits (ICs), such as deep submicron technologies, manufacturers are required to achieve equal or better performance. One baseline parameter that is utilized in most integrated circuits is a reference voltage. In circuits having higher performance requirements, a temperature stable reference voltage is required. One type of reference voltage circuit is known as a bandgap reference circuit. The main principal of generating a bandgap reference voltage is to balance a negative temperature coefficient of a pn junction with a positive temperature coefficient of thermal voltage (Vt=kT/q), where k is Bolzman's constant, T is absolute temperature (Kelvin) and q is charge.
- A typical bandgap circuit relies on two groups of transistors running at different emitter current densities. A rich transistor, for instance, will typically operate at a current density that is much (e.g., about ten times) greater than the current density of a leaner transistor. The difference in current densities will further cause a difference between the base-emitter voltages of the two transistor groups, referred to as a delta base-emitter voltages (ΔVbe). The ΔVbe is usually amplified by a factor (e.g., about 10) and added to a Vbe voltage of a transistor. The sum of these two voltages adds up to about 1.2 volts, which is approximately the bandgap of silicon.
- In many integrated circuits where high performance is required, the bandgap reference can be trimmed to a desired target voltage. For instance, the bandgap reference voltage may be required to provide a voltage within a predefined range of a desired voltage, which can be specified in terms of a percentage of variation of the bandgap reference. The specified voltage can vary according to the application of the IC. Where a precision bandgap reference is not required for a particular IC, the bandgap voltage can remain untrimmed.
- Since bandgap reference voltages may play a pivotal role in establishing the accuracy and performance of many integrated circuits and the systems in which they are implemented, various trimming techniques and algorithms have been developed to compensate for process variations, temperature, and complex second-order and third-order effects. The trimming process typically is performed during late stages of IC fabrication and includes a scan of the trim codes to meet a desired target bandgap reference voltage. As a common example, the trimming can be performed on individual die on the wafer.
- As device dimensions shrink into smaller submicron sizes, improved trimming procedures are needed to help ensure adequate performance of ICs for their intended applications.
- The present invention relates generally to a trimming approach that can be employed to achieve an accurate reference voltage for an integrated circuit chip. The trim methodology can be applied during production, such as on a die-by-die basis, or post-production, such as on a chip-by-chip basis. The trimming methodology operates to compensate for voltage offset that is usually introduced by transistor mismatches in one or more circuits in reference voltage circuitry. The trimming method also can compensate for process variations that are inherent in the manufacturing process
- One aspect of the present invention provides a method for trimming reference voltage circuitry. The method includes defining a desired target bandgap reference voltage for a set of at least one die. At least two bandgap reference voltages are measured for at least two different bandgap trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured bandgap voltages. A trim setting associated with the bandgap reference voltage circuitry of the given die is set according to the modified target bandgap reference voltage so as to compensate for an offset voltage and substantially achieve the desired target bandgap reference voltage. Another aspect of the present invention provides a system for trimming bandgap circuitry to provide a desired bandgap reference voltage for a given die. The system includes means for measuring at least two bandgap voltages for at least two different trim settings of the given die. The system also includes means for determining a modified target bandgap reference voltage for the given die based on the at least two measured bandgap reference voltages. The system also includes means for programming at least one trim setting of the bandgap voltage reference circuitry associated with the given die according to the modified target bandgap reference voltage.
- The foregoing examples as well as others contained herein can be utilized to reduce the effect of mismatch induced offset so as to achieve highly accurate bandgap voltage.
-
FIG. 1 depicts a system for trimming bandgap voltage reference circuitry according to an aspect of the present invention. -
FIG. 2 depicts a system for trimming bandgap voltage reference circuitry according to another aspect of the present invention. -
FIG. 3 is a graph depicting buffered reference voltages for a plurality of die having been trimmed according to an existing trim methodology. -
FIG. 4 is graph depicting buffered reference voltages for the same plurality of die as inFIG. 3 having been trimmed according to an aspect of the present invention. -
FIG. 5 depicts a schematic example of a bandgap reference voltage circuit and trimming system that can be implemented according to an aspect of the present invention. -
FIG. 6 depicts a flow diagram of a method for trimming bandgap reference voltage circuitry according to an aspect of the present invention. - The present invention relates generally to a system and method for trimming bandgap reference voltage circuitry to allow a more accurate bandgap reference voltage relative to conventional approaches. The approach described herein reduces the effect of mismatch, such as is induced by offset in the bandgap circuitry, including offset in the bandgap core as well as an associated output circuitry. As part of the trimming methodology, bandgap reference voltages are measured for at least two different trim codes to determine an amount of offset associated with the bandgap circuitry in a given die. A modified target trim voltage can be determined for the die based on the offset. Scanning of trim codes can be performed to set the bandgap reference voltage for the die to the modified target trim voltage. A second scan of the output trim can then be used to compensate for the modification in target trim to yield the desired reference voltage. The process can be performed for each die on a wafer to establish high accuracy bandgap voltage references. For example, the methodology can be employed to provide highly accurate reference voltages (e.g., better than 1.5%) in digital deep-sub-micron and other technologies.
-
FIG. 1 depicts an example of asystem 10 that can be utilized for trimming bandgapreference voltage circuitry 12 of anIC die 14 according to an aspect of the present invention. For purpose of simplicity of explanation and not by way of limitation, asingle IC die 14 on awafer 16 is depicted in the example ofFIG. 1 . Those skilled in the art will understand and appreciate that thewafer 16 typically will include a plurality (e.g., hundreds or thousands) of IC die formed as part of an IC fabrication process. - As is known in the art, the bandgap
voltage reference circuitry 12 provides a reference voltage for use by the IC chip that is to be formed from theIC die 14. Because different associated circuitry may require reference voltages different from the core bandgap reference voltage, thereference voltage circuitry 12 includes programmable or configurable networks that can be trimmed to set the reference voltage for the chip that comprises the IC die. For instance, ratios of resistor networks can be set to adjust the reference voltage above or below a core bandgap voltage provided by the bandgapreference voltage circuitry 12. Thereference voltage circuitry 12 provides the trimmed reference voltage to abuffer 18, such as a unity gain amplifier. Thebuffer 18 provides a buffered reference voltage for use byother circuitry 20 on theIC die 14. Thebuffer 18, for example, may provide the buffered reference voltage to a pad (or bus) 22 that distributes the bandgap reference to the rest of the chip. Thebuffer 18 thus provides desired isolation between thereference voltage circuitry 12 and theother circuitry 20 that is coupled to the pad (or bus) 22 for utilizing the reference voltage. It is to be understood that some circuitry on the IC die (not shown) may not require a bandgap voltage reference, but instead may utilize other internal or external power supplies. - The
system 10 can also include atest system 24 that is programmed and/or configured to test and program (e.g. trim) theIC die 14 on thewafer 16. Those skilled in the art will understand and appreciate various type of test systems that can be utilized to perform the testing and programming of thereference voltage circuitry 12, which may include commercially available components, proprietary components or a combination of commercially available and proprietary components. As used herein, the term “component” is intended to encompass hardware, software, or a combination of hardware and software. As an example, thetest system 24 can be a stand alone test system, such as automated test equipment (ATE). Alternatively, thetest system 24 can include a plurality of different components that cooperate to perform measurements and testing of the parameters of the IC die 14 for programming the bandgapvoltage reference circuitry 12 on the IC die 14 according to an aspect of the present invention. - The
test system 24 can also include wafer handling subsystem (e.g., part of the ATE or a separate system) that positions thewafer 16 and one or more probes of the test system for accessing appropriate pads on the IC die 14 (e.g., including the output pad 22). Thetest system 24 thus can position thewafer 16 to enable desired contact between one or more probe tips and thepads 22 on the IC die 14. Thetest system 24 can provide appropriate signals and power to the IC die 14 under test (which may include one or more IC die at a time). For example, thetest system 24 can provide one or more test signals to test and measure circuit parameters of the IC die 14. Thetest system 24 can also provide control signals that may operate to set one or more circuit parameters, including trimming circuitry as part of a reference voltage trimming operation. The trimming operation, for example, may include setting a ratio of appropriate resistors in the bandgapreference voltage circuitry 12 to trim the bandgap reference voltage to a specified voltage. As but one example, the test system may program memory (e.g., EEPROM, FLASH or other non-volatile memory) with appropriate control data that establishes the desired parameters (e.g., by setting trim codes) of thereference voltage circuitry 12 for providing a desired reference voltage. As mentioned above, the desired reference voltage can vary according to theother circuitry 20 in the IC die 14 and voltage requirements of the IC chip being fabricated. - In the example of
FIG. 1 , thetest system 24 includes ameasurement system 26. The measurement system can include one or more probes that contact one or more pads, including thepad 22 for measuring the buffered reference voltage of the IC die 14. As discussed herein, the reference voltage provided by the buffer and thepad 22 will include mismatch induced offset associated with the bandgapreference voltage circuitry 12. The offset can include a core offset as well as an output offset, such as may be due (at least in part) due to process variations associated with the fabrication process. For instance, as the gate lengths of transistor devices decrease, as occurs in deep submicron technologies, the mismatch between transistors increases. The core offset can statistically vary for each die across a substrate (e.g., a wafer). The transistor mismatch further causes offsets in associated circuits in the IC. Therefore, thetest system 24 is programmed and/or configured to determine the mismatch induced offsets in the reference voltage circuitry and perform trimming that compensates for such offset to provide more accurate bandgap reference voltage. Themeasurement system 26 provides the measurement of the buffered reference voltage to an associatedevaluation system 28 to increase the accuracy of trimming, as described herein. - The
evaluation system 28 can be implemented in a variety of ways, such as including hardware, software or a combination of hardware and software configured to perform the functions described herein. For instance, the evaluation system can be implemented as a personal computer or workstation or other types of test equipment having computer-executable instructions for performing the evaluation and control functions described herein based on the measurement data from themeasurement system 26. In the example ofFIG. 1 , theevaluation system 28 includes acalculator 30 that is programmed to calculate a compensated target bandgap reference voltage based on the measurements made by themeasurement system 26. - By way of example, the
measurement system 26 can measure the buffered bandgap reference voltage for a plurality (e.g., two or more) of bandgap trim code settings. For instance, the measurement system can obtain measurements of the bandgap reference voltage at thepad 22 for a lowest trim code setting and for a highest trim code setting. By obtaining measurements for different trim code settings, a suitable level of variation between bandgap reference voltages is provided from which thecalculator 30 can compute an appropriate offset value. Thecalculator 30 can compute a core offset value that is stored in memory, indicated asdata 32. Thedata 32 can also include the measured buffered reference voltage values, the corresponding trim code settings associated with such data, as well as other circuit parameters. Thecalculator 30 can also compute a new, modified target bandgap reference voltage as a function of the computed core offset. After thecalculator 30 determines the modified target bandgap reference voltage, the new target can be utilized to trim thereference voltage circuitry 12. - As part of the trimming process, the
evaluation system 28 employs the measurements provided by themeasurement system 26 to determine if the target voltage is met. In the example ofFIG. 1 , theevaluation system 28 also includestrim control 34 that is operative to control and scan the trim code settings of the bandgapvoltage reference circuitry 12 according to the computed modified target bandgap reference voltage. For example, thetrim control 34 can start a scan at an initial trim code setting and sequentially increment the trim codes until the measurement system measures a buffered bandgap value that is substantially equal to the computed modified target bandgap reference voltage. Themeasurement system 26 provides an indication of the measured voltage at thepad 22 for each of the respective trim codes, as set by thetrim control 34. The trim code that causes the reference voltage at thepad 22 to best match the target trim code can be utilized as the trim code for establishing the bandgap reference voltage of the IC die 14. - The trim control can implement a trim process that includes two phases: a first phase, as described above, for trimming core bandgap portion (not shown) of the bandgap circuitry, and a second phase for trimming an output stage (not shown in
FIG. 1 ) of the bandgap circuitry. For example, thecalculator 30 can also be programmed to determine another target bandgap voltage corresponding to a compensated voltage for trimming back to the original target bandgap voltage for the IC die 14. Thetrim control 34 thus can perform a scan of the output trim codes of the bandgapreference voltage circuitry 12 to set the output trim code so that the reference voltage at thepad 22 is substantially equal to the compensated target reference voltage, thereby further compensating for the offset in thereference voltage circuitry 12. -
FIG. 2 depicts another example of atest system 50 that can be implemented according to an aspect of the present invention. Thetest system 50 can be implemented in a computer having computer executable instructions to perform the various functions described herein. Additionally or alternatively, thesystem 50 can be implemented as one or more units of test equipment configured to perform the functions for trimming the voltage reference to a desired target voltage, which compensates for transistor offset in thecore bandgap circuit 54. For example, thetest system 50 can be implemented as part of a wafer sort process, such as may be implemented at the end of wafer fabrication for testing, for setting the voltage reference of each die on an associated wafer. Those skilled in the art will understand and appreciate that alternatively, thetest system 50 can be performed on a fabricated and packaged integrated circuit chip. - The
test system 50 can be coupled to anIC die 52, such as via one or more probes that are coupled to electrically conductive pads on the IC die (e.g., the IC die being part of a wafer including a plurality of die). The IC die 52 includes acore bandgap circuit 54 and an associatedoutput circuit 56, which collectively formbandgap circuitry 55 for the IC die. Thecore bandgap circuit 54 is configured to provide a predetermined core bandgap voltage (e.g., VBG—CORE=m*(ΔVbe)+Vbe=about 1.2 volts, where m is a constant corresponding to a ratio of resistors in the bandgap circuit). The core bandgapvoltage reference circuit 54 can be trimmed (e.g., by setting a ratio of resistors in the bandgap circuit) to adjust the core bandgap reference voltage. Thebandgap circuit 54 provides the core bandgap reference voltage to theoutput circuit 56, which is configured to adjust the core bandgap reference voltage (e.g., up or down) to achieve a target bandgap reference voltage, which can be specified for the IC that is formed from thedie 52. - The
test system 50 thus is programmed and/or configured to implement trimming by providing corresponding trim codes to the bandgapvoltage reference circuitry 55 so as to compensate for mismatch induced offset in thebandgap circuitry 55. The trim codes provided to thevoltage reference circuit 54 are referred to herein as core trim codes and the trim codes to theoutput circuit 56 are referred to as output trim codes. Collectively, the core trim codes and output trim codes can be referred to as the bandgap trim codes. Each of the trim codes can correspond to a digital value (e.g., one or more bits) that is employed to set a ratio of resistors for adjusting the bandgap reference voltage that is provided by thevoltage reference circuitry 55. The trim codes can be stored in memory (e.g., EEPROM, FLASH, registers, etc.) which can be employed to control switching in and out resistors in an associated resistor network to establish a corresponding resistor ratio for each of thecircuits - The
test system 50 also includes ameasurement system 58 that is coupled to the IC die 52 for measuring the bandgap voltage reference voltage of the IC die 52. As described herein, the bandgap reference voltage measured by themeasurement system 52 can vary based upon trim code settings for thebandgap circuit 54 and theoutput circuit 56. Themeasurement system 58 provides an indication of the measured bandgap reference voltage and stores it as measurement data, indicated at 60. Themeasurement data 60 can include data corresponding to the respective bandgap voltage reference measurements in conjunction with the trim codes associated with each respective measurement. For example, themeasurement data 60 can be stored in memory of a computer or workstation that is used to implement at least a portion of thetest system 50. - The
test system 50 includes an offsetcalculator 62 that is programmed to ascertain an offset voltage for the core of thebandgap circuit 54. As mentioned above, the offset results substantially from transistor mismatches in thebandgap circuitry 55. The offsetcalculator 62 can compute offset voltage VO—CORE as a function of the measured bandgap reference voltage, such as for two (or more) different trim code settings. As an example, the trim code can correspond to a lowest core trim code and highest core trim code for the bandgap voltage reference to provide sufficient variation between the bandgap voltages measured by themeasurement system 58. By way of further example, the offset voltage VO—CORE can be computed as follows: - where: RCORE1=resistor ratio for a first core trim setting (e.g., core trim code set to all 0's);
-
- RCORE0=resistor ratio for a second core trim setting (e.g., core trim code set to all 1's);
- VBG1=measured buffered bandgap voltage at trim code RCORE1;
- VBG0=measured buffered bandgap voltage at trim code RCORE0; and
- ROUT—NOM=nominal output trim ratio for
output circuit 56.
By including the core offset and associated offset of the buffer in thebandgap circuitry 55, the measured bandgap voltages VBG1 and VBG0 for RCORE1 and RCORE0, respectively, can be expressed as follows:
V BG0 =R OUT—NOM×(V BE +R CORE0×(ΔV BE +V O—CORE))+V O—BUF Eq. 2
V BG1 =R OUT—NOM×(V BE +R CORE1×(ΔV BE +V O—CORE))+V O—BUF Eq. 3
where: VBE=base-emitter voltage for a given temperature (e.g., room temperature, about 25 Deg. C.); - ΔVBE=a known constant for the given temperature; and
- VO—BUF=offset due to the output buffer of the
bandgap circuitry 55. Thus, it will be evident that, by subtracting the measurements of Eq. 2 from Eq. 3, the core offset voltage VO—CORE can be derived as set forth in Eq. 1. It should be noted that the offset due to the buffer in thebandgap circuitry 55 cancels out. Known parameters, including ΔVBE and ROUT—NOM, can be stored in memory asbandgap parameter data 63. Other parameters associated with the bandgap circuitry can also be stored in thebandgap parameter data 63.
- The
test system 50 also includes abandgap target calculator 64 that computes a target bandgap reference voltage that compensates for the mismatch induced offset, such as computed by the offsetcalculator 62. That is, thebandgap target calculator 64 can compute a modified target bandgap voltage for the IC die 52 as a function of the computed core offset voltage VO—CORE. For example, thevoltage target calculator 64 can compute a modified or adjusted bandgap target reference VBG—TGT as follows: - where: VBG—ORIGINAL=original bandgap reference voltage for the IC die not taking into account statistical mismatches; and
-
- RCORE—MID=resistor ratio for setting for core bandgap trim code (e.g., a core trim code that is between codes for RCORE1 and RCORE0)
- It will be further appreciated that the approach described above results in a bandgap target trim voltage VBG—TGT at room temperature that compensates for the particular offset for the given
die 52. The offset for each die can be computed individually for each die based upon the respective measurements of the bandgap voltage references for the two or more trim codes (see, e.g., Eqs. 2 and 3) for that die. Thus, the adjusted bandgap target trim voltage VBG—TGT may be different for each die on a wafer, thereby allowing optimum temperature performance. Thetest system 50 also includes abandgap trim control 66 that is programmed and/or configured to set core trim codes for thecore bandgap circuit 54. During the trimming process implemented by thetest system 50, for example, thebandgap trim control 66 can scan the corresponding trim codes until themeasurement system 58 measures a bandgap reference voltage from the die 52 that best approximates the bandgap target trim voltage VBG—TGT computed by thebandgap target calculator 64. The bandgap trimcontrol 66 can set the trim code for thebandgap circuit 54 when the measured bandgap reference voltage substantially equals adjusted bandgap target trim voltage VBG—TGT, such as according to Eq. 4. - As mentioned above, the
test system 50 can also be utilized to set the trim code for theoutput circuit 56 to trim back to get the desired ideal target voltage at the output of the output circuitry. Thetest system 50 thus includes a bufferedbandgap target calculator 68 that computes a buffered target reference voltage VBG—BUF. The bufferedbandgap target calculator 68 can compute the buffered bandgap target reference voltage to achieve the desired target reference voltage as a function of the bandgap target trim voltage VBG—TGT and a resistor ratio ROUT—NEW in theoutput circuit 56. For example, the bufferedbandgap target calculator 68 can determine the buffered bandgap target reference voltage VBG—BUF as follows: - where: VBG—BUF=buffered bandgap target reference voltage; and
-
- ROUT—NEW=new resistor ratio of
output circuit 56 to achieve desired target reference voltage.
A comparison between Eqs. 4 and 5 demonstrates that the second term of Eq. 5 (in parentheses) is equal to the adjusted bandgap target trim voltage VBG—TGT from Eq. 4.
- ROUT—NEW=new resistor ratio of
- The buffered
bandgap target calculator 68 provides an indication of the buffered target reference voltage to anoutput trim control 70. The output trimcontrol 70 is coupled to set the output trim code for theoutput circuit 56. For example, theoutput trim control 70 can perform a scan of trim codes (e.g., by setting ROUT—NEW to different values) until the bandgap reference voltage measured by themeasurement system 58 approximates the desired buffered bandgap target reference voltage VBG—BUF computed by thecalculator 68. This corresponds to trimming back to the desired reference voltage (specified for use by associated circuitry on the IC die) after the modified target voltage has been set in thecore bandgap circuit 54. Thus, when the measured voltage substantially equals the computed target voltage, theoutput trim control 70 can set the corresponding output trim code in the output circuit such that the voltage reference is set to mitigate the effects of mismatch induced offset for the IC die 52. - The
test system 50 can implement similar functions for each of the die on a respective wafer. As mentioned above, it will be appreciated that the target bandgap reference voltage VBG—TGT can vary for each die since the respective core offset voltage for each die on wafer may also vary. Additionally, those skilled in the art will further appreciate that thetest system 50 can implement the trim methodology, such as described herein, with only minor additional cost relative to many known trimming methodologies. -
FIGS. 3 and 4 depict a comparison of buffered bandgap voltages for a plurality of IC die. The data represented in each ofFIGS. 3 and 4 are for the same die, but trimmed using different trim methods. Specifically,FIG. 3 illustrates agraph 80 of bandgap voltages from die trimmed by an existing trim methodology, andFIG. 4 illustrates agraph 82 of bandgap voltages from the same die trimmed in accordance with an aspect of the present invention. In each ofFIGS. 3 and 4 , a first level of performance can be ascertained with reference to a pair oflines 84, such as corresponds to +/−2% variation relative to a specified target bandgap reference voltage at room temperature (e.g., at about 25 Deg. C.). A second level of performance is denoted byreference line pair 86, which corresponds to +/−1% variation relative to a specified target bandgap reference voltage at room temperature. - In
FIG. 3 , it is demonstrated that the bandgap voltages for three die, indicated atcurves curves FIG. 4 (having been trimmed according to the present invention) meet the more stringent 1% variation. Thus, the comparison ofFIGS. 3 and 4 demonstrates the efficacy of implementing a trim methodology in accordance with an aspect of the present invention. The benefits of more accurate bandgap reference voltage for the IC die will translate to the accuracy of all components on the die (e.g., including power supply circuitry, analog-to-digital converters, current references, etc.). -
FIG. 5 depicts an example of atrim control system 100 that is coupled to set trim codes for associatedbandgap circuitry 102. In the example ofFIG. 5 , the bandgap circuitry includes a core bandgapvoltage reference circuit 104 and anoutput circuit 106. Thebandgap output circuit 106 provides a bandgap reference voltage to buffer 108, which is coupled to an output node of the output circuit. Thebuffer 108 provides a corresponding buffered bandgap reference voltage, indicated at VBG—BUF. For example, thebuffer 108 can be implemented at a unity gain amplifier that is driven by an output of theoutput circuit 106. - The
trim control system 100 further includes a coretrim control component 110 and an outputtrim control component 112. The core trimcontrol component 110 is operative to set a corresponding resistor ratio in thecore bandgap circuit 104. In the example ofFIG. 3 , thecore bandgap circuit 104 includes avariable resistance 114 coupled in series with aresistance 116, which represents a ΔVBE associated with a VBE block 118. The ΔVBE can be a predetermined parameter for the bandgapreference voltage circuitry 102, which is fixed for a given temperature. The VBE block 118 further corresponds to the base-emitter voltage of a transistor that is utilized for generating the bandgap reference voltage. Thus, in thebandgap circuit 104, the base-emitter voltage is summed with the voltage drop across the ΔVBE resistance 116 to provide the core bandgap voltage. Thus, the coretrim control component 110 sets thevariable resistor 114 to set a corresponding resistor trim ratio (e.g., RCORE) intended to compensate for the core offset represented by theresistor 116, such as described herein. - The output
trim control component 112 is utilized to set another resistor ratio, namely, a resistor ratio of theoutput circuit 106 of the bandgapreference voltage circuitry 102. In the example ofFIG. 5 , theoutput circuit 106 is depicted as including aresistor 120 connected in series with avariable resistance 122 between the output of thecore bandgap circuit 104 and electrical ground. The node between theresistances reference voltage circuitry 102 that provides a corresponding trimmed bandgap reference voltage to thebuffer 108, such as to the non-inverting input of the unity gain amplifier. Theoutput trim control 112 is utilized to set the resistance ratio between therespective resistors trim control component 112 can set the output trim code to a nominal output trim code during a first phase of a trim procedure when trimming of thecore bandgap circuit 104. The outputtrim control component 112 can scan the output trim codes during a second phase of the trim procedure to trim the resistance ratio in theoutput circuit 106. The second phase compensates for the shift in target trim voltage in the first phase allowing recalibration to the desired reference voltage to theoutput buffer 108. This represents one possible configuration for the output trim. - In view of the foregoing structural and functional features described above, certain methods will be better appreciated with reference to
FIG. 6 . It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions from that shown inFIG. 6 . Moreover, not all illustrated features may be required to implement a method according to an aspect of the present invention. It is to be further understood that the methodology ofFIG. 6 can be implemented in hardware (e.g., a computer, a computer network, or test equipment), software (e.g., as executable instructions running on one or more computer systems and/or test equipment), or any combination of hardware and software. - The method begins at 200 in which starting parameters and desired parameters are set. The starting parameters can include, for example, a predetermined VOPT value. Trim codes and their corresponding resistor ratios can also be defined (e.g., each trim code corresponds to a predetermined resistor ratio). As an example, the predetermined VOPT value can be ascertained from initial measurements on a plurality of die (e.g., several a couple hundred dies), initial die produced in a wafer fab. This value of VOPT can then be utilized for trimming subsequent dies produced in the same fab, such that the procedure does not need be repeated on the remaining die. Based upon this optimum target voltage VOPT, a nominal ratio of trim resistors can be determined and stored as a fixed parameter associated with the initial target optimum voltage.
- At 220, the bandgap reference voltage is measured for at least two predetermined trim codes. As an example, the predetermined trim codes can correspond to a minimum and maximum trim code to provide a sufficient variation in the bandgap reference voltages that are generated by the bandgap reference voltage circuitry. Those skilled in the art will understand and appreciate that the measurements at 220 are not limited to the minimum and maximum trim codes as other trim code settings can be utilized to measure respective reference voltages.
- At 230, a compensated target bandgap voltage (VBG—TGT) is determined. The compensated bandgap reference voltage can be determined, for example, as set forth above in Eq. 4. The compensated target bandgap voltage can be determined as a function of core offset voltage in the bandgap circuitry. The core offset can be determined as a function of the measurements and the other known parameters associated with the bandgap circuitry (see, e.g., Eq. 1).
- After the compensated target bandgap voltage has been determined (at 230), the method proceeds to 240. At 240, the bandgap voltage is initialized according to a starting bandgap trim code. At 250, a determination is made as to whether the measured bandgap reference voltage (VBG) is equal to the target compensated bandgap reference VBG—TGT, which was determined at 230. If the measured bandgap does not equal (or substantially approximate) the determined compensated target bandgap reference (NO), the method proceeds to 260. At 260, the bandgap trim code is changed to the next value (may use many search algorithms including binary search). From 260, the method returns to 250 in which another determination is made. If the measured bandgap reference voltage is equal to (or substantially approximates) the determined compensated target bandgap reference (YES), the method proceeds from 250 to 270. This corresponds to setting the trim code of the core bandgap circuit to the trim code that resulted in the measured bandgap reference substantially equaling the target bandgap reference voltage, as determined at 230.
- At 270, another scan can be performed, namely, to set the output trim code for the output circuit of the bandgap circuitry. At 270, the output reference voltage is initialized according to a starting output trim code. At 280, a determination is made as to whether the measured output bandgap reference (VBG) is substantially equal to (or approximates) a new target reference voltage (VBG—BUF), such as determined by Eq. 5. This essentially corresponds to trimming back to the original specified reference voltage after trimming the core bandgap circuit. If the output reference VBG does not substantially equal the target reference voltage VBG—BUF (NO), the method proceeds from 280 to 290. At 290, the output trim code setting is changed and the method returns to 280. The method can loop between 280 and 290 as part of a scan process until the determination at 280 indicates that the measured output voltage VBG is substantially equal to the target bandgap reference voltage VBG—BUF (YES), and the method proceeds to 300. At 300, the trim method is complete for the die and the output trim code is set to the trim code setting that provided for the condition in which the output reference is equal to the target reference voltage. The method of
FIG. 4 can be repeated for each die on a wafer for setting the respective trim codes of the associated bandgap circuitry in each die. - What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. For example, while some of the foregoing has been described with respect to bandgap voltage of a bipolar junction transistor, the approach described herein is equally applicable to other types of transistors (e.g., field effect transistors). Accordingly, the present invention is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.
Claims (17)
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US8144541B2 (en) | 2008-05-28 | 2012-03-27 | Actions Semiconductor Co., Ltd. | Method and apparatus for adjusting and obtaining a reference voltage |
US10643944B2 (en) | 2018-07-30 | 2020-05-05 | Texas Instruments Incorporated | Additively manufactured programmable resistive jumpers |
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