US20070159881A1 - Nonvolatile semiconductor memory device including nand-type flash memory and the like - Google Patents

Nonvolatile semiconductor memory device including nand-type flash memory and the like Download PDF

Info

Publication number
US20070159881A1
US20070159881A1 US11/474,340 US47434006A US2007159881A1 US 20070159881 A1 US20070159881 A1 US 20070159881A1 US 47434006 A US47434006 A US 47434006A US 2007159881 A1 US2007159881 A1 US 2007159881A1
Authority
US
United States
Prior art keywords
memory cell
memory
threshold value
nonvolatile semiconductor
judgment potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/474,340
Inventor
Atsuhiro Sato
Keiji Shuto
Fumitaka Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2006001456A priority Critical patent/JP4177847B2/en
Priority to JP2006-001456 priority
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARAI, FUMITAKA, SATO, ATSUHIRO, SHUTO, KEIJI
Publication of US20070159881A1 publication Critical patent/US20070159881A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5642Multilevel memory with buffers, latches, registers at input or output

Abstract

A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-001456, filed Jan. 6, 2006, the entire contents of which are incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a nonvolatile semiconductor memory device, more particularly to an NAND-type flash memory.
  • 2. Description of the Related Art
  • In recent years, in an NAND-type multivalued flash memory, a threshold-value fluctuation of a read cell is generated by a parasitic capacity between floating gates of a memory cell (readout cell) as a readout object and a memory cell adjacent to this read-out cell, and this has been a serious problem (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-192789). This threshold-value fluctuation due to this parasitic capacity is referred to as a proximity effect herein. Since threshold values of bit data are tightly distributed in the multivalued memory, there is little margin in a breadth of the threshold-value distribution due to the proximity effect. Additionally, in recent years, a value of the proximity effect itself is increasing owing to miniaturization of the memory cell, and this has been a large barrier to realization of a minute multivalued memory.
  • BRIEF SUMMARY OF THE INVENTION
  • A nonvolatile semiconductor memory device in a first aspect of the present invention comprises: a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell as a readout object and second memory cells disposed adjacent to the first memory cell; a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the second memory cells; and a readout circuit which reads the first memory cell as the readout object by use of the judgment potential corrected by the judgment potential correction circuit.
  • A nonvolatile semiconductor memory device in a second aspect of the present invention comprises: a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell and a third memory cell, the first memory cell being connected to a word line, the second memory cell being disposed adjacent to the first memory cell and connected to the word line and a bit line, and the third memory cell being disposed adjacent to the second memory cell and connected to the bit line; a write circuit which writes data into the second memory cell after writing data into the first memory cell; a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the third memory cell disposed adjacent to the second memory cell and connected to the bit line; and a readout circuit which reads the second memory cell by use of the judgment potential corrected by the judgment potential correction circuit.
  • A nonvolatile semiconductor memory device in a third aspect of the present invention comprises: a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, the first memory cell being connected to a first word line and a first bit line, the second memory cell being disposed adjacent to the first memory cell and connected to the first word line, a third memory cell being disposed adjacent to the first memory cell and connected to a second word line and the first bit line, and the fourth memory cell being disposed adjacent to the third memory cell and connected to the second word line; and a write circuit which writes lower bit data into the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell, and upper bit data into the first memory cell and the second memory cell in this order.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
  • FIG. 1 is a sectional view showing a proximity effect produced between adjacent memory cells;
  • FIG. 2A is a threshold value distribution of the memory cells in a case where there is not any proximity effect;
  • FIG. 2B is a threshold value distribution of the memory cells in a case where there is the proximity effect;
  • FIG. 3 is a block diagram showing a constitution of a nonvolatile semiconductor memory device in a first embodiment of the present invention;
  • FIG. 4 is a diagram showing one example of a memory cell array in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 5 is a sectional view showing one example of a column direction structure of the memory cell array in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 6 is a sectional view showing one example of a row direction structure of the memory cell array in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 7 is a sectional view showing one example of a row direction structure of a selection transistor in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 8 is a diagram showing the memory cell array in the nonvolatile semiconductor memory device of the first embodiment, and a main part of a column control circuit;
  • FIG. 9 is a flowchart showing a write operation in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 10A shows a threshold value distribution in a case where there is not any proximity effect of the memory cells during writing into the nonvolatile semiconductor memory device;
  • FIG. 10B shows a threshold value distribution in a case where there is the proximity effect of the memory cells during the writing into the nonvolatile semiconductor memory device;
  • FIG. 11 is a diagram showing simple readout in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 12 is a first flowchart showing a readout operation in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 13 is a second flowchart showing a readout operation in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 14 shows a threshold value distribution during simple readout in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 15 shows a first threshold value distribution during readout in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 16 shows a second threshold value distribution during the readout in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 17 shows a third threshold value distribution during the readout in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 18 shows a fourth threshold value distribution during the readout in the nonvolatile semiconductor memory device of the first embodiment;
  • FIG. 19 is a flowchart showing a readout operation in a nonvolatile semiconductor memory device of a second embodiment of the present invention;
  • FIG. 20 is a diagram showing a write order into memory cells in a nonvolatile semiconductor memory device of a third embodiment of the present invention; and
  • FIG. 21 shows a threshold value distribution of the memory cells written in the third embodiment.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Here, there will be described one example of a nonvolatile semiconductor memory device in accordance with an NAND-type multivalued flash memory, but the present invention is not limited to this memory, and the present invention is also applicable to a memory other than the NAND-type multivalued flash memory.
  • In the NAND-type multivalued flash memory, a proximity effect has rapidly increased with miniaturization of a memory cell in recent years. The proximity effect means that a threshold value of the previously written memory cell during readout fluctuates depending on whether the adjacent memory cell is written or not with respect to the previously written memory cell as shown in FIG. 1. Since the threshold values are tightly distributed in the multivalued memory as shown in FIG. 2B, there is little margin with respect to a breadth of the distribution due to the proximity effect. It is to be noted that FIG. 2A shows a threshold value distribution in a case where there is not any proximity effect.
  • In an embodiment of the present invention, to realize a finer multivalued memory, there is proposed a system in which a threshold value shift of the proximity effect is predicted beforehand, and accordingly a data judgment potential of each memory cell is corrected during performing of readout, so that an influence of the proximity effect is eliminated.
  • There will be described a nonvolatile semiconductor memory device in an embodiment of the present invention with reference to the drawings. In the description with reference to all of the drawings, common components are denoted with common reference numerals.
  • First Embodiment
  • First, there will be described a nonvolatile semiconductor memory device in a first embodiment of the present invention.
  • FIG. 3 is a block diagram showing a constitution of the nonvolatile semiconductor memory device of the first embodiment.
  • In a memory cell array 1, nonvolatile semiconductor memory cells are arranged in a matrix form. One example of the nonvolatile semiconductor memory cell is a flash memory cell. A column control circuit 2 controls a bit line of the memory cell array 1, and performs erasing of data from the memory cells, writing of data into the memory cells, and reading of data from the memory cells. The column control circuit 2 is disposed adjacent to the memory cell array 1. A row control circuit 3 selects a word line of the memory cell array 1, and applies voltages required for the erasing, the writing, and the reading.
  • A source line control circuit (C-source control circuit) 4 controls a source line of the memory cell array 1. A P-well control circuit (C-p-well control circuit) 5 controls a potential of a P-type cell well in which the memory cell array 1 is formed.
  • A data input/output buffer 6 is electrically connected to the column control circuit 2 via an I/O line, and electrically connected to an external host (not shown) via an external I/O line. In the data input/output buffer 6, for example, an input/output buffer circuit is disposed. The data input/output buffer 6 receives write data, outputs readout data, and receives address data or command data. The data input/output buffer 6 sends the received write data to the column control circuit 2 via the I/O line, and receives the data read from the column control circuit 2 via the I/O line. Furthermore, the data input/output buffer 6 sends the address data to the column control circuit 2 or the row control circuit 3 via a state machine 8. The address data has been input from the outside in order to select an address of the memory cell array 1. The command data from an external host is sent to a command interface 7.
  • The command interface 7 receives a control signal from the external host via an external control signal line, and judges whether the data input into the data input/output buffer 6 is the write data, the command data, or the address data. When the data is the command data, the data is transferred as the received command data to the state machine 8. The state machine 8 manages the whole flash memory. That is, the state machine 8 receives the command data from the external host, and performs the reading, writing, and erasing of data. The state machine also manages input/output of the data. The state machine 8, the column control circuit 2, and the row control circuit 3 constitute a write circuit and a readout circuit.
  • FIG. 4 is a diagram showing one example of the memory cell array 1 shown in FIG. 3.
  • The memory cell array 1 is divided into a plurality of blocks, for example, 1024 blocks BLOCK 0 to BLOCK 1023. The block is a minimum unit to be erased at once during the erase. Each block BLOCKi (i=0, 1, 2, . . . , 1023) includes a plurality of NAND-type memory units, for example, 8512 NAND-type memory units. In this example, each NAND-type memory unit includes two selection transistors STD and STS, and a plurality of memory cells MC (four memory cells in the present example) connected in series between the transistors.
  • One end of the NAND-type memory unit is connected to a bit line BL via the selection transistor STD connected to a selection gate line SGD, and the other end of the unit is connected to a common source line C-source via the selection transistor STS connected to a selection gate line SGS. Each memory cell MC is connected to a word line WL. In a bit line BLe which is an even-number-th counted from 0, and an odd-number-th bit line BLo, the data is independently written and read. Among 8512 memory cells connected to one word line WL, the data is simultaneously written and read with respect to 4256 memory cells connected to the bit lines BLe. Assuming that, for example, one-bit data is stored in each memory cell MC, the data stored in 4256 memory cells constitute a page. The page is, for example, a minimum readout unit. In a case where one memory cell MC stores 2-bit data, 4256 memory cells store data of two pages. Similarly, 4256 memory cells connected to the bit line BLo constitute other two pages, and the data is written or read simultaneously with respect to the memory cells of the page.
  • FIG. 5 is a sectional view showing one example of a column direction structure of the memory cell array 1 shown in FIG. 3.
  • An n-type cell well 10 is formed in a p-type semiconductor substrate 9. A p-type cell well 11 is formed in the n-type cell well 10. The memory cell MC includes an n-type diffusion layer 12, a floating gate FG, and a control gate which functions as the word line WL. The selection transistors STD and STS include the n-type diffusion layers 12, and double-structure gates which functions as the selection gate lines SGD and SGS. The word line WL and the selection gate lines SGD and SGS are connected to the row control circuit 3, and controlled by the row control circuit 3.
  • One end of the NAND-type memory unit is connected to a first metal wire layer M0 via a first contact CB, and further connected to a second metal wire layer M1 which functions as the bit line BL via a second contact V1. The bit line BL is connected to the column control circuit 2. The other end of the NAND-type memory unit is connected to the first metal wire layer M0 which functions as the common source line C-source via a first contact hole CB. The common source line C-source is connected to the source line control circuit 4. The n-type cell well 10 and the p-type cell well 11 are set to an equal potential, and are connected to the P-well control circuit 5 via a well line C-p-well.
  • FIGS. 6 and 7 are sectional views showing one example of a row direction structure of the memory cell array 1 shown in FIG. 3, and show sections cut along the lines VI-VI and VII-VII in FIG. 5, respectively.
  • As shown in FIG. 6, the respective memory cells MC are separated from one another by device separation STI. The floating gates FG are laminated on a channel area via a tunnel oxide film 14. The word line WL is laminated on the floating gate FG via an ONO film 15.
  • As shown in FIG. 5, the selection gate line SGS has a double structure. Although not shown, the upper and lower selection gate lines SGS are connected to an end of the memory cell array 1 or every certain number of bit lines.
  • FIG. 8 is a diagram showing the memory cell array 1 in the nonvolatile semiconductor memory device shown in FIG. 3, and a main part of the column control circuit 2.
  • The first NAND-type memory unit is connected to an even-number bit line (even-number BL) via a selection transistor STD1. This even-number bit line is connected to a sense amplifier/data latch circuit 21 via an even-number bit line selection transistor BLTel. The second NAND-type memory unit is disposed adjacent to the first NAND-type memory unit, and the second NAND-type memory unit is connected to an odd-number bit line (odd-number BL). This odd-number bit line is connected to the sense amplifier/data latch circuit 21 via an odd-number bit line selection transistor BLTo1. The sense amplifier/data latch circuit 21 is connected to a state-storing latch circuit 22, and this state-storing latch circuit 22 is connected to a judgment potential correction circuit 23. The sense amplifier/data latch circuit 21 is also connected to the data input/output buffer 6. Gates of the memory cells which the first and second NAND-type memory units have are connected to word line WLn, WLn+1, WLn+2, and WLn+3, respectively.
  • FIG. 9 is a flowchart showing a write operation, and FIGS. 10A and 10B show threshold value distributions of memory cells during the writing. FIG. 10A shows a threshold value distribution before the distribution undergoes the proximity effect, and FIG. 10B shows a threshold value distribution at a time when the distribution undergoes the proximity effect.
  • The block is selected as a write object (step S1), and subsequently “n” is set to “0” (step S2). Moreover, in the block, as shown in FIG. 8, four values are written into each memory cell in order of (1) to (16).
  • First, the sense amplifier/data latch circuit 21 takes in lower and upper bit data to be written into a memory cell MC1 selected by the word line WLn and the even-number bit line (even-number BL) (step S3). Moreover, the lower bit data (1) is written into the memory cell MC1 selected by the word line WLn and the even-number bit line (step S4). Subsequently, the upper bit data (2) is written into the memory cell MC1 selected by the word line WLn and the even-number bit line (step S5). During the write of the upper bit data (2), the data is written more than usual, that is, the data is written so that the threshold value becomes higher than usual.
  • Next, the data latch circuit 21 takes in the lower and upper bit data to be written into memory cells MC2 and MC3 selected by the word line WLn and the odd-number bit line (odd-number BL) (step S6). Moreover, the lower bit data (3) is written into the memory cells MC2 and MC3 selected by the word line WLn and the odd-number bit line (step S7). Subsequently, the upper bit data (4) is written into the memory cells MC2 and MC3 selected by the word line WLn and the odd-number bit line (step S8). During the write of the upper bit data (4), the data is written more than usual, that is, the data is written so that the threshold value becomes higher than usual.
  • Thereafter, it is judged whether or not “n” is the last in the page (step S9). When “n” is the last in the page, the write operation ends. On the other hand, when “n” is not the last in the page, “n” is set to “n+1” (step S10), and the processing returns to the step S3 to perform similar processing. That is, the data latch circuit 21 takes in the lower bit data (5) and the upper bit data (6) to be written into the memory cell MC4 selected by the word line WLn+1 and the even-number bit line, and the lower bit data (5) and the upper bit data (6) are written in order into the memory cell MC4 selected by the word line WLn+1 and the even-number bit line. Subsequently, the data latch circuit 21 takes in the lower bit data (7) and the upper bit data (8) to be written into the memory cells MC5 and MC6 selected by the word line WLn+1 and the odd-number bit line, and the lower bit data (7) and the upper bit data (8) are written in order into the memory cells MC5 and MC6 selected by the word line WLn+1 and the odd-number bit line. Thereafter, similarly the lower bit data (9), the upper bit data (10), the lower bit data (11), the upper bit data (12), the lower bit data (13), the upper bit data (14), the lower bit data (15), and the upper bit data (16) are written in order.
  • Here, the memory cell MC1 in which the lower bit data (1) and the upper bit data (2) are first written receives the proximity effects from the memory cells MC2 and MC3 in which the data (3) and (4) are thereafter written and the memory cell MC4 in which the data (5) and (6) are written, and the threshold value shifts. When the data is written into all of the memory cells by repeating the above processing, as shown in FIG. 10B, the threshold value distribution expands owing to the influence of the proximity effect. As a result, data threshold value distributions overlap with each other, and the data cannot be judged.
  • To avoid this problem, during readout, the shift of the threshold value due to the influence of the proximity effect during the write is predicted from the memory cell (hereinafter referred to as the adjacent cell) disposed adjacent to the memory cell (hereinafter referred to as the readout cell) which is a readout object, and a judgment potential of the data is corrected every readout cell. This eliminates the influence of the proximity effect on the readout cell.
  • Specifically, as shown in FIG. 11, the data is simply read from the memory cell of the bit line disposed adjacent to the readout cell (memory cell in which the data (1) and (2) have been written) and the memory cell of the word line disposed adjacent to the readout cell, and it is checked whether the threshold value is high or low. Moreover, in consideration of the threshold value shift due to the proximity effect that would be received by the readout cell from the respective read threshold values, the judgment potential for use in reading the data from the readout cell is corrected. That is, when the judgment potential is corrected into an appropriate value every memory cell, the influence due to the proximity effect can be suppressed as much as possible. The judgment potential is set to be high, when the surrounding close memory cell indicates a high threshold value. The judgment potential is set to be low, when the surrounding close memory cell indicates a low threshold value.
  • Moreover, during the write, as shown in FIG. 10B, two center threshold value distributions (“10” and “00”) are detached from each other among the four-value threshold value distributions in order to judge without any mistake whether the threshold value is high or low even if there is a threshold value shift due to the proximity effect during the simple readout of the adjacent cells. To obtain a broad gap between two center threshold value distributions, the upper bit data is written to be larger than usual in the write flowchart shown in FIG. 9 (steps S5, S8). During this large write, even when there is the threshold value shift due to the proximity effect, the data can be written to such an extent that it can be judged without any mistake whether the threshold value is high or low.
  • Next, there will be described a readout operation in the nonvolatile semiconductor memory device of the first embodiment.
  • FIGS. 12 to 13 are flowcharts showing the readout operation, and FIGS. 14 to 18 show threshold value distributions of the memory cells from which the data is read during this readout.
  • First, a block as a readout object is selected (step Sil), and subsequently “n” is set to “0” (step S12). Next, the simple readout is executed with respect to three memory cells (hereinafter referred to as the three surrounding cells) disposed adjacent to the memory cell (hereinafter referred to as the readout cell) as the readout object. That is, assuming that the readout cell is the memory cell selected by the word line WLn and the even-number bit line (even-number BL), simple readout 1 (shown in FIG. 11) is performed with respect to the memory cell selected by the word line WLn and the odd-number bit line (odd-number BL) (step S13). Subsequently, simple readout 2 (shown in FIG. 11) is performed with respect to the memory cell selected by the word line WLn+1 and the even-number bit line (step S14). It is to be noted that three surrounding cells refer to the memory cell which is disposed adjacent to the memory cell (readout cell) as the readout object and which is written after the readout cell among two memory cells connected to a bit line common to the readout cell, and two memory cells which are disposed adjacent to the readout cell and which are connected to a word line common to the readout cell.
  • Next, from results of the simple readouts 1 and 2 with respect to the three cells surrounding the readout cell, states of the three surrounding cells are input into the state-storing latch circuit 22 for each bit line (step S15). Here, as shown in FIG. 14, with respect to the judgment potentials of the simple readouts 1 and 2, it is assumed that a state in which the threshold value is lower than the judgment potential is state A and that a state in which the threshold value is higher than the judgment potential is state B. The states of the three surrounding cells held in the state-storing latch circuit 22 are output to the judgment potential correction circuit 23. The judgment potential correction circuit 23 corrects the judgment potential based on the states of the three surrounding cells. To be more specific, the judgment potential correction circuit 23 sets the judgment potential during the readout to V1 in a case where all of the three surrounding cells have the state A. The circuit sets the judgment potential during the readout to V4 in a case where two of the three surrounding cells have the state A and one cell has the state B. The circuit sets the judgment potential during the readout to V7 in a case where one of the three surrounding cells have the state A and two cells have the state B. Furthermore, the circuit sets the judgment potential during the readout to V10 in a case where all of the three surrounding cells have the state B.
  • Next, the data latch circuit 21 is activated in a case where all of the three surrounding cells have the state A in the word line WLn and each even-number bit line. In another case, that is, a case where all of the three surrounding cells do not have the state A, the data latch circuit 21 is inactivated (step S16).
  • Subsequently, as shown in FIG. 15, the lower bit data is read (a) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V1 at a time when all of the three surrounding cells have the state A (step S17). Furthermore, the lower bit data is read (b) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V2 at a time when all of the three surrounding cells have the state A (step S18).
  • From the results of (a) and (b), the lower bit data is judged and held in the data latch circuit (step S19). Furthermore, the upper bit data is read (c) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V3 at a time when all of the three surrounding cells have the state A (step S20). The read upper bit data is held in the data latch circuit (step S21).
  • Next, the data latch circuit 21 is activated in a case where two of the three surrounding cells have the state A and the remaining cell has the state B in the word line WLn and each even-number bit line. In another case, the data latch circuit 21 is inactivated (step S22).
  • Subsequently, as shown in FIG. 16, the lower bit data is read (d) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V4 at a time when two of the three surrounding cells have the state A and the remaining cell has the state B (step S23). Furthermore, the lower bit data is read (e) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V5 at a time when two of the three surrounding cells have the state A and the remaining cell has the state B (step S24).
  • From the results of (d) and (e), the lower bit data is judged and held in the data latch circuit 21 (step S25). Furthermore, the upper bit data is read (f) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V6 at a time when two of the three surrounding cells have the state A and one of them has the state B (step S26). The read upper bit data is held in the data latch circuit 21 (step S27).
  • Next, the data latch circuit 21 is activated in a case where one of the three surrounding cells has the state A and the two remaining cells have the state B in the word line WLn and each even-number bit line. In another case, the data latch circuit 21 is inactivated (step S28).
  • Subsequently, as shown in FIG. 17, the lower bit data is read (g) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V7 at a time when one of the three surrounding cells has the state A and two of them have the state B (step S29). Furthermore, the lower bit data is read (h) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V8 at a time when one of the three surrounding cells has the state A and two of them have the state B (step S30).
  • From the results of (g) and (h), the lower bit data is judged and held in the data latch circuit 21 (step S31). Furthermore, the upper bit data is read (i) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V9 at a time when one of the three surrounding cells has the state A and two of them have the state B (step S32). The read upper bit data is held in the data latch circuit 21 (step S33).
  • Next, the data latch circuit 21 is activated in a case where all of the three surrounding cells have the state B in the word line WLn and each even-number bit line. In another case, that is, a case where all of the three surrounding cells do not have the state B, the data latch circuit 21 is inactivated (step S34).
  • Subsequently, as shown in FIG. 18, the lower bit data is read (j) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V10 at a time when all of the three surrounding cells have the state B (step S35). Furthermore, the lower bit data is read (k) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V11 at a time when all of the three surrounding cells have the state B (step S36).
  • From the results of (j) and (k), the lower bit data is judged and held in the data latch circuit 21 (step S37). Furthermore, the upper bit data is read (1) from the memory cell selected by the word line WLn and the even-number bit line by use of the judgment potential V12 at a time when all of the three surrounding cells have the state B (step S38). The read upper bit data is held in the data latch circuit (step S39).
  • Next, the lower bit data of the readout cell is output from the data latch circuit 21 via the data input/output buffer 6 (step S40). Subsequently, the upper bit data of the same cell is output from the data latch circuit 21 via the data input/output buffer 6 (step S41).
  • Thereafter, the similar operation is performed with respect to the odd-number bit line (step S42). Thereafter, it is judged whether or not “n” is the last in the page (step S43). When “n” is the last in the page, the write operation ends. On the other hand, when “n” is not the last in the page, “n” is set to “n+1” (step S44). The processing returns to the step S13, and the processing of and after the step S13 is similarly performed.
  • As described above, in this first embodiment, during the readout, the shift of the threshold value due to the influence of the proximity effect during the write is predicted from the memory cell disposed adjacent to the memory cell (readout cell) which is the readout object, and the judgment potential of the data is corrected every readout cell. This eliminates the influence of the proximity effect on the readout cell.
  • Second Embodiment
  • Next, there will be described a nonvolatile semiconductor memory device in a second embodiment of the present invention.
  • In the above-described first embodiment, during the write, the memory cell connected to the odd-number bit line does not receive any proximity effect of a memory cell connected to an even-number bit line adjacent to a memory cell connected to an odd-number bit line. This is because the data is first written into the memory cell of the even-number bit line, and thereafter the data is written into the memory cell of the odd-number bit line. Therefore, the simple readout is not performed with respect to the memory cell connected to the bit line adjacent to the memory cell of the odd-number bit line during the readout from the memory cell of the odd-number bit line, and the simple readout is performed with respect to the only memory cell connected to the adjacent word line, and the judgment potential of the readout cell is corrected.
  • FIG. 19 is a flowchart showing a readout operation in the nonvolatile semiconductor memory device of the second embodiment.
  • First, a block as a readout object is selected (step S51), and subsequently “n” is set to “0” (step S52). Next, the simple readout is executed with respect to a memory cell (hereinafter referred to as the adjacent cell) which is disposed adjacent to the memory cell (hereinafter referred to as the readout cell) as the readout object and which is connected to an odd-number bit line common to the readout cell. That is, assuming that the readout cell is the memory cell selected by the word line WLn and the odd-number bit line (odd-number BL), the simple readout is performed with respect to the memory cell selected by the word line WLn+1 and the odd-number bit line (step S53).
  • Next, from results of the simple readout from the adjacent cell, a state of the adjacent cell is input into a state-storing latch circuit 22 for each bit line (step S54). The state of the adjacent cell held in the state-storing latch circuit 22 is output to a judgment potential correction circuit 23. The judgment potential correction circuit 23 corrects a judgment potential for use during readout based on the state of the adjacent cell.
  • Next, the data latch circuit 21 is activated in a case where the adjacent cell has a state A in a word line WLn and each odd-number bit line. In another case, that is, a case where the adjacent cell is not in the state A, the data latch circuit 21 is inactivated (step S55).
  • Subsequently, lower bit data is read (a) from the memory cell selected by the word line WLn and the odd-number bit line by use of a judgment potential V13 at a time when the adjacent cell is in the state A (step S56). Furthermore, the lower bit data is read (b) from the memory cell selected by the word line WLn and the odd-number bit line by use of judgment potential V14 at a time when the adjacent cell has the state A (step S57).
  • From the results of (a) and (b), the lower bit data is judged and held in the data latch circuit 21 (step S58). Furthermore, upper bit data is read from the memory cell selected by the word line WLn and the odd-number bit line by use of judgment potential V15 at a time when the adjacent cell has the state A (step S59). The read upper bit data is held in the data latch circuit 21 (step S60).
  • Next, the data latch circuit 21 is activated in a case where the adjacent cell has the state B in the word line WLn and each odd-number bit line. In another case, that is, in a case where the adjacent cell does not have state B, the data latch circuit 21 is inactivated (step S61).
  • Subsequently, the lower bit data is read (c) from the memory cell selected by the word line WLn and the odd-number bit line by use of judgment potential V16 at a time when the adjacent cell has the state B (step S62). Furthermore, the lower bit data is read (d) from the memory cell selected by the word line WLn and the odd-number bit line by use of judgment potential V17 at a time when the adjacent cell has the state B (step S63).
  • From the results of (c) and (d), the lower bit data is judged and held in the data latch circuit 21 (step S64). Furthermore, the upper bit data is read from the memory cell selected by the word line WLn and the odd-number bit line by use of judgment potential V18 at a time when the adjacent cell has the state B (step S65). The read upper bit data is held in the data latch circuit 21 (step S66).
  • Next, the lower bit data of the readout cell is output from the data latch circuit 21 via a data input/output buffer 6 (step S67). Subsequently, the upper bit data of the same cell is output from the data latch circuit 21 via the data input/output buffer 6 (step S68). Thereafter, it is judged whether or not “n” is the last in a page (step S69). When “n” is the last in the page, the write operation ends. On the other hand, when “n” is not the last in the page, “n” is set to “n+1” (step S70). The processing returns to the step S53, and the processing of and after the step S53 is similarly performed.
  • As described above, in the second embodiment, the simple readout is not performed with respect to the memory cell which is disposed adjacent to the memory cell (readout cell) as the readout object and which is connected to the word line common to the readout cell. The simple readout is performed with respect to the only memory cell that is connected to the bit line common to the readout cell. According to the result of this simple readout, the judgment potential during the readout from the readout cell is set. Since the simple readout is not performed with respect to the memory cell which is disposed adjacent to the memory cell as the readout object and which is connected to the word line common to the memory cell as the readout object in this manner, a readout time is reduced.
  • Third Embodiment
  • Next, there will be described a nonvolatile semiconductor memory device in a third embodiment of the present invention.
  • In this third embodiment, the order of memory cells to be written is devised. Accordingly, a proximity effect is produced only during write of upper bit data.
  • FIG. 20 is a diagram showing a memory cell array 1, a main part of a column control circuit 2, and the write order into the memory cells in the nonvolatile semiconductor memory device of the third embodiment.
  • As shown in FIG. 20, four values are written into each memory cell in order of (1) to (14). First, lower bit data (1) is written into a memory cell MC1 selected by a word line WLn and an even-number bit line (even-number BL). Subsequently, lower bit data (2) is written into memory cells MC2 and MC3 selected by the word line WLn and an odd-number bit line (odd-number BL). Next, lower bit data (3) is written into a memory cell MC4 selected by a word line WLn+1 and an even-number bit line. Subsequently, lower bit data (4) is written into memory cells MC5 and MC6 selected by the word line WLn+1 and the odd-number bit line. Next, upper bit data (5) is written into the memory cell MC1 selected by the word line WLn and the even-number bit line. Subsequently, upper bit data (6) is written into the memory cells MC2 and MC3 selected by the word line WLn and the odd-number bit line. Next, lower bit data (7) is written into a memory cell MC7 selected by a word line WLn+2 and the even-number bit line. As shown in FIG. 20, the write is hereinafter performed in order of (8) to (14).
  • FIG. 21 shows a threshold value distribution of the written memory cells by the write shown in FIG. 20. FIG. 21 shows a distribution before the distribution undergoes the proximity effect. In the write shown in FIG. 20, the proximity effect is produced only during the write of the upper bit data. Therefore, since a breadth of the threshold value distribution due to the proximity effect of the memory cells can be suppressed, there can be obtained a broad threshold value distribution before undergoing the proximity effect. In consequence, a step width of a step-up voltage of a write pulse can be broadened, and a write time can be reduced. Another constitution and a readout operation are similar to those of the first embodiment.
  • Fourth Embodiment
  • Next, there will be described a nonvolatile semiconductor memory device in a fourth embodiment of the present invention.
  • In the above third embodiment, during readout, there are predicted proximity effects of both of a memory cell connected to a word line adjacent to a readout cell and a memory cell connected to a bit line adjacent to the readout cell, and a judgment potential during the readout is corrected. However, in a case where the memory cell connected to the adjacent word line has a strong proximity effect, and the memory cell connected to the adjacent bit line has a weak proximity effect, simple readout is performed from the memory cell connected to the adjacent word line, and the judgment potential of the readout cell is corrected.
  • In the fourth embodiment, the simple readout is not performed from a memory cell which is disposed adjacent to the readout cell and which is connected to a word line common to the readout cell, and the simple readout is performed from the only memory cell that is disposed adjacent to the readout cell and that is connected to a bit line common to the readout cell in the same manner as in the above second embodiment. According to this simple readout result, the judgment potential during the readout from the readout cell is set. In this manner, the simple readout is not performed from the memory cell which is disposed adjacent to the memory cell as the readout object and which is connected to the word line common to the memory cell as the readout object. Consequently, a readout time is reduced. A detailed readout operation is similar to that of the second embodiment of FIG. 19.
  • According to the embodiments of the present invention, there can be provided a nonvolatile semiconductor memory device capable of eliminating an influence of a threshold value fluctuation (proximity effect) generated by a parasitic capacity between adjacent memory cells.
  • Moreover, the above embodiments can be carried out alone, or an appropriate combination of the embodiments can be carried out. Furthermore, the above-described embodiments include various stages of inventions, and various stages of inventions can be extracted by appropriate combinations of a plurality of constituting factors disclosed in the respective embodiments.
  • Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general invention concept as defined by the appended claims and their equivalents.

Claims (21)

1. A nonvolatile semiconductor memory device comprising:
a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell as a readout object and second memory cells disposed adjacent to the first memory cell;
a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the second memory cells; and
a readout circuit which reads the first memory cell as the readout object by use of the judgment potential corrected by the judgment potential correction circuit.
2. The nonvolatile semiconductor memory device according to claim 1,
wherein the first memory cell is connected to a word line and a bit line, and the second memory cells disposed adjacent to the first memory cell includes:
a memory cell connected to the word line connected to the first memory cell; and
a memory cell connected to the bit line connected to the first memory cell.
3. The nonvolatile semiconductor memory device according to claim 1,
wherein the first memory cell is connected to a word line and a bit line, and the second memory cells disposed adjacent to the first memory cell includes a memory cell connected to the word line connected to the first memory cell.
4. The nonvolatile semiconductor memory device according to claim 1,
wherein the judgment potential correction circuit obtains, from the threshold values of the second memory cells, a threshold value fluctuation of the first memory cell generated by a parasitic capacity between the first memory cell and the second memory cells, and corrects the judgment potential based on the threshold value fluctuation.
5. The nonvolatile semiconductor memory device according to claim 1,
wherein each of the first and second memory cells stores a plurality of multivalued bits, and a threshold value difference between the bits has a threshold value difference capable of being judged irrespective of the threshold value fluctuation due to a parasitic capacity between the first memory cell and the second memory cells.
6. The nonvolatile semiconductor memory device according to claim 5,
wherein each of the first and second memory cells stores four values, and data is disposed from a higher threshold value in order of “01”, “00”, “10”, and “11”.
7. The nonvolatile semiconductor memory device according to claim 1,
wherein each of the first and second memory cells is a nonvolatile memory cell having a control gate and a floating gate.
8. A nonvolatile semiconductor memory device comprising:
a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell and a third memory cell, the first memory cell being connected to a word line, the second memory cell being disposed adjacent to the first memory cell and connected to the word line and a bit line, and the third memory cell being disposed adjacent to the second memory cell and connected to the bit line;
a write circuit which writes data into the second memory cell after writing data into the first memory cell;
a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the third memory cell disposed adjacent to the second memory cell and connected to the bit line; and
a readout circuit which reads the second memory cell by use of the judgment potential corrected by the judgment potential correction circuit.
9. The nonvolatile semiconductor memory device according to claim 8,
wherein the judgment potential correction circuit obtains, from the threshold value of the third memory cell, a threshold value fluctuation of the second memory cell generated by a parasitic capacity between the second memory cell and the third memory cell, and corrects the judgment potential based on the threshold value fluctuation.
10. The nonvolatile semiconductor memory device according to claim 8,
wherein the first memory cell is connected to even-number bit line, and the second and third memory cells are connected to odd-number bit line.
11. The nonvolatile semiconductor memory device according to claim 5,
wherein each of the first, second, and third memory cells stores a plurality of multivalued bits, and a threshold value difference between the bits has a threshold value difference capable of being judged irrespective of the threshold value fluctuation due to a parasitic capacity among the first, second, and third memory cells.
12. The nonvolatile semiconductor memory device according to claim 11,
wherein each of the first, second, and third memory cells stores four values, and data is disposed from a higher threshold value in order of “01”, “00”, “10”, and “11”.
13. The nonvolatile semiconductor memory device according to claim 8,
wherein each of the first, second, and third memory cells is a nonvolatile memory cell having a control gate and a floating gate.
14. A nonvolatile semiconductor memory device comprising:
a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, the first memory cell being connected to a first word line and a first bit line, the second memory cell being disposed adjacent to the first memory cell and connected to the first word line, a third memory cell being disposed adjacent to the first memory cell and connected to a second word line and the first bit line, and the fourth memory cell being disposed adjacent to the third memory cell and connected to the second word line; and
a write circuit which writes lower bit data into the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell, and upper bit data into the first memory cell and the second memory cell in this order.
15. The nonvolatile semiconductor memory device according to claim 14, further comprising:
a judgment potential correction circuit which corrects a judgment potential based on threshold values of the second and third memory cells; and
a readout circuit which reads the first memory cell by use of the judgment potential corrected by the judgment potential correction.
16. The nonvolatile semiconductor memory device according to claim 15,
wherein the judgment potential correction circuit:
obtains a fluctuation of the threshold value of the first memory cell generated by the parasitic capacities between the first memory cell and the third memory cell and between the first memory cell and the second memory cell from the threshold values of the second and third memory cells, and
corrects the judgment potential based on the fluctuation of the threshold value.
17. The nonvolatile semiconductor memory device according to claim 14, further comprising:
a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the third memory cell; and
a readout circuit which reads the first memory cell by use of the judgment potential corrected by the judgment potential correction circuit.
18. The nonvolatile semiconductor memory device according to claim 17,
wherein the judgment potential correction circuit:
obtains, from the threshold value of the second memory cell, a fluctuation of the threshold value of the first memory cell generated by a parasitic capacity between the first memory cell and the second memory cell, and
corrects the judgment potential based on the fluctuation of the threshold value.
19. The nonvolatile semiconductor memory device according to claim 14,
wherein each of the first, second, third, and fourth memory cells stores a plurality of multivalued bits, and a threshold value difference between the bits has a threshold value difference capable of being judged irrespective of the threshold value fluctuation due to a parasitic capacity among the, second, third, and fourth memory cells.
20. The nonvolatile semiconductor memory device according to claim 19,
wherein each of the first, second, third, and fourth memory cells stores four values, and data is disposed from a higher threshold value in order of “00”, “01”, “10”, and “11”.
21. The nonvolatile semiconductor memory device according to claim 14,
wherein each of the first, second, third, and fourth memory cells is a nonvolatile memory cell having a control gate and a floating gate.
US11/474,340 2006-01-06 2006-06-26 Nonvolatile semiconductor memory device including nand-type flash memory and the like Abandoned US20070159881A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006001456A JP4177847B2 (en) 2006-01-06 2006-01-06 Nonvolatile semiconductor memory device
JP2006-001456 2006-01-06

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/354,946 US7859898B2 (en) 2006-01-06 2009-01-16 Nonvolatile semiconductor memory device including NAND-type flash memory and the like
US12/955,621 US8139407B2 (en) 2006-01-06 2010-11-29 Nonvolatile semiconductor memory device including NAND-type flash memory and the like

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/354,946 Division US7859898B2 (en) 2006-01-06 2009-01-16 Nonvolatile semiconductor memory device including NAND-type flash memory and the like

Publications (1)

Publication Number Publication Date
US20070159881A1 true US20070159881A1 (en) 2007-07-12

Family

ID=38232594

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/474,340 Abandoned US20070159881A1 (en) 2006-01-06 2006-06-26 Nonvolatile semiconductor memory device including nand-type flash memory and the like
US12/354,946 Active 2026-07-26 US7859898B2 (en) 2006-01-06 2009-01-16 Nonvolatile semiconductor memory device including NAND-type flash memory and the like
US12/955,621 Active US8139407B2 (en) 2006-01-06 2010-11-29 Nonvolatile semiconductor memory device including NAND-type flash memory and the like

Family Applications After (2)

Application Number Title Priority Date Filing Date
US12/354,946 Active 2026-07-26 US7859898B2 (en) 2006-01-06 2009-01-16 Nonvolatile semiconductor memory device including NAND-type flash memory and the like
US12/955,621 Active US8139407B2 (en) 2006-01-06 2010-11-29 Nonvolatile semiconductor memory device including NAND-type flash memory and the like

Country Status (3)

Country Link
US (3) US20070159881A1 (en)
JP (1) JP4177847B2 (en)
KR (1) KR100895555B1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090251964A1 (en) * 2008-04-07 2009-10-08 Hitachi, Ltd. Nonvolatile semiconductor memory device
US20090323432A1 (en) * 2008-06-30 2009-12-31 Takuya Futatsuyama Nonvolatile semiconductor memory device
US20100110792A1 (en) * 2008-10-30 2010-05-06 Lutze Jeffrey W Pair bit line programming to improve boost voltage clamping
US20100149868A1 (en) * 2008-12-12 2010-06-17 Samsung Electronics Co., Ltd. Access method of non-volatile memory device
US7983086B2 (en) 2008-10-10 2011-07-19 Kabushiki Kaisha Toshiba NAND flash memory
US8023335B2 (en) 2008-09-19 2011-09-20 Samsung Electronics Co., Ltd. Flash memory device and systems and reading methods thereof
US8537619B2 (en) 2010-09-22 2013-09-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor storage device and method of controlling and manufacturing the same
US8837223B2 (en) 2011-11-21 2014-09-16 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacuring the same
CN104395966A (en) * 2012-06-01 2015-03-04 美光科技公司 Memory cell sensing
JP2016173868A (en) * 2015-03-17 2016-09-29 株式会社東芝 Nonvolatile semiconductor memory device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4912460B2 (en) * 2006-06-19 2012-04-11 サンディスク コーポレイションSanDisk Corporation Detecting individual size margin in nonvolatile memory read operation improvement and detection by compensation in selected state
KR101270685B1 (en) * 2007-08-24 2013-06-03 삼성전자주식회사 Apparatus and method for processing data of non-volitaile memory
KR101379820B1 (en) * 2007-10-17 2014-04-01 삼성전자주식회사 Apparatus for multi-bit programming and memory data detection apparatus
KR20090075062A (en) * 2008-01-03 2009-07-08 삼성전자주식회사 Semiconductor memory device comprising memory cell array having dynamic memory cells using floating body transistors
JP5710474B2 (en) * 2008-07-01 2015-04-30 エルエスアイ コーポレーション Method and apparatus for reducing inter-reader cell interference in flash memory
JP2012069192A (en) * 2010-09-22 2012-04-05 Toshiba Corp Memory system
JP2012069203A (en) 2010-09-22 2012-04-05 Toshiba Corp Nonvolatile semiconductor memory device and driving method for nonvolatile semiconductor memory device
JP2013242944A (en) 2012-05-22 2013-12-05 Toshiba Corp Semiconductor memory device
JP2014006940A (en) * 2012-06-21 2014-01-16 Toshiba Corp Semiconductor memory device
US9966125B2 (en) * 2016-09-15 2018-05-08 Toshiba Memory Corporation Memory device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6314026B1 (en) * 1999-02-08 2001-11-06 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device using local self boost technique
US6807104B2 (en) * 2002-11-29 2004-10-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and data program method thereof
US6878985B2 (en) * 2002-11-29 2005-04-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode
US6958938B2 (en) * 2001-02-20 2005-10-25 Kabushiki Kaisha Toshiba Data writing method for semiconductor memory device and semiconductor memory device
US7020025B2 (en) * 2003-09-22 2006-03-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781877B2 (en) 2002-09-06 2004-08-24 Sandisk Corporation Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
JP3935139B2 (en) 2002-11-29 2007-06-20 株式会社東芝 Semiconductor memory device
JP3913704B2 (en) 2003-04-22 2007-05-09 株式会社東芝 Nonvolatile semiconductor memory device and electronic device using the same
US7372730B2 (en) 2004-01-26 2008-05-13 Sandisk Corporation Method of reading NAND memory to compensate for coupling between storage elements
US7366013B2 (en) * 2005-12-09 2008-04-29 Micron Technology, Inc. Single level cell programming in a multiple level cell non-volatile memory device
JP2010009733A (en) 2008-06-30 2010-01-14 Toshiba Corp Nonvolatile semiconductor memory device
JP2010092559A (en) 2008-10-10 2010-04-22 Toshiba Corp Nand type flash memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6314026B1 (en) * 1999-02-08 2001-11-06 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device using local self boost technique
US6958938B2 (en) * 2001-02-20 2005-10-25 Kabushiki Kaisha Toshiba Data writing method for semiconductor memory device and semiconductor memory device
US6807104B2 (en) * 2002-11-29 2004-10-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and data program method thereof
US6878985B2 (en) * 2002-11-29 2005-04-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode
US7020025B2 (en) * 2003-09-22 2006-03-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090251964A1 (en) * 2008-04-07 2009-10-08 Hitachi, Ltd. Nonvolatile semiconductor memory device
US20090323432A1 (en) * 2008-06-30 2009-12-31 Takuya Futatsuyama Nonvolatile semiconductor memory device
US8711635B2 (en) 2008-06-30 2014-04-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US8315104B2 (en) 2008-06-30 2012-11-20 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US8023335B2 (en) 2008-09-19 2011-09-20 Samsung Electronics Co., Ltd. Flash memory device and systems and reading methods thereof
US8248858B2 (en) 2008-09-19 2012-08-21 Samsung Electronics Co., Ltd. Flash memory device and systems and reading methods thereof
US8159880B2 (en) 2008-10-10 2012-04-17 Kabushiki Kaisha Toshiba NAND flash memory
US7983086B2 (en) 2008-10-10 2011-07-19 Kabushiki Kaisha Toshiba NAND flash memory
US8520448B1 (en) 2008-10-30 2013-08-27 Sandisk Technologies Inc. Sequential programming of sets of non-volatile elements to improve boost voltage clamping
US8130556B2 (en) * 2008-10-30 2012-03-06 Sandisk Technologies Inc. Pair bit line programming to improve boost voltage clamping
US20100110792A1 (en) * 2008-10-30 2010-05-06 Lutze Jeffrey W Pair bit line programming to improve boost voltage clamping
US8451667B2 (en) 2008-10-30 2013-05-28 Sandisk Technologies Inc. Pair bit line programming to improve boost voltage clamping
US8503230B2 (en) 2008-12-12 2013-08-06 Samsung Electronics Co., Ltd. Access method of non-volatile memory device
US20100149868A1 (en) * 2008-12-12 2010-06-17 Samsung Electronics Co., Ltd. Access method of non-volatile memory device
US8537619B2 (en) 2010-09-22 2013-09-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor storage device and method of controlling and manufacturing the same
US8837223B2 (en) 2011-11-21 2014-09-16 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacuring the same
CN104395966A (en) * 2012-06-01 2015-03-04 美光科技公司 Memory cell sensing
JP2016173868A (en) * 2015-03-17 2016-09-29 株式会社東芝 Nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
US8139407B2 (en) 2012-03-20
US20090129158A1 (en) 2009-05-21
KR100895555B1 (en) 2009-04-29
KR20070074477A (en) 2007-07-12
US7859898B2 (en) 2010-12-28
JP2007184040A (en) 2007-07-19
US20110069542A1 (en) 2011-03-24
JP4177847B2 (en) 2008-11-05

Similar Documents

Publication Publication Date Title
US10672482B2 (en) Semiconductor memory device
US9472295B2 (en) Nonvolatile semiconductor memory device
US10346053B2 (en) Nonvolatile semiconductor memory device
US8513726B2 (en) EEPROM with increased reading speed
US8539144B2 (en) Nonvolatile semiconductor memory device with advanced multi-page program operation
US7995400B2 (en) Reducing effects of program disturb in a memory device
US8120959B2 (en) NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same
US7483301B2 (en) Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same
US7916534B2 (en) Semiconductor memory device
KR100790823B1 (en) Non-volatile semiconductor memory device with minimized read disturbance
DE60315532T2 (en) Method for rewriting the programming and reading faults of a non-volatile memory
US20190074061A1 (en) Erasable block segmentation for memory
US7916542B2 (en) Nonvolatile memory device with multiple page regions, and methods of reading and precharging the same
US8472266B2 (en) Reducing neighbor read disturb
US6930921B2 (en) NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages
TWI286754B (en) Algorithm dynamic reference programming
KR100644222B1 (en) Page buffer and multi-bit nonvolatile memory device including the same
US7876618B2 (en) Non-volatile memory with reduced leakage current for unselected blocks and method for operating same
US6055188A (en) Nonvolatile semiconductor memory device having a data circuit for erasing and writing operations
JP5383889B2 (en) Page buffer and non-volatile memory device including the same
KR100767137B1 (en) Nonvolatile semiconductor memory device
US6934194B2 (en) Nonvolatile memory having a trap layer
US7433241B2 (en) Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data
KR101913331B1 (en) Nonvolatile memory device, novolatile memory system, program method thereof, and operation method of controller controlling the same
JP3833970B2 (en) Nonvolatile semiconductor memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SATO, ATSUHIRO;SHUTO, KEIJI;ARAI, FUMITAKA;REEL/FRAME:018259/0593

Effective date: 20060804

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION