US20070147430A1 - Method and apparatus for transmitting data in an integrated circuit - Google Patents
Method and apparatus for transmitting data in an integrated circuit Download PDFInfo
- Publication number
- US20070147430A1 US20070147430A1 US11/275,303 US27530305A US2007147430A1 US 20070147430 A1 US20070147430 A1 US 20070147430A1 US 27530305 A US27530305 A US 27530305A US 2007147430 A1 US2007147430 A1 US 2007147430A1
- Authority
- US
- United States
- Prior art keywords
- data packet
- transmission
- data
- packet
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0079—Formats for control data
- H04L1/0082—Formats for control data fields explicitly indicating existence of error in data being transmitted, e.g. so that downstream stations can avoid decoding erroneous packet; relays
Definitions
- the present invention generally relates to integrated circuits and, more specifically, to the transmission of data in an integrated circuit.
- High-speed communication is typically accomplished by breaking the data into packets that can be transmitted (via a transmitter) and re-assembled (via a receiver) at the destination. The integrity of the data packets is ensured using data error/correction techniques such as Cyclic Redundancy Coding (CRC) and Variant CRC (VCRC).
- CRC Cyclic Redundancy Coding
- VCRC Variant CRC
- Typical vendor design solutions provide a transmitter/receiver package that implements the high-speed data packet communication between two distinct portions of a customer design according to a particular protocol such as InfinibandTM.
- the transmission mediums used in the package solution and the customer designs are not always of equal capacity. Consequently, the transmission of the data packets can be stalled by certain conditions such as the transmitter being filled to capacity or as a result of transmitting the data packet across differing clock domains.
- the present invention is a method of transmitting data packets using a protocol that verifies the integrity of the data packet with an integrity value residing in the data packet.
- the method includes the steps of receiving a data packet (the data packet can have a predetermined length), and receiving an indication that a transmission of the data packet has been interrupted prior to receiving the entire data packet.
- the method also includes the step of saving, in response to the interruption indication, the integrity value of the data packet.
- the method further includes the steps of receiving an end of packet indicator in the data packet, and inserting, in response to receiving the end of packet indicator, the saved integrity value into the transmission of the data packet.
- the method can include the step of generating the integrity value for the data packet as it is received.
- the method can further include the step of formatting the received data packet to match a specified transmission length.
- the method can include the step of adding, in response to the interruption indication, a wait cycle to the transmission of the data packet.
- a transmission medium that is used for transmitting the data packet can be smaller than the size of the received data packet.
- the step of formatting includes splitting the transmission of the data packet into a first portion that gets transmitted first and a second portion that gets transmitted second.
- Transmitting the data packet to a clock domain that differs from the destination clock domain can cause the interruption of the transmission of the data packet.
- FIG. 1 is drawing illustrating a communication core that can be incorporated into an integrated circuit and demonstrates how data is transferred from a local source to a remote source using a packet-based protocol according to the teachings of the present invention
- FIG. 2 is a circuit diagram illustrating in greater detail the transmitter of FIG. 1 according to the teachings of the present invention
- FIG. 3 is a diagram of a data packet that can be transmitted by the customer interface of FIG. 2 according to the teachings of the present invention
- FIG. 4 is a diagram of a data packet that can be transmitted by the pipeline stage of the transmitter of FIG. 2 according to the teachings of the present invention.
- FIG. 5 is a flow chart illustrating a method of processing pauses (stalls) that are generated during the receipt of packet data by the FIFO of FIG. 2 according to the teachings of the present invention.
- the present invention is a method and apparatus for transmitting data using a packet-based protocol that supports VCRC data integrity.
- a pause can occur from crossing one clock domain to another or for other similar reasons.
- the present invention resolves these pauses by adding a wait cycle to the transmission and saving the calculated VCRC value at the point the pause is detected. Once the end of the data packet has been received, the saved VCRC value is inserted into the data packet and transmitted.
- FIG. 1 a communication core 100 that can be incorporated into an integrated circuit is shown to demonstrate how data is transferred from a local source to a remote source using a packet-based protocol according to the teachings of the present invention.
- the packet-based protocol is the InfinibandTM architecture.
- Communication core 100 includes local and remote communication sources each having a customer interface ( 102 and 106 ) and a link/physical layer ( 104 and 108 ).
- the Link/Physical layers 108 and 104 include the following identical elements: transmitter ( 104 A and 108 A), a receiver ( 104 B and 108 B), a serializer ( 104 C and 108 C), and deserializer ( 104 D and 108 D).
- transmitter 104 A and 108 A
- receiver 104 B and 108 B
- serializer 104 C and 108 C
- deserializer 104 D and 108 D
- the customer interface 106 includes pins and the like for providing access to the remote source.
- the customer interface 106 provides data in packets using Cyclic Redundancy Coding (CRC) for data integrity.
- CRC Cyclic Redundancy Coding
- the receiver 108 A receives data packets from the transmitter 104 B and transmits them to the customer interface 106 using CRC.
- the transmitter 108 B receives data from the customer interface 106 and encodes the data packets using the CRC and transmits them to the serializer 108 c using Variant Cyclic Redundancy Coding (VCRC) for data integrity.
- VCRC Variant Cyclic Redundancy Coding
- the serializer 108 C serializes the packet data onto the available Wire/Cable 112 according to its configuration width in bytes of one (1), four (4), eight (8), and twelve (12) and in a speed of either Single Data Rate (SDR) or Double Data Rate (DDR).
- the deserializer 108 D receives data packet in the VCRC format on the Wire/Cable 110 and decodes the data packet and provides it to the receiver 108 .
- Transmitter 108 B transmits the data packet while resolving pauses in the receipt of the packet data by the local source as described in connection with FIG. 2 below.
- the transmitter 108 B includes a pipeline stage 204 and a physical lane/FIFO 206 .
- Data packet 300 has a Start Of Packet indicator, a payload (data which can include several bytes), a CRC value, a VCRC (two bytes) value, and an End Of Packet (EOP) indicator.
- Start Of Packet indicator e.g. 1 byte
- payload data which can include several bytes
- CRC value e.g. 1 byte
- VCRC two bytes
- EOP End Of Packet
- data packets received from the customer interface 106 by the pipeline stage 204 are formatted to comply with a Variant Cyclic Redundancy Coding (VCRC) data integrity and to comply the configuration of the physical lane 206 .
- VCRC Variant Cyclic Redundancy Coding
- a VCRC data packet can resemble the VCRC data packet 400 shown in FIG. 4 .
- the physical lanes 206 are dynamically configurable to support the transmission of one (1), four (4), eight (8), and twelve (12) bytes of data each clock cycle at either Single Data Rate (SDR) or Double Data Rate (DDR) speeds.
- SDR Single Data Rate
- DDR Double Data Rate
- speed of transfer i.e., SDR or DDR
- the length of the data packet received by the customer interface 106 the received data packet will be completely transmitted in one to three clock cycles.
- Physical lanes 206 includes a Clock Domain Crossing (CDC) detector 206 A which can detect pauses generated during the transmission of the data packet from the physical lanes 206 (e.g., filled to capacity or crossing clock domains).
- CDC Clock Domain Crossing
- the customer interface 106 transmits data packets in 192 bit increments (i.e., 6 words) to a format register 208 and a VCRC generator 214 .
- the format register 208 is responsible for formatting the received data packets into new data packets that are consistent with the data width supported by the physical lanes 206 . Depending upon the data packet width, the format register 208 can store a portion of the received packets in the buffer 216 . The newly formatted data packets are then sent to multiplexer M 4 from the format register 208 or buffer 216 .
- Packet format state machine 210 directs multiplexers M 1 -M 4 where to send the data packet and the shift register 220 when to send a portion of the data packet to multiplexer M 3 . If the current configuration of physical lanes 206 and data transfer speed can accomplish the transfer of the configured data packet in a single cycle, then packet format state machine 210 directs multiplexer M 4 to transmit the data packet in its entirety to multiplexer M 1 ; otherwise, packet format state machine 210 directs multiplexer M 4 to split the packet data into lower and upper portions and transmit to multiplexer M 1 and M 2 , respectively.
- the packet format state machine 210 directs multiplexer M 1 to place any received packet data in multiplexer M 3 . If the packet data was split into lower and upper portions then packet format state machine 210 directs multiplexer M 2 to transfer the upper portion to shift register 220 .
- Packet state machine 210 directs multiplexer M 3 to transmit the received data packet to the physical lanes 206 . If the data packet has been broken into multiple portions, then after multiplexer M 3 has completed its transfer, packet state machine 210 directs shift register 220 to transfer the remaining portion of the data packet to multiplexer M 3 , and multiplexer M 3 to transfer the portion of the data packet to the physical lanes 206 .
- the VCRC generator 214 generates a VCRC value using well-known and understood techniques for the received data packet.
- the generated VCRC value is provided to the VCRC multiplexer 218 .
- VCRC multiplexer 218 includes a set of latches (not shown) that store the VCRC value upon receiving a hold signal from the VCRC state machine 212 .
- the VCRC multiplexer 218 provides the VCRC value to either multiplexer M 2 or M 1 depending upon the stage of transfer for the data packet (current clock cycle and completion) and whether the packet data has been split into upper and lower portions.
- VCRC multiplexer 218 transfers the VCRC value to multiplexer M 1 for insertion into the data packet. If the data packet is split into upper and lower portions then VCRC multiplexer 218 transfers the VCRC value to multiplexer M 2 for insertion into the data packet.
- FIG. 5 a flow chart is shown illustrating a method of processing pauses (stalls) that are generated during the receipt of packet data by the FIFO 206 of FIG. 2 according to the teachings of the present invention.
- data packets are received from the customer interface 106 in a CRC packet-based protocol (Step 500 ).
- the VCRC state machine 212 monitors the receipt of the data packets and control signals for an EOP indicator (Step 504 ). Upon the detection of an EOP indicator, the VCRC state machine 212 determines whether the data packet has been split between multiplexers M 1 and M 2 (Step 506 ). If the data packet has been split, then the VCRC state machine 212 directs the VCRC multiplexer 218 to transmit the VCRC value to the multiplexer M 2 (Step 508 ), and the VCRC value is added to the packet data by multiplexer M 2 and the transmission of the data packet proceeds as previously described in connection with FIG. 2 (Step 522 ).
- the VCRC state machine 212 monitors the CDC detector 206 A to determine whether a pause (stall) in the transmission of packet data by the physical lanes 206 has occurred (Step 510 ).
- Step 512 a wait cycle is added to the processing of the transmission of the current data packet and the VCRC state machine 212 instructs the VCRC multiplexer 218 to hold the generated VCRC value via a hold signal.
- the VCRC state machine 212 determines whether a wait cycle was added as a result of a pause condition (Steps 514 - 516 ).
- the VCRC state machine 212 instructs the VCRC multiplexer 218 to use the held VCRC value; otherwise it instructs the multiplexer 218 to use the generated VCRC value (Steps 516 - 520 ). Thereafter, multiplexer 218 transmits the VCRC value to either multiplexer M 1 or M 2 as previously discussed in connection with FIG. 2 (Step 522 ).
- Table 1 below represents an example of how the data packet can appear if the physical lanes 206 were configured for 12 bytes (L0-L11 representing one lane transmitting a single byte serially) and each row represents one clock cycle.
- Table 1 represents an example of how the data packet can appear if the physical lanes 206 were configured for 12 bytes (L0-L11 representing one lane transmitting a single byte serially) and each row represents one clock cycle.
- Row one represents a 12 byte packet being sent in a single clock cycle.
- Rows 2 and 3 represents a 24 byte data packet being sent in two clock cycles.
- Row four represents a four byte data packet being sent in a single clock cycle.
- Table 2 represents the same transmission of the data packet as explained in Table 1 above, except a pause occurs during the transmission on clock cycle 1. In this case, the same 12 byte data packet is sent on the second clock cycle after the pause has ceased.
- row L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 1 SDP Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data VCRC VCRC EGP REPEAT SAME DATA 3 Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data VCRC VCRC EGP 4 SDP Data Data Data Data VCRC VCRC EGP Pad Pad Pad Pad Pad Pad Pad
Abstract
Description
- 1. Technical Field of the Present Invention
- The present invention generally relates to integrated circuits and, more specifically, to the transmission of data in an integrated circuit.
- 2. Description of Related Art
- In the past, communication of data at high speeds between various elements of a system was limited to a relatively few number of applications. Today, however, high-speed communication has become a requirement for most applications. High-speed communication is typically accomplished by breaking the data into packets that can be transmitted (via a transmitter) and re-assembled (via a receiver) at the destination. The integrity of the data packets is ensured using data error/correction techniques such as Cyclic Redundancy Coding (CRC) and Variant CRC (VCRC). The CRC and VCRC are part of the data packet and are calculated with each transmission.
- Typical vendor design solutions provide a transmitter/receiver package that implements the high-speed data packet communication between two distinct portions of a customer design according to a particular protocol such as Infiniband™.
- The transmission mediums used in the package solution and the customer designs are not always of equal capacity. Consequently, the transmission of the data packets can be stalled by certain conditions such as the transmitter being filled to capacity or as a result of transmitting the data packet across differing clock domains.
- Current designs of the transmitter/receiver package rely on each customer creating an individualized solution for resolving stalls. Unfortunately, this results in numerous differing solutions for the same problem; many of which are incompatible with one another.
- It would, therefore, be a distinct advantage to have a method and apparatus that would resolve theses transmission stalls in the transmitter/receiver package so as to provide a consistent and less error prone solution with multiple differing customer interfaces.
- In one aspect, the present invention is a method of transmitting data packets using a protocol that verifies the integrity of the data packet with an integrity value residing in the data packet. The method includes the steps of receiving a data packet (the data packet can have a predetermined length), and receiving an indication that a transmission of the data packet has been interrupted prior to receiving the entire data packet. The method also includes the step of saving, in response to the interruption indication, the integrity value of the data packet. The method further includes the steps of receiving an end of packet indicator in the data packet, and inserting, in response to receiving the end of packet indicator, the saved integrity value into the transmission of the data packet.
- The method can include the step of generating the integrity value for the data packet as it is received. The method can further include the step of formatting the received data packet to match a specified transmission length. In addition, the method can include the step of adding, in response to the interruption indication, a wait cycle to the transmission of the data packet.
- A transmission medium that is used for transmitting the data packet can be smaller than the size of the received data packet. In that case, the step of formatting includes splitting the transmission of the data packet into a first portion that gets transmitted first and a second portion that gets transmitted second.
- Transmitting the data packet to a clock domain that differs from the destination clock domain can cause the interruption of the transmission of the data packet.
- The present invention will be better understood and its advantages will become more apparent to those skilled in the art by reference to the following drawings, in conjunction with the accompanying specification, in which:
-
FIG. 1 is drawing illustrating a communication core that can be incorporated into an integrated circuit and demonstrates how data is transferred from a local source to a remote source using a packet-based protocol according to the teachings of the present invention; -
FIG. 2 is a circuit diagram illustrating in greater detail the transmitter ofFIG. 1 according to the teachings of the present invention; -
FIG. 3 is a diagram of a data packet that can be transmitted by the customer interface ofFIG. 2 according to the teachings of the present invention; -
FIG. 4 is a diagram of a data packet that can be transmitted by the pipeline stage of the transmitter ofFIG. 2 according to the teachings of the present invention; and -
FIG. 5 is a flow chart illustrating a method of processing pauses (stalls) that are generated during the receipt of packet data by the FIFO ofFIG. 2 according to the teachings of the present invention. - The present invention is a method and apparatus for transmitting data using a packet-based protocol that supports VCRC data integrity. During the transmission of the data packet, a pause can occur from crossing one clock domain to another or for other similar reasons. The present invention resolves these pauses by adding a wait cycle to the transmission and saving the calculated VCRC value at the point the pause is detected. Once the end of the data packet has been received, the saved VCRC value is inserted into the data packet and transmitted.
- Reference now being made to
FIG. 1 , acommunication core 100 that can be incorporated into an integrated circuit is shown to demonstrate how data is transferred from a local source to a remote source using a packet-based protocol according to the teachings of the present invention. In the preferred embodiment of the present invention, the packet-based protocol is the Infiniband™ architecture. -
Communication core 100 includes local and remote communication sources each having a customer interface (102 and 106) and a link/physical layer (104 and 108). The Link/Physical layers Physical layer 108 is equally applicable to the equivalent elements of Link/Physical layer 104. - The
customer interface 106 includes pins and the like for providing access to the remote source. In the preferred embodiment of the present invention, thecustomer interface 106 provides data in packets using Cyclic Redundancy Coding (CRC) for data integrity. - The
receiver 108A receives data packets from thetransmitter 104B and transmits them to thecustomer interface 106 using CRC. - The
transmitter 108B receives data from thecustomer interface 106 and encodes the data packets using the CRC and transmits them to the serializer 108 c using Variant Cyclic Redundancy Coding (VCRC) for data integrity. The serializer 108C serializes the packet data onto the available Wire/Cable 112 according to its configuration width in bytes of one (1), four (4), eight (8), and twelve (12) and in a speed of either Single Data Rate (SDR) or Double Data Rate (DDR). - The deserializer 108D receives data packet in the VCRC format on the Wire/Cable 110 and decodes the data packet and provides it to the
receiver 108. -
Transmitter 108B transmits the data packet while resolving pauses in the receipt of the packet data by the local source as described in connection withFIG. 2 below. - Reference now being made to
FIG. 2 , a circuit diagram is shown illustrating in greater detail thetransmitter 108B ofFIG. 1 according to the teachings of the present invention. Thetransmitter 108B includes apipeline stage 204 and a physical lane/FIFO 206. - In a packet-based protocol, data is received in packets having a predefined length (e.g., 1 byte). In the preferred embodiment of the present invention, a data packet transmitted by the
customer interface 106 can resemble thedata packet 300 shown inFIG. 3 .Data packet 300 has a Start Of Packet indicator, a payload (data which can include several bytes), a CRC value, a VCRC (two bytes) value, and an End Of Packet (EOP) indicator. - In the preferred embodiment of the present invention, data packets received from the
customer interface 106 by thepipeline stage 204 are formatted to comply with a Variant Cyclic Redundancy Coding (VCRC) data integrity and to comply the configuration of thephysical lane 206. A VCRC data packet can resemble the VCRCdata packet 400 shown inFIG. 4 . - In the preferred embodiment of the present invention, the
physical lanes 206 are dynamically configurable to support the transmission of one (1), four (4), eight (8), and twelve (12) bytes of data each clock cycle at either Single Data Rate (SDR) or Double Data Rate (DDR) speeds. Depending upon the configured width of thephysical lanes 206, speed of transfer (i.e., SDR or DDR) and the length of the data packet received by thecustomer interface 106, the received data packet will be completely transmitted in one to three clock cycles.Physical lanes 206 includes a Clock Domain Crossing (CDC)detector 206A which can detect pauses generated during the transmission of the data packet from the physical lanes 206 (e.g., filled to capacity or crossing clock domains). - The
customer interface 106 transmits data packets in 192 bit increments (i.e., 6 words) to aformat register 208 and aVCRC generator 214. - The
format register 208 is responsible for formatting the received data packets into new data packets that are consistent with the data width supported by thephysical lanes 206. Depending upon the data packet width, theformat register 208 can store a portion of the received packets in thebuffer 216. The newly formatted data packets are then sent to multiplexer M4 from theformat register 208 orbuffer 216. - Packet
format state machine 210 directs multiplexers M1-M4 where to send the data packet and theshift register 220 when to send a portion of the data packet to multiplexer M3. If the current configuration ofphysical lanes 206 and data transfer speed can accomplish the transfer of the configured data packet in a single cycle, then packetformat state machine 210 directs multiplexer M4 to transmit the data packet in its entirety to multiplexer M1; otherwise, packetformat state machine 210 directs multiplexer M4 to split the packet data into lower and upper portions and transmit to multiplexer M1 and M2, respectively. - The packet
format state machine 210 directs multiplexer M1 to place any received packet data in multiplexer M3. If the packet data was split into lower and upper portions then packetformat state machine 210 directs multiplexer M2 to transfer the upper portion to shiftregister 220. -
Packet state machine 210 directs multiplexer M3 to transmit the received data packet to thephysical lanes 206. If the data packet has been broken into multiple portions, then after multiplexer M3 has completed its transfer,packet state machine 210 directsshift register 220 to transfer the remaining portion of the data packet to multiplexer M3, and multiplexer M3 to transfer the portion of the data packet to thephysical lanes 206. - The
VCRC generator 214 generates a VCRC value using well-known and understood techniques for the received data packet. The generated VCRC value is provided to theVCRC multiplexer 218. -
VCRC multiplexer 218 includes a set of latches (not shown) that store the VCRC value upon receiving a hold signal from theVCRC state machine 212. TheVCRC multiplexer 218 provides the VCRC value to either multiplexer M2 or M1 depending upon the stage of transfer for the data packet (current clock cycle and completion) and whether the packet data has been split into upper and lower portions. - If the packet data is fully contained in multiplexer M1 then
VCRC multiplexer 218 transfers the VCRC value to multiplexer M1 for insertion into the data packet. If the data packet is split into upper and lower portions thenVCRC multiplexer 218 transfers the VCRC value to multiplexer M2 for insertion into the data packet. - Reference now being made to
FIG. 5 , a flow chart is shown illustrating a method of processing pauses (stalls) that are generated during the receipt of packet data by theFIFO 206 ofFIG. 2 according to the teachings of the present invention. In the preferred embodiment of the present invention, data packets are received from thecustomer interface 106 in a CRC packet-based protocol (Step 500). - The
VCRC state machine 212 monitors the receipt of the data packets and control signals for an EOP indicator (Step 504). Upon the detection of an EOP indicator, theVCRC state machine 212 determines whether the data packet has been split between multiplexers M1 and M2 (Step 506). If the data packet has been split, then theVCRC state machine 212 directs theVCRC multiplexer 218 to transmit the VCRC value to the multiplexer M2 (Step 508), and the VCRC value is added to the packet data by multiplexer M2 and the transmission of the data packet proceeds as previously described in connection withFIG. 2 (Step 522). - If, however, the data packet has not been split, then the
VCRC state machine 212 monitors theCDC detector 206A to determine whether a pause (stall) in the transmission of packet data by thephysical lanes 206 has occurred (Step 510). - If a pause occurs, then a wait cycle is added to the processing of the transmission of the current data packet and the
VCRC state machine 212 instructs theVCRC multiplexer 218 to hold the generated VCRC value via a hold signal (Step 512). - After the packet ends, which can occur in 1 to 3 clock cycles as previously explained in connection with
FIG. 2 , theVCRC state machine 212 determines whether a wait cycle was added as a result of a pause condition (Steps 514-516). - If a wait cycle was added, then the
VCRC state machine 212 instructs theVCRC multiplexer 218 to use the held VCRC value; otherwise it instructs themultiplexer 218 to use the generated VCRC value (Steps 516-520). Thereafter,multiplexer 218 transmits the VCRC value to either multiplexer M1 or M2 as previously discussed in connection withFIG. 2 (Step 522). - Table 1 below represents an example of how the data packet can appear if the
physical lanes 206 were configured for 12 bytes (L0-L11 representing one lane transmitting a single byte serially) and each row represents one clock cycle.TABLE 1 row L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 1 SDP Data Data Data Data Data Data Data Data VCRC VCRC EGP 2 SDP Data Data Data Data Data Data Data Data Data Data Data 3 Data Data Data Data Data Data Data Data Data VCRC VCRC EGP 4 SDP Data Data Data Data VCRC VCRC EGP Pad Pad Pad Pad - Row one represents a 12 byte packet being sent in a single clock cycle. Rows 2 and 3 represents a 24 byte data packet being sent in two clock cycles. Row four represents a four byte data packet being sent in a single clock cycle.
- Table 2 below represents the same transmission of the data packet as explained in Table 1 above, except a pause occurs during the transmission on clock cycle 1. In this case, the same 12 byte data packet is sent on the second clock cycle after the pause has ceased.
row L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 1 SDP Data Data Data Data Data Data Data Data VCRC VCRC EGP PAUSE 2 SDP Data Data Data Data Data Data Data Data VCRC VCRC EGP REPEAT SAME DATA 3 Data Data Data Data Data Data Data Data Data VCRC VCRC EGP 4 SDP Data Data Data Data VCRC VCRC EGP Pad Pad Pad Pad - It is thus believed that the operation and construction of the present invention will be apparent from the foregoing description. While the method and system shown and described has been characterized as being preferred, it will be readily apparent that various changes and/or modifications could be made without departing from the spirit and scope of the present invention as defined in the following claims.
Claims (22)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/275,303 US7571377B2 (en) | 2005-12-22 | 2005-12-22 | Method and apparatus for transmitting data in an integrated circuit |
CN2006101446763A CN1988430B (en) | 2005-12-22 | 2006-11-14 | A method and apparatus for transmitting data in an integrated circuit |
KR1020060120018A KR100985684B1 (en) | 2005-12-22 | 2006-11-30 | A method and apparatus for transmitting data in an integrated circuit |
JP2006343593A JP4791339B2 (en) | 2005-12-22 | 2006-12-20 | Method and apparatus for transmitting data in an integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/275,303 US7571377B2 (en) | 2005-12-22 | 2005-12-22 | Method and apparatus for transmitting data in an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070147430A1 true US20070147430A1 (en) | 2007-06-28 |
US7571377B2 US7571377B2 (en) | 2009-08-04 |
Family
ID=36261799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/275,303 Expired - Fee Related US7571377B2 (en) | 2005-12-22 | 2005-12-22 | Method and apparatus for transmitting data in an integrated circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US7571377B2 (en) |
JP (1) | JP4791339B2 (en) |
KR (1) | KR100985684B1 (en) |
CN (1) | CN1988430B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6279140B1 (en) * | 1999-01-07 | 2001-08-21 | International Business Machines Corporation | Method and apparatus for checksum verification with receive packet processing |
US7210056B2 (en) * | 2004-06-08 | 2007-04-24 | Sun Microsystems, Inc. | Low latency comma detection and clock alignment |
US7463649B2 (en) * | 2004-04-09 | 2008-12-09 | Hon Hai Precision Industry Co., Ltd. | System and method for checking validity of data transmission |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3501305B2 (en) | 1993-08-04 | 2004-03-02 | サン・マイクロシステムズ・インコーポレイテッド | Interconnect control device and method |
US6058462A (en) * | 1998-01-23 | 2000-05-02 | International Business Machines Corporation | Method and apparatus for enabling transfer of compressed data record tracks with CRC checking |
US6865222B1 (en) | 1999-09-23 | 2005-03-08 | Texas Instruments Incorporated | Method and apparatus for testing a serial transmitter circuit |
US7327690B2 (en) * | 2002-08-12 | 2008-02-05 | Harris Corporation | Wireless local or metropolitan area network with intrusion detection features and related methods |
US7240200B2 (en) * | 2002-09-26 | 2007-07-03 | International Business Machines Corporation | System and method for guaranteeing software integrity via combined hardware and software authentication |
GB0226420D0 (en) * | 2002-11-13 | 2002-12-18 | Koninkl Philips Electronics Nv | An improved communications protocol |
JP4064914B2 (en) * | 2003-12-02 | 2008-03-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Information processing apparatus, server apparatus, method for information processing apparatus, method for server apparatus, and apparatus executable program |
GB0408868D0 (en) * | 2004-04-21 | 2004-05-26 | Level 5 Networks Ltd | Checking data integrity |
-
2005
- 2005-12-22 US US11/275,303 patent/US7571377B2/en not_active Expired - Fee Related
-
2006
- 2006-11-14 CN CN2006101446763A patent/CN1988430B/en not_active Expired - Fee Related
- 2006-11-30 KR KR1020060120018A patent/KR100985684B1/en not_active IP Right Cessation
- 2006-12-20 JP JP2006343593A patent/JP4791339B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6279140B1 (en) * | 1999-01-07 | 2001-08-21 | International Business Machines Corporation | Method and apparatus for checksum verification with receive packet processing |
US7463649B2 (en) * | 2004-04-09 | 2008-12-09 | Hon Hai Precision Industry Co., Ltd. | System and method for checking validity of data transmission |
US7210056B2 (en) * | 2004-06-08 | 2007-04-24 | Sun Microsystems, Inc. | Low latency comma detection and clock alignment |
Also Published As
Publication number | Publication date |
---|---|
KR20070066868A (en) | 2007-06-27 |
JP2007174670A (en) | 2007-07-05 |
KR100985684B1 (en) | 2010-10-05 |
CN1988430A (en) | 2007-06-27 |
US7571377B2 (en) | 2009-08-04 |
JP4791339B2 (en) | 2011-10-12 |
CN1988430B (en) | 2010-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8165257B2 (en) | Methods and apparatus for interface buffer management and clock compensation in data transfers | |
US7792014B2 (en) | Method of skipping nullified packets during mass replay from replay buffer | |
US7555693B2 (en) | Auxiliary data transmitted within a display's serialized data stream | |
AU595437B2 (en) | Universal protocol data receiver | |
US6452927B1 (en) | Method and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer | |
US8464145B2 (en) | Serial interface devices, systems and methods | |
US20120030438A1 (en) | Method and Apparatus for Performing Skew Removal in the Receiver of a Multi-Lane Communication Link | |
US7480282B2 (en) | Methods and apparatus for controlling ethernet packet transfers between clock domains | |
JPH11252062A (en) | Method and device for effectively executing synchronization and cyclic redundancy check of signal in communication system | |
US7627806B1 (en) | Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device | |
US7321596B2 (en) | Packet control system and communication method | |
US9178692B1 (en) | Serial link training method and apparatus with deterministic latency | |
US8295161B2 (en) | Network apparatus that determines whether data is written into buffer based on detection of a memory error | |
US7571377B2 (en) | Method and apparatus for transmitting data in an integrated circuit | |
US6505321B1 (en) | Fault tolerant parity generation | |
US7327725B2 (en) | Method and apparatus capable of transferring very high data rates across a midplane or backplane | |
US6937624B1 (en) | System for manintaining inter-packet gaps in cascade transmission system for packet-based data | |
EP3671720B1 (en) | Real-time on-chip data transfer system | |
JPH0338943A (en) | Terminal adapter having many adlc communication channel receiver | |
KR20210032680A (en) | In-vehicle device and multimedia stream synchronization method thereof | |
JP3941096B2 (en) | Data transfer method in bus interface and bus interface | |
JPS59201556A (en) | Communication control system | |
JPH0784897A (en) | Information processing system suitable for data transfer between equipments | |
JPH09266472A (en) | Fault informing circuit | |
KR20000067248A (en) | Apparatus and method for controlling data transmission |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CONNOLLY, BRIAN JOHN;LEONARD, TODD EDWIN;REEL/FRAME:016935/0899;SIGNING DATES FROM 20051220 TO 20051221 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
SULP | Surcharge for late payment | ||
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20170804 |