US20070143755A1 - Speculative execution past a barrier - Google Patents
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- US20070143755A1 US20070143755A1 US11/305,506 US30550605A US2007143755A1 US 20070143755 A1 US20070143755 A1 US 20070143755A1 US 30550605 A US30550605 A US 30550605A US 2007143755 A1 US2007143755 A1 US 2007143755A1
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- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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Definitions
- Transactional support in hardware for lock-free shared data structures using transactional memory is described in M. Herlihy and J. Moss, Transactional memory: Architectural support for lock - free data structures , Proceedings of the 20 th Annual International Symposium on Computer Architecture 20, 1993 (Herlihy and Moss). This approach describes a set of extensions to existing multiprocessor cache coherence protocols that enable such lock free access. Transactions using a transactional memory are referred to as transactional memory transactions or lock free transactions herein.
- Barrier synchronization is a commonly used paradigm in multi-thread programming, such as for example in the OpenMP system. Barrier synchronization may also be used in other widely used concurrent programming systems including systems based on threads implemented in pthreads or Java.
- a barrier in a concurrent computation is a synchronization point shared by multiple threads or processes. For multiple threads to correctly execute past a barrier it is sufficient that each thread verifies that all other threads executing concurrently have reached the barrier.
- some predicate that is a prerequisite for continued correct execution of the multithreaded program is guaranteed to be true, and thus program execution can continue in all threads.
- a synchronization variable In general, a synchronization variable, often incorporating a counter, is used by threads to communicate to each other that they have reached a barrier.
- Mutually exclusive access to the barrier variable thus may force a serialization point at the barrier in a typical implementation, and a suspension of useful execution of each thread that has reached the barrier until all threads reach the barrier, thus potentially lowering performance.
- all threads reaching the barrier is a sufficient but not a necessary condition for correct execution of any other thread past the barrier, it may be possible in some instances for threads to correctly execute past the barrier even if all threads have not yet reached the barrier.
- FIG. 1 depicts a processor based system in one embodiment.
- FIG. 2 depicts processing in one embodiment.
- FIG. 1 depicts a processor based system that may include one or more processors 105 coupled to a bus 110 .
- the system may have a processor that is a multi-core processor, or in other instances, multiple multi-core processors.
- the bus 110 may be coupled to system memory 115 , storage devices such as disk drives or other storage devices 120 , peripheral devices 145 .
- the storage 120 may store various software or data.
- the system may be connected to a variety of peripheral devices 145 via one or more bus systems. Such peripheral devices may include displays and printing systems among many others as is known.
- a processor system such as that depicted in the figure adds a transactional memory system 100 that allows for the execution of lock free transactions with shared data structures cached in the transactional memory system, as described in Herlihy and Moss.
- the processor(s) 105 may then include an instruction set architecture that supports such lock free or transactional memory based transactions.
- the system in this embodiment supports a set of instructions, including an instruction to begin a transaction; an instruction to commit and terminate a transaction normally; and an instruction to abort a transaction.
- an instruction to begin a transaction Within a transaction all memory locations are accessed speculatively, and all memory updates are buffered.
- a cache coherence protocol indicates whether another thread is trying to access the same memory locations. If any conflicts are detected, an interrupt is generated that may be handled by an abort handler.
- the speculative updates become visible atomically. Transactional execution may also be terminated due to other reasons such as oversubscription of hardware resources, and other exceptions.
- the system of FIG. 1 is only an example and the present invention is not limited to any particular architecture. Variations on the specific components of the systems of other architectures may include the inclusion of transactional memory as a component of a processor or processors of the system in some instances; in others, it may be a separate component on a bus connected to the processor. In other embodiments, the system may have additional instructions to manage lock free transactions. The actual form or format of the instructions in other embodiments may vary. Additional memory or storage components may be present. A large number of other variations are possible.
- a code sequence like that shown below in Table 1 may be used to implement barrier synchronization.
- the operation lockedInc is a mutually exclusive increment operation that increments the field numberThreadsAtBarrier of the variable barrierObject which is a barrier synchronization variable shared by all threads, initially set to zero. Furthermore, the value of the field numberThreadsInTeam of the barrier variable is the number of threads in the multi-threaded computation. As may be seen from the code sequence above, each thread arriving at the barrier first increments the barrier variable, and then waits in a spin lock loop at lines 6 through 8, until all threads have reached the barrier.
- barrierObject->numberThreadsAtBarrier! barrierObject->numberThreadsInTeam becoming true, which is when every thread that is in the computation, has incremented the field numberThreadsAtBarrier and thus indicated that it has reached the barrier.
- the code sequence in Table 1 represents barrier synchronization, as typically implemented. As is well-known, such synchronization is expensive, because every thread needs to access the shared barrier variable, barrierObject, which must be accessed sequentially at least for increment, and moreover because each thread must sit and spin in a spin lock loop until all other threads have incremented the barrier variable.
- the processor may internally speculate past the check in barrierWait and execute program instructions speculatively following the barrier. During such speculation, the processor also ensures consistency; that is it makes sure no other processor or thread is accessing the same data that it has accessed. However, if all threads have not reached the barrier the speculation will trigger a branch mis-prediction exception in the out of order processor, causing all the speculative work to be discarded, and the processor will revert to spinning in the spinlock loop.
- a processor based system that supports transactional memory in hardware may be used to speculatively execute past a barrier using properties of instruction set architecture support for transactional memory. This enables speculative execution past a synchronization barrier in processors that do not have support for out of order execution. Even in processors that have support for out of order execution, this allows speculative execution of a multithreaded program past a barrier, without the risk of the out of order processor speculation being discarded as described above.
- FIG. 2 describes processing in one such embodiment.
- the processing implements a speculative barrier based on transactional memory, starting at 210 .
- the multithreaded program first checks, at 220 , if all threads have reached the barrier, for example by checking a barrier synchronization variable. Because this action is a read action, it need not be mutually exclusive. If all threads have already reached the barrier, there is no need for speculative execution and normal execution may continue at 230 until it terminates at 295 .
- the program proceeds to, begin a speculative execution, past the barrier, for this thread.
- the program invokes the instruction to begin a transactional memory based transaction provided by the architecture at 240 . It then speculatively executes the remaining portion of the program, 250 until it is interrupted by an external event that requires the attention of the transaction abort handler at 255 .
- This external event in one case is the exhaustion of hardware resources devoted to speculative execution in the transactional memory system. Because only a finite amount of hardware is available for transactional memory support and thus for speculative execution, this interrupt will eventually be generated.
- this interrupt is generated due to a data error in speculation, such as interference between threads that has caused the speculative execution to be compromised.
- the interrupt transfers control to the abort handler at 260 . It should be noted that the interrupt merely transfers control to the handler and there is neither an abort and roll back, or a commit of the transaction at this point.
- the abort handler then takes over at 270 . First, the handler determines the cause of the interrupt that invoked it. If the interrupting event was only the exhaustion of hardware resources dedicated to transactional memory, then no error that affects the correctness of the speculative computation has yet occurred.
- the handler checks if all threads have reached the barrier by reading the synchronization variable. If there are still threads that have not arrived at the barrier, the thread must wait in a spinlock loop at 280 because at this point either hardware resources for speculation may no longer be available, or a speculation related error may have occurred: that is, no further speculation is possible in any case.
- the transaction may then be committed at 290 , and normal execution may continue at 230 . At this point all previously speculative execution is no longer speculative, that is it becomes effective and its side effects visible to all other threads.
- the abort handler was invoked due to an event created by an actual error in speculation, such as an attempt by a different thread to write a variable that has already been read by this thread.
- the speculation needs to be rolled back. This is done by aborting the transaction at 285 and returning to the beginning of the process at 220 .
- the abort discards all speculative execution, because no commit action has occurred.
- the thread may retry a speculative execution once again at this point.
- FIG. 2 is merely that of one embodiment. Other embodiments may differ. Specific terms, for example, may differ in descriptions of other embodiments: the term thread may be replaced by “process,” the term program, by “computation,” the term “interrupt” by “trap” among many others as is known in the art. The flow of control depicted may be varied to obtain equivalent programs flows by an artisan in other embodiments. Many such variations are possible.
- Tables 1 and 2 list pseudocode used to implement speculative barriers as generally described above.
- non-transactional code first checks if other threads are left to enter. If that is so the spinlock loop at line 12 executes until the barrier is available. If at line 10, the code detects that it is the last thread to enter the barrier then it is done with its barrier wait and can proceed.
- the transactional phase of the code can begin. It may be noted that the code at lines 21 through 38 in Table 2 corresponds generally to blocks 220 - 260 from FIG. 2 . As in the non-transactional case, the code at line 23 first checks to see if other threads are left to enter the barrier. If there are such threads, then a speculative transaction begins.
- the BeginTransaction call at line 24 is a wrapper for an instruction provided by the transactional memory architecture underlying this implementation. In this embodiment, the BeginTransaction call yields a specific code TransactionStarted if it succeeds.
- the code stores information about this barrier in a memory location that is local to the executing thread, otherwise known in the literature as thread local storage (TLS). Specifically at lines 25 through 27, the code stores the fact that this particular thread has speculated past the barrier, a reference to the barrier variable, and a reference to the epoch to check if all threads have hit the barrier. It then returns at line 28, which means that the thread can now continue to execute speculatively until an abort occurs. On the other hand, at line 22, this function may find that it is the last thread to attempt to enter the barrier. Thus no speculative execution is necessary and the code may just return as in the normal, nonspeculative case at lines 36 through 38.
- TLS thread local storage
- Table 3 shows pseudocode for the abort handler in this embodiment, that operates in the context of transactional memory related events generated during transactions begun by the speculative transaction code from Table 2.
- the transactional memory hardware architecture transfers control to this handler when an event related to transactional memory that would need the attention of this handler has occurred.
- the event may be an exhaustion of the hardware resources allocated to supporting speculative execution or transactional memory resources in general; a data consistency error caused by a conflicting access by a different thread to a memory location to which this process has written or from which this process has read speculatively; or some other external error condition relating to transactional memory.
- the pseudocode in Table 3 corresponds generally to blocks 270 - 290 in FIG. 2 .
- the handler in Table 3 first determines, at line 3, whether the interrupt that transferred control to the handler was generated by hardware resource exhaustion or by another kind of error. If the event was caused by an error relating to the correctness of the speculative execution, such as a data consistency error, the test at line 3 is true and the handler aborts and rolls back the speculative execution at line 4 by aborting the transaction that was begun earlier. Otherwise, the speculative execution is successful, but now the handler needs to wait on the other threads to complete because it can no longer operate speculatively, as there are insufficient resources for further speculation.
- the handler recovers the references to the barrier and the epoch at lines 6 and 7 respectively, and then uses these to wait in the spin lock loop at line 8 until all the other threads are done. Once all threads have reached the barrier, the handler at line 9 then commits the transaction that this thread began, and all changes made speculatively are now effective and become visible atomically.
- the tables above are merely exemplary code fragments in one embodiment.
- the implementation language may be another language, e.g. C or Java; the variable names used may vary, and the names of all the functions defined or called may vary. Structure and logic of programs to accomplish the functions accomplished by the programs listed above may be arbitrarily varied, without changing the input and output relationship, as is known.
- a design of an embodiment that is implemented in a processor may go through various stages, from creation to simulation to fabrication.
- Data representing a design may represent the design in a number of manners.
- the hardware may be represented using a hardware description language or another functional description language.
- a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
- most designs, at some stage reach a level of data representing the physical placement of various devices in the hardware model.
- data representing a hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
- the data may be stored in any form of a machine-readable medium.
- An optical or electrical wave modulated or otherwise generated to transmit such information, a memory, or a magnetic or optical storage such as a disc may be the machine readable medium. Any of these mediums may “carry” or “indicate” the design or software information.
- an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made.
- a communication provider or a network provider may make copies of an article (a carrier wave) that constitute or represent an embodiment.
- Embodiments may be provided as a program product that may include a machine-readable medium having stored thereon data which when accessed by a machine may cause the machine to perform a process according to the claimed subject matter.
- the machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, DVD-ROM disks, DVD-RAM disks, DVD-RW disks, DVD+RW disks, CD-R disks, CD-RW disks, CD-ROM disks, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media machine-readable medium suitable for storing electronic instructions.
- embodiments may also be downloaded as a program product, wherein the program may be transferred from a remote data source to a requesting device by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).
- a communication link e.g., a modem or network connection
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US11/305,506 US20070143755A1 (en) | 2005-12-16 | 2005-12-16 | Speculative execution past a barrier |
CN2006800471997A CN101331456B (zh) | 2005-12-16 | 2006-12-06 | 用于多线程程序的方法和设备 |
EP06845165A EP1960880A1 (de) | 2005-12-16 | 2006-12-06 | Spekulative ausführung nach einer sperre |
PCT/US2006/047141 WO2007075313A1 (en) | 2005-12-16 | 2006-12-06 | Speculative execution past a barrier |
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WO2007075313A1 (en) | 2007-07-05 |
EP1960880A1 (de) | 2008-08-27 |
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