US20070131982A1 - Memory cell structure and method for fabricating the same - Google Patents
Memory cell structure and method for fabricating the same Download PDFInfo
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- US20070131982A1 US20070131982A1 US11/298,836 US29883605A US2007131982A1 US 20070131982 A1 US20070131982 A1 US 20070131982A1 US 29883605 A US29883605 A US 29883605A US 2007131982 A1 US2007131982 A1 US 2007131982A1
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- 238000000034 method Methods 0.000 title claims description 53
- 125000006850 spacer group Chemical group 0.000 claims abstract description 86
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 79
- 229920005591 polysilicon Polymers 0.000 claims abstract description 79
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
Definitions
- the present invention relates to a memory cell structure and method for fabricating the same, and more particularly, to memory cell structure having a transistor with source and drain positioned on a semiconductor substrate and the method for fabricating the same.
- FIG. 1 illustrates a semiconductor transistor structure according to a prior art.
- the semiconductor transistor structure comprises a gate structure positioned on a semiconductor substrate 100 , which has an isolation device 102 to isolate the transistors on the semiconductor substrate 100 .
- the gate structure comprises a gate oxide layer 104 positioned on the semiconductor substrate 104 , a polysilicon gate 106 positioned on the gate oxide layer 104 , and a nitride layer 108 positioned on the polysilicon gate 106 .
- Spacers 112 are positioned on the sidewalls of the gate structure.
- Lightly doped drain (LDD) regions 110 are positioned in the semiconductor substrate 100 , and a source/drain 114 is positioned in the semiconductor substrate 100 and nearby in the LDD regions 110 .
- the semiconductor transistor structure further comprises an oxide layer 116 positioned on the semiconductor substrate 100 , and contacts 118 in the oxide layer 116 .
- LDD Lightly doped drain
- the conventional dynamic random access memory structure can no longer meet the requirements of junction leakage current and subthreshold leakage current.
- the subthreshold leakage current can be reduced by increasing the channel doping concentration up to 4 ⁇ 10 18 cm ⁇ 3 , the junction leakage current will increase dramatically as a result of tunneling current between band to band.
- the objective of the present invention is to provide a memory cell structure having conductive polysilicon blocks serving as source and drain, which are positioned on a semiconductor substrate rather than in the semiconductor substrate and electrically connected to a carrier channel in the semiconductor substrate via conductive spacers on sidewalls of the conductive polysilicon blocks to avoid the junction leakage current and the short channel effect.
- one embodiment of the present invention discloses a memory cell structure comprising a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers on the sidewalls of the two stack structures and a gate structure positioned at least on the gate oxide layer.
- each of the stack structures includes a first oxide block, a conductive block made of doped polysilicon and a second oxide block.
- the conductive spacers on the sidewalls of the two stack structures are preferably made of polysilicon, and have a top end even with or lower than the bottom surface of the second oxide block.
- the conductive spacers could be an L-shaped profile, while a dielectric spacer is further positioned on the corner of the L-shaped conductive spacer, and the gate oxide layer is formed at least on the exposed conductive spacers and the exposed semiconductor substrate uncovered by the dielectric spacer.
- the semiconductor substrate preferably has a recess between the conductive spacers on the sidewalls of the two stack structures, and the gate oxide layer covers the surface of the semiconductor substrate in the recess.
- the method for fabricating a memory cell structure comprises steps of forming two stack structures separated by an opening, and each of the two stack structure has a first oxide block, a conductive block and a second oxide block on a semiconductor substrate, forming two conductive spacers on sidewalls of the two stack structures, forming a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers on the sidewalls of the two stack structures and forming a gate structure positioned at least on the gate oxide layer.
- the conductive spacers are prepared by depositing a polysilicon layer on the semiconductor substrate and performing an anisotropic etching process to remove a portion of the polysilicon layer.
- the conductive spacers can be prepared by depositing a polysilicon layer on the semiconductor substrate, forming a dielectric spacer on a predetermined surface of the polysilicon layer, and removing a portion of the exposed polysilicon layer uncovered by the dielectric spacer to form the conductive spacers having an L-shaped profile.
- FIG. 1 illustrates a semiconductor transistor structure according to a prior art
- FIG. 2 to FIG. 7 illustrate a method for fabricating a memory cell structure according to one embodiment of the present invention
- FIG. 8 to FIG. 9 illustrate a method for fabricating a memory cell structure according to another embodiment of the present invention.
- FIG. 10 illustrates a method for fabricating a memory cell structure according to another embodiment of the present invention.
- FIG. 11 and FIG. 12 illustrate a method for fabricating a memory cell structure according to another embodiment of the present invention.
- FIG. 13 to FIG. 15 illustrate a method for fabricating a memory cell structure according to another embodiment of the present invention.
- FIG. 2 to FIG. 7 illustrate a method for fabricating a memory cell structure 50 according to one embodiment of the present invention.
- a first oxide layer 12 is formed on a semiconductor substrate 10 such as a silicon substrate having a cell region 10 A and a peripheral region 10 B, a doped polysilicon layer 14 is then formed on the first oxide layer 12 , and a second oxide layer 16 is formed on the doped polysilicon layer 14 .
- a first photoresist layer (not shown in the drawing) is formed on the second oxide layer 16 , and an etching process is performed to remove a portion of the second oxide layer 16 , the doped polysilicon layer 14 and the first oxide layer 12 in the peripheral region 10 B down to the surface of the semiconductor substrate 10 .
- a silicon layer 18 is then formed on the semiconductor substrate 10 in the peripheral region 10 B by an epitaxy process, and the upper surface of the silicon layer 18 in the peripheral region 10 B is aligned with or slightly lower than the surface of the second oxide layer 16 in the cell region 10 A.
- a third photoresist layer having shallow trench isolation patterns (not shown in the drawing) is formed on the semiconductor substrate 10 , and an etching process is then performed to form a first opening (not shown in the drawing) between the cell region 10 A and peripheral region 10 B by removing a portion of the second oxide layer 16 , the doped polysilicon layer 14 and the first oxide layer 12 in the cell region 10 A, a portion of the silicon layer 18 in the peripheral region 10 B and a portion of the semiconductor substrate 10 . Subsequently, the first opening is filled with silicon oxide to form a shallow trench isolation structure 20 , which is used as an isolation device for the memory structure.
- a fourth photoresist layer (not shown in the drawing) is formed in the cell region 10 A, and an etching process is then performed to form a second opening 22 by removing a portion of the second oxide layer 16 , the doped polysilicon layer 14 and the first oxide layer 12 so as to form two stack structures 11 each including a first oxide block 12 A, a conductive block 14 A and a second oxide block 16 A.
- the second opening 22 separates the two stack structures 11 and exposes a portion of the semiconductor substrate 10 and the sidewalls of the two stack structures 11 .
- a polysilicon layer is formed in the second opening 22 by deposition process, and an anisotropic etching process is performed to remove a portion of the polysilicon layer to form two polysilicon spacers 24 on the sidewalls of the two stack structures 11 .
- a thermal oxidation process is performed to form a gate oxide layer 26 on the exposed surface of the semiconductor substrate 10 between the two polysilicon spacers 24 and on the surface of the polysilicon spacers 24 in the cell region 10 A and on the surface of the silicon layer 18 in the peripheral region 10 B.
- the gate oxide layer 26 in the second opening 22 in the cell region 10 A covers the two polysilicon spacers 24 and the semiconductor substrate 10 between the two polysilicon spacers 24 .
- a polysilicon layer 28 is then formed on the gate oxide layer 26 and on the second oxide block 16 A, and a nitride layer 30 and a third oxide layer 32 are formed on the polysilicon layer 28 in sequence.
- a fifth photoresist layer having a first gate pattern and a second gate pattern (not shown in the drawing) is formed on the third oxide layer 32 , and an etching process is then performed to form a first gate structure in the cell region 10 A and a second gate structure in the peripheral region 10 B.
- the first gate structure is formed by etching the third oxide layer 32 , the first nitride layer 30 and the polysilicon layer 28 , and using the second oxide block 16 A as an etch stop layer;
- the second gate structure in the peripheral region 10 B is formed by etching the third oxide layer 32 , the first nitride layer 30 and the polysilicon layer 28 , and using the gate oxide layer 26 as an etch stop layer.
- the second gate structure is used as a mask, and ions are implanted into the semiconductor substrate 10 in the peripheral region 10 B to form LDD regions 34 .
- a second nitride layer is formed on the semiconductor substrate 10 , and an etching process is then performed to remove a portion of the second nitride layer to form two nitride spacers 36 on sidewalls of the first gate structure and the second gate structure. Ions are then implanted into the semiconductor substrate 10 in the peripheral region 10 B to form source/drain regions 38 nearby the LDD regions 34 . As shown in FIG.
- a dielectric layer 40 is formed on the semiconductor substrate 10 , and contact structure 42 is formed in the dielectric layer 40 near the first gate structure to electrically connect the conductive block 14 A serving as a source and a drain to devices subsequently formed in an upper layer.
- FIG. 8 and FIG. 9 illustrate a method for fabricating a memory cell structure 60 according to another embodiment of the present invention.
- the fabrication process of the memory cell structure 60 (as shown in FIGS. 8 and 9 ) also forms the two polysilicon spacers 24 ′ on the sidewalls of the two stack structures 11 but increases the etching time of the etch process so that the top end of the two polysilicon spacers 24 ′ is lower than the bottom surface of the second oxide block 16 A, as shown in FIG. 8 .
- the top end of the two polysilicon spacers 24 ′ is even with or lower than the bottom surface of the second oxide block 16 A to prevent short circuit between the two polysilicon spacers 24 ′ and the polysilicon layer 28 .
- the same fabricating processes shown in FIG. 6 and FIG. 7 are performed to complete the memory cell structure 60 , as shown in FIG. 9 .
- FIG. 10 illustrate a method for fabricating a memory cell structure 60 ′ according to another embodiment of the present invention.
- two dielectric spacers 62 are formed on the polysilicon spacers 24 ′ before the gate oxide layer 26 is formed so as to enhance the insulation between the polysilicon spacers 24 ′ and the polysilicon layer 28 , as shown in FIG. 10 .
- the dielectric spacers 62 is formed in the second opening 22 by deposition a dielectric layer and an anisotropic etching process is performed to remove a portion of the dielectric layer to form the dielectric spacers 62 covering the surfaces of the two polysilicon spacers 24 ′.
- FIG. 11 and FIG. 12 illustrate a method for fabricating a memory cell structure 70 according to another embodiment of the present invention.
- an etching process is performed to etch a portion of the semiconductor substrate 10 between the two polysilicon spacers 24 ′ to form a recess 72 in the semiconductor substrate 10 , and the gate oxide layer 26 is then formed on the surface of the recess 72 in the semiconductor substrate 10 and on the polysilicon spacers 24 ′ in the cell region 10 A and on the surface of the silicon layer 18 in the peripheral region 10 B.
- the total length of the channel 44 consists of not only the lateral width of the recess 72 but also the vertical depth of the recess 72 .
- the transistor in the memory cell structure 70 possesses a longer channel length.
- FIG. 13 to FIG. 15 illustrate a method for fabricating a memory cell structure 80 according to another embodiment of the present invention.
- the fabrication process of the memory cell structure 80 further includes a step of forming a polysilicon layer 82 on the semiconductor substrate 10 and two dielectric spacers 84 having a conventional spacer shape on the polysilicon layer 82 in the second opening 22 , as shown in FIG. 13 .
- An etching process is then performed using the two dielectric spacers 84 as an etching mask to remove a portion of the polysilicon layer 82 uncovered by the two dielectric spacers 84 and above a predetermined height “H” to form two polysilicon spacers 86 having an L-shaped profile on the sidewalls of the two stack structure 11 , as shown in FIG. 14 .
- a portion of the polysilicon layer above a top end of the dielectric spacer 84 is removed by the etching process so that the top end of the two polysilicon spacers 86 is even with or lower than the bottom surface of the second oxide block 16 A.
- the same fabricating processes shown in FIG. 6 and FIG. 7 are performed to complete the memory cell structure 80 , as shown in FIG. 15 .
- the two polysilicon spacers 24 can be made of doped polysilicon or non-doped polysilicon.
- the conductive block 14 A of the stack structure 11 is made of doped polysilicon, and dopants in the conductive blocks 14 A serving as source and drain will diffuse into the polysilicon spacer 24 and the semiconductor substrate 10 in the subsequent thermal process.
- the polysilicon spacer 24 is also made of doped polysilicon. Consequently, the polysilicon block 14 A serves as a source and drain region, and the first oxide block 12 A can be regarded as a buried isolation between the polysilicon block 14 A and the semiconductor substrate 10 .
- the polysilicon spacer 24 is used to electrically connect the conductive polysilicon blocks 14 A to the channel 44 in the semiconductor substrate 10 , and therefore the junction does not exist between the polysilicon block 14 A (the source and the drain) and the semiconductor substrate 10 due to isolation of the first oxide block 12 A.
- the junction is formed only at a small area in the semiconductor substrate 10 right below the polysilicon spacer 24 , i.e., the lateral width of the junction of the present invention is substantially the same as the lateral width of the polysilicon spacer 24 , which much smaller than the lateral width of the junction consisting of the LDD regions 110 and source/drain 114 in the semiconductor substrate 100 (as shown in FIG. 1 ), and therefore the junction leakage current can be dramatically reduced.
- the short-channel effect depends on the junction depth below the polysilicon spacers 24 , and the junction depth further depends on the diffusion of dopants from the polysilicon spacer 24 or the conductive polysilicon block 14 A into the semiconductor substrate 10 right below the polysilicon spacer 24 .
- the junction depth depends on the dopants diffused from the polysilicon spacer 24 or the conductive polysilicon block 14 A into the small area in the semiconductor substrate 10 during the subsequent thermal processes.
- the junction depth formed by the diffusion of the dopants from the polysilicon spacer 24 is generally very shallow according to the embodiment of the present invention.
- the junction depth in the conventional technology is controlled by both the implanting energy and the diffusion of the implanted dopants, which generally form a deep junction in the semiconductor substrate.
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Abstract
Description
- (A) Field of the Invention
- The present invention relates to a memory cell structure and method for fabricating the same, and more particularly, to memory cell structure having a transistor with source and drain positioned on a semiconductor substrate and the method for fabricating the same.
- (B) Description of the Related Art
-
FIG. 1 illustrates a semiconductor transistor structure according to a prior art. The semiconductor transistor structure comprises a gate structure positioned on asemiconductor substrate 100, which has an isolation device 102 to isolate the transistors on thesemiconductor substrate 100. The gate structure comprises agate oxide layer 104 positioned on thesemiconductor substrate 104, apolysilicon gate 106 positioned on thegate oxide layer 104, and anitride layer 108 positioned on thepolysilicon gate 106.Spacers 112 are positioned on the sidewalls of the gate structure. Lightly doped drain (LDD)regions 110 are positioned in thesemiconductor substrate 100, and a source/drain 114 is positioned in thesemiconductor substrate 100 and nearby in theLDD regions 110. In addition, the semiconductor transistor structure further comprises anoxide layer 116 positioned on thesemiconductor substrate 100, andcontacts 118 in theoxide layer 116. - As semiconductor transistor structures become smaller, the conventional dynamic random access memory structure can no longer meet the requirements of junction leakage current and subthreshold leakage current. Although the subthreshold leakage current can be reduced by increasing the channel doping concentration up to 4×1018 cm−3, the junction leakage current will increase dramatically as a result of tunneling current between band to band.
- The objective of the present invention is to provide a memory cell structure having conductive polysilicon blocks serving as source and drain, which are positioned on a semiconductor substrate rather than in the semiconductor substrate and electrically connected to a carrier channel in the semiconductor substrate via conductive spacers on sidewalls of the conductive polysilicon blocks to avoid the junction leakage current and the short channel effect.
- In order to achieve the above-mentioned objective and avoid the problems of the prior art, one embodiment of the present invention discloses a memory cell structure comprising a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers on the sidewalls of the two stack structures and a gate structure positioned at least on the gate oxide layer. Particularly, each of the stack structures includes a first oxide block, a conductive block made of doped polysilicon and a second oxide block.
- The conductive spacers on the sidewalls of the two stack structures are preferably made of polysilicon, and have a top end even with or lower than the bottom surface of the second oxide block. In addition, the conductive spacers could be an L-shaped profile, while a dielectric spacer is further positioned on the corner of the L-shaped conductive spacer, and the gate oxide layer is formed at least on the exposed conductive spacers and the exposed semiconductor substrate uncovered by the dielectric spacer. Further, the semiconductor substrate preferably has a recess between the conductive spacers on the sidewalls of the two stack structures, and the gate oxide layer covers the surface of the semiconductor substrate in the recess.
- The method for fabricating a memory cell structure comprises steps of forming two stack structures separated by an opening, and each of the two stack structure has a first oxide block, a conductive block and a second oxide block on a semiconductor substrate, forming two conductive spacers on sidewalls of the two stack structures, forming a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers on the sidewalls of the two stack structures and forming a gate structure positioned at least on the gate oxide layer. Preferably, the conductive spacers are prepared by depositing a polysilicon layer on the semiconductor substrate and performing an anisotropic etching process to remove a portion of the polysilicon layer. In addition, the conductive spacers can be prepared by depositing a polysilicon layer on the semiconductor substrate, forming a dielectric spacer on a predetermined surface of the polysilicon layer, and removing a portion of the exposed polysilicon layer uncovered by the dielectric spacer to form the conductive spacers having an L-shaped profile.
- The objectives and advantages of the present invention will become apparent upon reading the following description and upon reference to the accompanying drawings in which:
-
FIG. 1 illustrates a semiconductor transistor structure according to a prior art; -
FIG. 2 toFIG. 7 illustrate a method for fabricating a memory cell structure according to one embodiment of the present invention; -
FIG. 8 toFIG. 9 illustrate a method for fabricating a memory cell structure according to another embodiment of the present invention; -
FIG. 10 illustrates a method for fabricating a memory cell structure according to another embodiment of the present invention; -
FIG. 11 andFIG. 12 illustrate a method for fabricating a memory cell structure according to another embodiment of the present invention; and -
FIG. 13 toFIG. 15 illustrate a method for fabricating a memory cell structure according to another embodiment of the present invention. -
FIG. 2 toFIG. 7 illustrate a method for fabricating amemory cell structure 50 according to one embodiment of the present invention. Afirst oxide layer 12 is formed on asemiconductor substrate 10 such as a silicon substrate having acell region 10A and aperipheral region 10B, adoped polysilicon layer 14 is then formed on thefirst oxide layer 12, and asecond oxide layer 16 is formed on thedoped polysilicon layer 14. Subsequently, a first photoresist layer (not shown in the drawing) is formed on thesecond oxide layer 16, and an etching process is performed to remove a portion of thesecond oxide layer 16, thedoped polysilicon layer 14 and thefirst oxide layer 12 in theperipheral region 10B down to the surface of thesemiconductor substrate 10. - Referring to
FIG. 3 , asilicon layer 18 is then formed on thesemiconductor substrate 10 in theperipheral region 10B by an epitaxy process, and the upper surface of thesilicon layer 18 in theperipheral region 10B is aligned with or slightly lower than the surface of thesecond oxide layer 16 in thecell region 10A. - Referring to
FIG. 4 , a third photoresist layer having shallow trench isolation patterns (not shown in the drawing) is formed on thesemiconductor substrate 10, and an etching process is then performed to form a first opening (not shown in the drawing) between thecell region 10A andperipheral region 10B by removing a portion of thesecond oxide layer 16, the dopedpolysilicon layer 14 and thefirst oxide layer 12 in thecell region 10A, a portion of thesilicon layer 18 in theperipheral region 10B and a portion of thesemiconductor substrate 10. Subsequently, the first opening is filled with silicon oxide to form a shallowtrench isolation structure 20, which is used as an isolation device for the memory structure. - Referring to
FIG. 5 , a fourth photoresist layer (not shown in the drawing) is formed in thecell region 10A, and an etching process is then performed to form asecond opening 22 by removing a portion of thesecond oxide layer 16, the dopedpolysilicon layer 14 and thefirst oxide layer 12 so as to form two stack structures 11 each including afirst oxide block 12A, a conductive block 14A and asecond oxide block 16A. Thesecond opening 22 separates the two stack structures 11 and exposes a portion of thesemiconductor substrate 10 and the sidewalls of the two stack structures 11. Subsequently, a polysilicon layer is formed in thesecond opening 22 by deposition process, and an anisotropic etching process is performed to remove a portion of the polysilicon layer to form twopolysilicon spacers 24 on the sidewalls of the two stack structures 11. - Referring to
FIG. 6 , a thermal oxidation process is performed to form agate oxide layer 26 on the exposed surface of thesemiconductor substrate 10 between the twopolysilicon spacers 24 and on the surface of thepolysilicon spacers 24 in thecell region 10A and on the surface of thesilicon layer 18 in theperipheral region 10B. Particularly, thegate oxide layer 26 in thesecond opening 22 in thecell region 10A covers the twopolysilicon spacers 24 and thesemiconductor substrate 10 between the twopolysilicon spacers 24. Apolysilicon layer 28 is then formed on thegate oxide layer 26 and on thesecond oxide block 16A, and anitride layer 30 and athird oxide layer 32 are formed on thepolysilicon layer 28 in sequence. - Subsequently, a fifth photoresist layer having a first gate pattern and a second gate pattern (not shown in the drawing) is formed on the
third oxide layer 32, and an etching process is then performed to form a first gate structure in thecell region 10A and a second gate structure in theperipheral region 10B. Particularly, the first gate structure is formed by etching thethird oxide layer 32, thefirst nitride layer 30 and thepolysilicon layer 28, and using thesecond oxide block 16A as an etch stop layer; the second gate structure in theperipheral region 10B is formed by etching thethird oxide layer 32, thefirst nitride layer 30 and thepolysilicon layer 28, and using thegate oxide layer 26 as an etch stop layer. - The second gate structure is used as a mask, and ions are implanted into the
semiconductor substrate 10 in theperipheral region 10B to formLDD regions 34. Subsequently, a second nitride layer is formed on thesemiconductor substrate 10, and an etching process is then performed to remove a portion of the second nitride layer to form twonitride spacers 36 on sidewalls of the first gate structure and the second gate structure. Ions are then implanted into thesemiconductor substrate 10 in theperipheral region 10B to form source/drain regions 38 nearby theLDD regions 34. As shown inFIG. 7 , adielectric layer 40 is formed on thesemiconductor substrate 10, andcontact structure 42 is formed in thedielectric layer 40 near the first gate structure to electrically connect the conductive block 14A serving as a source and a drain to devices subsequently formed in an upper layer. -
FIG. 8 andFIG. 9 illustrate a method for fabricating amemory cell structure 60 according to another embodiment of the present invention. Compared to the fabrication process of the memory cell structure 40 (as shown inFIG. 5 ) forming the twopolysilicon spacers 24 on the sidewalls of the two stack structures 11, the fabrication process of the memory cell structure 60 (as shown inFIGS. 8 and 9 ) also forms the twopolysilicon spacers 24′ on the sidewalls of the two stack structures 11 but increases the etching time of the etch process so that the top end of the twopolysilicon spacers 24′ is lower than the bottom surface of thesecond oxide block 16A, as shown inFIG. 8 . Preferably, the top end of the twopolysilicon spacers 24′ is even with or lower than the bottom surface of thesecond oxide block 16A to prevent short circuit between the twopolysilicon spacers 24′ and thepolysilicon layer 28. Subsequently, the same fabricating processes shown inFIG. 6 andFIG. 7 are performed to complete thememory cell structure 60, as shown inFIG. 9 . -
FIG. 10 illustrate a method for fabricating amemory cell structure 60′ according to another embodiment of the present invention. Compared to the fabrication process shown in theFIGS. 8 and 9 , twodielectric spacers 62 are formed on thepolysilicon spacers 24′ before thegate oxide layer 26 is formed so as to enhance the insulation between thepolysilicon spacers 24′ and thepolysilicon layer 28, as shown inFIG. 10 . Preferably, thedielectric spacers 62 is formed in thesecond opening 22 by deposition a dielectric layer and an anisotropic etching process is performed to remove a portion of the dielectric layer to form thedielectric spacers 62 covering the surfaces of the twopolysilicon spacers 24′. -
FIG. 11 andFIG. 12 illustrate a method for fabricating amemory cell structure 70 according to another embodiment of the present invention. After the twopolysilicon spacers 24′ are formed on the sidewalls of the two stack structure 11 as shown inFIG. 8 , an etching process is performed to etch a portion of thesemiconductor substrate 10 between the twopolysilicon spacers 24′ to form arecess 72 in thesemiconductor substrate 10, and thegate oxide layer 26 is then formed on the surface of therecess 72 in thesemiconductor substrate 10 and on thepolysilicon spacers 24′ in thecell region 10A and on the surface of thesilicon layer 18 in theperipheral region 10B. Subsequently, the same fabricating processes shown inFIG. 6 andFIG. 7 are performed to complete thememory cell structure 70, as shown inFIG. 12 . Particularly, the total length of thechannel 44 consists of not only the lateral width of therecess 72 but also the vertical depth of therecess 72. As a result, the transistor in thememory cell structure 70 possesses a longer channel length. -
FIG. 13 toFIG. 15 illustrate a method for fabricating amemory cell structure 80 according to another embodiment of the present invention. Compared to the fabrication process of thememory cell structure 40 formingpolysilicon spacers 24 on the sidewall of the stack structure 11 (as shown inFIG. 5 ), the fabrication process of thememory cell structure 80 further includes a step of forming apolysilicon layer 82 on thesemiconductor substrate 10 and twodielectric spacers 84 having a conventional spacer shape on thepolysilicon layer 82 in thesecond opening 22, as shown inFIG. 13 . An etching process is then performed using the twodielectric spacers 84 as an etching mask to remove a portion of thepolysilicon layer 82 uncovered by the twodielectric spacers 84 and above a predetermined height “H” to form twopolysilicon spacers 86 having an L-shaped profile on the sidewalls of the two stack structure 11, as shown inFIG. 14 . Preferably, a portion of the polysilicon layer above a top end of thedielectric spacer 84 is removed by the etching process so that the top end of the twopolysilicon spacers 86 is even with or lower than the bottom surface of thesecond oxide block 16A. Subsequently, the same fabricating processes shown inFIG. 6 andFIG. 7 are performed to complete thememory cell structure 80, as shown inFIG. 15 . - Particularly, the two polysilicon spacers 24 (functional equivalent to the
polysilicon spacer 24′ and the polysilicon spacer 86) can be made of doped polysilicon or non-doped polysilicon. In the case that the conductive block 14A of the stack structure 11 is made of doped polysilicon, and dopants in the conductive blocks 14A serving as source and drain will diffuse into thepolysilicon spacer 24 and thesemiconductor substrate 10 in the subsequent thermal process. Preferably, thepolysilicon spacer 24 is also made of doped polysilicon. Consequently, the polysilicon block 14A serves as a source and drain region, and thefirst oxide block 12A can be regarded as a buried isolation between the polysilicon block 14A and thesemiconductor substrate 10. - In addition, the
polysilicon spacer 24 is used to electrically connect the conductive polysilicon blocks 14A to thechannel 44 in thesemiconductor substrate 10, and therefore the junction does not exist between the polysilicon block 14A (the source and the drain) and thesemiconductor substrate 10 due to isolation of thefirst oxide block 12A. In other words, the junction is formed only at a small area in thesemiconductor substrate 10 right below thepolysilicon spacer 24, i.e., the lateral width of the junction of the present invention is substantially the same as the lateral width of thepolysilicon spacer 24, which much smaller than the lateral width of the junction consisting of theLDD regions 110 and source/drain 114 in the semiconductor substrate 100 (as shown inFIG. 1 ), and therefore the junction leakage current can be dramatically reduced. - Further, the short-channel effect depends on the junction depth below the
polysilicon spacers 24, and the junction depth further depends on the diffusion of dopants from thepolysilicon spacer 24 or the conductive polysilicon block 14A into thesemiconductor substrate 10 right below thepolysilicon spacer 24. In other words, the junction depth depends on the dopants diffused from thepolysilicon spacer 24 or the conductive polysilicon block 14A into the small area in thesemiconductor substrate 10 during the subsequent thermal processes. As a result, the junction depth formed by the diffusion of the dopants from thepolysilicon spacer 24 is generally very shallow according to the embodiment of the present invention. Conversely, the junction depth in the conventional technology is controlled by both the implanting energy and the diffusion of the implanted dopants, which generally form a deep junction in the semiconductor substrate. - The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.
Claims (18)
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US10720444B2 (en) | 2018-08-20 | 2020-07-21 | Sandisk Technologies Llc | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same |
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US20050224860A1 (en) * | 2002-06-20 | 2005-10-13 | Koninklijke Philips Electronics N.V. | Conductive spacers extended floating gates |
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US6869849B2 (en) * | 2000-10-25 | 2005-03-22 | Nec Electronics Corporation | Semiconductor device and its manufacturing method |
US7045852B2 (en) * | 2002-05-08 | 2006-05-16 | Koninklijke Philips Electronics N.V. | Floating gate memory cells with increased coupling radio |
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US10720444B2 (en) | 2018-08-20 | 2020-07-21 | Sandisk Technologies Llc | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same |
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