US20070075400A1 - Semiconductor device with a toroidal-like junction - Google Patents
Semiconductor device with a toroidal-like junction Download PDFInfo
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- US20070075400A1 US20070075400A1 US11/539,845 US53984506A US2007075400A1 US 20070075400 A1 US20070075400 A1 US 20070075400A1 US 53984506 A US53984506 A US 53984506A US 2007075400 A1 US2007075400 A1 US 2007075400A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Definitions
- This invention relates generally to a process for fabricating an integrated circuit structure, and more specifically to electronic devices having semiconductor junctions and to a process for their manufacture.
- limit-of-resolution L r
- level-to-level alignment accuracy L r
- depth-of-focus throughput
- Typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, ⁇ , and geometrical configurations of the projection system optics.
- L r 0.61 ⁇ ⁇ NA
- n the index of refraction of the medium which the radiation traverses (usually air for this application, so n ⁇ 1)
- ⁇ is a half-angle of the divergence of the actinic radiation.
- DUV deep ultraviolet illumination
- Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks.
- an emitter window is directly opened without some means of providing an etch stop. This overetch produces a damaged region in the silicon and may result in excessive consumption of silicon underlying the contact. Further, formation of an oxide spacer without an etch stop presents manufacturing difficulties as timing and other recipe tolerances become overly stringent.
- Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate.
- Vertical npn transistors are much used in the integrated circuit art. Accordingly, improved means and methods for their formation, which are not limited by constraints of photolithography, have great utility and importance.
- the conductivity types shown herein may be reversed if it is desired to form a vertical pnp transistor on an N-type substrate. Additionally, the same techniques may be used to fabricate other types of devices. For example, a gate-source junction (as well as other device junction types) may be fabricated using the methods described herein.
- the present invention includes a method of fabricating an electronic device comprising forming a slot region for a doped polycrystalline silicon plug material within an outer periphery of an etched window region.
- the window region is formed by etching a film stack residing on a topmost surface of a semiconductor substrate having a p-type conductivity.
- the slot region is then filled with the polycrystalline silicon plug material, followed by depositing a dielectric separation layer over the polycrystalline silicon plug material.
- a dopant for example, boron, is implanted into a limited area of the substrate located within a region circumscribed by the slot region.
- a temporary spacer e.g., an oxide spacer
- the temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer.
- the boot shape is indicative of a projection of a dielectric layer extending radially inward (see FIG. 15 , element 1501 ).
- An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Therefore, level-to-level alignment issues with multiple masks are eliminated. Additionally, feature sizes are also determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated. Thus, limit-of-resolution and depth-of-focus are unimportant parameters.
- the dopant from a lower edge of the polycrystalline silicon plug is driven into the substrate, forming a toroidal-like junction with low capacitance.
- the toroidal-like junction in three-dimensions, is similar to a toroid shape but radial symmetry is not necessary.
- a toroid is a surface generated by a plane-closed curve rotated about a line that lies in the same plane as the curve but does not intersect it.
- the toroidal-like junction of the present invention may take a form of a closed shape not necessarily rotated equidistantly from an imaginary line.
- any remaining film layers within a region substantially circumscribed by the dielectric boot are etched down to the topmost surface of the substrate; and an emitter polycrystalline silicon layer is deposited.
- the present invention is also an electronic device.
- the electronic device comprises a semiconductor substrate having thereon at least one region laterally enclosed by a dielectric isolation region and coupled to a principal surface of the substrate.
- a polycrystalline silicon plug region is peripherally disposed on an outermost boundary of the dielectric isolation region and coupled to the dielectric isolation region.
- the polycrystalline silicon plug region is further electrically coupled to the semiconductor substrate.
- a doped region extends from the polycrystalline silicon plug region distally into the substrate and is electrically coupled to said polycrystalline silicon plug region.
- a doping concentration of the doped region has a toroidal-like topology.
- FIG. 1 shows an exemplary embodiment of a schematic cross-sectional view of deposited films used to create an electronic device structure.
- FIG. 2 shows the deposited films of FIG. 1 with an etched dielectric area 201 .
- FIG. 4 shows the third nitride layer of FIG. 3 anisotropically etched.
- FIG. 5 shows a thermally grown oxide within the confines created by the etched nitride layer of FIG. 4 .
- FIG. 6 shows the device structure of FIG. 5 with the etched nitride layer removed.
- FIG. 7 shows etched films defining an etched poly slot.
- FIG. 8 shows a conformally deposited poly plug layer filling the poly plug slot of FIG. 7 with a doped polycrystalline silicon.
- FIG. 9 shows the poly plug layer of FIG. 8 anisotropically etched to form an etched poly plug.
- FIG. 10 shows an emitter window formed by etching through a central portion of a first nitride layer first shown in FIG. 1 .
- FIG. 11 shows a nitride layer conformally deposited into the emitter window of FIG. 10 .
- FIG. 12 shows a boron diffusion through the nitride layer of FIG. 11 .
- FIG. 13 shows a deposited conformal oxide spacer deposited over the nitride layer of FIG. 12 .
- FIG. 14 shows the oxide spacer of FIG. 13 after etching.
- FIG. 15 shows the emitter window of FIG. 10 opened further by anisotropic etching of the nitride layer of FIG. 11 .
- FIG. 16 shows a toroidal-like topology formed from a redistributed dopant from the poly plug of FIG. 9 formed during an implant anneal.
- FIG. 17 shows electronic device structure after an etch of the oxide spacer of FIG. 14 .
- FIG. 18 shows the electronic device structure of FIG. 17 after a ramped poly emitter is conformally applied.
- FIG. 1 shows an exemplary embodiment of a cross-sectional view of deposited films used to form an electronic device structure. Each film layer is deposited in compliance with process steps that are well-known in the semiconductor art.
- FIG. 1 includes a base substrate 101 , a pad oxide 103 , a first nitride layer 105 , a first polycrystalline silicon (“poly”) layer 107 , a second nitride layer 109 , and an isolation oxide 111 .
- nominal film thicknesses and methods of deposit are provided as follows; the pad oxide is a thermally grown 400 ⁇ oxide, the first nitride is 1000 ⁇ thick, the first poly is 1800 ⁇ thick, the second nitride layer is 700 ⁇ thick, and the isolation oxide is 7000 ⁇ thick, deposited by a plasma-enhanced chemical vapor deposition (PECVD) process.
- PECVD plasma-enhanced chemical vapor deposition
- the base substrate 101 is frequently a silicon wafer.
- the specific silicon wafer is doped as a p-type substrate.
- another semiconductor may be selected for base substrate 101 .
- FIG. 2 shows the deposited films of FIG. 1 with an etched dielectric area 201 .
- Etching may be accomplished through various wet etch (e.g., in hydrofluoric, such as contained in a standard buffered oxide etch, or orthophosphoric acid) or dry etch (e.g., reactive-ion etch (RIE)) techniques.
- An edge wall angle 203 will depend on several factors such as a size of the etched dielectric area 201 and type of etchant used.
- FIG. 3 shows a conformal blanket deposition of a third nitride layer 301 .
- the third nitride layer 301 is used as a mask for later oxidation steps (described infra).
- FIG. 4 shows the third nitride layer anisotropically etched 401 to a top of the first poly layer 107 .
- Nitride can be anisotropically etched, for example, by RIE.
- a high selectivity to either silicon or silicon dioxide is accomplished using CHF 3 /O 2 , CH 2 F 2 , or CH 3 F.
- a thermally grown oxide 501 in FIG. 5 serves as a mask for the underlying poly 107 , nitride 105 , and oxide 103 layers.
- the thermally grown oxide 501 is substantially thicker than the underlying pad oxide 103 to prevent the thermally grown oxide 501 from being completely etched prior to etching through the pad oxide 103 in later steps.
- Thermal growth techniques combine oxygen with underlying silicon (i.e., the polycrystalline silicon 107 ). Mechanisms for thermal oxide growth are well understood with 44% of the underlying poly 107 being consumed to form the oxide 501 .
- oxide 501 could be deposited.
- the remainder of the etched nitride layer 401 is removed as shown in FIG. 6 .
- the first three film layers surrounding the thermally grown oxide 501 of FIG. 6 are anisotropically etched (e.g., by RIE) to form a poly plug slot 701 .
- the thermally grown oxide 501 (not shown in FIG. 7 ) has also been etched away (either through the anisotropic etch process or through a separate wet-etch or dry-etch process).
- the poly plug slot forms a via for a transistor base contact formed later in the process flow.
- FIG. 8 shows a conformally deposited poly plug layer 801 filling the poly plug slot 701 with a doped polycrystalline silicon.
- the poly plug layer 801 is then anisotropically etched ( FIG. 9 ) with an over etch through a central portion of the first poly layer 107 A ( FIG. 8 ) and into a central portion of the underlying first nitride layer 105 A. This anisotropic etch step also forms an etched poly plug 901 .
- an emitter window 1001 is formed by etching through the central portion of the first nitride layer 105 A.
- a central portion of the underlying pad oxide 103 A may also be partially etched in this nitride etch step.
- a high selectivity (nitride to silicon dioxide) etchant will be used during this etch step, thereby minimizing etching the central portion of the pad oxide 103 A.
- FIG. 11 shows a fourth nitride layer 1101 conformally deposited into the emitter window and surrounding areas.
- the fourth nitride layer 1101 is an LPCVD nitride approximately 1000 ⁇ thick.
- the fourth nitride layer 1101 forms a dielectric separation between the etched poly plug 901 and an ensuing polysilicon structure.
- boron is diffused through the fourth nitride layer 1101 and any remaining portion of the underlying pad oxide 103 A and forms a boron implant 1201 .
- the boron implant 1201 will serve as an active base region.
- a boron dosage level is chosen to provide the desired device characteristics.
- FIG. 13 shows a deposited conformal oxide spacer 1301 .
- the oxide spacer 1301 defines a width of a nitride “boot” (described infra).
- the nitride boot allows feature sizes in general, and the emitter-base contact region in particular, to be formed smaller than conventional photolithographic techniques allow.
- the oxide spacer 1301 additionally provides for self-alignment of the base-emitter region.
- the oxide spacer 1301 is deposited using LPCVD techniques, although other deposition techniques may be used as well.
- the oxide spacer 1301 is formed using polycrystalline silicon instead of oxide.
- FIG. 14 shows an exemplary etched oxide spacer 1401 .
- the etched oxide spacer 1401 is achieved by anisotropic etching (e.g., an RIE process) of the oxide spacer 1301 .
- anisotropic etching e.g., an RIE process
- oxide from the “horizontal” surfaces are etched away.
- the anisotropic etch combined with the thickness of the etched oxide spacer 1401 determine a width of an emitter opening.
- the emitter window 1001 ( FIG. 10 ) is opened further through the use of an anisotropic etch of the fourth nitride layer 1101 .
- An RIE process is effective at removing portions of the fourth nitride layer 1101 .
- a bottom portion of the emitter window 1001 and all nitride on a top portion of the device structure are removed. Since a nitride thickness on the top portion of the device structure is roughly the same as a thickness of the nitride in a bottom portion of the emitter window 1001 , good endpoint control is achieved through selective etching techniques described supra.
- the RIE process described above also produces a radially inward projecting boot shape 1501 which defines an emitter contact window by non-photolithographic means. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region (described infra). Therefore, level-to-level alignment issues with multiple masks are eliminated. Additionally, feature sizes are also determined by deposition and etching techniques and can be far smaller than features defined by photolithography. Consequently, photolithography of small features is eliminated.
- the boron implant 1201 in the intrinsic base is annealed. Additionally, boron from doped base poly is redistributed from poly plug 901 into the underlying base structure 101 . This boron anneal step creates a redistributed boron implant 1601 with a toroidal-like topology underlying the poly plug 901 .
- the topology of the redistributed boron implant 1601 produces an inherently low junction capacitance, thereby increasing device speed. Further, this unique topology reduces or eliminates the absorption of current through recombination at a boundary surface, resulting in a reduction of the dependence of the current amplification factor on electric current.
- FIG. 17 shows the device structure after an oxide wet etch.
- a timed, wet etch process removes residual oxide from the bottom of the emitter window 1001 and also removes all or part of the etched oxide spacer 1401 ( FIG. 14 ). The etch process also reduce a thickness of the isolation oxide 111 . Removal of only part of the etched oxide spacer 1401 will not affect final device performance.
- a ramped emitter poly layer 1801 is conformally applied over a remaining portion of the device structure. Precautions are taken to minimize or eliminate any native oxide growth on the bottom of the emitter window 1001 . Techniques to minimize native oxide growth from silicon are well known in the art and will not be discussed herein.
- ramped emitter poly layer 1801 Following deposition of the ramped emitter poly layer 1801 , techniques well known to a skilled artisan are completed to form, for example, collector definition and implants, and metallization steps to complete the semiconductor device.
- an embodiment depicts formation of an npn bipolar transistor base-emitter junction
- a skilled artisan will recognize that the present invention is readily adaptable to a pnp bipolar transistor or to a gate-source junction of a field effect transistor.
- many industries allied with the semiconductor industry could make use of this technique.
- a thin-film head (TFH) process in the data storage industry or an active matrix liquid crystal display (AMLCD) in the flat panel display industry could readily make use of the processes and techniques described herein.
- THF thin-film head
- AMLCD active matrix liquid crystal display
- semiconductor should be recognized as including the aforementioned and related industries.
Abstract
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.
Description
- This is a divisional of pending application Ser. No. 10/680,355, filed Oct. 6, 2003.
- This invention relates generally to a process for fabricating an integrated circuit structure, and more specifically to electronic devices having semiconductor junctions and to a process for their manufacture.
- There is a need in the integrated circuit art for obtaining increasingly smaller devices without sacrificing device performance. The small device size requires small device regions, precise and accurate alignment between regions and minimization of parasitic resistances and capacitances. Device size can be reduced by putting more reliance on fine line lithography, but as discussed below, it becomes impractical or impossible to continue to reduce feature size and achieve the required greater increase in alignment accuracy. As lithography is pushed to the limit, yield and production throughput decrease.
- Four governing performance parameters of a photolithographic system are limit-of-resolution, Lr, level-to-level alignment accuracy, and depth-of-focus, and throughput. For purposes of this discussion, limit-of-resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.
- Typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, λ, and geometrical configurations of the projection system optics. According to Rayleigh's criterion,
where NA is the numerical aperture of the optical system and is defined as NA=nsinα, where n is the index of refraction of the medium which the radiation traverses (usually air for this application, so n≅1) and α is a half-angle of the divergence of the actinic radiation. For example, using deep ultraviolet illumination (DUV) with λ=193 nm, and NA=0.7, the lower limit of resolution is 168 nanometers (1680 Å). Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks. - Along with the limit-of-resolution, the second parameter, level-to-level alignment accuracy becomes more critical as feature sizes on photomasks decrease and a number of total photomasks increases. For example, if photomask alignment by itself causes a reduction in device yield to 95% per layer, then 25 layers of photomask translates to a total device yield of 0.9525=0.28 or 28% yield (assuming independent errors). Therefore, a more complicated mask, such a phase-shifted mask is not only more expensive but device yield can suffer dramatically.
- Further, although the numerical aperture of the photolithographic system may be increased to lower the limit-of-resolution, the third parameter, depth-of-focus, will suffer as a result. Depth-of-focus is inversely proportional to NA2. Therefore, as NA increases, limit-of-resolution decreases but depth-of-focus decreases more rapidly. The reduced depth-of-focus makes accurate focusing more difficult especially on non-planar features such as “Manhattan Geometries” becoming increasingly popular in advanced semiconductor devices.
- Recently, techniques have been developed to make smaller scale transistors and related devices. One such method of making transistors is described in U.S. Pat. No. 5,067,022 to Zdebel et al., assigned to Motorola, Inc. Here, a process is disclosed for fabricating improved integrated, circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. However, that process is still limited by requiring large implant areas. For example, a bipolar transistor base region still requires photomasks and photolithographic techniques for its production. An integrated circuit device, or even a single transistor or other electronic device fabricated by this method cannot be scaled down beyond a given point. Further, a high base-emitter capacitance resulting from use of this method severely affects device performance.
- Additionally, in a conventional method for fabricating a bipolar device, an emitter window is directly opened without some means of providing an etch stop. This overetch produces a damaged region in the silicon and may result in excessive consumption of silicon underlying the contact. Further, formation of an oxide spacer without an etch stop presents manufacturing difficulties as timing and other recipe tolerances become overly stringent.
- For at least the aforementioned reasons, integrated circuit manufacturers have been unable to sufficiently reduce a size of electronic devices while still maintaining high performance. In view of the desire for integrated circuits having higher device counts, smaller device sizes, and greater circuit performance, a need continues to exist for an improved process to manufacture the required devices without resorting to unrealistic and expensive photolithography requirements.
- Accordingly, what is needed is a way to provide an improved process and structure for fabricating integrated circuit devices. Such a structure for producing integrated circuit devices would have devices with a reduced size with reasonable photolithographic tolerances.
- Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Vertical npn transistors are much used in the integrated circuit art. Accordingly, improved means and methods for their formation, which are not limited by constraints of photolithography, have great utility and importance. Those of skill in the art will appreciate that the conductivity types shown herein may be reversed if it is desired to form a vertical pnp transistor on an N-type substrate. Additionally, the same techniques may be used to fabricate other types of devices. For example, a gate-source junction (as well as other device junction types) may be fabricated using the methods described herein.
- In one embodiment, the present invention includes a method of fabricating an electronic device comprising forming a slot region for a doped polycrystalline silicon plug material within an outer periphery of an etched window region. The window region is formed by etching a film stack residing on a topmost surface of a semiconductor substrate having a p-type conductivity. The slot region is then filled with the polycrystalline silicon plug material, followed by depositing a dielectric separation layer over the polycrystalline silicon plug material. A dopant, for example, boron, is implanted into a limited area of the substrate located within a region circumscribed by the slot region. A temporary spacer (e.g., an oxide spacer) is deposited over the dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. The boot shape is indicative of a projection of a dielectric layer extending radially inward (see
FIG. 15 , element 1501). An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Therefore, level-to-level alignment issues with multiple masks are eliminated. Additionally, feature sizes are also determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated. Thus, limit-of-resolution and depth-of-focus are unimportant parameters. - During an anneal cycle, the dopant from a lower edge of the polycrystalline silicon plug is driven into the substrate, forming a toroidal-like junction with low capacitance. The toroidal-like junction, in three-dimensions, is similar to a toroid shape but radial symmetry is not necessary. For example, a toroid is a surface generated by a plane-closed curve rotated about a line that lies in the same plane as the curve but does not intersect it. The toroidal-like junction of the present invention may take a form of a closed shape not necessarily rotated equidistantly from an imaginary line.
- Finally, any remaining film layers within a region substantially circumscribed by the dielectric boot are etched down to the topmost surface of the substrate; and an emitter polycrystalline silicon layer is deposited.
- The present invention is also an electronic device. In one embodiment, the electronic device comprises a semiconductor substrate having thereon at least one region laterally enclosed by a dielectric isolation region and coupled to a principal surface of the substrate. A polycrystalline silicon plug region is peripherally disposed on an outermost boundary of the dielectric isolation region and coupled to the dielectric isolation region. The polycrystalline silicon plug region is further electrically coupled to the semiconductor substrate. A doped region extends from the polycrystalline silicon plug region distally into the substrate and is electrically coupled to said polycrystalline silicon plug region. A doping concentration of the doped region has a toroidal-like topology.
-
FIG. 1 shows an exemplary embodiment of a schematic cross-sectional view of deposited films used to create an electronic device structure. -
FIG. 2 shows the deposited films ofFIG. 1 with an etcheddielectric area 201. -
FIG. 3 shows a conformal blanket deposition of a third nitride layer. -
FIG. 4 shows the third nitride layer ofFIG. 3 anisotropically etched. -
FIG. 5 shows a thermally grown oxide within the confines created by the etched nitride layer ofFIG. 4 . -
FIG. 6 shows the device structure ofFIG. 5 with the etched nitride layer removed. -
FIG. 7 shows etched films defining an etched poly slot. -
FIG. 8 shows a conformally deposited poly plug layer filling the poly plug slot ofFIG. 7 with a doped polycrystalline silicon. -
FIG. 9 shows the poly plug layer ofFIG. 8 anisotropically etched to form an etched poly plug. -
FIG. 10 shows an emitter window formed by etching through a central portion of a first nitride layer first shown inFIG. 1 . -
FIG. 11 shows a nitride layer conformally deposited into the emitter window ofFIG. 10 . -
FIG. 12 shows a boron diffusion through the nitride layer ofFIG. 11 . -
FIG. 13 shows a deposited conformal oxide spacer deposited over the nitride layer ofFIG. 12 . -
FIG. 14 shows the oxide spacer ofFIG. 13 after etching. -
FIG. 15 shows the emitter window ofFIG. 10 opened further by anisotropic etching of the nitride layer ofFIG. 11 . -
FIG. 16 shows a toroidal-like topology formed from a redistributed dopant from the poly plug ofFIG. 9 formed during an implant anneal. -
FIG. 17 shows electronic device structure after an etch of the oxide spacer ofFIG. 14 . -
FIG. 18 shows the electronic device structure ofFIG. 17 after a ramped poly emitter is conformally applied. - With reference to
FIGS. 1-18 , an exemplary embodiment of the present invention is described in detail according to the following process steps. To start,FIG. 1 shows an exemplary embodiment of a cross-sectional view of deposited films used to form an electronic device structure. Each film layer is deposited in compliance with process steps that are well-known in the semiconductor art.FIG. 1 includes abase substrate 101, apad oxide 103, afirst nitride layer 105, a first polycrystalline silicon (“poly”)layer 107, asecond nitride layer 109, and anisolation oxide 111. - In a specific exemplary embodiment, nominal film thicknesses and methods of deposit are provided as follows; the pad oxide is a thermally grown 400 Å oxide, the first nitride is 1000 Å thick, the first poly is 1800 Å thick, the second nitride layer is 700 Å thick, and the isolation oxide is 7000 Å thick, deposited by a plasma-enhanced chemical vapor deposition (PECVD) process.
- The
base substrate 101 is frequently a silicon wafer. In this embodiment, the specific silicon wafer is doped as a p-type substrate. Alternatively, another semiconductor may be selected forbase substrate 101. -
FIG. 2 shows the deposited films ofFIG. 1 with an etcheddielectric area 201. Etching may be accomplished through various wet etch (e.g., in hydrofluoric, such as contained in a standard buffered oxide etch, or orthophosphoric acid) or dry etch (e.g., reactive-ion etch (RIE)) techniques. Anedge wall angle 203 will depend on several factors such as a size of the etcheddielectric area 201 and type of etchant used. -
FIG. 3 shows a conformal blanket deposition of athird nitride layer 301. Thethird nitride layer 301 is used as a mask for later oxidation steps (described infra).FIG. 4 shows the third nitride layer anisotropically etched 401 to a top of thefirst poly layer 107. Nitride can be anisotropically etched, for example, by RIE. A high selectivity to either silicon or silicon dioxide is accomplished using CHF3/O2, CH2F2, or CH3F. - A thermally grown
oxide 501 inFIG. 5 serves as a mask for theunderlying poly 107,nitride 105, andoxide 103 layers. Ideally, the thermally grownoxide 501 is substantially thicker than theunderlying pad oxide 103 to prevent the thermally grownoxide 501 from being completely etched prior to etching through thepad oxide 103 in later steps. Thermal growth techniques combine oxygen with underlying silicon (i.e., the polycrystalline silicon 107). Mechanisms for thermal oxide growth are well understood with 44% of theunderlying poly 107 being consumed to form theoxide 501. Alternatively,oxide 501 could be deposited. Next, the remainder of the etchednitride layer 401 is removed as shown inFIG. 6 . - With reference to
FIG. 7 , after removing the etchednitride layer 401, the first three film layers surrounding the thermally grownoxide 501 ofFIG. 6 are anisotropically etched (e.g., by RIE) to form apoly plug slot 701. The thermally grown oxide 501 (not shown inFIG. 7 ) has also been etched away (either through the anisotropic etch process or through a separate wet-etch or dry-etch process). The poly plug slot forms a via for a transistor base contact formed later in the process flow. -
FIG. 8 shows a conformally depositedpoly plug layer 801 filling thepoly plug slot 701 with a doped polycrystalline silicon. Thepoly plug layer 801 is then anisotropically etched (FIG. 9 ) with an over etch through a central portion of thefirst poly layer 107A (FIG. 8 ) and into a central portion of the underlyingfirst nitride layer 105A. This anisotropic etch step also forms an etchedpoly plug 901. - With reference to
FIG. 10 , anemitter window 1001 is formed by etching through the central portion of thefirst nitride layer 105A. A central portion of theunderlying pad oxide 103A may also be partially etched in this nitride etch step. Typically, a high selectivity (nitride to silicon dioxide) etchant will be used during this etch step, thereby minimizing etching the central portion of thepad oxide 103A. -
FIG. 11 shows afourth nitride layer 1101 conformally deposited into the emitter window and surrounding areas. In an exemplary embodiment, thefourth nitride layer 1101 is an LPCVD nitride approximately 1000 Å thick. Thefourth nitride layer 1101 forms a dielectric separation between the etchedpoly plug 901 and an ensuing polysilicon structure. - With reference to
FIG. 12 , boron is diffused through thefourth nitride layer 1101 and any remaining portion of theunderlying pad oxide 103A and forms aboron implant 1201. Theboron implant 1201 will serve as an active base region. A boron dosage level is chosen to provide the desired device characteristics. -
FIG. 13 shows a depositedconformal oxide spacer 1301. Theoxide spacer 1301 defines a width of a nitride “boot” (described infra). The nitride boot allows feature sizes in general, and the emitter-base contact region in particular, to be formed smaller than conventional photolithographic techniques allow. Theoxide spacer 1301 additionally provides for self-alignment of the base-emitter region. In an exemplary embodiment, theoxide spacer 1301 is deposited using LPCVD techniques, although other deposition techniques may be used as well. Alternatively, theoxide spacer 1301 is formed using polycrystalline silicon instead of oxide. -
FIG. 14 shows an exemplaryetched oxide spacer 1401. The etchedoxide spacer 1401 is achieved by anisotropic etching (e.g., an RIE process) of theoxide spacer 1301. In the anisotropic etch process, oxide from the “horizontal” surfaces are etched away. The anisotropic etch, combined with the thickness of the etchedoxide spacer 1401 determine a width of an emitter opening. - With reference to
FIG. 15 , the emitter window 1001 (FIG. 10 ) is opened further through the use of an anisotropic etch of thefourth nitride layer 1101. An RIE process is effective at removing portions of thefourth nitride layer 1101. A bottom portion of theemitter window 1001 and all nitride on a top portion of the device structure are removed. Since a nitride thickness on the top portion of the device structure is roughly the same as a thickness of the nitride in a bottom portion of theemitter window 1001, good endpoint control is achieved through selective etching techniques described supra. - With further reference to
FIG. 15 , the RIE process described above also produces a radially inward projectingboot shape 1501 which defines an emitter contact window by non-photolithographic means. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region (described infra). Therefore, level-to-level alignment issues with multiple masks are eliminated. Additionally, feature sizes are also determined by deposition and etching techniques and can be far smaller than features defined by photolithography. Consequently, photolithography of small features is eliminated. - In
FIG. 16 , theboron implant 1201 in the intrinsic base is annealed. Additionally, boron from doped base poly is redistributed frompoly plug 901 into theunderlying base structure 101. This boron anneal step creates a redistributedboron implant 1601 with a toroidal-like topology underlying thepoly plug 901. The topology of the redistributedboron implant 1601 produces an inherently low junction capacitance, thereby increasing device speed. Further, this unique topology reduces or eliminates the absorption of current through recombination at a boundary surface, resulting in a reduction of the dependence of the current amplification factor on electric current. -
FIG. 17 shows the device structure after an oxide wet etch. In one embodiment, a timed, wet etch process removes residual oxide from the bottom of theemitter window 1001 and also removes all or part of the etched oxide spacer 1401 (FIG. 14 ). The etch process also reduce a thickness of theisolation oxide 111. Removal of only part of the etchedoxide spacer 1401 will not affect final device performance. - With reference to
FIG. 18 , a rampedemitter poly layer 1801 is conformally applied over a remaining portion of the device structure. Precautions are taken to minimize or eliminate any native oxide growth on the bottom of theemitter window 1001. Techniques to minimize native oxide growth from silicon are well known in the art and will not be discussed herein. - In an exemplary embodiment following deposition of the ramped
emitter poly layer 1801, techniques well known to a skilled artisan are completed to form, for example, collector definition and implants, and metallization steps to complete the semiconductor device. - To facilitate an understanding of the present invention, a process and arrangement for forming a vertical bipolar transistor, particularly a vertical npn transistor on a p-type substrate has been discussed herein. However, the invented process and arrangements of layers and regions described herein are also useful for forming a wide range of other device types and structures having utility as individual devices or in combinations.
- For example, although an embodiment depicts formation of an npn bipolar transistor base-emitter junction, a skilled artisan will recognize that the present invention is readily adaptable to a pnp bipolar transistor or to a gate-source junction of a field effect transistor. Additionally, many industries allied with the semiconductor industry could make use of this technique. For example, a thin-film head (TFH) process in the data storage industry or an active matrix liquid crystal display (AMLCD) in the flat panel display industry could readily make use of the processes and techniques described herein. The term “semiconductor” should be recognized as including the aforementioned and related industries.
- Additionally, although process steps and techniques are shown and described in detail, a skilled artisan will recognize that other techniques and methods may be utilized which are still included within the scope of the appended claims. For example, there are frequently several techniques used for depositing a film layer (e.g., chemical vapor deposition, plasma-enhanced vapor deposition, epitaxy, atomic layer deposition, etc.). Although not all techniques are amenable to all film types described herein, one skilled in the art will recognize that multiple methods for depositing a given layer and/or film type may be used.
Claims (5)
1. An electronic device comprising:
a semiconductor substrate having thereon at least one region laterally enclosed by a dielectric isolation region and coupled to a principal surface of said substrate;
a polycrystalline semiconductor plug region peripherally disposed on an outermost boundary of the dielectric region and coupled to said dielectric isolation region, said polycrystalline semiconductor plug region further being electrically coupled to said semiconductor substrate; and
a doped region extending from said polycrystalline semiconductor plug region distally into said substrate and electrically coupled to said polycrystalline semiconductor plug region, said doped region further having a doping concentration toroidal-like in topology.
2. The electronic device of claim 1 further comprising a polycrystalline semiconductor layer deposited within a region circumscribed by said dielectric isolation region.
3. The electronic device of claim 2 wherein the polycrystalline semiconductor layer is an emitter contact on a bipolar junction transistor.
4. The electronic device of claim 1 further comprising a second doped region peripherally bounded laterally by said doped region.
5. The electronic device of claim 1 wherein the doped region and the second doped region form a transistor base region.
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US11/539,845 US20070075400A1 (en) | 2003-10-06 | 2006-10-09 | Semiconductor device with a toroidal-like junction |
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US10229985B1 (en) | 2017-12-04 | 2019-03-12 | International Business Machines Corporation | Vertical field-effect transistor with uniform bottom spacer |
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US20070087557A1 (en) | 2007-04-19 |
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