US20070013044A9 - Packaged integrated circuits and methods of producing thereof - Google Patents

Packaged integrated circuits and methods of producing thereof Download PDF

Info

Publication number
US20070013044A9
US20070013044A9 US10/451,564 US45156404A US2007013044A9 US 20070013044 A9 US20070013044 A9 US 20070013044A9 US 45156404 A US45156404 A US 45156404A US 2007013044 A9 US2007013044 A9 US 2007013044A9
Authority
US
United States
Prior art keywords
integrated circuit
plurality
packaged integrated
electrical
portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/451,564
Other versions
US7408249B2 (en
US20040183185A1 (en
Inventor
Avner Badihi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Invensas Corp
Original Assignee
Tessera Technologies Hungary Kft
Shellcase Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to IL12320798A priority Critical patent/IL123207D0/en
Priority to PCT/IL1999/000071 priority patent/WO1999040624A1/en
Priority to US09/601,895 priority patent/US6646289B1/en
Priority to IL14048200A priority patent/IL140482A/en
Priority to IL140482 priority
Priority to US09/758,906 priority patent/US6624505B2/en
Priority to US09758906 priority
Application filed by Tessera Technologies Hungary Kft, Shellcase Ltd filed Critical Tessera Technologies Hungary Kft
Priority to US10/451,564 priority patent/US7408249B2/en
Priority to PCT/IL2001/001183 priority patent/WO2002051217A2/en
Assigned to SHELLCASE LTD. reassignment SHELLCASE LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BADIHI, AVNER
Publication of US20040183185A1 publication Critical patent/US20040183185A1/en
Assigned to TESSERA TECHNOLOGIES HUNGARY KFT. reassignment TESSERA TECHNOLOGIES HUNGARY KFT. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHELLCASE LTD., ALSO SOMETIMES KNOWN AS SHELLCASE, LTD.
Publication of US20070013044A9 publication Critical patent/US20070013044A9/en
Application granted granted Critical
Publication of US7408249B2 publication Critical patent/US7408249B2/en
Assigned to TESSERA TECHNOLOGIES IRELAND LIMITED reassignment TESSERA TECHNOLOGIES IRELAND LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TESSERA TECHNOLOGIES HUNGARY HOLDING LIMITED LIABILITY COMPANY
Assigned to DIGITALOPTICS CORPORATION EUROPE LIMITED reassignment DIGITALOPTICS CORPORATION EUROPE LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: TESSERA TECHNOLOGIES IRELAND LIMITED
Assigned to DigitalOptics Corporation Europe Limited reassignment DigitalOptics Corporation Europe Limited CORRECTION TO REEL 026739 FRAME 0875 TO CORRECTION THE ADDRESS OF RECEIVING PARTY. Assignors: TESSERA TECHNOLOGIES IRELAND LIMITED
Assigned to INVENSAS CORPORATION reassignment INVENSAS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DigitalOptics Corporation Europe Limited
Assigned to ROYAL BANK OF CANADA, AS COLLATERAL AGENT reassignment ROYAL BANK OF CANADA, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DIGITALOPTICS CORPORATION, DigitalOptics Corporation MEMS, DTS, INC., DTS, LLC, IBIQUITY DIGITAL CORPORATION, INVENSAS CORPORATION, PHORUS, INC., TESSERA ADVANCED TECHNOLOGIES, INC., TESSERA, INC., ZIPTRONIX, INC.
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.

Description

    FIELD OF THE INVENTION
  • The present invention relates to integrated packaging, packaged integrated circuits and methods of producing packaged integrated circuits.
  • REFERENCE TO CO-PENDING APPLICATIONS
  • Applicants hereby claim priority of Israel Patent Application No. 140,482, filed Dec. 21, 2001, entitled “Packaged Integrated Circuits and Methods of Producing Thereof”, and U.S. patent application Ser. No. 09/758,906 filed Jan. 11, 2001, entitled “Packaged Integrated Circuits and Methods of Producing Thereof”.
  • BACKGROUND OF THE INVENTION
  • Various types of packaged integrated circuits are known in the prior art. The following patents and published patent applications of the present inventor and the references cited therein are believed to represent the state of the art: U.S. Pat. Nos. 4,551,629; 4,764,846; 4,794,092; 4,862,249; 4,984,358; 5,104,820; 5,126,286; 5,266,833; 5,546,654; 5,567,657; 5,612,570; 5,657,206; 5,661,087; 5,675,180; 5,703,400; 5,837,566; 5,849,623; 5,857,858; 5,859,475; 5,869,353; 5,888,884; 5,891,761; 5,900,674; 5,938,45; 5,985,695; 6,002,163; 6,046,410; 6,080,596; 6,092,280; 6,098,278; 6,124,637; 6,134,118. EP 490739 A1; JP 63-166710 WO 85/02283; WO 89/04113; WO 95/19645
  • The disclosures in the following publications:
  • “Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technology” by R. J. Wojnarowski, R. A. Filliion, B. Gorowitz and R. Sala of General Electric Company, Corporate Research & Development, P.O. Box 8, Schenectady, N.Y. 12301, USA, International Conference on Wafer Scale Integration, 1993.
  • “M-DENSUS”, Dense-Pac Microsystems, Inc., Semiconductor International, December 1997, p. 50;
  • “Introduction to Cubic Memory, Inc.” Cubic Memory Incorporated, 27 Janis Way, Scotts Valley, Calif. 95066, USA;
  • “A Highly Integrated Memory Subsystem for the Smaller Wireless Devices” Intel(r) Stacked-CSP, Intel Corporation, January 2000;
  • “Product Construction Analysis (Stack CSP)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
  • “Four Semiconductor Manufacturers Agree to Unified Specifications for Stacked Chip Scale Packages”, Mitsubishi Semiconductors, Mitsubishi Electronics America, Inc., 1050 East Arques Avenue, Sunnyvale, Calif. 94086, USA;
  • “Assembly & Packaging, John Baliga, Technology News, Semiconductor International, December 1999;
  • “<6 mils Wafer Thickness Solution (DBG Technology)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
  • “Memory Modules Increase Density”, DensePac Micro Systems, Garden Grove, Calif., USA, Electronics Packaging and Production, p. 24, Nov. 1994;
  • “First Three-Chip Staked CSP Developed”, Semiconductor International, January 2000, p. 22;
  • “High-Density Packaging: The Next Interconnect Challenge”, Semiconductor International, February 2000, pp. 91-100;
  • “3-D IC Packaging”, Semiconductor International, p. 20, May 1998;
  • “High Density Pixel Detector Module Using Flip Chip and Thin Film Technology” J. Wolf, P. Gerlach, E. Beyne, M. Topper, L. Dietrich, K. H. Becks, N. Wermes, O. Ehrmann and H. Reichl, International System Packaging Symposium, January 1999, San Diego;
  • “Copper Wafer Bonding”, A. Fan, A. Rahman and R. Rief, Electrochemical and Solid State Letters, 2(10), pp. 534-536, 1999;
  • “Front-End 3-D Packaging”, J. Baliga, Semiconductor International, December 1999, p 52, are also believed to represent the state of the art.
  • SUMMARY OF THE INVENTION
  • The present invention seeks to provide improved packaged integrated circuits and methods for producing same.
  • There is thus provided in accordance with a preferred embodiment of the present invention a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
  • Further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
  • Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is partially transparent to infra-red radiation.
  • There is also provided in accordance with another preferred embodiment of the present invention a packaged integrated circuit assembly including a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and at least one additional electrical circuit element mounted onto and supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
  • Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
  • Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • Still further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
  • There is further provided in accordance with a preferred embodiment of the present invention a method for producing packaged integrated circuits. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
  • Further in accordance with a preferred embodiment of the present invention the plurality of individual chip packages are chip scale packages.
  • Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • There is also provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages and mounting onto the at second planar surface of at least one of the plurality of individual chip packages, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
  • Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
  • Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • There is further provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, mounting onto the at second planar surface of the wafer scale packaging, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
  • Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
  • Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
  • FIG. 1 is a simplified pictorial illustration of a chip-scale packaged integrated circuit constructed and operative in accordance with a preferred embodiment of the present invention;
  • FIGS. 2A, 2B and 2C are simplified pictorial illustrations of three examples of packaged integrated circuit assemblies constructed and operative in accordance with a preferred embodiment of the present invention;
  • FIGS. 3A and 3B are simplified illustrations of a first series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention;
  • FIGS. 3C, 3D, 3E and 3F, are simplified sectional illustrations of a first series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention;
  • FIG. 4A is a simplified pictorial illustration of an in-production packaged wafer following the stage illustrated in FIG. 3F and following a first grooving stage;
  • FIG. 4B is a simplified pictorial illustration of an in-production packaged wafer following the stages illustrated in FIGS. 3F and 4A and following a second grooving stage;
  • FIGS. 5A, 5B, 5C, 5D and 5E are simplified sectional illustrations taken along lines VI-VI in FIG. 4A of a second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention;
  • FIGS. 6A, 6B, 6C, 6D and 6E are simplified sectional illustrations taken along lines V-V in FIG. 4B of the second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention; and
  • FIGS. 7A and 7B taken together illustrate apparatus and methodologies for producing integrated circuit devices in accordance with a preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Reference is now made to FIG. 1, which is a simplified pictorial illustration of a chip-scale packaged integrated circuit constructed and operative in accordance with a preferred embodiment of the present invention. FIG. 1 illustrates a preferred embodiment of integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention and includes a relatively thin and compact, environmentally protected and mechanically strengthened packaged integrated circuit 10, having a multiplicity of electrical contacts plated along edge surfaces and planar surfaces thereof.
  • In contrast with prior art devices, such as those described in applicant's published PCT application WO 95/19645, the packaged integrated circuit shown in FIG. 1 is characterized in that it has electrical contacts 12 extending along a first planar surface 14 thereof and also has electrical contacts 16 extending along an oppositely facing second planar surface 18 thereof This arrangement enables the packaged integrated circuit to be conveniently mounted in a stacked arrangement.
  • As seen in FIG. 1, the packaged integrated circuit 10 includes a plurality of generally planar edge surfaces which extend non-perpendicularly with respect to planar surfaces 14 and 18. These edge surfaces include first and second edge surfaces 20 and 22, each of which intersects the plane of a silicon substrate 24 on which is formed an integrated circuit 26 and extends from a location slightly beyond that plane to planar surface 14.
  • There are also provided third and fourth edge surfaces 30 and 32, each of which intersects the plane of silicon substrate 24 and extends from a location slightly beyond that plane to planar surface 18. There are also provided fifth and sixth edge surfaces 40 and 42, neither of which intersects the plane of silicon substrate 24. Each of edge surfaces 40 and 42 intersects a respective one of surfaces 30 and 32 and extends therefrom to planar surface 14. There are additionally provided seventh and eighth edge surfaces 50 and 52, neither of which intersects the plane of silicon substrate 24. Each of edge surfaces 50 and 52 intersects a respective one of surfaces 20 and 22 and extends therefrom to planar surface 18.
  • It is seen that contacts 12 extend along respective edge surfaces 20 and 22 and onto planar surface 14 and are in electrical contact with edges of pads 60 extending from silicon substrate 24 in the plane thereof It is also seen that contacts 16 extend along respective edge surfaces 30 and 32 and onto planar surface 18 and are in electrical contact with edges of pads 62 extending from silicon substrate 24 in the plane thereof.
  • Reference is now made to FIGS. 2A, 2B and 2C, which are simplified pictorial illustrations of three examples of packaged integrated circuit assemblies constructed and operative in accordance with a preferred embodiment of the present invention.
  • FIG. 2A illustrates a packaged integrated circuit 70 having mounted onto a planar surface 72 thereof, a plurality of other electrical devices, such as integrated circuits 78 and 74. It is seen that, for example, integrated circuit 74 electrically engages a pair of contacts 76 formed on planar surface 72, while integrated circuit 78 electrically engages six contacts 76 formed on planar surface 72.
  • FIG. 2B illustrates a packaged integrated circuit 80 having mounted onto a planar surface 82 thereof, a plurality of other electrical devices, such as four integrated circuits 84. It is seen that, for example, integrated circuits 84 each electrically engage a pair of contacts 86 formed on planar surface 82.
  • FIG. 2C illustrates a pair of packaged integrated circuits 90 and 92 mounted in a stacked arrangement, wherein contacts 94 of integrated circuit 92 are in electrical contact with corresponding contacts 96 of integrated circuit 90. It is appreciated that stacks having more than two integrated circuits of this type may be provided and that the integrated circuits need not be stacked in registration with each other, thus providing branched stacks.
  • Reference is now made to FIGS. 3A, 3B, 3C, 3D, 3E and 3F, which are simplified pictorial and sectional illustrations of a first series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention.
  • In accordance with a preferred embodiment of the present invention, and as illustrated in FIGS. 3A, 3B and 3C a complete silicon wafer 120 having a plurality of finished dies 122 formed thereon by conventional techniques, is bonded at its active surface 124 to a protective insulating cover plate 126 via a layer 128 of epoxy. The insulating cover plate 126 typically comprises glass, quartz, sapphire or any other suitable insulative substrate. FIG. 3A illustrates the initial mutual arrangement of cover plate 126 and wafer 120, FIG. 3B illustrates the final placement and FIG. 3C shows the bonding in a sectional illustration.
  • The cover plate 126 may be opaque or transparent or may be colored or tinted in order to operate as a spectral filter. Alternatively, a dichroic or colored spectral filter may be formed on at least one surface of the cover plate 126.
  • It is appreciated that certain steps in the conventional fabrication of silicon wafer 120 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating.
  • The complete silicon wafer 120 may be formed with an integral color filter array by conventional lithography techniques at any suitable location therein. Prior to the bonding step of FIGS. 3A, 3B & 3C, a filter may be formed and configured by conventional techniques over the cover plate 126, such that the filter plane lies between cover plate 126 and the epoxy layer 128.
  • Following the bonding step described hereinabove, the silicon wafer 120 is preferably ground down to a decreased thickness, typically 100 microns, as shown in FIG. 3D. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereof of the insulating cover plate 126.
  • Following the reduction in thickness of the wafer, which is optional, the wafer is etched, using a photolithography process, along its back surface along predetermined dice lines which separate the individual dies. Etched channels 130 are thus produced, which extend entirely through the thickness of the silicon substrate, typically 100 microns thick. The etched wafer is shown in FIG. 3E.
  • The aforementioned etching typically takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the silicon down to the field oxide layer, as shown in FIG. 3E.
  • The result of the silicon etching is a plurality of separated dies 140, each of which includes silicon of thickness of about 100 microns.
  • As seen in FIG. 3F, following the silicon etching, a second insulating packaging layer 142 is bonded over the dies 140 on the side thereof opposite to insulating packaging layer 126. A layer 144 of epoxy lies between the dies 140 and the layer 142 and epoxy also fills the interstices defined by etched channels 130 between dies 140. In certain applications, the packaging layer 142 and the epoxy layer 144 are both transparent in the relevant spectral wavebands, such as, the visible waveband or the infrared waveband.
  • The sandwich of the etched wafer 120 and the first and second insulating packaging layers 126 and 142 is then partially cut along lines 150, lying along the interstices between adjacent dies 140 to define notches along the outlines of a plurality of pre-packaged integrated circuits. It is noted that lines 150 are selected such that the edges of the dies along the notches are distanced from the outer extent of the silicon 140 by at least a distance d, as shown in FIG. 3F.
  • It is noted that partial cutting of the sandwich of FIG. 3F along lines 150 exposes edges of a multiplicity of pads on the silicon wafer 120, which pad edges, when so exposed, define contact surfaces on dies 140. These contact surfaces are in electrical contact with the contacts, such as contacts 12 or 16 shown in FIG. 1 and are designated in FIG. 1 by reference numerals 60 or 62 respectively.
  • It is a particular feature of the present invention that notches are formed in the sandwich of FIG. 3F in a grid pattern, wherein notches in a first direction are formed inwardly from a first planar surface of the sandwich and cut through the plane of the active surface of silicon substrate 120 and notches in a second direction, orthogonal to the first direction are formed inwardly from a second planar surface of the sandwich, parallel to the first planar surface and opposite thereto, and also cut through the plane of the active surface of silicon substrate 120.
  • FIG. 4A illustrates notching of the sandwich of FIG. 3F, producing notches 180 which extend typically inwardly from substrate 142 and engaging a plane 160 of the active surface of silicon substrate 120. FIG. 4B illustrates notching of the sandwich of FIG. 4A, producing notches 181 inwardly from substrate 126. It is seen that the notches 181 of FIG. 4B extend perpendicularly to notches 180 of FIGS. 4A & 4B and that both notches 180 and 181 pass through plane 160.
  • Reference is now made to FIGS. 5A, 5B, 5C, 5D & 5E which are simplified sectional illustrations taken along lines V-V in FIG. 4A and lines VI-VI in FIG. 4B of a second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention.
  • FIG. 5A is a sectional illustration of the sandwich of FIG. 3F, which illustrates more clearly than in FIG. 3F, the dies 140 and pads 172 extending outwardly thereof in the plane 160 (FIGS. 4A and 4B). The remaining structural elements shown in FIG. 3F are identified by the same reference numerals in FIG. 5A.
  • FIG. 5B shows the notches 180 illustrated in FIG. 4A.
  • FIG. 5C illustrates a preferred cross sectional configuration of a notch 180 produced by partially cutting as described hereinabove in connection with FIG. 4A. Vertical lines 182 indicate the intersection of the notch 180 with the pads 172, defining exposed sectional pad surfaces 62 (FIG. 1). Vertical lines 184 indicate the location of a subsequent final cut which separates the dies into individual integrated circuits at a later stage.
  • FIG. 5D illustrates the formation of metal contacts 16 (FIG. 1) along the edges 30 and 32 and part of the surface 18 (FIG. 1). These contacts, which may be formed by any suitable metal deposition technique, are seen to extend inside notch 180, thus establishing electrical contact with surfaces 62 of pads 172.
  • It is noted that metal contacts are formed onto the dies in electrical contact with surfaces 62 of pads 172 without first separating the dies into individual chips.
  • FIG. 5E illustrates subsequent dicing of the individual dies on the wafer, along the lines 184, subsequent to metal contact formation thereon, into individual pre-packaged integrated circuit devices.
  • Reference is now made to FIGS. 6A, 6B, 6C, 6D and 6E, which are simplified sectional illustrations taken along lines V-V in FIG. 4B of the second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention.
  • FIG. 6A is a sectional illustration of the sandwich of FIG. 3F, which illustrates more clearly than in FIG. 3F, the dies 140 and the pads 272 extending outwardly thereof in the plane 160 (FIGS. 4A and 4B) in directions perpendicular to the directions along which extend pads 172. The remaining structural elements shown in FIG. 3F are identified by the same reference numerals in FIG. 6A.
  • FIG. 6B shows the notches 181 illustrated in FIG. 4B.
  • FIG. 6C illustrates a preferred cross sectional configuration of a notch 181 produced by partially cutting as described hereinabove in connection with FIG. 4B. Vertical lines 282 indicate the intersection of the notch 181 with pads 272, defining exposed sectional pad surfaces 60 (FIG. 1). Vertical lines 284 indicate the location of a subsequent final cut which separates the dies into individual integrated circuits at a later stage.
  • FIG. 6D illustrates the formation of metal contacts 12 (FIG. 1) along the edges 20 and 22 and part of the surface 14 (FIG. 1). These contacts, which may be formed by any suitable metal deposition technique, are seen to extend inside notch 181, thus establishing electrical contact with surfaces 60 of pads 272.
  • It is noted that metal contacts are formed onto the dies in electrical contact with surfaces 60 of pads 272 without first separating the dies into individual chips.
  • FIG. 6E illustrates subsequent dicing of the individual dies on the wafer, subsequent to metal contact formation thereon, into individual pre-packaged integrated circuit devices.
  • Reference is now made to FIGS. 7A and 7B, which together illustrate apparatus and methodologies for producing integrated circuit devices in accordance with a preferred embodiment of the present invention. A conventional wafer fabrication facility 380 provides complete wafers 120 (FIG. 3A). Individual wafers 120 are bonded on their active surfaces to protective layers, such as glass layers 126 (FIG. 3A), using epoxy 128 (FIG. 3C), by bonding apparatus 382, preferably having facilities for rotation of the wafer 120, the layer 126 and the epoxy 128 so as to obtain even distribution of the epoxy.
  • The bonded wafer 121 (FIG. 3C) is thinned (FIG. 3D) at its non-active surface as by grinding apparatus 384, such as Model 32BTGW using 12.5A abrasive, which is commercially available from Speedfam Machines Co. Ltd. of England.
  • The wafer 121 is then etched at its non-active surface, preferably by photolithography, such as by using conventional spin-coated photoresist, which is commercially available from Hoechst, under the brand designation AZ 4562.
  • The photoresist is preferably mask exposed by a suitable UV exposure system 385, such as a Karl Suss Model KSMA6, through a lithography mask 386 to define etched channels 130 (FIG. 3E).
  • The photoresist is then developed in a development bath (not shown), baked and then etched in a silicon etch solution 388 located in a temperature controlled bath 390. Commercially available equipment for this purpose include a Chemkleen bath and an WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A.. A suitable conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro-Image Technology Ltd. of England. The wafer is conventionally rinsed after etching. The resulting etched wafer is shown in FIG. 3E.
  • Alternatively, the foregoing wet chemical etching step may be replaced by dry plasma etching.
  • The etched wafer is bonded on the non-active side to another protective layer. 142 by bonding apparatus 392, which may be essentially the same as apparatus 382, to produce a doubly bonded wafer sandwich 393 as shown in FIG. 3F.
  • Notching apparatus 394 initially partially cuts the bonded wafer sandwich 393 of FIG. 3F inwardly from layer 142 to a configuration shown in FIG. 4A including notches 180 (FIG. 4A).
  • Notching apparatus 394 thereafter partially cuts the bonded wafer sandwich 393 of FIG. 3F inwardly from layer 126 to a configuration shown in FIG. 4B including notches 180 and 181 (FIG. 4B) and cuts the bonded wafer sandwich 393 of FIG. 3F inwardly from layer 142 a configuration shown in FIG. 4B including notches 180 and 181 (FIG. 4B), extending mutually non-collinear and normally mutually perpendicular to each other.
  • The notched wafer 393 is then subjected to anti-corrosion treatment in a bath 396, containing a chromating solution 398, such as described in any of the following U.S. Pat. Nos. 2,507,956; 2,851,385 and 2,796,370, the disclosure of which is hereby incorporated by reference.
  • Conductive layer deposition apparatus 400, which operates by vacuum deposition techniques, such as a Model 903M sputtering machine manufactured by Material Research Corporation of the U.S.A., is employed to produce a conductive layer initially on surfaces 30, 32 and 18 of each die of the wafer as shown in FIG. 1 and thereafter on surfaces 20, 22 and 14 of each die of the wafer as shown in FIG. 1.
  • Configuration of contact strips 12 and 16 as shown in FIG. 1, is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle. The photoresist is applied to the wafers in a photoresist bath assembly 402 which is commercially available from DuPont or Shipley.
  • The photoresist is preferably light configured by a UV exposure system 404, which may be identical to system 385, using masks 405 and 406 to define suitable etching patterns. The photoresist is then developed in a development bath 407, and then etched in a metal etch solution 408 located in an etching bath 410, thus providing a conductor configuration such as that shown in FIG. 1.
  • The exposed conductive strips 12 and 16 shown in FIG. 1 are then plated, preferably by electroless plating apparatus 412, which is commercially available from Okuno of Japan.
  • The wafer is then diced into individual pre-packaged integrated circuit devices. Preferably the dicing blade 414 is a diamond resinoid blade of thickness 4-12 mils. The resulting dies appear as illustrated generally in FIG. 1.
  • It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove as well as variations and modifications which would occur to persons skilled in the art upon reading the specification and which are not in the prior art.

Claims (33)

1. A packaged integrated circuit comprising:
an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane; and
a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface.
2. A packaged integrated circuit according to claim 1 and wherein said package is a chip-scale package.
3. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
4. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
5. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
6. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
7. A packaged integrated circuit assembly comprising:
a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and a plurality of electrical contacts, each connected to said electrical circuitry at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and
at least one additional electrical circuit element mounted onto and supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.
8. A packaged integrated circuit assembly according to claim 7 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
9. A packaged integrated circuit according to claim 7 and wherein said package is a chip-scale package.
10. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
11. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
12. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
13. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
14. A method for producing packaged integrated circuits comprising:
producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and
separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.
15. A method for producing packaged integrated circuits according to claim 14 and wherein said plurality of individual chip packages are chip scale packages.
16. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
17. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
18. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
19. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
20. A method for producing packaged integrated circuit assemblies, the method comprising:
producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;
separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages; and
mounting onto said at second planar surface of at least one of said plurality of individual chip packages, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.
21. A method of forming a packaged integrated circuit assembly according to claim 20 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
22. A method for producing packaged integrated circuits according to claim 20 and wherein said plurality of individual chip packages are chip scale packages.
23. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
24. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
25. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
26. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
27. A method for producing packaged integrated circuit assemblies, the method comprising:
producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;
mounting onto said at second planar surface of said wafer scale packaging, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong; and
separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.
28. A method of forming a packaged integrated circuit assembly according to claim 27 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
29. A method for producing packaged integrated circuits according to claim 27 and wherein said plurality of individual chip packages are chip scale packages.
30. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
31. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
32. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
33. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
US10/451,564 1998-02-06 2001-12-19 Packaged integrated circuits and methods of producing thereof Expired - Lifetime US7408249B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
IL12320798A IL123207D0 (en) 1998-02-06 1998-02-06 Integrated circuit device
PCT/IL1999/000071 WO1999040624A1 (en) 1998-02-06 1999-02-03 Integrated circuit device
US09/601,895 US6646289B1 (en) 1998-02-06 1999-02-03 Integrated circuit device
IL140482 2000-12-21
IL14048200A IL140482A (en) 2000-12-21 2000-12-21 Packaged integrated circuits and methods of production thereof
US09/758,906 US6624505B2 (en) 1998-02-06 2001-01-11 Packaged integrated circuits and methods of producing thereof
US09758906 2001-01-11
US10/451,564 US7408249B2 (en) 1998-02-06 2001-12-19 Packaged integrated circuits and methods of producing thereof
PCT/IL2001/001183 WO2002051217A2 (en) 2000-12-21 2001-12-19 Packaged integrated circuits and methods of producing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/451,564 US7408249B2 (en) 1998-02-06 2001-12-19 Packaged integrated circuits and methods of producing thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/758,906 Continuation US6624505B2 (en) 1998-02-06 2001-01-11 Packaged integrated circuits and methods of producing thereof

Publications (3)

Publication Number Publication Date
US20040183185A1 US20040183185A1 (en) 2004-09-23
US20070013044A9 true US20070013044A9 (en) 2007-01-18
US7408249B2 US7408249B2 (en) 2008-08-05

Family

ID=26323996

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/451,564 Expired - Lifetime US7408249B2 (en) 1998-02-06 2001-12-19 Packaged integrated circuits and methods of producing thereof

Country Status (7)

Country Link
US (1) US7408249B2 (en)
EP (1) EP1356718A4 (en)
JP (1) JP2004534375A (en)
KR (1) KR100855015B1 (en)
AU (1) AU1635202A (en)
TW (1) TW546807B (en)
WO (1) WO2002051217A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070042562A1 (en) * 1998-02-06 2007-02-22 Tessera Technologies Hungary Kft. Integrated circuit device

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI227550B (en) * 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
TWI239607B (en) 2002-12-13 2005-09-11 Sanyo Electric Co Method for making a semiconductor device
JP4153325B2 (en) * 2003-02-13 2008-09-24 株式会社ディスコ Method for processing a semiconductor wafer
FR2852190B1 (en) * 2003-03-03 2005-09-23 Process for producing a component or an electronic module and corresponding component or module
DE102005006995B4 (en) * 2005-02-15 2008-01-24 Infineon Technologies Ag of the same semiconductor device with plastic housing and external terminals and methods for preparing
KR100752713B1 (en) * 2005-10-10 2007-08-29 삼성전기주식회사 Wafer level chip scale package of image sensor and manufacturing method thereof
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
DE102006048583B3 (en) * 2006-10-13 2008-01-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Component has two connections and four side surfaces with contact areas, where two side surfaces are opposite to each other, and contact areas of opposite side surfaces are connected with different connections
US7759166B2 (en) * 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
DE102007030284B4 (en) * 2007-06-29 2009-12-31 Schott Ag A method of packaging of semiconductor devices and methods in accordance prepared intermediate
WO2009017758A2 (en) 2007-07-27 2009-02-05 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
EP2186131A2 (en) 2007-08-03 2010-05-19 Tessera Technologies Hungary Kft. Stack packages using reconstituted wafers
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
SG150404A1 (en) * 2007-08-28 2009-03-30 Micron Technology Inc Semiconductor assemblies and methods of manufacturing such assemblies
CN102067310B (en) 2008-06-16 2013-08-21 泰塞拉公司 Stacking of wafer-level chip scale packages having edge contacts and manufacture method thereof
US7863722B2 (en) * 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies
KR101187214B1 (en) 2009-03-13 2012-10-02 테세라, 인코포레이티드 Stacked microelectronic assembly with microelectronic elements having vias extending through bond pads
US8624342B2 (en) 2010-11-05 2014-01-07 Invensas Corporation Rear-face illuminated solid state image sensors
JP6022792B2 (en) 2012-03-30 2016-11-09 国立大学法人東北大学 Method of manufacturing integrated devices and integrated device
KR20150073742A (en) 2013-12-23 2015-07-01 삼성전자주식회사 NFC antenna module and NFC module including the same

Citations (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2507956A (en) * 1947-11-01 1950-05-16 Lithographic Technical Foundat Process of coating aluminum
US2796370A (en) * 1955-03-04 1957-06-18 Charles W Ostrander Composition and method for producing corrosion resistant protective coating on aluminum and aluminum alloys
US2851385A (en) * 1952-04-03 1958-09-09 Amchem Prod Process and composition for coating aluminum surfaces
US3971065A (en) * 1975-03-05 1976-07-20 Eastman Kodak Company Color imaging array
US3981023A (en) * 1974-09-16 1976-09-14 Northern Electric Company Limited Integral lens light emitting diode
US4259679A (en) * 1977-01-17 1981-03-31 Plessey Handel Und Investments A.G. Display devices
US4279690A (en) * 1975-10-28 1981-07-21 Texas Instruments Incorporated High-radiance emitters with integral microlens
US4339689A (en) * 1979-01-29 1982-07-13 Matsushita Electric Industrial Co., Ltd. Light emitting diode and method of making the same
US4551629A (en) * 1980-09-16 1985-11-05 Irvine Sensors Corporation Detector array module-structure and fabrication
US4764846A (en) * 1987-01-05 1988-08-16 Irvine Sensors Corporation High density electronic package comprising stacked sub-modules
US4794092A (en) * 1987-11-18 1988-12-27 Grumman Aerospace Corporation Single wafer moated process
US4797179A (en) * 1987-06-09 1989-01-10 Lytel Corporation Fabrication of integral lenses on LED devices
US4862249A (en) * 1987-04-17 1989-08-29 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4933601A (en) * 1987-12-09 1990-06-12 Hitachi Cable Limited Light emitting diode array chip and method of fabricating same
US4984358A (en) * 1989-03-10 1991-01-15 Microelectronics And Computer Technology Corporation Method of assembling stacks of integrated circuit dies
US5037779A (en) * 1989-05-19 1991-08-06 Whalley Peter D Method of encapsulating a sensor device using capillary action and the device so encapsulated
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5118924A (en) * 1990-10-01 1992-06-02 Eastman Kodak Company Static control overlayers on opto-electronic devices
US5124543A (en) * 1989-08-09 1992-06-23 Ricoh Company, Ltd. Light emitting element, image sensor and light receiving element with linearly varying waveguide index
US5126286A (en) * 1990-10-05 1992-06-30 Micron Technology, Inc. Method of manufacturing edge connected semiconductor die
US5177753A (en) * 1990-06-14 1993-01-05 Rohm Co., Ltd. Semi-conductor laser unit
US5250462A (en) * 1990-08-24 1993-10-05 Nec Corporation Method for fabricating an optical semiconductor device
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5266501A (en) * 1991-05-09 1993-11-30 Kabushiki Kaisha Toshiba Method for manufacturing a solid state image sensing device using transparent thermosetting resin layers
US5321303A (en) * 1985-12-20 1994-06-14 Seiko Instruments Inc. Semiconductor device having linearly arranged semiconductor chips
US5455455A (en) * 1992-09-14 1995-10-03 Badehi; Peirre Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US5455386A (en) * 1994-01-14 1995-10-03 Olin Corporation Chamfered electronic package component
US5500540A (en) * 1994-04-15 1996-03-19 Photonics Research Incorporated Wafer scale optoelectronic package
US5526449A (en) * 1993-01-08 1996-06-11 Massachusetts Institute Of Technology Optoelectronic integrated circuits and method of fabricating and reducing losses using same
US5546654A (en) * 1994-08-29 1996-08-20 General Electric Company Vacuum fixture and method for fabricating electronic assemblies
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5595930A (en) * 1995-06-22 1997-01-21 Lg Semicon Co., Ltd. Method of manufacturing CCD image sensor by use of recesses
US5612570A (en) * 1995-04-13 1997-03-18 Dense-Pac Microsystems, Inc. Chip stack and method of making same
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US5661087A (en) * 1994-06-23 1997-08-26 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5672519A (en) * 1994-02-23 1997-09-30 Lg Semicon Co., Ltd. Method of fabricating solid state image sensing elements
US5677200A (en) * 1995-05-12 1997-10-14 Lg Semicond Co., Ltd. Color charge-coupled device and method of manufacturing the same
US5814894A (en) * 1995-04-07 1998-09-29 Nitto Denko Corporation Semiconductor device, production method thereof, and tape carrier for semiconductor device used for producing the semiconductor device
US5817541A (en) * 1997-03-20 1998-10-06 Raytheon Company Methods of fabricating an HDMI decal chip scale package
US5849623A (en) * 1994-12-05 1998-12-15 General Electric Company Method of forming thin film resistors on organic surfaces
US5857858A (en) * 1996-12-23 1999-01-12 General Electric Company Demountable and repairable low pitch interconnect for stacked multichip modules
US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US5888884A (en) * 1998-01-02 1999-03-30 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US5909052A (en) * 1986-03-12 1999-06-01 Hitachi, Ltd. Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane
US5938452A (en) * 1996-12-23 1999-08-17 General Electric Company Flexible interface structures for electronic devices
US5952712A (en) * 1996-07-18 1999-09-14 Nec Corporation Packaged semiconductor device and method of manufacturing the same
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
US5986746A (en) * 1994-02-18 1999-11-16 Imedge Technology Inc. Topographical object detection system
US5993981A (en) * 1997-04-18 1999-11-30 Raytheon Company Broadband protective optical window coating
US6020217A (en) * 1997-02-21 2000-02-01 Daimler-Benz Aktiengesellschaft Semiconductor devices with CSP packages and method for making them
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US6083766A (en) * 1999-07-01 2000-07-04 Viking Tech Corporation Packaging method of thin film passive components on silicon chip
US6087586A (en) * 1997-05-13 2000-07-11 Caesar Technology, Inc. Chip scale package
US6106735A (en) * 1997-01-11 2000-08-22 Robert Bosch Gmbh Wafer stack and method of producing sensors
US6235141B1 (en) * 1996-09-27 2001-05-22 Digital Optics Corporation Method of mass producing and packaging integrated optical subsystems
US6265763B1 (en) * 2000-03-14 2001-07-24 Siliconware Precision Industries Co., Ltd. Multi-chip integrated circuit package structure for central pad chip
US6307261B1 (en) * 1992-05-27 2001-10-23 Thomson Csf Method for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device
US6329708B1 (en) * 1999-04-26 2001-12-11 Oki Electric Industry Co. Ltd. Micro ball grid array semiconductor device and semiconductor module
US6548911B2 (en) * 2000-12-06 2003-04-15 Siliconware Precision Industries Co., Ltd. Multimedia chip package
US6590291B2 (en) * 2000-01-31 2003-07-08 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method therefor
US6624505B2 (en) * 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
US6646289B1 (en) * 1998-02-06 2003-11-11 Shellcase Ltd. Integrated circuit device
US6768190B2 (en) * 2002-01-25 2004-07-27 Advanced Semiconductor Engineering, Inc. Stack type flip-chip package
US20050074954A1 (en) * 2002-10-11 2005-04-07 Hideo Yamanaka Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6977431B1 (en) * 2003-11-05 2005-12-20 Amkor Technology, Inc. Stackable semiconductor package and manufacturing method thereof
US7033664B2 (en) * 2002-10-22 2006-04-25 Tessera Technologies Hungary Kft Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0161246B1 (en) 1983-11-07 1990-01-31 Irvine Sensors Corporation Detector array module-structure and fabrication
US4798659A (en) 1986-12-22 1989-01-17 Dow Corning Corporation Addition of calcium compounds to the carbothermic reduction of silica
EP0385979B1 (en) 1987-10-20 1993-08-11 Irvine Sensors Corporation High-density electronic modules, process and product
FR2670323B1 (en) 1990-12-11 1997-12-12 Thomson Csf Method and device interconnection of integrated circuits in three dimensions.
US5648653A (en) 1993-10-22 1997-07-15 Canon Kabushiki Kaisha Optical filter having alternately laminated thin layers provided on a light receiving surface of an image sensor
IL108359A (en) * 1994-01-17 2001-04-30 Shellcase Ltd Method and apparatus for producing integrated circuit devices
JP3507251B2 (en) 1995-09-01 2004-03-15 キヤノン株式会社 Light sensor ic package and its assembly method
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
JPH11168150A (en) 1997-12-04 1999-06-22 Mitsubishi Electric Corp Semiconductor integrated circuit device
KR100266693B1 (en) 1998-05-30 2000-09-15 김영환 Stackable ball grid array semiconductor package and fabrication method thereof
JP3715816B2 (en) * 1999-02-18 2005-11-16 ローム株式会社 Semiconductor chip

Patent Citations (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2507956A (en) * 1947-11-01 1950-05-16 Lithographic Technical Foundat Process of coating aluminum
US2851385A (en) * 1952-04-03 1958-09-09 Amchem Prod Process and composition for coating aluminum surfaces
US2796370A (en) * 1955-03-04 1957-06-18 Charles W Ostrander Composition and method for producing corrosion resistant protective coating on aluminum and aluminum alloys
US3981023A (en) * 1974-09-16 1976-09-14 Northern Electric Company Limited Integral lens light emitting diode
US3971065A (en) * 1975-03-05 1976-07-20 Eastman Kodak Company Color imaging array
US4279690A (en) * 1975-10-28 1981-07-21 Texas Instruments Incorporated High-radiance emitters with integral microlens
US4259679A (en) * 1977-01-17 1981-03-31 Plessey Handel Und Investments A.G. Display devices
US4339689A (en) * 1979-01-29 1982-07-13 Matsushita Electric Industrial Co., Ltd. Light emitting diode and method of making the same
US4551629A (en) * 1980-09-16 1985-11-05 Irvine Sensors Corporation Detector array module-structure and fabrication
US5321303A (en) * 1985-12-20 1994-06-14 Seiko Instruments Inc. Semiconductor device having linearly arranged semiconductor chips
US5909052A (en) * 1986-03-12 1999-06-01 Hitachi, Ltd. Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane
US4764846A (en) * 1987-01-05 1988-08-16 Irvine Sensors Corporation High density electronic package comprising stacked sub-modules
US4862249A (en) * 1987-04-17 1989-08-29 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4797179A (en) * 1987-06-09 1989-01-10 Lytel Corporation Fabrication of integral lenses on LED devices
US4794092A (en) * 1987-11-18 1988-12-27 Grumman Aerospace Corporation Single wafer moated process
US4933601A (en) * 1987-12-09 1990-06-12 Hitachi Cable Limited Light emitting diode array chip and method of fabricating same
US4984358A (en) * 1989-03-10 1991-01-15 Microelectronics And Computer Technology Corporation Method of assembling stacks of integrated circuit dies
US5037779A (en) * 1989-05-19 1991-08-06 Whalley Peter D Method of encapsulating a sensor device using capillary action and the device so encapsulated
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5124543A (en) * 1989-08-09 1992-06-23 Ricoh Company, Ltd. Light emitting element, image sensor and light receiving element with linearly varying waveguide index
US5177753A (en) * 1990-06-14 1993-01-05 Rohm Co., Ltd. Semi-conductor laser unit
US5250462A (en) * 1990-08-24 1993-10-05 Nec Corporation Method for fabricating an optical semiconductor device
US5118924A (en) * 1990-10-01 1992-06-02 Eastman Kodak Company Static control overlayers on opto-electronic devices
US5126286A (en) * 1990-10-05 1992-06-30 Micron Technology, Inc. Method of manufacturing edge connected semiconductor die
US5266501A (en) * 1991-05-09 1993-11-30 Kabushiki Kaisha Toshiba Method for manufacturing a solid state image sensing device using transparent thermosetting resin layers
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US6307261B1 (en) * 1992-05-27 2001-10-23 Thomson Csf Method for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device
US5455455A (en) * 1992-09-14 1995-10-03 Badehi; Peirre Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US5526449A (en) * 1993-01-08 1996-06-11 Massachusetts Institute Of Technology Optoelectronic integrated circuits and method of fabricating and reducing losses using same
US5455386A (en) * 1994-01-14 1995-10-03 Olin Corporation Chamfered electronic package component
US5986746A (en) * 1994-02-18 1999-11-16 Imedge Technology Inc. Topographical object detection system
US5672519A (en) * 1994-02-23 1997-09-30 Lg Semicon Co., Ltd. Method of fabricating solid state image sensing elements
US5500540A (en) * 1994-04-15 1996-03-19 Photonics Research Incorporated Wafer scale optoelectronic package
US6098278A (en) * 1994-06-23 2000-08-08 Cubic Memory, Inc. Method for forming conductive epoxy flip-chip on chip
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US5661087A (en) * 1994-06-23 1997-08-26 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5837566A (en) * 1994-06-23 1998-11-17 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US5546654A (en) * 1994-08-29 1996-08-20 General Electric Company Vacuum fixture and method for fabricating electronic assemblies
US5849623A (en) * 1994-12-05 1998-12-15 General Electric Company Method of forming thin film resistors on organic surfaces
US6134118A (en) * 1995-01-19 2000-10-17 Cubic Memory Inc. Conductive epoxy flip-chip package and method
US5814894A (en) * 1995-04-07 1998-09-29 Nitto Denko Corporation Semiconductor device, production method thereof, and tape carrier for semiconductor device used for producing the semiconductor device
US5612570A (en) * 1995-04-13 1997-03-18 Dense-Pac Microsystems, Inc. Chip stack and method of making same
US5677200A (en) * 1995-05-12 1997-10-14 Lg Semicond Co., Ltd. Color charge-coupled device and method of manufacturing the same
US5595930A (en) * 1995-06-22 1997-01-21 Lg Semicon Co., Ltd. Method of manufacturing CCD image sensor by use of recesses
US5703400A (en) * 1995-12-04 1997-12-30 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US6124637A (en) * 1996-04-24 2000-09-26 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array and method of making
US5985695A (en) * 1996-04-24 1999-11-16 Amkor Technology, Inc. Method of making a molded flex circuit ball grid array
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
US5952712A (en) * 1996-07-18 1999-09-14 Nec Corporation Packaged semiconductor device and method of manufacturing the same
US6235141B1 (en) * 1996-09-27 2001-05-22 Digital Optics Corporation Method of mass producing and packaging integrated optical subsystems
US5857858A (en) * 1996-12-23 1999-01-12 General Electric Company Demountable and repairable low pitch interconnect for stacked multichip modules
US6046410A (en) * 1996-12-23 2000-04-04 General Electric Company Interface structures for electronic devices
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US5938452A (en) * 1996-12-23 1999-08-17 General Electric Company Flexible interface structures for electronic devices
US6092280A (en) * 1996-12-23 2000-07-25 General Electric Co. Flexible interface structures for electronic devices
US6106735A (en) * 1997-01-11 2000-08-22 Robert Bosch Gmbh Wafer stack and method of producing sensors
US6020217A (en) * 1997-02-21 2000-02-01 Daimler-Benz Aktiengesellschaft Semiconductor devices with CSP packages and method for making them
US5817541A (en) * 1997-03-20 1998-10-06 Raytheon Company Methods of fabricating an HDMI decal chip scale package
US5993981A (en) * 1997-04-18 1999-11-30 Raytheon Company Broadband protective optical window coating
US6087586A (en) * 1997-05-13 2000-07-11 Caesar Technology, Inc. Chip scale package
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US6002163A (en) * 1998-01-02 1999-12-14 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
US5888884A (en) * 1998-01-02 1999-03-30 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
US6624505B2 (en) * 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
US6646289B1 (en) * 1998-02-06 2003-11-11 Shellcase Ltd. Integrated circuit device
US6329708B1 (en) * 1999-04-26 2001-12-11 Oki Electric Industry Co. Ltd. Micro ball grid array semiconductor device and semiconductor module
US6083766A (en) * 1999-07-01 2000-07-04 Viking Tech Corporation Packaging method of thin film passive components on silicon chip
US6590291B2 (en) * 2000-01-31 2003-07-08 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method therefor
US6265763B1 (en) * 2000-03-14 2001-07-24 Siliconware Precision Industries Co., Ltd. Multi-chip integrated circuit package structure for central pad chip
US6548911B2 (en) * 2000-12-06 2003-04-15 Siliconware Precision Industries Co., Ltd. Multimedia chip package
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6768190B2 (en) * 2002-01-25 2004-07-27 Advanced Semiconductor Engineering, Inc. Stack type flip-chip package
US20050074954A1 (en) * 2002-10-11 2005-04-07 Hideo Yamanaka Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device
US7033664B2 (en) * 2002-10-22 2006-04-25 Tessera Technologies Hungary Kft Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6977431B1 (en) * 2003-11-05 2005-12-20 Amkor Technology, Inc. Stackable semiconductor package and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070042562A1 (en) * 1998-02-06 2007-02-22 Tessera Technologies Hungary Kft. Integrated circuit device
US7781240B2 (en) * 1998-02-06 2010-08-24 Tessera Technologies Hungary Kft. Integrated circuit device
US8592831B2 (en) 1998-02-06 2013-11-26 Invensas Corp. Integrated circuit device
US9530945B2 (en) 1998-02-06 2016-12-27 Invensas Corporation Integrated circuit device

Also Published As

Publication number Publication date
JP2004534375A (en) 2004-11-11
KR100855015B1 (en) 2008-08-28
AU1635202A (en) 2002-07-01
TW546807B (en) 2003-08-11
EP1356718A2 (en) 2003-10-29
EP1356718A4 (en) 2009-12-02
WO2002051217A2 (en) 2002-06-27
US7408249B2 (en) 2008-08-05
US20040183185A1 (en) 2004-09-23
KR20040040404A (en) 2004-05-12
WO2002051217A3 (en) 2003-07-24

Similar Documents

Publication Publication Date Title
US6787394B2 (en) Methods of wafer level fabrication and assembly of chip scale packages
US7312521B2 (en) Semiconductor device with holding member
US5466634A (en) Electronic modules with interconnected surface metallization layers and fabrication methods therefore
US8940636B2 (en) Through hole vias at saw streets including protrusions or recesses for interconnection
US7919844B2 (en) Tier structure with tier frame having a feedthrough structure
US7883991B1 (en) Temporary carrier bonding and detaching processes
US8513789B2 (en) Edge connect wafer level stacking with leads extending along edges
CN1186810C (en) Semiconductor device chip scale surface assembling and packaging, and mfg. method therefor
US5019943A (en) High density chip stack having a zigzag-shaped face which accommodates connections between chips
US6586836B1 (en) Process for forming microelectronic packages and intermediate structures formed therewith
KR100575591B1 (en) CSP for wafer level stack package and manufacturing method thereof
US7192810B2 (en) Semiconductor packaging
US6221751B1 (en) Wafer fabrication of die-bottom contacts for electronic devices
US7712211B2 (en) Method for packaging circuits and packaged circuits
US7919875B2 (en) Semiconductor device with recess portion over pad electrode
US7675169B2 (en) Apparatus and method for packaging circuits
US20040118806A1 (en) Etch thinning techniques for wafer-to-wafer vertical stacks
US5432999A (en) Integrated circuit lamination process
US7075181B2 (en) Semiconductor package having semiconductor constructing body and method of manufacturing the same
US5682062A (en) System for interconnecting stacked integrated circuits
JP3986575B2 (en) Method for producing a three-dimensional integrated circuit
US20030080399A1 (en) Transfer wafer level packaging
JP3649993B2 (en) The method of manufacturing a semiconductor device and a semiconductor device
US5608264A (en) Surface mountable integrated circuit with conductive vias
CN103165477B (en) The method of forming a vertical semiconductor device and the interconnect structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHELLCASE LTD., ISRAEL

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BADIHI, AVNER;REEL/FRAME:016040/0729

Effective date: 20040328

AS Assignment

Owner name: TESSERA TECHNOLOGIES HUNGARY KFT., HUNGARY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHELLCASE LTD., ALSO SOMETIMES KNOWN AS SHELLCASE, LTD.;REEL/FRAME:017552/0170

Effective date: 20060330

CC Certificate of correction
AS Assignment

Owner name: TESSERA TECHNOLOGIES IRELAND LIMITED, IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TESSERA TECHNOLOGIES HUNGARY HOLDING LIMITED LIABILITY COMPANY;REEL/FRAME:025592/0734

Effective date: 20101119

AS Assignment

Owner name: DIGITALOPTICS CORPORATION EUROPE LIMITED, CALIFOR

Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA TECHNOLOGIES IRELAND LIMITED;REEL/FRAME:026739/0875

Effective date: 20110713

AS Assignment

Owner name: DIGITALOPTICS CORPORATION EUROPE LIMITED, IRELAND

Free format text: CORRECTION TO REEL 026739 FRAME 0875 TO CORRECTION THE ADDRESS OF RECEIVING PARTY;ASSIGNOR:TESSERA TECHNOLOGIES IRELAND LIMITED;REEL/FRAME:027137/0397

Effective date: 20110713

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: INVENSAS CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIGITAL OPTICS CORPORATION EUROPE LIMITED;REEL/FRAME:030065/0817

Effective date: 20130318

Owner name: INVENSAS CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIGITALOPTICS CORPORATION EUROPE LIMITED;REEL/FRAME:030065/0817

Effective date: 20130318

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA

Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001

Effective date: 20161201