US20070001245A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
- Publication number
- US20070001245A1 US20070001245A1 US11/071,119 US7111905A US2007001245A1 US 20070001245 A1 US20070001245 A1 US 20070001245A1 US 7111905 A US7111905 A US 7111905A US 2007001245 A1 US2007001245 A1 US 2007001245A1
- Authority
- US
- United States
- Prior art keywords
- impurity
- gate electrode
- source
- ion implantation
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title description 30
- 239000012535 impurity Substances 0.000 claims abstract description 333
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims description 124
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims 2
- 238000004590 computer program Methods 0.000 claims 1
- 238000002513 implantation Methods 0.000 abstract description 19
- 238000005468 ion implantation Methods 0.000 description 243
- 150000002500 ions Chemical class 0.000 description 87
- 230000001133 acceleration Effects 0.000 description 78
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 54
- 229910052796 boron Inorganic materials 0.000 description 54
- 239000010410 layer Substances 0.000 description 51
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 48
- 229910052698 phosphorus Inorganic materials 0.000 description 48
- 239000011574 phosphorus Substances 0.000 description 48
- 238000004380 ashing Methods 0.000 description 39
- 238000004151 rapid thermal annealing Methods 0.000 description 27
- 238000002955 isolation Methods 0.000 description 19
- 230000000149 penetrating effect Effects 0.000 description 16
- 238000005530 etching Methods 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 13
- 229910018999 CoSi2 Inorganic materials 0.000 description 10
- 229910052785 arsenic Inorganic materials 0.000 description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- 229910017052 cobalt Inorganic materials 0.000 description 8
- 239000010941 cobalt Substances 0.000 description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- This invention relates to a semiconductor device having a gate and source-and-drain regions, and a method of fabricating thereof, which are particularly preferable when applied to a CMOS transistor.
- CMOS transistors generally employ a polysilicon gate electrode doped with an n-type impurity for the n-channel MOS transistor (nMOS transistor) composing thereof. This is because the threshold voltage can readily be controlled to desired values.
- the nMOS transistor is turned ON when applied with a positive voltage through the gate electrode, which causes bending of the energy band of polysilicon, and generates a depletion layer within the gate electrode in the vicinity of the interface with a gate insulating film. Such production of the depletion layer undesirably lowers the gate capacitance and thus reduces ON current. To suppress the lowering of the gate capacitance, it is necessary to raise concentration of the n-type impurity within the gate electrode in the vicinity of the interface with the gate insulating film.
- pMOS transistor which employs a polysilicon gate electrode doped with a p-type impurity, where it is also necessary to raise concentration of the p-type impurity within the gate electrode in the vicinity of the interface with the gate insulating film in order to suppress lowering of the gate capacitance during the ON status.
- the source-and-drain regions are formed by ion implantation, where the gate electrodes which serve as masks are also concomitantly doped.
- One known solution for addressing the problem relates to reduction in height of the gate electrode, which can substantially increase the impurity concentration even if the dose of impurity introduced to the gate electrode remains unchanged.
- This solution raises another problem that too low height of the gate electrode may result in punch-through of the impurity introduced into the gate electrode into the channel, which undesirably varies the threshold voltage.
- the technique for reducing the height of gate electrode is thus limitative.
- the present invention is thus to provide a highly-reliable semiconductor device and a method of fabricating thereof, both of which are aimed at raising impurity concentration within the gate electrode without increasing impurity concentration in the source-and-drain regions, and as a consequence at improving gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- a method of fabricating a semiconductor device comprises a first step of patterning a gate electrode above a semiconductor substrate having an element isolation structure previously formed therein; a second step of forming sidewalls covering only on both side faces of the gate electrode; a third step of removing the upper portion of the sidewalls to thereby expose a part of both side faces of the gate electrode; and a fourth step for introducing an impurity into the gate electrode along a direction inclined to the surface of the semiconductor substrate.
- a method of fabricating a semiconductor device comprises a first step of patterning a gate electrode above a semiconductor substrate; a second step of forming a mask having an opening which allows the gate electrode to be exposed therein; and a third step of introducing an impurity into the gate electrode along a direction inclined to the surface of the semiconductor substrate, wherein in the second step, the opening of the mask is formed in a size which ensures protection of areas for forming source-and-drain regions on both sides of the gate electrode from the tilt-angle introduction of the impurity.
- a semiconductor device comprises a gate electrode; source-and-drain regions; sidewalls covering only the lower portion of both side faces of the gate electrode; and a silicide film formed on the exposed surface of the gate electrode, wherein the gate electrode contains an impurity having a conductivity type same as that of the impurity contained in the source-and-drain regions, and the gate electrode has an impurity concentration larger than that of the source-and-drain regions.
- FIG. 1 is a schematic sectional view showing a major principle of a first technique
- FIG. 2 is a schematic sectional view showing a major principle of a second technique
- FIG. 3 is a schematic sectional view showing an exemplary case of a combination of the first and second techniques
- FIGS. 4A to 4 D are schematic sectional views sequentially showing process steps of a method of fabricating a CMOS transistor according to a first embodiment
- FIGS. 5A to 5 D are schematic sectional views sequentially showing process steps as continued from FIG. 4D ;
- FIGS. 6A and 6B are schematic sectional views sequentially showing process steps as continued from FIG. 5D ;
- FIGS. 7A to 7 D are schematic sectional views sequentially showing process steps as continued from FIG. 6B ;
- FIGS. 8A to 8 D are schematic sectional views sequentially showing process steps as continued from FIG. 7D ;
- FIG. 9 is a plan view for explaining tilt-angled ion implantation
- FIG. 10 is a plan view for explaining a modified example of tilt-angled ion implantation in the first embodiment
- FIGS. 11A to 11 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a second embodiment
- FIGS. 12A to 12 D are sequentially showing major process steps of a method of fabricating a CMOS transistor according to a third embodiment
- FIGS. 13A to 13 D are schematic sectional views sequentially showing process steps as continued from FIG. 12D ;
- FIG. 14 is a plan view for explaining tilt-angled ion implantation
- FIGS. 15A to 15 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fourth embodiment
- FIGS. 16A to 16 D are schematic sectional views sequentially showing process steps as continued from FIG. 15D ;
- FIG. 17 is a plan view for explaining tilt-angled ion implantation
- FIGS. 18A to 18 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fifth embodiment
- FIGS. 19A to 19 D are schematic sectional views sequentially showing process steps as continued from FIG. 18D ;
- FIG. 20 is a plan view for explaining tilt-angled ion implantation
- FIGS. 21A to 21 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a sixth embodiment
- FIGS. 22A to 22 D are schematic sectional views sequentially showing process steps as continued from FIG. 21D ;
- FIGS. 23A to 23 D are schematic sectional views sequentially showing process steps as continued from FIG. 22D ;
- FIG. 24 is a plan view for explaining tilt-angled ion implantation
- FIGS. 25A to 25 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a seventh embodiment
- FIGS. 26A to 26 D are schematic sectional views sequentially showing process steps as continued from FIG. 25D ;
- FIGS. 27A to 27 C are schematic sectional views sequentially showing process steps as continued from FIG. 26D ;
- FIGS. 28A to 28 C are schematic sectional views sequentially showing process steps of a method of fabricating a CMOS transistor according to a modified example of the seventh embodiment
- FIGS. 29A to 29 C are schematic sectional views sequentially showing process steps as continued from FIG. 28C ;
- FIGS. 30A to 30 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a eighth embodiment
- FIGS. 31A to 31 D are schematic sectional views sequentially showing process steps as continued from FIG. 30D ;
- FIGS. 32A to 32 D are schematic sectional views sequentially showing process steps as continued from FIG. 31D ;
- FIGS. 33A to 33 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a ninth embodiment
- FIGS. 34A to 34 C are schematic sectional views sequentially showing process steps as continued from FIG. 33D ;
- FIG. 35 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the gate electrode in the fourth and fifth embodiments;
- FIG. 36 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the fourth and fifth embodiments;
- FIG. 37 is a characteristic chart showing a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the fourth and fifth embodiments;
- FIG. 38 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the gate electrode in the sixth through ninth embodiments;
- FIG. 39 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the sixth through ninth embodiments;
- FIG. 40 is a characteristic chart showing a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the sixth through ninth embodiments.
- FIG. 41 is a block diagram showing an internal constitution of a general personal user terminal device.
- the present inventors reached an idea of a semiconductor device in which the gate electrode is designed to have an impurity concentration higher than that of the source-and-drain regions, and proposed, as a specific technique for realizing such semiconductor device, a method of fabricating thereof as explained below.
- FIG. 1 A major principle of a first technique is shown in FIG. 1 .
- sidewalls 103 are formed on both side faces of a gate electrode 102 . Portions of a semiconductor substrate 101 which fall on both sides of the gate electrode 102 and sidewalls 103 serve as source-and-drain (S/D) regions 104 , respectively.
- S/D source-and-drain
- the sidewalls 103 are over-etched to thereby allow the upper portion of the gate electrode 102 to be exposed.
- the gate electrode 102 herein is remained so as to expose an area extending from the top surface thereof to the upper portion of both side faces thereof.
- an impurity having a conductivity same as that doped in the source-and-drain regions is then implanted into the exposed surface of the gate electrode 102 from a direction inclined to the surface of the semiconductor substrate 101 .
- the gate electrode 102 herein is doped with the impurity in its top surface and in the upper portion of one side face (indicated with reference numeral 102 a in the figure). Since the impurity can rapidly diffuse in polysilicon, the impurity rapidly diffuses during the later annealing to thereby attain a uniform distribution. That is, carrying out of the tilt-angled ion implantation is nearly worth ion implantation repeated twice, and can raise the impurity concentration at the interface with the gate insulating film as compared with that attainable by vertical ion implantation.
- either of the source-and-drain regions 104 is introduced with the impurity only in a dose corresponding to a single implantation (indicated with reference numeral 104 a in the figure), where the other region is not introduced at all, or only slightly introduced (indicated with reference numeral 104 b ) although being almost not influential.
- the impurity concentration of the gate electrode 102 can be raised to a desired degree as compared with that of the source-and-drain regions 104 , while varying the direction of implantation [typically once each in the directions opposed along the width of the gate electrode 102 (referred to as a direction normal to the gate length, hereinafter) and once each in the directions opposed along the length of the gate electrode (referred to as a direction parallel to the gate length)].
- FIG. 2 A major principle of a second technique is shown in FIG. 2 .
- a resist mask 105 having an opening 105 a which is formed in a size allowing the gate electrode 102 to expose therein and allowing the source-and-drain regions 104 to be protected (prevented) from the tilt-angled ion implantation, is formed, and the tilt-angled ion implantation is carried out in this situation. Also in this case, the tilt-angled ion implantation is carried out in a plural number of times while varying the direction of implantation.
- the gate electrode 102 herein is doped with the impurity in its top surface and in the upper portion of one side face (indicated with reference numeral 102 a in the figure). Since the impurity can rapidly diffuse in polysilicon, the impurity rapidly diffuses during the later annealing to thereby attain a uniform distribution. That is, a single tilt-angled ion implantation is nearly worth ion implantation repeated twice, and can raise the impurity concentration at the interface with the gate insulating film as compared with that attainable by vertical ion implantation.
- FIGS. 4A through 8D are schematic sectional views sequentially showing process steps of a method of fabricating a CMOS transistor.
- trenches are formed in an element isolation region of a semiconductor substrate 1 , filled with an insulating material such as silicon oxide, and the surface thereof is planarized typically by CMP (chemical mechanical polishing) to thereby form a STI-type (shallow trench isolation-type) element isolation structures 2 .
- This partitions element active regions on the semiconductor substrate 1 which are an nMOS region 11 and a pMOS region 12 .
- a resist mask 13 is formed so as to cover the pMOS region 12 , and a p-type impurity is introduced by ion implantation into the nMOS region 11 , to thereby form a p-well 3 , and a channel stopper layer (not shown) in the surficial portion of the substrate.
- the resist mask 13 is removed typically by ashing, a resist mask 14 is formed so as to cover the nMOS region 11 as shown in FIG. 4C , and an n-type impurity is introduced by ion implantation into the PMOS region 12 , to thereby form an n-well 4 , and a channel stopper layer (not shown) in the surficial portion of the substrate.
- the resist mask 14 is removed typically by ashing, and, as shown in FIG. 4D , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for 3 seconds to thereby restore the substrate from damage caused by introduction of the impurities into the wells 3 , 4 and channel stopper layers.
- RTA rapid thermal annealing
- a thin gate insulating film 5 is formed on the surface of the semiconductor substrate 1 by thermal oxidation, and further thereon, a non-doped polysilicon film 15 is deposited by the CVD process as shown in FIG. 5B .
- the polysilicon film 15 and the gate insulating film 5 are patterned by photolithography and succeeding dry etching to thereby form gate electrodes 6 a , 6 b of approx. 100 nm high and approx. 50 nm wide on the gate insulating film 5 in the nMOS and PMOS regions 11 , 12 , respectively, as shown in FIG. 5C .
- the polysilicon film 15 has no impurity previously introduced therein, because polysilicon doped with an n-type impurity and that doped with a p-type impurity generally differ in the etchrate, which makes it difficult to form respective gate electrodes of nMOS transistor and pMOS transistor at a same time.
- a resist mask 16 is formed so as to cover the PMOS region 12 , and an n-type impurity, which is arsenic (As) herein, is introduced by vertical ion implanted into the nMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6 ⁇ 10 14 /cm 2 , and also a p-type impurity, which is boron (B) herein, is introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8 ⁇ 10 12 /cm 2 , and an angle of incidence of 30° from four directions, to thereby form n-type extension layers 7 a and p -type pocket layers 8 a , respectively.
- n-type impurity which is arsenic (As) herein
- a resist mask 17 is formed so as to cover the nMOS region 11 as shown in FIG. 6A , and a p-type impurity, which is boron (B) herein, is introduced by vertical ion implantation into the pMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6 ⁇ 10 14 /cm 2 , and also an n-type impurity, which is arsenic (As) herein, is introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6 ⁇ 10 12 /cm 2 , and an angle of incidence of 30° from four directions, to thereby form p-type extension layers 7 b and n -type pocket layers 8 a , respectively.
- a p-type impurity which is boron (B) herein
- the resist mask 17 is removed typically by ashing, and, as shown in FIG. 6B , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore the substrate from damage generated by introduction of the impurities into the extension layers 7 a , 7 b and pocket layers 8 a , 8 b.
- RTA rapid thermal annealing
- a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the gate electrodes 6 a , 6 b , to thereby form sidewalls 9 a , 9 b having a maximum width of 80 nm or around, as shown in FIG. 7A .
- a resist mask 18 is formed so as to cover the pMOS region 12 as shown in FIG. 7B , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 4.5 ⁇ 10 15 /cm 2 and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a .
- the dose of phosphorus in this process is controlled to a smaller value (6 ⁇ 10 15 /cm 2 , for example) than that in general formation process of n-type, source-and-drain regions.
- a p-type impurity which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV, a dose of 2.25 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b .
- Boron herein is also implanted into the gate electrode 6 b .
- the dose of boron in this process is controlled to a smaller value (3 ⁇ 10 15 /cm 2 , for example) than that in general formation process of p-type, source-and-drain regions.
- the resist mask 19 is removed typically by ashing, and the sidewalls 9 a , 9 b are dry-etched (over-etched) to thereby allow the upper portion of both side faces of the gate electrodes 6 a , 6 b to expose as much as 50 nm or around as shown in FIG. 7D .
- the gate electrodes 6 a , 6 b herein are remained so as to expose an area extending from the top surface thereof to the upper portion of both side faces thereof, and the sidewalls 9 a , 9 b are adjusted so as to have a height of 50 nm or around.
- the gate electrodes 6 a , 6 b are subjected to tilt-angled ion implantation described later, the more the sidewalls 9 a , 9 b are etched, the more the gate electrodes 6 a , 6 b will have an impurity incorporated therein. Too much amount of etching of the sidewalls 9 a , 9 b may, however, result in excessive diffusion of the incorporated impurities in the source-and-drain regions 10 a , 10 b towards the channel, or may raise a risk of short-circuiting between silicides, which are formed later on the source-and-drain regions 10 a , 10 b and on the gate electrodes 6 a , 6 b . Thus there is an appropriate range for the amount of etching of the sidewalls 9 a , 9 b , and 50 nm is one exemplary amount falls within such range.
- the sidewalls 9 a , 9 b and STI-type element isolation structure 2 it is preferable to use different materials to form the sidewalls 9 a , 9 b and STI-type element isolation structure 2 so that the sidewalls 9 a , 9 b will have a higher etchrate than that of the element isolation structure 2 .
- One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-type element isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for the sidewalls 9 a , 9 b.
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 a ).
- a resist mask 21 is formed so as to cover the pMOS region 12 , and an n-type impurity, which is phosphorus (P) herein, is implanted at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto). The ion implantation repeated four times is shown in a schematic plan view in FIG. 9 .
- FIG. 8A shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of the gate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one n-type, source-and-drain region 10 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. Another n-type, source-and-drain region 10 a , which is shadowed by the gate electrode 6 a , is not introduced with the impurity, or introduced only in a less affective amount.
- a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the gate electrode 6 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both n-type, source-and-drain regions 10 a in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°.
- the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated six times, in addition to a dose of 4.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 7.5 ⁇ 10 15 /cm 2 .
- each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated three times, in addition to a dose of 4.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 6 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 a , to prevent the impurity from penetrating the sidewall 10 a and gate electrode 6 a and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel.
- a p-type impurity is implanted into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 b ).
- a resist mask 21 is removed typically by ashing, and a resist mask 22 is formed so as to cover the nMOS region 11 , and a p-type impurity, which is boron (B) herein, is implanted at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto).
- FIG. 8B shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of the gate electrode 6 b herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one p-type, source-and-drain region 10 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. Another p-type, source-and-drain region 10 b , which is shadowed by the gate electrode 6 b , is not introduced with the impurity, or introduced only in a less affective amount.
- a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the gate electrode 6 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both p-type, source-and-drain regions 10 b in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated six times, in addition to a dose of 2.25 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3.75 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated three times, in addition to a dose of 2.25 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 b , to prevent the impurity from penetrating the sidewall 10 b and gate electrode 6 b and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the p-type, source-and-drain region 10 b from diffusing toward the channel.
- the resist mask 22 is removed typically by ashing, and, as shown in FIG. 8C , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- RTA rapid thermal annealing
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 8D .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the first embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by forming the sidewalls 9 a , 9 a so as to expose the upper portion of the gate electrodes 6 a , 6 b , and by carrying out the ion implantation at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx.
- the present embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the present invention is by no means limited to mode of the ion implantation in the first embodiment described in the above, where conditions for the first ion implantation for forming the source-and-drain regions or successive tilt-angled ion implantations can properly be selected provided that the impurity concentration of the gate electrodes can be raised without increasing the impurity concentration of the source-and-drain regions.
- the first ion implantation of phosphorus for forming the n-type, source-and-drain region 10 a is carried out at an ion acceleration energy of 8 keV, a dose of 5.5 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 and an angle of incidence of 45°.
- the gate electrode 6 a By the ion implantation repeated twice, as shown later in Table 1, the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated four times, in addition to a dose of 5.5 ⁇ 10 ⁇ 5 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 7.5 ⁇ 10 15 /cm 2 .
- each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 5.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 6 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation of boron for forming the p-type, source-and-drain region 10 b is carried out at an ion acceleration energy of 4 keV, a dose of 2.75 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length individually at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 and an angle of incidence of 45°.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated four times, in addition to a dose of 2.75 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3.75 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 2.75 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- FIGS. 11A to 11 D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a second embodiment.
- the individual process steps previously shown in FIGS. 4A through 8B are executed to thereby control the dose of phosphorus to 7.5 ⁇ 10 15 /cm 2 for the gate electrode 6 a and 6 ⁇ 10 15 /cm 2 for the n-type, source-and-drain region 10 a in the nMOS region 11 , and the dose of boron to 3.75 ⁇ 10 15 /cm 2 for the gate electrode 6 b and 3 ⁇ 10 15 /cm 2 for the p-type, source-and-drain region 10 b in the pMOS region 12 .
- the semiconductor substrate 1 is then annealed by RTA at 1,030° C. for 1 second ( FIG. 11A ).
- a silicon oxide film 27 is formed over the entire surface by the CVD process, and then as shown in FIG. 1C , the silicon oxide film 27 is then anisotropically etched back so as to allow the film to remain only on both side faces of the gate electrodes 6 a , 6 b , to thereby form sidewalls 9 a , 9 b . That is, the sidewalls 9 a , 9 b now recover the status previously shown in FIG. 7A .
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 11D .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the second embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by forming the sidewalls 9 a , 9 a so as to expose the upper portion of the gate electrodes 6 a , 6 b , and by carrying out the ion implantation at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx.
- the present embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the second embodiment is also successful in certainly prevent short-circuiting between CoSi 2 formed on the source-and-drain regions 10 a , 10 b and CoSi 2 formed on the gate electrodes 6 a , 6 b , since the sidewalls 9 a , 9 b recover their initial form almost completely covering the side faces of the gate electrodes before the CoSi 2 layer 23 is formed.
- the sidewalls 9 a , 9 b can thoroughly be over-etched in preparation for the tilt-angled ion implantation without anticipating the short-circuiting. It is therefore also preferable to raise the amount of over-etching larger than that in the first embodiment (50%), to thereby further increase dose of implanted ion in the gate electrodes 6 a , 6 b.
- conditions for the first ion implantation for forming the source-and-drain regions or successive tilt-angled ion implantations can properly be selected provided that the impurity concentration of the gate electrodes can be raised without increasing the impurity concentration of the source-and-drain regions.
- the first ion implantation of phosphorus for forming the n-type, source-and-drain region 10 a is carried out at an ion acceleration energy of 8 keV, a dose of 5.5 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 and an angle of incidence of 45°.
- the gate electrode 6 a By the ion implantation repeated twice, as shown later in Table 1, the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated four times, in addition to a dose of 5.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 7.5 ⁇ 10 15 /cm 2 .
- each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 5.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 6 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation of boron for forming the p-type, source-and-drain region 10 b is carried out at an ion acceleration energy of 4 keV, a dose of 2.75 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, and the tilt-angled ion implantation of boron is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 and an angle of incidence of 45°.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated four times, in addition to a dose of 2.75 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3.75 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 2.75 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- FIGS. 12A through 13D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a third embodiment.
- the individual process steps previously shown in FIGS. 4A through 6B are executed to thereby form the sidewalls 9 a , 9 b which cover both side faces of the gate electrodes 6 a , 6 b and having a maximum width of 80 nm or around ( FIG. 12A ).
- the resist mask 18 is formed so as to cover the pMOS region 12 , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 5 ⁇ 10 15 /cm 2 , and an angle of incidence of 0°, to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a .
- the dose of phosphorus in this process is controlled to a smaller value (6 ⁇ 10 15 /cm 2 , for example) than that in general formation process of n-type, source-and-drain regions.
- the resist mask 18 is removed typically by ashing, the resist mask 19 is formed so as to cover the nMOS region 11 as shown in FIG. 12C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV, a dose of 2.5 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b . Boron herein is also implanted into the gate electrode 6 b . The dose of boron in this process is controlled to a smaller value (3 ⁇ 10 5 /cm 2 , for example) than that in general formation process of p-type, source-and-drain regions.
- a p-type impurity which is boron (B) herein
- the resist mask 19 is removed typically by ashing, and the sidewalls 9 a , 9 b are dry-etched (over-etched) to thereby allow the upper portion of both side faces of the gate electrodes 6 a , 6 b to expose as much as 50 nm or around as shown in FIG. 12D .
- the gate electrodes 6 a , 6 b herein are remained so as to expose an area extending from the top surface thereof to the upper portion of both side faces thereof, and the sidewalls 9 a , 9 b are adjusted so as to have a height of 50 nm or around.
- the gate electrodes 6 a , 6 b are subjected to tilt-angled ion implantation described later, the more the sidewalls 9 a , 9 b are etched, the more the gate electrodes 6 a , 6 b will have an impurity incorporated therein. Too much amount of etching of the sidewalls 9 a , 9 b may, however, result in excessive diffusion of the incorporated impurity in the source-and-drain regions 10 a , 10 b towards the channel, or may raise a risk of short-circuiting between silicides, which are formed later on the source-and-drain regions 10 a , 10 b and on the gate electrodes 6 a , 6 b . Thus there is an appropriate range for the amount of etching of the sidewalls 9 a , 9 b , and 50 nm is one exemplary amount falls within such range.
- the sidewalls 9 a , 9 b and STI-type element isolation structure 2 it is preferable to use different materials to form the sidewalls 9 a , 9 b and STI-type element isolation structure 2 so that the sidewalls 9 a , 9 b will have a higher etchrate than that of the element isolation structure 2 .
- One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-type element isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for the sidewalls 9 a , 9 b.
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 a ).
- the resist mask 21 is formed so as to cover the pMOS region 12 , and an n-type impurity, which is phosphorus (P) herein, is implanted at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). The ion implantation repeated four times is shown in a schematic plan view in FIG. 14 .
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one n-type, source-and-drain region 10 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°.
- Another n-type, source-and-drain region 10 a which is shadowed by the gate electrode 6 a , is not introduced with the impurity, or introduced only in a less affective amount.
- the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated eight times, in addition to a dose of 5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 9 ⁇ 10 15 /cm 2 .
- each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 6 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 a , to prevent the impurity from penetrating the sidewall 10 a and gate electrode 6 a and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel.
- a p-type impurity is implanted into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 b ).
- the resist mask 21 is removed typically by ashing, and the resist mask 22 is formed so as to cover the nMOS region 11 , and a p-type impurity, which is boron (B) herein, is implanted at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one p-type, source-and-drain region 10 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°.
- Another p-type, source-and-drain region 10 b which is shadowed by the gate electrode 6 b , is not introduced with the impurity, or introduced only in a less affective amount.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated eight times, in addition to a dose of 2.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 4.5 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 2.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 b , to prevent the impurity from penetrating the sidewall 10 b and gate electrode 6 b and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the p-type, source-and-drain region 10 b from diffusing toward the channel.
- the resist mask 22 is removed typically by ashing, and, as shown in FIG. 13C , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- RTA rapid thermal annealing
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 13D .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the third embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by forming the sidewalls 9 a , 9 a so as to expose the upper portion of the gate electrodes 6 a , 6 b , and by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx.
- the third embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- FIGS. 15A through 16D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fourth embodiment.
- the individual process steps previously shown in FIGS. 4A through 6B are executed to thereby form the sidewalls 9 a , 9 b which cover both side faces of the gate electrodes 6 a , 6 b and having a maximum width of 80 nm or around ( FIG. 15A ).
- the resist mask 18 is formed so as to cover the pMOS region 12 , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 5 ⁇ 10 15 /cm 2 , and an angle of incidence of 0°, to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a .
- the dose of phosphorus in this process is controlled to a smaller value (6 ⁇ 10 15 /cm 2 , for example) than that in general formation process of n-type, source-and-drain regions.
- the resist mask 18 is removed typically by ashing, the resist mask 19 is formed so as to cover the nMOS region 11 as shown in FIG. 15C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV, a dose of 2.5 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b . Boron herein is also implanted into the gate electrode 6 b . The dose of boron in this process is controlled to a smaller value (3 ⁇ 10 15 /cm 2 , for example) than that in general formation process of p-type, source-and-drain regions.
- a p-type impurity which is boron (B) herein
- the resist mask 19 is removed typically by ashing, and the sidewalls 9 a , 9 b are dry-etched (over-etched) to thereby allow the upper portion of both side faces of the gate electrodes 6 a , 6 b to expose as much as 50 nm or around as shown in FIG. 15D .
- the gate electrodes 6 a , 6 b herein are remained so as to expose an area extending from the top surface thereof to the upper portion of both side faces thereof, and the sidewalls 9 a , 9 b are adjusted so as to have a height of 50 nm or around.
- the gate electrodes 6 a , 6 b are subjected to tilt-angled ion implantation described later, the more the sidewalls 9 a , 9 b are etched, the more the gate electrodes 6 a , 6 b will have an impurity incorporated therein. Too much amount of etching of the sidewalls 9 a , 9 b may, however, result in excessive diffusion of the incorporated impurity in the source-and-drain regions 10 a , 10 b towards the channel, or may raise a risk of short-circuiting between silicides, which are formed later on the source-and-drain regions 10 a , 10 b and on the gate electrodes 6 a , 6 b . Thus there is an appropriate range for the amount of etching of the sidewalls 9 a , 9 b , and 50 nm is one exemplary amount falls within such range.
- the sidewalls 9 a , 9 b and STI-type element isolation structure 2 it is preferable to use different materials to form the sidewalls 9 a , 9 b and STI-type element isolation structure 2 so that the sidewalls 9 a , 9 b will have a higher etchrate than that of the element isolation structure 2 .
- One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-type element isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for the sidewalls 9 a , 9 b.
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 a ).
- a resist mask 31 is formed so as to cover the PMOS region 12 , which mask 31 having an opening 31 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation.
- the resist mask 31 herein is approx. 120 nm high, and the opening 31 a has an edge 120 nm away from the edge of the gate electrode 6 a .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- n-type impurity which is phosphorus (P) herein, is implanted into the nMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from four directions differing from each other (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto).
- the ion implantation repeated four times is shown in a schematic plan view in FIG. 17 .
- FIG. 16A shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of the gate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of n-type, source-and-drain regions 10 a are protected by the resist mask 31 against the ion implantation, and are thus prevented from being implanted with the impurity.
- a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the gate electrode 6 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both n-type, source-and-drain regions 10 a in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°.
- the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated six times, in addition to a dose of 5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 8 ⁇ 10 15 /cm 2 .
- each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 6 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 a , to prevent the impurity from penetrating the sidewall 10 a and gate electrode 6 a and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel.
- a p-type impurity is implanted along a direction inclined into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 b ).
- the resist mask 31 is removed typically by ashing, and a resist mask 32 is formed so as to cover the nMOS region 11 , which mask 32 having an opening 32 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation.
- the resist mask 32 herein is approx. 120 nm high, and the opening 32 a has an edge 120 nm away from the edge of the gate electrode 6 b .
- a p-type impurity which is boron (B) herein, is implanted into the pMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from four directions differing from each other (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto).
- FIG. 16B shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of the gate electrode 6 b herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resist mask 32 against the ion implantation, and are thus prevented from being implanted with the impurity.
- a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the gate electrode 6 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both p-type, source-and-drain regions 10 b in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated six times, in addition to a dose of 2.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 4 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 2.5 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 3 ⁇ 10 15 /cm 2 (same level with that of general source-and-drain region).
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 b , to prevent the impurity from penetrating the sidewall 10 b and gate electrode 6 b and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the p-type, source-and-drain region 10 b from diffusing toward the channel.
- the resist mask 32 is removed typically by ashing, and, as shown in FIG. 16C , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- RTA rapid thermal annealing
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 16D .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the fourth embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by forming the sidewalls 9 a , 9 a so as to expose the upper portion of the gate electrodes 6 a , 6 b , and by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx.
- the fourth embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the source-and-drain regions 10 a , 10 b are successfully prevented from being implanted with the impurities by virtue of the resist masks 31 , 32 , and only the gate electrodes 6 a , 6 b are implanted with impurity ions. This strongly ensures the gate electrodes 6 a , 6 b to have a higher impurity concentration than the source-and-drain regions 10 a , 10 b have.
- conditions for the first ion implantation for forming the source-and-drain regions or successive tilt-angled ion implantations can properly be selected provided that the impurity concentration of the gate electrodes can be raised without increasing the impurity concentration of the source-and-drain regions.
- the first ion implantation of phosphorus for forming the n-type, source-and-drain region 10 a is carried out at an ion acceleration energy of 8 keV, a dose of 6 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 and an angle of incidence of 450.
- the gate electrode 6 a By the ion implantation repeated twice, as shown later in Table 1, the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated four times, in addition to a dose of 6 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 8 ⁇ 10 15 /cm 2 .
- each n-type, source-and-drain region 10 a will contain the impurity only in an amount of 6 ⁇ 10 15 /cm 2 which has initially been attained, which will be at the same level with that of general source-and-drain region.
- the first ion implantation of boron for forming the p-type, source-and-drain region 10 b is carried out at an ion acceleration energy of 4 keV, a dose of 3 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, and the tilt-angled ion implantation of boron is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 and an angle of incidence of 45°.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated four times, in addition to a dose of 3 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 4 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will contain the impurity only in an amount of 3 ⁇ 10 15 /cm 2 which has initially been attained, which will be at the same level with that of general source-and-drain region.
- FIGS. 18A through 19D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fifth embodiment.
- the individual process steps previously shown in FIGS. 4A through 6B are executed to thereby form the sidewalls 9 a , 9 b which cover both side faces of the gate electrodes 6 a , 6 b and having a maximum width of 80 nm or around ( FIG. 18A ).
- the resist mask 18 is formed so as to cover the pMOS region 12 , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6 ⁇ 10 15 /cm 2 , and an angle of incidence of 0°, to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a.
- the resist mask 18 is removed typically by ashing, the resist mask 19 is formed so as to cover the nMOS region 11 as shown in FIG. 18C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV, a dose of 3 ⁇ 10 15 /cm 2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b . Boron herein is also implanted into the gate electrode 6 b.
- a p-type impurity which is boron (B) herein
- the resist mask 19 is removed typically by ashing, and the sidewalls 9 a , 9 b are dry-etched (over-etched) to thereby allow the upper portion of both side faces of the gate electrodes 6 a , 6 b to expose as much as 50 nm or around as shown in FIG. 18D .
- the gate electrodes 6 a , 6 b herein are remained so as to expose an area extending from the top surface thereof to the upper portion of both side faces thereof, and the sidewalls 9 a , 9 b are adjusted so as to have a height of 50 nm or around.
- the gate electrodes 6 a , 6 b are subjected to tilt-angled ion implantation described later, the more the sidewalls 9 a , 9 b are etched, the more the gate electrodes 6 a , 6 b will have an impurity incorporated therein. Too much amount of etching of the sidewalls 9 a , 9 b may, however, result in excessive diffusion of the incorporated impurity in the source-and-drain regions 10 a , 10 b towards the channel, or may raise a risk of short-circuiting between suicides, which are formed later on the source-and-drain regions 10 a , 10 b and on the gate electrodes 6 a , 6 b . Thus there is an appropriate range for the amount of etching of the sidewalls 9 a , 9 b , and 50 nm is one exemplary amount falls within such range.
- the sidewalls 9 a , 9 b and STI-type element isolation structure 2 it is preferable to use different materials to form the sidewalls 9 a , 9 b and STI-type element isolation structure 2 so that the sidewalls 9 a , 9 b will have a higher etchrate than that of the element isolation structure 2 .
- One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-type element isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for the sidewalls 9 a , 9 b.
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 a ).
- a resist mask 33 is formed so as to cover the pMOS region 12 , which mask 33 having an opening 33 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation.
- the resist mask 33 herein is approx. 120 nm high, and the opening 33 a has an edge 120 nm away from the edge of the gate electrode 6 a .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- n-type impurity which is phosphorus (P) herein, is implanted into the nMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). The ion implantation repeated four times is shown in a schematic plan view in FIG. 20 .
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of n-type, source-and-drain regions 10 a are protected by the resist mask 33 against the ion implantation, and are thus prevented from being implanted with the impurity.
- the gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5 ⁇ 10 14 /cm 2 ) repeated eight times, in addition to a dose of 6 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of phosphorus of 1 ⁇ 10 16 /cm 2 .
- each n-type, source-and-drain region 10 a will contain the impurity only in an amount of 6 ⁇ 10 15 /cm 2 which has initially been attained, which will be at the same level with that of general source-and-drain region.
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 a , to prevent the impurity from penetrating the sidewall 10 a and gate electrode 6 a and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel.
- a p-type impurity is implanted into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from the sidewall 9 b ).
- the resist mask 33 is removed typically by ashing, and a resist mask 34 is formed so as to cover the nMOS region 11 , which mask 34 having an opening 34 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation.
- the resist mask 34 herein is approx. 120 nm high, and the opening 34 a has an edge 120 nm away from the edge of the gate electrode 6 b .
- a p-type impurity which is boron (B) herein, is implanted into the pMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of p-type, source-and-drain regions 10 b are protected by the resist mask 34 against the ion implantation, and are thus prevented from being implanted with the impurity.
- the gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5 ⁇ 10 14 /cm 2 ) repeated eight times, in addition to a dose of 3 ⁇ 10 15 /cm 2 which has previously been attained, and thus will have a total dose of boron of 5 ⁇ 10 15 /cm 2 .
- each p-type, source-and-drain region 10 b will contain the impurity only in an amount of 3 ⁇ 10 15 /cm 2 which has initially been attained, which will be at the same level with that of general source-and-drain region.
- the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV.
- the energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating the gate electrode 6 b , to prevent the impurity from penetrating the sidewall 10 b and gate electrode 6 b and intruding into the semiconductor substrate 1 , and to prevent the impurity implanted into the n-type, source-and-drain region 10 b from diffusing toward the channel.
- the resist mask 34 is removed typically by ashing, and, as shown in FIG. 19C , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- RTA rapid thermal annealing
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 19D .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the fifth embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by forming the sidewalls 9 a , 9 a so as to expose the upper portion of the gate electrodes 6 a , 6 b , and by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx.
- the fifth embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the source-and-drain regions 10 a , 10 b are successfully prevented from being implanted with the impurities by virtue of the resist masks 33 , 34 , and only the gate electrodes 6 a , 6 b are implanted with impurity ions. This strongly ensures the gate electrodes 6 a , 6 b to have a higher impurity concentration than the source-and-drain regions 10 a , 10 b have.
- Short-circuiting between the silicides formed on the source-and-drain regions 10 a , 10 b and the silicides formed on the gate electrodes 6 a , 6 b can be prevented by combining the fifth embodiment and second embodiment.
- This desirably increases the amount of etching of the sidewalls 9 a , 9 b than that in the fifth embodiment, and makes it possible to further increase the dose of impurities incorporated into the gate electrodes 6 a , 6 b .
- FIGS. 21A through 23D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a sixth embodiment.
- the individual process steps previously shown in FIGS. 4A through 5C are executed similarly to as described in the first embodiment, to thereby pattern the gate electrodes 6 a , 6 b ( FIG. 21A ).
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide).
- a resist mask 35 is formed so as to cover the pMOS region 12 , which mask 35 having an opening 35 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation.
- the resist mask 35 herein is approx. 120 nm high, and the opening 35 a has an edge 80 nm away from the edge of the gate electrode 6 a .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- n-type impurity which is phosphorus (P) herein, is implanted into the nMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of the gate electrode 6 b .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- a p-type impurity which is boron (B) herein, is implanted into the pMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of p-type, source-and-drain regions 10 b are protected by the resist mask 36 against the ion implantation, and are thus prevented from being implanted with the impurity.
- the resist mask 36 is removed typically by ashing, the resist mask 16 is formed so as to cover the pMOS region 12 as shown in FIG. 21D , and an n-type impurity, which is arsenic (As) herein, is introduced by vertical ion implantation into the nMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8 ⁇ 10 12 /cm 2 and at an angle of incidence of 30° from four directions to thereby form n-type extension layers 7 a and p -type pocket layers 8 a , respectively.
- n-type impurity which is arsenic (As) herein
- the resist mask 16 is removed typically by ashing, the resist mask 17 is formed so as to cover the nMOS region 11 as shown in FIG. 22A , and a p-type impurity, which is boron (B) herein, is introduced by vertical ion implantation into the pMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6 ⁇ 10 12 /cm 2 and at an angle of incidence of 30° from four directions to thereby form p-type extension layers 7 b and n -type pocket layers 8 b , respectively.
- a p-type impurity which is boron (B) herein
- the resist mask 17 is removed typically by ashing, and, as shown in FIG. 22B , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore it from damage caused by the ion implantation into the extension layers 7 a , 7 b and pocket layers 8 a , 8 b.
- RTA rapid thermal annealing
- a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the gate electrodes 6 a , 6 b , to thereby form sidewalls 20 a , 20 b having a maximum width of 80 nm or around, as shown in FIG. 22C .
- a resist mask 18 is formed so as to cover the pMOS region 12 as shown in FIG. 22D , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6 ⁇ 10 15 /cm 2 , and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a.
- the gate electrode 6 a is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 5 ⁇ 10 14 /cm 2 plus 6 ⁇ 10 15 /cm 2 , total 1 ⁇ 10 16 /cm 2 of phosphorus.
- each n-type, source-and-drain region 10 a will have introduced therein the impurity only in an amount of 6 ⁇ 10 15 /cm 2 , into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form COSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 23C .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes as shown in FIG. 23D .
- the sixth embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx. 66%, where the impurity concentration of the gate electrodes 6 a , 6 b can be raised while keeping the general impurity concentration of the source-and-drain regions 10 a , 10 b unchanged.
- the sixth embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the source-and-drain regions 10 a , 10 b are successfully prevented from being implanted with the impurities by virtue of the resist masks 35 , 36 , and only the gate electrodes 6 a , 6 b are implanted with impurity ions. This strongly ensures the gate electrodes 6 a , 6 b to have a higher impurity concentration than the source-and-drain regions 10 a , 10 b have.
- the sixth embodiment is also advantageous in reducing the production cost of CMOS transistor, since a process step of thinning the sidewalls 20 a , 20 b by over-etching is omissible, although the amounts of dose of impurities in the source-and-drain regions 10 a , 10 b and gate electrodes 6 a , 6 b are attainable at the same level with those in the fifth embodiment.
- FIGS. 25A through 27D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a seventh embodiment.
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of n-type, source-and-drain regions 10 a are protected by the resist mask 37 against the ion implantation, and are thus prevented from being implanted with the impurity.
- an n-type impurity which is arsenic (As) herein, is vertically implanted into the nMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8 ⁇ 10 12 /cm 2 and at an angle of incidence of 15° from four directions to thereby form n-type extension layers 7 a and p -type pocket layers 8 a , respectively.
- As arsenic
- a p-type impurity is implanted along a direction inclined into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide).
- the resist mask 37 is removed typically by ashing, and a resist mask 38 is formed so as to cover the nMOS region 11 , which mask 38 having an opening 38 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation.
- the resist mask 38 herein is approx. 120 nm high, and the opening 38 a has an edge 80 nm away from the edge of the gate electrode 6 b .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- a p-type impurity which is boron (B) herein, is implanted into the pMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of p-type, source-and-drain regions 10 b are protected by the resist mask 38 against the ion implantation, and are thus prevented from being implanted with the impurity.
- a p-type impurity which is boron (B) herein, is vertically implanted into the pMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6 ⁇ 10 12 /cm 2 and at an angle of incidence of 15° from four directions to thereby form p-type extension layers 7 b and n -type pocket layers 8 b , respectively.
- B boron
- the resist mask 38 is removed typically by ashing, and, as shown in FIG. 26A , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore it from damage caused by the ion implantation into the extension layers 7 a , 7 b and pocket layers 8 a , 8 b.
- RTA rapid thermal annealing
- a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the gate electrodes 6 a , 6 b , to thereby form sidewalls 9 a , 9 b having a maximum width of 80 nm or around, as shown in FIG. 26B .
- a resist mask 18 is formed so as to cover the pMOS region 12 as shown in FIG. 26C , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6 ⁇ 10 15 /cm 2 , and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a.
- the gate electrode 6 a is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 5 ⁇ 10 14 /cm 2 plus 6 ⁇ 10 15 /cm 2 , total 1 ⁇ 10 16 /cm 2 of phosphorus.
- each n-type, source-and-drain region 10 a will have introduced therein the impurity only in an amount of 6 ⁇ 10 15 /cm 2 , which will be at the same level with that of general source-and-drain region.
- a resist mask 18 is removed typically by ashing, and the resist mask 19 is formed so as to cover the nMOS region 11 as shown in FIG. 26D , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV, a dose of 3 ⁇ 10 15 /cm 2 , and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b . Boron herein is also implanted into the gate electrode 6 b.
- B boron
- the gate electrode 6 b is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 2.5 ⁇ 10 14 /cm 2 plus 3 ⁇ 10 15 /cm 2 , total 5 ⁇ 10 15 /cm 2 of boron.
- each p-type, source-and-drain region 10 b will have introduced therein the impurity only in an amount of 3 ⁇ 10 15 /cm 2 , which will be at the same level with that of general source-and-drain region.
- the resist mask 19 is removed typically by ashing, and, as shown in FIG. 27A , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- RTA rapid thermal annealing
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 27B .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes as shown in FIG. 27C .
- the seventh embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx. 66%, where the impurity concentration of the gate electrodes 6 a , 6 b can be raised while keeping the general impurity concentration of the source-and-drain regions 10 a , 10 b unchanged.
- the seventh embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the source-and-drain regions 10 a , 10 b are successfully prevented from being implanted with the impurities by virtue of the resist masks 37 , 38 , and only the gate electrodes 6 a , 6 b are implanted with impurity ions. This strongly ensures the gate electrodes 6 a , 6 b to have a higher impurity concentration than the source-and-drain regions 10 a , 10 b have.
- the seventh embodiment is also advantageous in further reducing the production cost of CMOS transistor, since a process step of thinning the sidewalls 20 a , 20 b by over-etching is omissible, and since a process step of photolithography for forming the extension layers 7 a , 7 b and pocket layers 8 a , 8 b is omissible, although the amounts of dose of impurities in the source-and-drain regions 10 a , 10 b and gate electrodes 6 a , 6 b are attainable at the same level with those in the fifth embodiment.
- FIGS. 28A through 29C are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a modified example of the seventh embodiment.
- the gate electrode 6 a is subjected to the tilt-angled ion implantation in the presence of the resist mask 37 ( FIG. 28A ).
- the resist mask 37 is trimmed so that the opening 37 a is widened to have an edge recessed by 100 nm from the edge of the gate electrode 6 a.
- an n-type impurity which is arsenic (As) herein, is vertically implanted into the nMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8 ⁇ 10 12 /cm 2 and at an angle of incidence of 30° from four directions to thereby form the n-type extension layers 7 a and p -type pocket layers 8 a , respectively.
- As arsenic
- B boron
- the resist mask 37 is removed typically by ashing, and then similarly to as previously shown in FIG. 25C , the gate electrode 6 b is subjected to the tilt-angled ion implantation in the presence of the resist mask 38 ( FIG. 29A ).
- the resist mask 38 is trimmed so that the opening 38 a is widened to have an edge recessed by 100 nm from the edge of the gate electrode 6 b.
- a p-type impurity which is boron (B) herein, is vertically implanted into the PMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6 ⁇ 10 12 /cm 2 and at an angle of incidence of 30° from four directions to thereby form the p-type extension layers 7 b and n -type pocket layers 8 b , respectively.
- B boron
- As arsenic
- the resist mask 38 is then removed typically by ashing, and a CMOS transistor is completed after executing various process steps similarly to those in the seventh embodiment as shown in FIGS. 26A to 27 C.
- this modified example makes it possible to form the extension layers 7 a , 7 b and pocket layers 8 a , 8 b expanded to desired dimensions at a high degree of freedom by trimming the resist masks 37 , 38 , without limiting dimensions of the extension layers 7 a , 7 b and pocket layers 8 a , 8 b in view of preventing the tilt-angled ion implantation.
- FIGS. 30A through 32D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a eighth embodiment.
- the individual process steps previously shown in FIGS. 4A through 5C are executed similarly to as described in the first embodiment, to thereby pattern the gate electrodes 6 a , 6 b ( FIG. 30A ).
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide).
- the resist mask 35 is formed so as to cover the PMOS region 12 , which mask 35 having the opening 35 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation.
- the resist mask 35 herein is approx. 120 nm high, and the opening 35 a has an edge 80 nm away from the edge of the gate electrode 6 a .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- n-type impurity which is phosphorus (P) herein, is implanted into the nMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of n-type, source-and-drain regions 10 a are protected by the resist mask 35 against the ion implantation, and are thus prevented from being implanted with the impurity.
- a p-type impurity is implanted along a direction inclined into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide).
- the resist mask 35 is removed typically by ashing, and the resist mask 36 is formed so as to cover the nMOS region 11 , which mask 36 having the opening 36 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation.
- the resist mask 36 herein is approx. 120 nm high, and the opening 36 a has an edge 80 nm away from the edge of the gate electrode 6 b .
- a p-type impurity which is boron (B) herein, is implanted into the pMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of p-type, source-and-drain regions 10 b are protected by the resist mask 36 against the ion implantation, and are thus prevented from being implanted with the impurity.
- the resist mask 36 is removed typically by ashing, and, as shown in FIG. 30D , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,050° C. for 1 second to thereby thoroughly diffuse the impurities incorporated into the gate electrodes 6 a , 6 b.
- RTA rapid thermal annealing
- the resist mask 16 is formed so as to cover the pMOS region 12 as shown in FIG. 31A , and an n-type impurity, which is arsenic (As) herein, is introduced by vertical ion implantation into the nMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8 ⁇ 10 12 /cm 2 and at an angle of incidence of 30° from four directions to thereby form the n-type extension layers 7 a and p -type pocket layers 8 a , respectively.
- n-type impurity which is arsenic (As) herein
- the resist mask 16 is removed typically by ashing, the resist mask 17 is formed so as to cover the nMOS region 11 as shown in FIG. 31B , and a p-type impurity, which is boron (B) herein, is introduced by vertical ion implantation into the pMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6 ⁇ 10 14 /cm 2 ; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6 ⁇ 10 12 /cm 2 and at an angle of incidence of 30° from four directions to thereby form the p-type extension layers 7 b and n -type pocket layers 8 b , respectively.
- a p-type impurity which is boron (B) herein
- the resist mask 17 is removed typically by ashing, and, as shown in FIG. 31C , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore it from damage caused by the ion implantation into the extension layers 7 a , 7 b and pocket layers 8 a , 8 b.
- RTA rapid thermal annealing
- a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the gate electrodes 6 a , 6 b , to thereby form sidewalls 9 a , 9 b having a maximum width of 80 nm or around, as shown in FIG. 31D .
- a resist mask 18 is formed so as to cover the pMOS region 12 as shown in FIG. 32A , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6 ⁇ 10 15 /cm 2 , and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a .
- Phosphorus herein is also implanted into the gate electrode 6 a.
- the gate electrode 6 a is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 5 ⁇ 10 14 /cm 2 plus 6 ⁇ 10 15 /cm 2 , total 1 ⁇ 10 16 /cm 2 of phosphorus.
- each n-type, source-and-drain region 10 a will have introduced therein the impurity only in an amount of 6 ⁇ 10 15 /cm 2 , which will be at the same level with that of general source-and-drain region.
- a resist mask 18 is removed typically by ashing, and the resist mask 19 is formed so as to cover the nMOS region 11 as shown in FIG. 32B , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV, a dose of 3 ⁇ 10 15 /cm 2 , and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b . Boron herein is also implanted into the gate electrode 6 b.
- the gate electrode 6 b is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 2.5 ⁇ 10 14 /cm 2 plus 3 ⁇ 10 15 /cm 2 , total 5 ⁇ 10 15 /cm 2 of boron.
- each p-type, source-and-drain region 10 b will have introduced therein the impurity only in an amount of 3 ⁇ 10 15 /cm 2 , which will be at the same level with that of general source-and-drain region.
- the resist mask 19 is removed typically by ashing, and, as shown in FIG. 32C , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,020° C. for one second to thereby restore it from damage caused by ion implantation into the gate electrodes 6 a , 6 b and source-and-drain regions 10 a , 10 b , and to thereby activate the impurities.
- annealing temperature herein in the eighth embodiment can be reduced from 1,030° C. to 1,020° C. since the impurities introduced into the gate electrode 6 a , 6 b have already been activated in the process step shown in FIG. 30D , which is advantageous in further suppressing diffusion of the impurities in the extension layers 7 a , 7 b and pocket layers 8 a , 8 b , and thus suppressing the short-channel effect.
- a silicide-forming metal which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi 2 layers 23 on the exposed surface of the gate electrodes 6 a , 6 b and on the surface of the source-and-drain region 10 a , 10 b as shown in FIG. 32D .
- Co cobalt
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the eighth embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b becomes higher than that of the source-and-drain regions 10 a , 10 b by approx. 66%, where the impurity concentration of the gate electrodes 6 a , 6 b can be raised while keeping the general impurity concentration of the source-and-drain regions 10 a , 10 b unchanged.
- the eighth embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- the source-and-drain regions 10 a , 10 b are successfully prevented from being implanted with the impurities by virtue of the resist masks 35 , 36 , and only the gate electrodes 6 a , 6 b are implanted with impurity ions. This strongly ensures the gate electrodes 6 a , 6 b to have a higher impurity concentration than the source-and-drain regions 10 a , 10 b have.
- the eighth embodiment is also advantageous in reducing the production cost of CMOS transistor, since a process step of thinning the sidewalls 20 a , 20 b by over-etching is omissible, although the amounts of dose of impurities in the source-and-drain regions 10 a , 10 b and gate electrodes 6 a , 6 b are attainable at the same level with those in the fifth embodiment. Still another advantage resides in that the impurity concentration of the gate electrodes 6 a , 6 b can be raised in the vicinity of the gate insulating film 5 , since the semiconductor substrate 1 is once annealed immediately after the gate electrodes 6 a , 6 b are subjected to the tilt-angled ion implantation.
- FIGS. 33A through 34C are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a ninth embodiment.
- the individual process steps previously shown in FIGS. 4A through 5C are executed similarly to as described in the first embodiment, to thereby pattern the gate electrodes 6 a , 6 b ( FIG. 33A ).
- an n-type impurity is implanted along a direction inclined into the nMOS region 11 to thereby introduce the impurity to the exposed surface of the gate electrode 6 a (the top surface of 50 nm wide).
- the resist mask 35 is formed so as to cover the pMOS region 12 , which mask 35 having the opening 35 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation.
- the resist mask 35 herein is approx. 120 nm high, and the opening 35 a has an edge 80 nm away from the edge of the gate electrode 6 a .
- employing the gate electrode as an alignment mark, in place of a mark formed in the STI process can successfully reduce mis-alignment.
- n-type impurity which is phosphorus (P) herein, is implanted into the nMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5 ⁇ 10 14 /cm 2 and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of n-type, source-and-drain regions 10 a are protected by the resist mask 35 against the ion implantation, and are thus prevented from being implanted with the impurity.
- a p-type impurity is implanted along a direction inclined into the pMOS region 12 to thereby introduce the impurity to the exposed surface of the gate electrode 6 b (the top surface of 50 nm wide).
- the resist mask 35 is removed typically by ashing, and the resist mask 36 is formed so as to cover the nMOS region 11 , which mask 36 having the opening 36 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation.
- the resist mask 36 herein is approx. 120 nm high, and the opening 36 a has an edge 80 nm away from the edge of the gate electrode 6 b .
- a p-type impurity which is boron (B) herein, is implanted into the PMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5 ⁇ 10 14 /cm 2 , and an angle of incidence of 45°.
- the implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length).
- a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice.
- a pair of p-type, source-and-drain regions 10 b are protected by the resist mask 36 against the ion implantation, and are thus prevented from being implanted with the impurity.
- the resist mask 36 is removed typically by ashing, and, as shown in FIG. 33D , a resist mask 41 is formed so as to cover the pMOS region 12 , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into the nMOS region 11 at an ion acceleration energy of 8 keV and a dose of 6 ⁇ 10 15 /cm 2 , to thereby form n-type, source-and-drain regions 43 a.
- P phosphorus
- the resist mask 41 is removed typically by ashing, and, as shown in FIG. 34A , a resist mask 42 is formed so as to cover the nMOS region 11 , and an p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV and a dose of 3 ⁇ 10 15 /cm 2 , to thereby form p-type, source-and-drain regions 43 b.
- a resist mask 42 is formed so as to cover the nMOS region 11 , and an p-type impurity, which is boron (B) herein, is introduced by ion implantation into the pMOS region 12 at an ion acceleration energy of 4 keV and a dose of 3 ⁇ 10 15 /cm 2 , to thereby form p-type, source-and-drain regions 43 b.
- the resist mask 42 is removed typically by ashing, and, as shown in FIG. 34B , the semiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for 1 second to thereby thoroughly activate the impurities incorporated into the gate electrodes 6 a , 6 b and the source-and-drain regions 43 a , 43 b.
- RTA rapid thermal annealing
- An interlayer insulating film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25 , and a CMOS transistor is completed after some additional post-processes.
- the ninth embodiment is successful in controlling the impurity concentration of the gate electrodes 6 a , 6 b higher than that of the source-and-drain regions 10 a , 10 b by carrying out the ion implantation from four inclined directions at an angle of incidence of 45°.
- the impurity concentration of the gate electrodes 6 a , 6 b can be raised without altering the general impurity concentration of the source-and-drain regions 10 a , 10 b .
- the ninth embodiment is thus to provide a highly-reliable CMOS transistor having an improved gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode, by a less number of process steps.
- the source-and-drain regions 10 a , 10 b are successfully prevented from being implanted with the impurities by virtue of the resist masks 35 , 36 , and only the gate electrodes 6 a , 6 b are implanted with impurity ions. This strongly ensures the gate electrodes 6 a , 6 b to have a higher impurity concentration than the source-and-drain regions 10 a , 10 b have.
- FIG. 35 shows a method of determining an alignment rule of a resist masks 31 through 34 with respect to the gate electrodes 6 a , 6 b (simply referred to as “gate electrode”, hereinafter), which is applicable to the fourth and fifth embodiments.
- Rp 1 represents the length of the sidewalls 9 a , 9 b (simply referred to as “sidewall” hereinafter) sufficient for shielding impurity implanted along direction inclined
- Rp 2 represents the length of the resist mask sufficient for shielding impurity implanted along direction inclined.
- L 1 ′ is determined so that the projection range of the impurity implanted along a direction inclined in the sidewall will be longer than Rp 1 based on the shape of the over-etched sidewall.
- L 1 ′′ is determined so that the projection range of the impurity implanted along a direction inclined in the resist mask will be longer than Rp 2 .
- L 1 ′ and L 1 ′′ are then compared, the shorter one of which is defined as L 1 , and a rule for the distance between the gate electrode and resist mask can be given as L 1 ⁇ L, where ⁇ L is an alignment error between the gate electrode and resist pattern.
- FIGS. 36 and 37 show a method of determining an alignment rule for the case with aligned gate electrodes in the fourth and fifth embodiments.
- Rp 3 herein represents the length of the gate electrode sufficient for shielding impurity implanted along direction inclined.
- L 2 ′ is determined so that the projection range of the impurity implanted along a direction inclined in the over-etched sidewall will be longer than Rp 1 based on the shape of the over-etched sidewall.
- L 2 ′′′ is determined so as to allow the projection range of the impurity implanted along a direction inclined in the gate electrode impurity will be longer than Rp 3 .
- L 2 ′ and L 2 ′′′ are then compared, and the shorter one of which is defined as L 2 . Assuming now a minimum formable width of a resist pattern 111 as L 3 . If the distance between the adjacent gate electrodes is longer than 2(L 1 ⁇ L)+L 3 , the resist pattern 111 can be formed between the adjacent gate electrodes according to the rule shown in FIG. 37 .
- the distance between the adjacent gate electrodes is shorter than 2(L 1 ⁇ L)+L 3 but longer than L 2 , it is necessary to fill the space between the adjacent gate electrodes with a resist pattern 111 having a width of L 3 . If the distance between the adjacent gate electrodes is shorter than L 2 , there is no need to form the resist pattern 111 between the adjacent gate electrodes.
- FIG. 38 shows a method of determining an alignment rule of a resist masks 35 through 38 , 41 and 42 with respect to the gate electrode, which is applicable to the sixth through ninth embodiments.
- Rp 2 represents the length of the resist mask sufficient for shielding impurity implanted along direction inclined
- Rp 3 represents the length of the gate electrode sufficient for shielding impurity implanted along direction inclined.
- L 1 ′′ is determined so that the projection range of the impurity implanted along a direction inclined in the resist mask will be longer than Rp 2 .
- L 1 ′′′ is determined so that the projection range of the impurity implanted along a direction inclined in the gate electrode will be longer than Rp 3 .
- L 1 ′′ and L 1 ′′′ are then compared, the shorter one of which is defined as L 1 , and a rule for the distance between the gate electrode and resist mask can be given as L 1 ⁇ L, where ⁇ L is an alignment error between the ate electrode and resist pattern.
- FIGS. 39 and 40 show a method of determining a rule for the case with aligned gate electrodes in the sixth through ninth embodiments.
- Rp 3 herein represents the length of the gate electrode sufficient for shielding impurity implanted along direction inclined.
- L 2 is determined so that the projection range of the impurity implanted along a direction inclined in the gate electrode will be longer than Rp 3 . If the distance between the adjacent gate electrodes is longer than 2(L 1 ⁇ L)+L 3 , the resist pattern 111 as a part of the resist mask can be formed between the adjacent gate electrodes according to the rule shown in FIG. 40 , where L 3 is a minimum formable width of the resist pattern 111 .
- the distance between the adjacent gate electrodes is shorter than 2(L 1 ⁇ L)+L 3 but longer than L 2 , it is necessary to fill the space between the adjacent gate electrodes with a resist pattern 111 having a width of L 3 . If the distance between the adjacent gate electrodes is shorter than L 2 , there is no need to form the resist pattern 111 between the adjacent gate electrodes.
- This embodiment materializes a CAD software for producing a resist mask according to the rule explained referring to FIGS. 35 to 40 .
- This makes it possible to readily produce a reticle for forming the resist mask which can prevent the impurity introduced along a direction tilt-angled from getting into the source-and-drain region.
- This can be realized by running a program stored in an RAM or ROM of a computer. Also such program and a computer-readable storage medium having recorded therein such program also fall within a scope of the present invention.
- the program is provided to a computer while being stored in a recording medium such as CD-ROM, or other various transmission media.
- the recording media besides CD-ROM, capable of storing the program include flexible disk, hard disk, magnetic tape, magneto-optical disk and non-volatile memory card.
- the transmission media for the program include a communication medium (such as connected line such as using optical fiber, or radio line) in a computer network system (e.g., LAN, WAN such as the Internet, radio communication network), whereby program information is transmitted as being modulated by a carrier wave.
- the aforementioned program fall within a scope of the present invention not only for the case where the functions of the above-described embodiments are materialized by the supplied program run on a computer, but also for the case where the functions of the above-described embodiments are realized by the program in cooperation with an OS (operating system) run on the computer or with any other application software, and for the case where the functions of the above-described embodiments are realized by the whole or a part of the program executed on a function expansion board or function expansion unit of the computer.
- OS operating system
- FIG. 41 shows a block diagram of an internal constitution of a general personal user terminal device.
- reference numeral 1200 denotes computer PC.
- the PC 1200 has a CPU 1201 , which is designed to execute a device control software stored in a ROM 1202 or a hard disk (HD) 1211 , or supplied from a flexible disk drive (FD) 1212 , so as to totally control the individual devices connected to a system bus.
- a device control software stored in a ROM 1202 or a hard disk (HD) 1211 , or supplied from a flexible disk drive (FD) 1212 , so as to totally control the individual devices connected to a system bus.
- HD hard disk
- FD flexible disk drive
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-254672, filed on Aug. 30, 2002, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- This invention relates to a semiconductor device having a gate and source-and-drain regions, and a method of fabricating thereof, which are particularly preferable when applied to a CMOS transistor.
- 2. Description of the Related Art
- Conventional CMOS transistors generally employ a polysilicon gate electrode doped with an n-type impurity for the n-channel MOS transistor (nMOS transistor) composing thereof. This is because the threshold voltage can readily be controlled to desired values. The nMOS transistor is turned ON when applied with a positive voltage through the gate electrode, which causes bending of the energy band of polysilicon, and generates a depletion layer within the gate electrode in the vicinity of the interface with a gate insulating film. Such production of the depletion layer undesirably lowers the gate capacitance and thus reduces ON current. To suppress the lowering of the gate capacitance, it is necessary to raise concentration of the n-type impurity within the gate electrode in the vicinity of the interface with the gate insulating film.
- The same will apply to the p-channel MOS transistor (pMOS transistor) which employs a polysilicon gate electrode doped with a p-type impurity, where it is also necessary to raise concentration of the p-type impurity within the gate electrode in the vicinity of the interface with the gate insulating film in order to suppress lowering of the gate capacitance during the ON status.
- In a general procedure for fabricating the aforementioned nMOS and pMOS transistors, the source-and-drain regions are formed by ion implantation, where the gate electrodes which serve as masks are also concomitantly doped.
- To suppress lowering in the gate capacitance, it is necessary to suppress formation of the depletion layer within the gate electrode, and it is thus necessary to raise the dose of the impurity introduced into the gate electrode, which impurity is concomitantly doped also into the source-and-drain regions. This successfully raises the impurity concentration within the gate electrode, but also raises the impurity concentration in the source-and-drain regions, which undesirably promotes lateral diffusion of the impurity in the source-and-drain regions, and results in degradation of short-channel resistance.
- One known solution for addressing the problem relates to reduction in height of the gate electrode, which can substantially increase the impurity concentration even if the dose of impurity introduced to the gate electrode remains unchanged. This solution, however, raises another problem that too low height of the gate electrode may result in punch-through of the impurity introduced into the gate electrode into the channel, which undesirably varies the threshold voltage. The technique for reducing the height of gate electrode is thus limitative.
- The present invention is thus to provide a highly-reliable semiconductor device and a method of fabricating thereof, both of which are aimed at raising impurity concentration within the gate electrode without increasing impurity concentration in the source-and-drain regions, and as a consequence at improving gate capacitance and short-channel resistance without anticipating fluctuation in the threshold voltage due to variation in shape of the gate electrode.
- After extensive investigations and discussions, the present inventors reached the various aspects of the present invention described below.
- A method of fabricating a semiconductor device according to one aspect of the present invention comprises a first step of patterning a gate electrode above a semiconductor substrate having an element isolation structure previously formed therein; a second step of forming sidewalls covering only on both side faces of the gate electrode; a third step of removing the upper portion of the sidewalls to thereby expose a part of both side faces of the gate electrode; and a fourth step for introducing an impurity into the gate electrode along a direction inclined to the surface of the semiconductor substrate.
- A method of fabricating a semiconductor device according to another aspect of the present invention comprises a first step of patterning a gate electrode above a semiconductor substrate; a second step of forming a mask having an opening which allows the gate electrode to be exposed therein; and a third step of introducing an impurity into the gate electrode along a direction inclined to the surface of the semiconductor substrate, wherein in the second step, the opening of the mask is formed in a size which ensures protection of areas for forming source-and-drain regions on both sides of the gate electrode from the tilt-angle introduction of the impurity.
- A semiconductor device according to one aspect of the present invention comprises a gate electrode; source-and-drain regions; sidewalls covering only the lower portion of both side faces of the gate electrode; and a silicide film formed on the exposed surface of the gate electrode, wherein the gate electrode contains an impurity having a conductivity type same as that of the impurity contained in the source-and-drain regions, and the gate electrode has an impurity concentration larger than that of the source-and-drain regions.
-
FIG. 1 is a schematic sectional view showing a major principle of a first technique; -
FIG. 2 is a schematic sectional view showing a major principle of a second technique; -
FIG. 3 is a schematic sectional view showing an exemplary case of a combination of the first and second techniques; -
FIGS. 4A to 4D are schematic sectional views sequentially showing process steps of a method of fabricating a CMOS transistor according to a first embodiment; -
FIGS. 5A to 5D are schematic sectional views sequentially showing process steps as continued fromFIG. 4D ; -
FIGS. 6A and 6B are schematic sectional views sequentially showing process steps as continued fromFIG. 5D ; -
FIGS. 7A to 7D are schematic sectional views sequentially showing process steps as continued fromFIG. 6B ; -
FIGS. 8A to 8D are schematic sectional views sequentially showing process steps as continued fromFIG. 7D ; -
FIG. 9 is a plan view for explaining tilt-angled ion implantation; -
FIG. 10 is a plan view for explaining a modified example of tilt-angled ion implantation in the first embodiment; -
FIGS. 11A to 11D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a second embodiment; -
FIGS. 12A to 12D are sequentially showing major process steps of a method of fabricating a CMOS transistor according to a third embodiment; -
FIGS. 13A to 13D are schematic sectional views sequentially showing process steps as continued fromFIG. 12D ; -
FIG. 14 is a plan view for explaining tilt-angled ion implantation; -
FIGS. 15A to 15D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fourth embodiment; -
FIGS. 16A to 16D are schematic sectional views sequentially showing process steps as continued fromFIG. 15D ; -
FIG. 17 is a plan view for explaining tilt-angled ion implantation; -
FIGS. 18A to 18D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fifth embodiment; -
FIGS. 19A to 19D are schematic sectional views sequentially showing process steps as continued fromFIG. 18D ; -
FIG. 20 is a plan view for explaining tilt-angled ion implantation; -
FIGS. 21A to 21D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a sixth embodiment; -
FIGS. 22A to 22D are schematic sectional views sequentially showing process steps as continued fromFIG. 21D ; -
FIGS. 23A to 23D are schematic sectional views sequentially showing process steps as continued fromFIG. 22D ; -
FIG. 24 is a plan view for explaining tilt-angled ion implantation; -
FIGS. 25A to 25D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a seventh embodiment; -
FIGS. 26A to 26D are schematic sectional views sequentially showing process steps as continued fromFIG. 25D ; -
FIGS. 27A to 27C are schematic sectional views sequentially showing process steps as continued fromFIG. 26D ; -
FIGS. 28A to 28C are schematic sectional views sequentially showing process steps of a method of fabricating a CMOS transistor according to a modified example of the seventh embodiment; -
FIGS. 29A to 29C are schematic sectional views sequentially showing process steps as continued fromFIG. 28C ; -
FIGS. 30A to 30D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a eighth embodiment; -
FIGS. 31A to 31D are schematic sectional views sequentially showing process steps as continued fromFIG. 30D ; -
FIGS. 32A to 32D are schematic sectional views sequentially showing process steps as continued fromFIG. 31D ; -
FIGS. 33A to 33D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a ninth embodiment; -
FIGS. 34A to 34C are schematic sectional views sequentially showing process steps as continued fromFIG. 33D ; -
FIG. 35 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the gate electrode in the fourth and fifth embodiments; -
FIG. 36 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the fourth and fifth embodiments; -
FIG. 37 is a characteristic chart showing a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the fourth and fifth embodiments; -
FIG. 38 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the gate electrode in the sixth through ninth embodiments; -
FIG. 39 is a schematic drawing for explaining a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the sixth through ninth embodiments; -
FIG. 40 is a characteristic chart showing a method of determining an alignment rule of a resist mask with respect to the aligned gate electrodes in the sixth through ninth embodiments; and -
FIG. 41 is a block diagram showing an internal constitution of a general personal user terminal device. - —Basic Concept of the Present Invention—
- First a basic concept of a major constitution of the present invention will be described.
- In pursuit of solving the aforementioned problems, the present inventors reached an idea of a semiconductor device in which the gate electrode is designed to have an impurity concentration higher than that of the source-and-drain regions, and proposed, as a specific technique for realizing such semiconductor device, a method of fabricating thereof as explained below.
- (First Technique)
- A major principle of a first technique is shown in
FIG. 1 . - First, sidewalls 103 are formed on both side faces of a
gate electrode 102. Portions of asemiconductor substrate 101 which fall on both sides of thegate electrode 102 andsidewalls 103 serve as source-and-drain (S/D)regions 104, respectively. - Next, the
sidewalls 103 are over-etched to thereby allow the upper portion of thegate electrode 102 to be exposed. Thegate electrode 102 herein is remained so as to expose an area extending from the top surface thereof to the upper portion of both side faces thereof. - Next, an impurity having a conductivity same as that doped in the source-and-drain regions is then implanted into the exposed surface of the
gate electrode 102 from a direction inclined to the surface of thesemiconductor substrate 101. - The
gate electrode 102 herein is doped with the impurity in its top surface and in the upper portion of one side face (indicated with reference numeral 102 a in the figure). Since the impurity can rapidly diffuse in polysilicon, the impurity rapidly diffuses during the later annealing to thereby attain a uniform distribution. That is, carrying out of the tilt-angled ion implantation is nearly worth ion implantation repeated twice, and can raise the impurity concentration at the interface with the gate insulating film as compared with that attainable by vertical ion implantation. - On the contrary, either of the source-and-
drain regions 104 is introduced with the impurity only in a dose corresponding to a single implantation (indicated with reference numeral 104 a in the figure), where the other region is not introduced at all, or only slightly introduced (indicated withreference numeral 104 b) although being almost not influential. - Therefore by repeating the tilt-angled ion implantation in a plural number of times, the impurity concentration of the
gate electrode 102 can be raised to a desired degree as compared with that of the source-and-drain regions 104, while varying the direction of implantation [typically once each in the directions opposed along the width of the gate electrode 102 (referred to as a direction normal to the gate length, hereinafter) and once each in the directions opposed along the length of the gate electrode (referred to as a direction parallel to the gate length)]. - (Second Technique)
- A major principle of a second technique is shown in
FIG. 2 . - In this technique, a resist
mask 105 having an opening 105 a, which is formed in a size allowing thegate electrode 102 to expose therein and allowing the source-and-drain regions 104 to be protected (prevented) from the tilt-angled ion implantation, is formed, and the tilt-angled ion implantation is carried out in this situation. Also in this case, the tilt-angled ion implantation is carried out in a plural number of times while varying the direction of implantation. - The
gate electrode 102 herein is doped with the impurity in its top surface and in the upper portion of one side face (indicated with reference numeral 102 a in the figure). Since the impurity can rapidly diffuse in polysilicon, the impurity rapidly diffuses during the later annealing to thereby attain a uniform distribution. That is, a single tilt-angled ion implantation is nearly worth ion implantation repeated twice, and can raise the impurity concentration at the interface with the gate insulating film as compared with that attainable by vertical ion implantation. - On the contrary, a pair of source-and-
drain regions 104 protected by the resistmask 105 are prevented from being introduced with the impurity. - Since increase in the impurity concentration in the
gate electrode 102 does not affect or increase the impurity concentration of the source-and-drain regions 104 as described in the above, short-channel effect is certainly prevented from being worsened. - It is to be noted now that it is also allowable, as shown in
FIG. 3 , to over-etch thesidewalls 103 so as to expose the upper portion of both side faces of thegate electrode 102 as described in the first technique, and then to form the resistmask 105 having the opening 105 a formed in a size which ensures protection (prevention) of the source-and-drain regions 104 from the tilt-angled ion implantation as described in the second technique, and to carry out the tilt-angled ion implantation in this situation. This ensures introduction of the impurity only into thegate electrode 102 in a more precise manner. - Based on the basic concept of the present invention described in the above, specific embodiments whereby the present invention is applied to a CMOS transistor will be explained with reference to the attached drawings.
-
FIGS. 4A through 8D are schematic sectional views sequentially showing process steps of a method of fabricating a CMOS transistor. - First as shown in
FIG. 4A , trenches are formed in an element isolation region of asemiconductor substrate 1, filled with an insulating material such as silicon oxide, and the surface thereof is planarized typically by CMP (chemical mechanical polishing) to thereby form a STI-type (shallow trench isolation-type)element isolation structures 2. This partitions element active regions on thesemiconductor substrate 1, which are annMOS region 11 and apMOS region 12. - Next, as shown in
FIG. 4B , a resistmask 13 is formed so as to cover thepMOS region 12, and a p-type impurity is introduced by ion implantation into thenMOS region 11, to thereby form a p-well 3, and a channel stopper layer (not shown) in the surficial portion of the substrate. - Next, the resist
mask 13 is removed typically by ashing, a resistmask 14 is formed so as to cover thenMOS region 11 as shown inFIG. 4C , and an n-type impurity is introduced by ion implantation into thePMOS region 12, to thereby form an n-well 4, and a channel stopper layer (not shown) in the surficial portion of the substrate. - Next, the resist
mask 14 is removed typically by ashing, and, as shown inFIG. 4D , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for 3 seconds to thereby restore the substrate from damage caused by introduction of the impurities into thewells - Next, as shown in
FIG. 5A , a thingate insulating film 5 is formed on the surface of thesemiconductor substrate 1 by thermal oxidation, and further thereon, anon-doped polysilicon film 15 is deposited by the CVD process as shown inFIG. 5B . - Next, the
polysilicon film 15 and thegate insulating film 5 are patterned by photolithography and succeeding dry etching to thereby formgate electrodes gate insulating film 5 in the nMOS andPMOS regions FIG. 5C . In this process, thepolysilicon film 15 has no impurity previously introduced therein, because polysilicon doped with an n-type impurity and that doped with a p-type impurity generally differ in the etchrate, which makes it difficult to form respective gate electrodes of nMOS transistor and pMOS transistor at a same time. - Next, as shown in
FIG. 5D , a resistmask 16 is formed so as to cover thePMOS region 12, and an n-type impurity, which is arsenic (As) herein, is introduced by vertical ion implanted into thenMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6×1014/cm2, and also a p-type impurity, which is boron (B) herein, is introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8×1012/cm2, and an angle of incidence of 30° from four directions, to thereby form n-type extension layers 7 a and p-type pocket layers 8 a, respectively. - Next, the resist
mask 16 is removed typically by ashing, a resistmask 17 is formed so as to cover thenMOS region 11 as shown inFIG. 6A , and a p-type impurity, which is boron (B) herein, is introduced by vertical ion implantation into thepMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6×1014/cm2, and also an n-type impurity, which is arsenic (As) herein, is introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6×1012/cm2, and an angle of incidence of 30° from four directions, to thereby form p-type extension layers 7 b and n-type pocket layers 8 a, respectively. - Next, as shown in
FIG. 6B , the resistmask 17 is removed typically by ashing, and, as shown inFIG. 6B , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore the substrate from damage generated by introduction of the impurities into the extension layers 7 a, 7 b andpocket layers - Next, a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the
gate electrodes FIG. 7A . - Next, a resist
mask 18 is formed so as to cover thepMOS region 12 as shown inFIG. 7B , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 4.5×1015/cm2 and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. The dose of phosphorus in this process is controlled to a smaller value (6×1015/cm2, for example) than that in general formation process of n-type, source-and-drain regions. - Next, the resist
mask 18 is removed typically by ashing, a resistmask 19 is formed so as to cover thenMOS region 11 as shown inFIG. 7C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV, a dose of 2.25×1015/cm2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b. Boron herein is also implanted into thegate electrode 6 b. The dose of boron in this process is controlled to a smaller value (3×1015/cm2, for example) than that in general formation process of p-type, source-and-drain regions. - Next, the resist
mask 19 is removed typically by ashing, and thesidewalls gate electrodes FIG. 7D . Thegate electrodes sidewalls - Considering now that the
gate electrodes sidewalls gate electrodes sidewalls drain regions drain regions gate electrodes sidewalls - To prevent the STI-type
element isolation structure 2 from being etched together with thesidewalls sidewalls element isolation structure 2 so that thesidewalls element isolation structure 2. One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-typeelement isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls - Next, as shown in
FIG. 8A , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a). - More specifically, a resist
mask 21 is formed so as to cover thepMOS region 12, and an n-type impurity, which is phosphorus (P) herein, is implanted at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto). The ion implantation repeated four times is shown in a schematic plan view inFIG. 9 . -
FIG. 8A shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of thegate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one n-type, source-and-drain region 10 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. Another n-type, source-and-drain region 10 a, which is shadowed by thegate electrode 6 a, is not introduced with the impurity, or introduced only in a less affective amount. - Although not being illustrated for convenience, a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the
gate electrode 6 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both n-type, source-and-drain regions 10 a in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated six times, in addition to a dose of 4.5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 7.5×1015/cm2. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated three times, in addition to a dose of 4.5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 6×1015/cm2 (same level with that of general source-and-drain region). - In the aforementioned process for forming the n-type, source-and-
drain region 10 a, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 a, to prevent the impurity from penetrating thesidewall 10 a andgate electrode 6 a and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel. - Next, as shown in
FIG. 8B , a p-type impurity is implanted into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 b). - More specifically, a resist
mask 21 is removed typically by ashing, and a resistmask 22 is formed so as to cover thenMOS region 11, and a p-type impurity, which is boron (B) herein, is implanted at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto). -
FIG. 8B shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of thegate electrode 6 b herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one p-type, source-and-drain region 10 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. Another p-type, source-and-drain region 10 b, which is shadowed by thegate electrode 6 b, is not introduced with the impurity, or introduced only in a less affective amount. - Although not being illustrated for convenience, a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the
gate electrode 6 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both p-type, source-and-drain regions 10 b in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated six times, in addition to a dose of 2.25×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3.75×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated three times, in addition to a dose of 2.25×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3×1015/cm2 (same level with that of general source-and-drain region). - In the aforementioned process for forming the p-type, source-and-
drain region 10 b, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 b, to prevent the impurity from penetrating thesidewall 10 b andgate electrode 6 b and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the p-type, source-and-drain region 10 b from diffusing toward the channel. - Next, the resist
mask 22 is removed typically by ashing, and, as shown inFIG. 8C , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into thegate electrodes drain regions - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 8D . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the first embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions sidewalls gate electrodes gate electrodes drain regions gate electrodes drain regions - (Modified Example)
- A modified example of the present embodiment will be described.
- The present invention is by no means limited to mode of the ion implantation in the first embodiment described in the above, where conditions for the first ion implantation for forming the source-and-drain regions or successive tilt-angled ion implantations can properly be selected provided that the impurity concentration of the gate electrodes can be raised without increasing the impurity concentration of the source-and-drain regions.
- For example, in this modified example, as shown in
FIG. 10 , the first ion implantation of phosphorus for forming the n-type, source-and-drain region 10 a is carried out at an ion acceleration energy of 8 keV, a dose of 5.5×1015/cm2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2 and an angle of incidence of 45°. - By the ion implantation repeated twice, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated four times, in addition to a dose of 5.5×10−5/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 7.5×1015/cm2. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 5.5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 6×1015/cm2 (same level with that of general source-and-drain region). - Similarly to the above, the first ion implantation of boron for forming the p-type, source-and-
drain region 10 b is carried out at an ion acceleration energy of 4 keV, a dose of 2.75×1015/cm2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length individually at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2 and an angle of incidence of 45°. - By the ion implantation repeated twice, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated four times, in addition to a dose of 2.75×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3.75×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 2.75×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3×1015/cm2 (same level with that of general source-and-drain region). -
FIGS. 11A to 11D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a second embodiment. - In the second embodiment, the individual process steps previously shown in
FIGS. 4A through 8B are executed to thereby control the dose of phosphorus to 7.5×1015/cm2 for thegate electrode 6 a and 6×1015/cm2 for the n-type, source-and-drain region 10 a in thenMOS region 11, and the dose of boron to 3.75×1015/cm2 for thegate electrode drain region 10 b in thepMOS region 12. Thesemiconductor substrate 1 is then annealed by RTA at 1,030° C. for 1 second (FIG. 11A ). - Next, as shown in
FIG. 11B , asilicon oxide film 27 is formed over the entire surface by the CVD process, and then as shown inFIG. 1C , thesilicon oxide film 27 is then anisotropically etched back so as to allow the film to remain only on both side faces of thegate electrodes sidewalls FIG. 7A . - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 11D . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the second embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions sidewalls gate electrodes gate electrodes drain regions gate electrodes drain regions - The second embodiment is also successful in certainly prevent short-circuiting between CoSi2 formed on the source-and-
drain regions gate electrodes sidewalls sidewalls gate electrodes - Also in the second embodiment, similarly to the modified example of the first embodiment, conditions for the first ion implantation for forming the source-and-drain regions or successive tilt-angled ion implantations can properly be selected provided that the impurity concentration of the gate electrodes can be raised without increasing the impurity concentration of the source-and-drain regions.
- For example, the first ion implantation of phosphorus for forming the n-type, source-and-
drain region 10 a is carried out at an ion acceleration energy of 8 keV, a dose of 5.5×1015/cm2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2 and an angle of incidence of 45°. - By the ion implantation repeated twice, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated four times, in addition to a dose of 5.5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 7.5×1015/cm2. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 5.5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 6×1015/cm2 (same level with that of general source-and-drain region). - Similarly to the above, the first ion implantation of boron for forming the p-type, source-and-
drain region 10 b is carried out at an ion acceleration energy of 4 keV, a dose of 2.75×1015/cm2 and an angle of incidence of 0°, and the tilt-angled ion implantation of boron is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2 and an angle of incidence of 45°. - By the ion implantation repeated twice, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated four times, in addition to a dose of 2.75×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3.75×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, in addition to a dose of 2.75×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3×1015/cm2 (same level with that of general source-and-drain region). -
FIGS. 12A through 13D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a third embodiment. - In the third embodiment, the individual process steps previously shown in
FIGS. 4A through 6B are executed to thereby form thesidewalls gate electrodes FIG. 12A ). - Next, as shown in
FIG. 12B , the resistmask 18 is formed so as to cover thepMOS region 12, and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 5×1015/cm2, and an angle of incidence of 0°, to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. The dose of phosphorus in this process is controlled to a smaller value (6×1015/cm2, for example) than that in general formation process of n-type, source-and-drain regions. - Next, the resist
mask 18 is removed typically by ashing, the resistmask 19 is formed so as to cover thenMOS region 11 as shown inFIG. 12C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV, a dose of 2.5×1015/cm2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b. Boron herein is also implanted into thegate electrode 6 b. The dose of boron in this process is controlled to a smaller value (3×105/cm2, for example) than that in general formation process of p-type, source-and-drain regions. - Next, the resist
mask 19 is removed typically by ashing, and thesidewalls gate electrodes FIG. 12D . Thegate electrodes sidewalls - Considering now that the
gate electrodes sidewalls gate electrodes sidewalls drain regions drain regions gate electrodes sidewalls - To prevent the STI-type
element isolation structure 2 from being etched together with thesidewalls sidewalls element isolation structure 2 so that thesidewalls element isolation structure 2. One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-typeelement isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls - Next, as shown in
FIG. 13A , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a). - More specifically, the resist
mask 21 is formed so as to cover thepMOS region 12, and an n-type impurity, which is phosphorus (P) herein, is implanted at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). The ion implantation repeated four times is shown in a schematic plan view inFIG. 14 . - Since the top surface and the upper portion of one side face of the
gate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one n-type, source-and-drain region 10 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. Another n-type, source-and-drain region 10 a, which is shadowed by thegate electrode 6 a, is not introduced with the impurity, or introduced only in a less affective amount. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated eight times, in addition to a dose of 5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 9×1015/cm2. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 6×1015/cm2 (same level with that of general source-and-drain region). - In the aforementioned process for forming the n-type, source-and-
drain region 10 a, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 a, to prevent the impurity from penetrating thesidewall 10 a andgate electrode 6 a and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel. - Next, as shown in
FIG. 13B , a p-type impurity is implanted into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 b). - More specifically, the resist
mask 21 is removed typically by ashing, and the resistmask 22 is formed so as to cover thenMOS region 11, and a p-type impurity, which is boron (B) herein, is implanted at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - Since the top surface and the upper portion of one side face of the
gate electrode 6 b herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, and also results in introduction of the impurity into one p-type, source-and-drain region 10 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. Another p-type, source-and-drain region 10 b, which is shadowed by thegate electrode 6 b, is not introduced with the impurity, or introduced only in a less affective amount. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated eight times, in addition to a dose of 2.5×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 4.5×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 2.5×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3×1015/cm2 (same level with that of general source-and-drain region). - In the aforementioned process for forming the p-type, source-and-
drain region 10 b, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 b, to prevent the impurity from penetrating thesidewall 10 b andgate electrode 6 b and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the p-type, source-and-drain region 10 b from diffusing toward the channel. - Next, the resist
mask 22 is removed typically by ashing, and, as shown inFIG. 13C , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into thegate electrodes drain regions - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 13D . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the third embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions sidewalls gate electrodes gate electrodes drain regions gate electrodes drain regions -
FIGS. 15A through 16D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fourth embodiment. - In the fourth embodiment, the individual process steps previously shown in
FIGS. 4A through 6B are executed to thereby form thesidewalls gate electrodes FIG. 15A ). - Next, as shown in
FIG. 15B , the resistmask 18 is formed so as to cover thepMOS region 12, and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 5×1015/cm2, and an angle of incidence of 0°, to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. The dose of phosphorus in this process is controlled to a smaller value (6×1015/cm2, for example) than that in general formation process of n-type, source-and-drain regions. - Next, the resist
mask 18 is removed typically by ashing, the resistmask 19 is formed so as to cover thenMOS region 11 as shown inFIG. 15C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV, a dose of 2.5×1015/cm2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b. Boron herein is also implanted into thegate electrode 6 b. The dose of boron in this process is controlled to a smaller value (3×1015/cm2, for example) than that in general formation process of p-type, source-and-drain regions. - Next, the resist
mask 19 is removed typically by ashing, and thesidewalls gate electrodes FIG. 15D . Thegate electrodes sidewalls - Considering now that the
gate electrodes sidewalls gate electrodes sidewalls drain regions drain regions gate electrodes sidewalls - To prevent the STI-type
element isolation structure 2 from being etched together with thesidewalls sidewalls element isolation structure 2 so that thesidewalls element isolation structure 2. One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-typeelement isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls - Next, as shown in
FIG. 16A , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a). - More specifically, a resist
mask 31 is formed so as to cover thePMOS region 12, which mask 31 having an opening 31 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation. The resistmask 31 herein is approx. 120 nm high, and theopening 31 a has anedge 120 nm away from the edge of thegate electrode 6 a. In alignment of a reticle for forming the opening 31 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. An n-type impurity, which is phosphorus (P) herein, is implanted into thenMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from four directions differing from each other (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto). The ion implantation repeated four times is shown in a schematic plan view inFIG. 17 . -
FIG. 16A shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of thegate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of n-type, source-and-drain regions 10 a are protected by the resistmask 31 against the ion implantation, and are thus prevented from being implanted with the impurity. - Although not being illustrated for convenience, a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the
gate electrode 6 a in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both n-type, source-and-drain regions 10 a in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated six times, in addition to a dose of 5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 8×1015/cm2. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 5×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 6×1015/cm2 (same level with that of general source-and-drain region). - In the aforementioned process for forming the n-type, source-and-
drain region 10 a, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 a, to prevent the impurity from penetrating thesidewall 10 a andgate electrode 6 a and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel. - Next, as shown in
FIG. 16B , a p-type impurity is implanted along a direction inclined into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 b). - More specifically, the resist
mask 31 is removed typically by ashing, and a resistmask 32 is formed so as to cover thenMOS region 11, which mask 32 having an opening 32 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation. The resistmask 32 herein is approx. 120 nm high, and theopening 32 a has anedge 120 nm away from the edge of thegate electrode 6 b. In alignment of a reticle for forming the opening 31 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. A p-type impurity, which is boron (B) herein, is implanted into thepMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from four directions differing from each other (twice in two opposing directions parallel to the gate length and twice in two opposing directions normal thereto). -
FIG. 16B shows an exemplary ion implantation effected along a direction parallel to the gate length and at an angle of incidence of 45°. Since the top surface and the upper portion of one side face of thegate electrode 6 b herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resistmask 32 against the ion implantation, and are thus prevented from being implanted with the impurity. - Although not being illustrated for convenience, a single ion implantation normal to the gate length at an angle of incidence of 45° results in introduction of the impurity into the
gate electrode 6 b in an amount equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°, and also results in introduction of the impurity into both p-type, source-and-drain regions 10 b in an amount again equivalent to that possibly attained by a single ion implantation at an angle of incidence of 0°. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated six times, in addition to a dose of 2.5×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 4×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice, in addition to a dose of 2.5×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 3×1015/cm2 (same level with that of general source-and-drain region). - In the aforementioned process for forming the p-type, source-and-
drain region 10 b, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 b, to prevent the impurity from penetrating thesidewall 10 b andgate electrode 6 b and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the p-type, source-and-drain region 10 b from diffusing toward the channel. - Next, the resist
mask 32 is removed typically by ashing, and, as shown inFIG. 16C , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into thegate electrodes drain regions - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 16D . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the fourth embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions sidewalls gate electrodes gate electrodes drain regions gate electrodes drain regions - Moreover in the tilt-angled ion implantation, the source-and-
drain regions masks gate electrodes gate electrodes drain regions - (Modified Example)
- Also in the fourth embodiment, similarly to the modified example of the first embodiment, conditions for the first ion implantation for forming the source-and-drain regions or successive tilt-angled ion implantations can properly be selected provided that the impurity concentration of the gate electrodes can be raised without increasing the impurity concentration of the source-and-drain regions.
- For example, the first ion implantation of phosphorus for forming the n-type, source-and-
drain region 10 a is carried out at an ion acceleration energy of 8 keV, a dose of 6×1015/cm2 and an angle of incidence of 0°, and the tilt-angled ion implantation of phosphorus is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2 and an angle of incidence of 450. - By the ion implantation repeated twice, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated four times, in addition to a dose of 6×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 8×1015/cm2. On the contrary, each n-type, source-and-drain region 10 a will contain the impurity only in an amount of 6×1015/cm2 which has initially been attained, which will be at the same level with that of general source-and-drain region. - Similarly to the above, the first ion implantation of boron for forming the p-type, source-and-
drain region 10 b is carried out at an ion acceleration energy of 4 keV, a dose of 3×1015/cm2 and an angle of incidence of 0°, and the tilt-angled ion implantation of boron is carried out twice along the direction parallel to the gate length respectively at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2 and an angle of incidence of 45°. - By the ion implantation repeated twice, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated four times, in addition to a dose of 3×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 4×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will contain the impurity only in an amount of 3×1015/cm2 which has initially been attained, which will be at the same level with that of general source-and-drain region. -
FIGS. 18A through 19D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a fifth embodiment. - In the fifth embodiment, the individual process steps previously shown in
FIGS. 4A through 6B are executed to thereby form thesidewalls gate electrodes FIG. 18A ). - Next, as shown in
FIG. 18B , the resistmask 18 is formed so as to cover thepMOS region 12, and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6×1015/cm2, and an angle of incidence of 0°, to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. - Next, the resist
mask 18 is removed typically by ashing, the resistmask 19 is formed so as to cover thenMOS region 11 as shown inFIG. 18C , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV, a dose of 3×1015/cm2 and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b. Boron herein is also implanted into thegate electrode 6 b. - Next, the resist
mask 19 is removed typically by ashing, and thesidewalls gate electrodes FIG. 18D . Thegate electrodes sidewalls - Considering now that the
gate electrodes sidewalls gate electrodes sidewalls drain regions drain regions gate electrodes sidewalls - To prevent the STI-type
element isolation structure 2 from being etched together with thesidewalls sidewalls element isolation structure 2 so that thesidewalls element isolation structure 2. One preferable example is such that using a plasma oxide film formed in an HDP (high density plasma) apparatus for the STI-typeelement isolation structure 2 and using an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls - Next, as shown in
FIG. 19A , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a). - More specifically, a resist
mask 33 is formed so as to cover thepMOS region 12, which mask 33 having an opening 33 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation. The resistmask 33 herein is approx. 120 nm high, and theopening 33 a has anedge 120 nm away from the edge of thegate electrode 6 a. In alignment of a reticle for forming the opening 33 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. An n-type impurity, which is phosphorus (P) herein, is implanted into thenMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). The ion implantation repeated four times is shown in a schematic plan view inFIG. 20 . - A single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the
gate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of n-type, source-and-drain regions 10 a are protected by the resistmask 33 against the ion implantation, and are thus prevented from being implanted with the impurity. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 a will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (5×1014/cm2) repeated eight times, in addition to a dose of 6×1015/cm2 which has previously been attained, and thus will have a total dose of phosphorus of 1×1016/cm2. On the contrary, each n-type, source-and-drain region 10 a will contain the impurity only in an amount of 6×1015/cm2 which has initially been attained, which will be at the same level with that of general source-and-drain region. - In the aforementioned process for forming the n-type, source-and-
drain region 10 a, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 8 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 4 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 a, to prevent the impurity from penetrating thesidewall 10 a andgate electrode 6 a and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the n-type, source-and-drain region 10 a from diffusing toward the channel. - Next, as shown in
FIG. 19B , a p-type impurity is implanted into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 b). - More specifically, the resist
mask 33 is removed typically by ashing, and a resistmask 34 is formed so as to cover thenMOS region 11, which mask 34 having an opening 34 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation. The resistmask 34 herein is approx. 120 nm high, and theopening 34 a has anedge 120 nm away from the edge of thegate electrode 6 b. In alignment of a reticle for forming the opening 31 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. A p-type impurity, which is boron (B) herein, is implanted into thepMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - A single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the
gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resistmask 34 against the ion implantation, and are thus prevented from being implanted with the impurity. - By the aforementioned ion implantation repeated four times, as shown later in Table 1, the
gate electrode 6 b will have introduced therein the impurity in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° (2.5×1014/cm2) repeated eight times, in addition to a dose of 3×1015/cm2 which has previously been attained, and thus will have a total dose of boron of 5×1015/cm2. On the contrary, each p-type, source-and-drain region 10 b will contain the impurity only in an amount of 3×1015/cm2 which has initially been attained, which will be at the same level with that of general source-and-drain region. - In the aforementioned process for forming the p-type, source-and-
drain region 10 b, the first ion implantation (at an angle of incidence of 0°) was carried out at an ion acceleration energy of 4 keV, whereas the successive tilt-angled ion implantation was carried at an ion acceleration energy reduced to as low as 2 keV. The energy was thus reduced because it was necessary to prevent the impurity from laterally penetrating thegate electrode 6 b, to prevent the impurity from penetrating thesidewall 10 b andgate electrode 6 b and intruding into thesemiconductor substrate 1, and to prevent the impurity implanted into the n-type, source-and-drain region 10 b from diffusing toward the channel. - Next, the resist
mask 34 is removed typically by ashing, and, as shown inFIG. 19C , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into thegate electrodes drain regions - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 19D . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the fifth embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions sidewalls gate electrodes gate electrodes drain regions gate electrodes drain regions - In addition, the source-and-
drain regions masks gate electrodes gate electrodes drain regions - Short-circuiting between the silicides formed on the source-and-
drain regions gate electrodes sidewalls gate electrodes sidewalls drain regions masks sidewalls -
FIGS. 21A through 23D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a sixth embodiment. - In the sixth embodiment, the individual process steps previously shown in
FIGS. 4A through 5C are executed similarly to as described in the first embodiment, to thereby pattern thegate electrodes FIG. 21A ). - Next, as shown in
FIG. 21B , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide). - More specifically, a resist
mask 35 is formed so as to cover thepMOS region 12, which mask 35 having an opening 35 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation. The resistmask 35 herein is approx. 120 nm high, and theopening 35 a has an edge 80 nm away from the edge of thegate electrode 6 a. In alignment of a reticle for forming the opening 35 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. An n-type impurity, which is phosphorus (P) herein, is implanted into thenMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of thegate electrode 6 b. In alignment of a reticle for forming the opening 36 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. A p-type impurity, which is boron (B) herein, is implanted into thepMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - A single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the
gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resistmask 36 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, the resist
mask 36 is removed typically by ashing, the resistmask 16 is formed so as to cover thepMOS region 12 as shown inFIG. 21D , and an n-type impurity, which is arsenic (As) herein, is introduced by vertical ion implantation into thenMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6×1014/cm2; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8×1012/cm2 and at an angle of incidence of 30° from four directions to thereby form n-type extension layers 7 a and p-type pocket layers 8 a, respectively. - Next, the resist
mask 16 is removed typically by ashing, the resistmask 17 is formed so as to cover thenMOS region 11 as shown inFIG. 22A , and a p-type impurity, which is boron (B) herein, is introduced by vertical ion implantation into thepMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6×1014/cm2; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6×1012/cm2 and at an angle of incidence of 30° from four directions to thereby form p-type extension layers 7 b and n-type pocket layers 8 b, respectively. - It is to be noted now that the individual process steps shown in
FIGS. 21B through 22A can be executed in an arbitrary order. - Next, the resist
mask 17 is removed typically by ashing, and, as shown inFIG. 22B , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore it from damage caused by the ion implantation into the extension layers 7 a, 7 b andpocket layers - Next, a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the
gate electrodes FIG. 22C . - Next, a resist
mask 18 is formed so as to cover thepMOS region 12 as shown inFIG. 22D , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6×1015/cm2, and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. - In this case, the
gate electrode 6 a is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 5×1014/cm2 plus 6×1015/cm2, total 1×1016/cm2 of phosphorus. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity only in an amount of 6×1015/cm2, into thegate electrodes drain regions - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form COSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 23C . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes as shown inFIG. 23D . - As has been described in the above, the sixth embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions gate electrodes drain regions gate electrodes drain regions - Moreover, in the tilt-angled ion implantation, the source-and-
drain regions masks gate electrodes gate electrodes drain regions - The sixth embodiment is also advantageous in reducing the production cost of CMOS transistor, since a process step of thinning the sidewalls 20 a, 20 b by over-etching is omissible, although the amounts of dose of impurities in the source-and-
drain regions gate electrodes -
FIGS. 25A through 27D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a seventh embodiment. - directions inclined by 45° away from the direction of gate length).
- Since the top surface and the upper portion of one side face of the
gate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of n-type, source-and-drain regions 10 a are protected by the resistmask 37 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, as shown in
FIG. 25B , in the presence of the resistmask 37 remained unremoved, an n-type impurity, which is arsenic (As) herein, is vertically implanted into thenMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6×1014/cm2; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8×1012/cm2 and at an angle of incidence of 15° from four directions to thereby form n-type extension layers 7 a and p-type pocket layers 8 a, respectively. - Next, as shown in
FIG. 25C , a p-type impurity is implanted along a direction inclined into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide). - More specifically, the resist
mask 37 is removed typically by ashing, and a resistmask 38 is formed so as to cover thenMOS region 11, which mask 38 having an opening 38 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation. The resistmask 38 herein is approx. 120 nm high, and theopening 38 a has an edge 80 nm away from the edge of thegate electrode 6 b. In alignment of a reticle for forming the opening 38 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. A p-type impurity, which is boron (B) herein, is implanted into thepMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - A single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the
gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resistmask 38 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, as shown in
FIG. 25D , in the presence of the resistmask 38 remained unremoved, a p-type impurity, which is boron (B) herein, is vertically implanted into thepMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6×1014/cm2; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6×1012/cm2 and at an angle of incidence of 15° from four directions to thereby form p-type extension layers 7 b and n-type pocket layers 8 b, respectively. - Next, the resist
mask 38 is removed typically by ashing, and, as shown inFIG. 26A , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore it from damage caused by the ion implantation into the extension layers 7 a, 7 b andpocket layers - Next, a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the
gate electrodes FIG. 26B . - Next, a resist
mask 18 is formed so as to cover thepMOS region 12 as shown inFIG. 26C , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6×1015/cm2, and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. - In this case, the
gate electrode 6 a is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 5×1014/cm2 plus 6×1015/cm2, total 1×1016/cm2 of phosphorus. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity only in an amount of 6×1015/cm2, which will be at the same level with that of general source-and-drain region. - Next, a resist
mask 18 is removed typically by ashing, and the resistmask 19 is formed so as to cover thenMOS region 11 as shown inFIG. 26D , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV, a dose of 3×1015/cm2, and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b. Boron herein is also implanted into thegate electrode 6 b. - In this case, the
gate electrode 6 b is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 2.5×1014/cm2 plus 3×1015/cm2, total 5×1015/cm2 of boron. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity only in an amount of 3×1015/cm2, which will be at the same level with that of general source-and-drain region. - Next, the resist
mask 19 is removed typically by ashing, and, as shown inFIG. 27A , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for one second to thereby restore it from damage caused by ion implantation into thegate electrodes drain regions - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 27B . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes as shown inFIG. 27C . - As has been described in the above, the seventh embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions gate electrodes drain regions gate electrodes drain regions - Moreover, in the tilt-angled ion implantation, the source-and-
drain regions masks gate electrodes gate electrodes drain regions - The seventh embodiment is also advantageous in further reducing the production cost of CMOS transistor, since a process step of thinning the sidewalls 20 a, 20 b by over-etching is omissible, and since a process step of photolithography for forming the extension layers 7 a, 7 b and
pocket layers drain regions gate electrodes - (Modified Example)
- A modified example of the seventh embodiment will be described.
-
FIGS. 28A through 29C are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a modified example of the seventh embodiment. - In this modified example, similarly to as previously shown in
FIG. 25B , thegate electrode 6 a is subjected to the tilt-angled ion implantation in the presence of the resist mask 37 (FIG. 28A ). - Next, as shown in
FIG. 28B , the resistmask 37 is trimmed so that the opening 37 a is widened to have an edge recessed by 100 nm from the edge of thegate electrode 6 a. - In this status, as shown in
FIG. 28C , an n-type impurity, which is arsenic (As) herein, is vertically implanted into thenMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6×1014/cm2; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8×1012/cm2 and at an angle of incidence of 30° from four directions to thereby form the n-type extension layers 7 a and p-type pocket layers 8 a, respectively. - Next, the resist
mask 37 is removed typically by ashing, and then similarly to as previously shown inFIG. 25C , thegate electrode 6 b is subjected to the tilt-angled ion implantation in the presence of the resist mask 38 (FIG. 29A ). - Next, as shown in
FIG. 29B , the resistmask 38 is trimmed so that the opening 38 a is widened to have an edge recessed by 100 nm from the edge of thegate electrode 6 b. - In this status, a p-type impurity, which is boron (B) herein, is vertically implanted into the
PMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6×1014/cm2; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6×1012/cm2 and at an angle of incidence of 30° from four directions to thereby form the p-type extension layers 7 b and n-type pocket layers 8 b, respectively. - The resist
mask 38 is then removed typically by ashing, and a CMOS transistor is completed after executing various process steps similarly to those in the seventh embodiment as shown inFIGS. 26A to 27C. - In addition to various effects obtainable from the seventh embodiment, this modified example makes it possible to form the extension layers 7 a, 7 b and
pocket layers masks pocket layers -
FIGS. 30A through 32D are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a eighth embodiment. - In the eighth embodiment, the individual process steps previously shown in
FIGS. 4A through 5C are executed similarly to as described in the first embodiment, to thereby pattern thegate electrodes FIG. 30A ). - Next, as shown in
FIG. 30B , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide). - More specifically, the resist
mask 35 is formed so as to cover thePMOS region 12, which mask 35 having the opening 35 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation. The resistmask 35 herein is approx. 120 nm high, and theopening 35 a has an edge 80 nm away from the edge of thegate electrode 6 a. In alignment of a reticle for forming the opening 35 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. An n-type impurity, which is phosphorus (P) herein, is implanted into thenMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - Since the top surface and the upper portion of one side face of the
gate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of n-type, source-and-drain regions 10 a are protected by the resistmask 35 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, as shown in
FIG. 30C , a p-type impurity is implanted along a direction inclined into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide). - More specifically, the resist
mask 35 is removed typically by ashing, and the resistmask 36 is formed so as to cover thenMOS region 11, which mask 36 having the opening 36 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation. The resistmask 36 herein is approx. 120 nm high, and theopening 36 a has an edge 80 nm away from the edge of thegate electrode 6 b. In alignment of a reticle for forming the opening 36 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. A p-type impurity, which is boron (B) herein, is implanted into thepMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - A single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the
gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resistmask 36 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, the resist
mask 36 is removed typically by ashing, and, as shown inFIG. 30D , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,050° C. for 1 second to thereby thoroughly diffuse the impurities incorporated into thegate electrodes - Next, the resist
mask 16 is formed so as to cover thepMOS region 12 as shown inFIG. 31A , and an n-type impurity, which is arsenic (As) herein, is introduced by vertical ion implantation into thenMOS region 11 at an ion acceleration energy of 5 keV and a dose of 6×1014/cm2; and a p-type impurity, which is boron (B) herein, is also introduced by ion implantation at an ion acceleration energy of 10 keV, a dose of 8×1012/cm2 and at an angle of incidence of 30° from four directions to thereby form the n-type extension layers 7 a and p-type pocket layers 8 a, respectively. - Next, the resist
mask 16 is removed typically by ashing, the resistmask 17 is formed so as to cover thenMOS region 11 as shown inFIG. 31B , and a p-type impurity, which is boron (B) herein, is introduced by vertical ion implantation into thepMOS region 12 at an ion acceleration energy of 0.5 keV and a dose of 6×1014/cm2; and an n-type impurity, which is arsenic (As) herein, is also introduced by ion implantation at an ion acceleration energy of 50 keV, a dose of 6×1012/cm2 and at an angle of incidence of 30° from four directions to thereby form the p-type extension layers 7 b and n-type pocket layers 8 b, respectively. - Next, the resist
mask 17 is removed typically by ashing, and, as shown inFIG. 31C , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,000° C. for one second to thereby restore it from damage caused by the ion implantation into the extension layers 7 a, 7 b andpocket layers - Next, a silicon oxide film (not shown) is deposited on the entire surface by the CVD process, and the film is then anisotropically etched back so as to allow the film to remain only on both side faces of the
gate electrodes FIG. 31D . - Next, a resist
mask 18 is formed so as to cover thepMOS region 12 as shown inFIG. 32A , and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV, a dose of 6×1015/cm2, and an angle of incidence of 0° (that is, normal to the surface of the substrate), to thereby form the n-type, source-and-drain regions 10 a. Phosphorus herein is also implanted into thegate electrode 6 a. - In this case, the
gate electrode 6 a is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 5×1014/cm2 plus 6×1015/cm2, total 1×1016/cm2 of phosphorus. On the contrary, each n-type, source-and-drain region 10 a will have introduced therein the impurity only in an amount of 6×1015/cm2, which will be at the same level with that of general source-and-drain region. - Next, a resist
mask 18 is removed typically by ashing, and the resistmask 19 is formed so as to cover thenMOS region 11 as shown inFIG. 32B , and a p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV, a dose of 3×1015/cm2, and an angle of incidence of 0°, to thereby form the p-type, source-and-drain regions 10 b. Boron herein is also implanted into thegate electrode 6 b. - In this case, the
gate electrode 6 b is subjected to four times of the aforementioned tilt-angled ion implantation and a single ion implantation at an angle of incidence of 0°, which results in introduction of the impurity in an amount equivalent to eight times of 2.5×1014/cm2 plus 3×1015/cm2, total 5×1015/cm2 of boron. On the contrary, each p-type, source-and-drain region 10 b will have introduced therein the impurity only in an amount of 3×1015/cm2, which will be at the same level with that of general source-and-drain region. - Next, the resist
mask 19 is removed typically by ashing, and, as shown inFIG. 32C , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,020° C. for one second to thereby restore it from damage caused by ion implantation into thegate electrodes drain regions gate electrode FIG. 30D , which is advantageous in further suppressing diffusion of the impurities in the extension layers 7 a, 7 b andpocket layers - Next, a silicide-forming metal, which is cobalt (Co) herein, is deposited over the entire surface, annealed so as to proceed silicidation, and unreacted Co is removed, to thereby form CoSi2 layers 23 on the exposed surface of the
gate electrodes drain region FIG. 32D . - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the eighth embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions gate electrodes drain regions gate electrodes drain regions - Moreover, in the tilt-angled ion implantation, the source-and-
drain regions masks gate electrodes gate electrodes drain regions - The eighth embodiment is also advantageous in reducing the production cost of CMOS transistor, since a process step of thinning the sidewalls 20 a, 20 b by over-etching is omissible, although the amounts of dose of impurities in the source-and-
drain regions gate electrodes gate electrodes gate insulating film 5, since thesemiconductor substrate 1 is once annealed immediately after thegate electrodes -
FIGS. 33A through 34C are schematic sectional views sequentially showing major process steps of a method of fabricating a CMOS transistor according to a ninth embodiment. - In the ninth embodiment, the individual process steps previously shown in
FIGS. 4A through 5C are executed similarly to as described in the first embodiment, to thereby pattern thegate electrodes FIG. 33A ). - Next, as shown in
FIG. 33B , an n-type impurity is implanted along a direction inclined into thenMOS region 11 to thereby introduce the impurity to the exposed surface of thegate electrode 6 a (the top surface of 50 nm wide). - More specifically, the resist
mask 35 is formed so as to cover thepMOS region 12, which mask 35 having the opening 35 a formed in a size capable of protecting the n-type, source-and-drain regions 10 a from the tilt-angled ion implantation. The resistmask 35 herein is approx. 120 nm high, and theopening 35 a has an edge 80 nm away from the edge of thegate electrode 6 a. In alignment of a reticle for forming the opening 35 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. An n-type impurity, which is phosphorus (P) herein, is implanted into thenMOS region 11 at an ion acceleration energy of 4 keV, a dose of 5×1014/cm2 and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - Since the top surface and the upper portion of one side face of the
gate electrode 6 a herein have almost equivalent exposed areas, a single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of thegate electrode 6 a in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of n-type, source-and-drain regions 10 a are protected by the resistmask 35 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, as shown in
FIG. 33C , a p-type impurity is implanted along a direction inclined into thepMOS region 12 to thereby introduce the impurity to the exposed surface of thegate electrode 6 b (the top surface of 50 nm wide). - More specifically, the resist
mask 35 is removed typically by ashing, and the resistmask 36 is formed so as to cover thenMOS region 11, which mask 36 having the opening 36 a formed in a size capable of protecting the p-type, source-and-drain regions 10 b from the tilt-angled ion implantation. The resistmask 36 herein is approx. 120 nm high, and theopening 36 a has an edge 80 nm away from the edge of thegate electrode 6 b. In alignment of a reticle for forming the opening 36 a by photolithography, employing the gate electrode as an alignment mark, in place of a mark formed in the STI process, can successfully reduce mis-alignment. A p-type impurity, which is boron (B) herein, is implanted into thePMOS region 12 at an ion acceleration energy of 2 keV, a dose of 2.5×1014/cm2, and an angle of incidence of 45°. The implantation is repeated four times from directions differing from each other (four different directions inclined by 45° away from the direction of gate length). - A single ion implantation according to the above conditions results in introduction of the impurity over the area extending from the top surface to the upper portion of one side face of the
gate electrode 6 b in an amount equivalent to that possibly attained by ion implantations at an angle of incidence of 0° repeated twice. On the other hand, a pair of p-type, source-and-drain regions 10 b are protected by the resistmask 36 against the ion implantation, and are thus prevented from being implanted with the impurity. - Next, the resist
mask 36 is removed typically by ashing, and, as shown inFIG. 33D , a resistmask 41 is formed so as to cover thepMOS region 12, and an n-type impurity, which is phosphorus (P) herein, is introduced by ion implantation into thenMOS region 11 at an ion acceleration energy of 8 keV and a dose of 6×1015/cm2, to thereby form n-type, source-and-drain regions 43 a. - Next, the resist
mask 41 is removed typically by ashing, and, as shown inFIG. 34A , a resistmask 42 is formed so as to cover thenMOS region 11, and an p-type impurity, which is boron (B) herein, is introduced by ion implantation into thepMOS region 12 at an ion acceleration energy of 4 keV and a dose of 3×1015/cm2, to thereby form p-type, source-and-drain regions 43 b. - Next, the resist
mask 42 is removed typically by ashing, and, as shown inFIG. 34B , thesemiconductor substrate 1 is then annealed by RTA (rapid thermal annealing) at 1,030° C. for 1 second to thereby thoroughly activate the impurities incorporated into thegate electrodes - An interlayer insulating
film 24 is deposited over the entire surface, wirings 26 are formed so as to make contact through contact holes 25, and a CMOS transistor is completed after some additional post-processes. - As has been described in the above, the ninth embodiment is successful in controlling the impurity concentration of the
gate electrodes drain regions gate electrodes drain regions - Moreover, in the tilt-angled ion implantation, the source-and-
drain regions masks gate electrodes gate electrodes drain regions - The amount of dose in the gate electrodes and source-and-drain regions according to the first through ninth embodiments are now listed in Table 1 below.
TABLE 1 nMOS pMOS Dose in gate Dose in S/D Dose in gate Dose in S/D Prior art 6 × 1015 6 × 1015 3 × 1015 3 × 1015 (1/cm2) 1st 7.5 × 1015 (1a) 6 × 1015 (1b) 3.75 × 1015 3 × 1015 (1d) embodiment (1c) Modified 7.5 × 1015 (2a) 6 × 1015 (2b) 3.75 × 1015 3 × 1015 (2d) example (2c) 3rd 9 × 1015 (3a) 6 × 1015 (3b) 4.5 × 1015 3 × 1015 (3d) embodiment (3c) 4th 8 × 1015 (4a) 6 × 1015 (4b) 4 × 1015 3 × 1015 (4d) embodiment (4c) Modified 8 × 1015 (5a) 6 × 1015 (5b) 4 × 1015 3 × 1015 (5d) example (5c) 5th 1 × 1016 (6a) 6 × 1015 (6b) 5 × 1015 3 × 1015 (6d) embodiment (6c)
(1a) 4.5 × 1015 + 5 × 1014 × 6
(2a) 5.5 × 1015 + 5 × 1014 × 4
(3a) 5 × 1015 + 5 × 1014 × 8
(4a) 5 × 1015 + 5 × 1014 × 6
(5a) 6 × 1015 + 5 × 1014 × 4
(6a) 6 × 1015 + 5 × 1014 × 8
(1b) 4.5 × 1015 + 5 × 1014 × 3
(2b) 5.5 × 1015 + 5 × 1014 × 1
(3b) 5 × 1015 + 5 × 1014 × 2
(4b) 5 × 1015 + 5 × 1014 × 2
(5b) 6 × 1015
(6b) 6 × 1015
(1c) 2.25 × 1015 + 2.5 × 1014 × 6
(2c) 2.75 × 1015 + 2.5 × 1014 × 4
(3c) 2.5 × 1015 + 2.5 × 1014 × 8
(4c) 2.5 × 1015 + 2.5 × 1014 × 6
(5c) 3 × 1015 + 2.5 × 1014 × 4
(6c) 3 × 1015 + 2.5 × 1014 × 8
(1d) 2.25 × 1015 + 2.5 × 1014 × 3
(1d) 2.75 × 1015 + 2.5 × 1014 × 1
(1d) 2.5 × 1015 + 2.5 × 1014 × 2
(1d) 2.5 × 1015 + 2.5 × 1014 × 2
(1d) 3 × 1015
(1d) 3 × 1015
—Specific Alignment Conditions for Resist Mask and Gate Electrode Suitable for Tilt-angled Ion Implantation— - Next paragraphs will describe alignment rules for the resist mask for the tilt-angled ion implantation, and alignment rules for the gate electrode taking the tilt-angled ion implantation into account, which are applicable to the fourth through ninth embodiments.
-
FIG. 35 shows a method of determining an alignment rule of a resist masks 31 through 34 with respect to thegate electrodes sidewalls - First, L1′ is determined so that the projection range of the impurity implanted along a direction inclined in the sidewall will be longer than Rp1 based on the shape of the over-etched sidewall. Next, L1″ is determined so that the projection range of the impurity implanted along a direction inclined in the resist mask will be longer than Rp2. L1′ and L1″ are then compared, the shorter one of which is defined as L1, and a rule for the distance between the gate electrode and resist mask can be given as L1−ΔL, where ΔL is an alignment error between the gate electrode and resist pattern.
-
FIGS. 36 and 37 show a method of determining an alignment rule for the case with aligned gate electrodes in the fourth and fifth embodiments. - Rp3 herein represents the length of the gate electrode sufficient for shielding impurity implanted along direction inclined.
- First, L2′ is determined so that the projection range of the impurity implanted along a direction inclined in the over-etched sidewall will be longer than Rp1 based on the shape of the over-etched sidewall. Next, L2′″ is determined so as to allow the projection range of the impurity implanted along a direction inclined in the gate electrode impurity will be longer than Rp3. L2′ and L2′″ are then compared, and the shorter one of which is defined as L2. Assuming now a minimum formable width of a resist
pattern 111 as L3. If the distance between the adjacent gate electrodes is longer than 2(L1−ΔL)+L3, the resistpattern 111 can be formed between the adjacent gate electrodes according to the rule shown inFIG. 37 . - On the other hand, if the distance between the adjacent gate electrodes is shorter than 2(L1−ΔL)+L3 but longer than L2, it is necessary to fill the space between the adjacent gate electrodes with a resist
pattern 111 having a width of L3. If the distance between the adjacent gate electrodes is shorter than L2, there is no need to form the resistpattern 111 between the adjacent gate electrodes. -
FIG. 38 shows a method of determining an alignment rule of a resist masks 35 through 38, 41 and 42 with respect to the gate electrode, which is applicable to the sixth through ninth embodiments. Rp2 represents the length of the resist mask sufficient for shielding impurity implanted along direction inclined, and Rp3 represents the length of the gate electrode sufficient for shielding impurity implanted along direction inclined. - First, L1″ is determined so that the projection range of the impurity implanted along a direction inclined in the resist mask will be longer than Rp2. Next, L1′″ is determined so that the projection range of the impurity implanted along a direction inclined in the gate electrode will be longer than Rp3. L1″ and L1′″ are then compared, the shorter one of which is defined as L1, and a rule for the distance between the gate electrode and resist mask can be given as L1−ΔL, where ΔL is an alignment error between the ate electrode and resist pattern.
-
FIGS. 39 and 40 show a method of determining a rule for the case with aligned gate electrodes in the sixth through ninth embodiments. Rp3 herein represents the length of the gate electrode sufficient for shielding impurity implanted along direction inclined. - First, L2 is determined so that the projection range of the impurity implanted along a direction inclined in the gate electrode will be longer than Rp3. If the distance between the adjacent gate electrodes is longer than 2(L1−ΔL)+L3, the resist
pattern 111 as a part of the resist mask can be formed between the adjacent gate electrodes according to the rule shown inFIG. 40 , where L3 is a minimum formable width of the resistpattern 111. - On the other hand, if the distance between the adjacent gate electrodes is shorter than 2(L1−ΔL)+L3 but longer than L2, it is necessary to fill the space between the adjacent gate electrodes with a resist
pattern 111 having a width of L3. If the distance between the adjacent gate electrodes is shorter than L2, there is no need to form the resistpattern 111 between the adjacent gate electrodes. - This embodiment materializes a CAD software for producing a resist mask according to the rule explained referring to FIGS. 35 to 40. This makes it possible to readily produce a reticle for forming the resist mask which can prevent the impurity introduced along a direction tilt-angled from getting into the source-and-drain region. This can be realized by running a program stored in an RAM or ROM of a computer. Also such program and a computer-readable storage medium having recorded therein such program also fall within a scope of the present invention.
- More specifically, the program is provided to a computer while being stored in a recording medium such as CD-ROM, or other various transmission media. The recording media, besides CD-ROM, capable of storing the program include flexible disk, hard disk, magnetic tape, magneto-optical disk and non-volatile memory card. On the other hand, the transmission media for the program include a communication medium (such as connected line such as using optical fiber, or radio line) in a computer network system (e.g., LAN, WAN such as the Internet, radio communication network), whereby program information is transmitted as being modulated by a carrier wave.
- The aforementioned program fall within a scope of the present invention not only for the case where the functions of the above-described embodiments are materialized by the supplied program run on a computer, but also for the case where the functions of the above-described embodiments are realized by the program in cooperation with an OS (operating system) run on the computer or with any other application software, and for the case where the functions of the above-described embodiments are realized by the whole or a part of the program executed on a function expansion board or function expansion unit of the computer.
- For example,
FIG. 41 shows a block diagram of an internal constitution of a general personal user terminal device. InFIG. 41 ,reference numeral 1200 denotes computer PC. ThePC 1200 has aCPU 1201, which is designed to execute a device control software stored in aROM 1202 or a hard disk (HD) 1211, or supplied from a flexible disk drive (FD) 1212, so as to totally control the individual devices connected to a system bus.
Claims (6)
1-18. (canceled)
19. A semiconductor device comprising:
a gate electrode;
source-and-drain regions;
sidewalls covering only the lower portion of both side faces of said gate electrode; and
a silicide film formed on the exposed surface of said gate electrode, wherein
said gate electrode contains an impurity having a conductivity type same as that of the impurity contained in said source-and-drain regions, and said gate electrode has an impurity concentration larger than that of said source-and-drain regions.
20. The semiconductor device according to claim 19 , wherein said silicide film is formed as being extended from the top surface to the upper portion of both side faces of said gate electrode.
21. The semiconductor device according to claim 19 , wherein said sidewalls are composed only of an oxide film.
22. A computer program product comprising a computer-readable program code means for allowing a computer to execute a procedure for automatically forming an opening in a resist which covers a semiconductor substrate used for masking thereof in a process of introducing an impurity into a gate electrode along a direction tilt-angled to the surface of said semiconductor substrate,
said opening being formed in a size which ensures protection of areas for forming source-and-drain regions on both sides of said gate electrode from the tilt-angle introduction of the impurity.
23. A computer-readable recording medium having recorded therein a program product,
said program product comprising a computer-readable program code means for allowing a computer to execute a procedure for automatically forming an opening in a resist which covers a semiconductor substrate used for masking thereof in a process of introducing an impurity into a gate electrode along a direction tilt-angled to the surface of said semiconductor substrate,
said opening being formed in a size which ensures protection of areas for forming source-and-drain regions on both sides of said gate electrode from the tilt-angle introduction of the impurity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/071,119 US20070001245A1 (en) | 2002-08-30 | 2005-03-04 | Semiconductor device and method of fabricating the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002254672A JP4302952B2 (en) | 2002-08-30 | 2002-08-30 | Manufacturing method of semiconductor device |
JP2002-254672 | 2002-08-30 | ||
US10/648,487 US7060578B2 (en) | 2002-08-30 | 2003-08-27 | Semiconductor device and method of fabricating the same |
US11/071,119 US20070001245A1 (en) | 2002-08-30 | 2005-03-04 | Semiconductor device and method of fabricating the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/648,487 Division US7060578B2 (en) | 2002-08-30 | 2003-08-27 | Semiconductor device and method of fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070001245A1 true US20070001245A1 (en) | 2007-01-04 |
Family
ID=31972849
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/648,487 Expired - Fee Related US7060578B2 (en) | 2002-08-30 | 2003-08-27 | Semiconductor device and method of fabricating the same |
US11/071,119 Abandoned US20070001245A1 (en) | 2002-08-30 | 2005-03-04 | Semiconductor device and method of fabricating the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/648,487 Expired - Fee Related US7060578B2 (en) | 2002-08-30 | 2003-08-27 | Semiconductor device and method of fabricating the same |
Country Status (5)
Country | Link |
---|---|
US (2) | US7060578B2 (en) |
JP (1) | JP4302952B2 (en) |
KR (1) | KR100875590B1 (en) |
CN (1) | CN1256775C (en) |
TW (1) | TWI237292B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080254586A1 (en) * | 2007-04-12 | 2008-10-16 | Min Byoung W | Soi semiconductor device with body contact and method thereof |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060289800A1 (en) * | 2005-03-22 | 2006-12-28 | Murrell Adrian J | Implanting a substrate using an ion beam |
KR100935770B1 (en) * | 2007-11-26 | 2010-01-06 | 주식회사 동부하이텍 | Semiconductor device and method of fabricating the same |
KR100973267B1 (en) * | 2008-01-10 | 2010-07-30 | 주식회사 하이닉스반도체 | Method of manufacturing MOSFET device |
JP2009218580A (en) * | 2008-03-06 | 2009-09-24 | Toshiba Corp | Bidirectional halo injection |
CN102024703B (en) * | 2009-09-17 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Doping method |
JP2011119606A (en) | 2009-12-07 | 2011-06-16 | Sen Corp | Method of manufacturing semiconductor device |
CN102185003B (en) * | 2011-04-15 | 2013-04-10 | 复旦大学 | Optical detector consisting of tunneling field effect transitor and manufacturing method thereof |
CN102306630B (en) * | 2011-09-01 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | The forming method of transistor PN junction |
US10096489B2 (en) * | 2014-03-06 | 2018-10-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
WO2017113266A1 (en) * | 2015-12-31 | 2017-07-06 | 上海凯世通半导体有限公司 | Finfet doping method |
JP2020057639A (en) * | 2018-09-28 | 2020-04-09 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and method of manufacturing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5726479A (en) * | 1995-01-12 | 1998-03-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having polysilicon electrode minimization resulting in a small resistance value |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2685149B2 (en) * | 1988-04-11 | 1997-12-03 | 住友電気工業株式会社 | Method for manufacturing field effect transistor |
KR100329769B1 (en) | 1998-12-22 | 2002-07-18 | 박종섭 | method for forming titanium polycide gate electrode |
JP3147108B2 (en) * | 1999-01-20 | 2001-03-19 | 日本電気株式会社 | Method for manufacturing semiconductor memory device |
KR100289810B1 (en) * | 1999-05-10 | 2001-05-15 | 김영환 | Halo ion implantation method for fabricating a semiconductor device |
US6194278B1 (en) * | 1999-06-21 | 2001-02-27 | Infineon Technologies North America Corp. | Device performance by employing an improved method for forming halo implants |
US6458666B2 (en) * | 2000-06-09 | 2002-10-01 | Texas Instruments Incorporated | Spot-implant method for MOS transistor applications |
-
2002
- 2002-08-30 JP JP2002254672A patent/JP4302952B2/en not_active Expired - Fee Related
-
2003
- 2003-08-22 TW TW092123169A patent/TWI237292B/en not_active IP Right Cessation
- 2003-08-27 US US10/648,487 patent/US7060578B2/en not_active Expired - Fee Related
- 2003-08-28 CN CNB031555594A patent/CN1256775C/en not_active Expired - Fee Related
- 2003-08-29 KR KR1020030060160A patent/KR100875590B1/en not_active IP Right Cessation
-
2005
- 2005-03-04 US US11/071,119 patent/US20070001245A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5726479A (en) * | 1995-01-12 | 1998-03-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having polysilicon electrode minimization resulting in a small resistance value |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080254586A1 (en) * | 2007-04-12 | 2008-10-16 | Min Byoung W | Soi semiconductor device with body contact and method thereof |
US7927934B2 (en) * | 2007-04-12 | 2011-04-19 | Freescale Semiconductor, Inc. | SOI semiconductor device with body contact and method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP4302952B2 (en) | 2009-07-29 |
KR100875590B1 (en) | 2008-12-23 |
US20040041177A1 (en) | 2004-03-04 |
CN1256775C (en) | 2006-05-17 |
CN1489220A (en) | 2004-04-14 |
TW200416778A (en) | 2004-09-01 |
US7060578B2 (en) | 2006-06-13 |
JP2004095835A (en) | 2004-03-25 |
KR20040020035A (en) | 2004-03-06 |
TWI237292B (en) | 2005-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070001245A1 (en) | Semiconductor device and method of fabricating the same | |
US6403423B1 (en) | Modified gate processing for optimized definition of array and logic devices on same chip | |
US6180472B1 (en) | Method for fabricating semiconductor device | |
JP4931267B2 (en) | Semiconductor device | |
US6992358B2 (en) | Semiconductor device and method for manufacturing the same | |
US7656008B2 (en) | Semiconductor devices and methods of forming the same | |
US7939397B2 (en) | Method of manufacturing semiconductor device | |
US7419864B2 (en) | Semiconductor device and method of manufacturing the same | |
US7928515B2 (en) | Semiconductor device and manufacturing method of the semiconductor device | |
US7417283B2 (en) | CMOS device with dual polycide gates and method of manufacturing the same | |
WO2006117851A1 (en) | Semiconducteur device and method for manufacturing same | |
US6849490B2 (en) | Semiconductor device having a memory cell region and a peripheral circuit region and method of manufacturing thereof | |
JP2004363443A (en) | Non-volatile semiconductor storage device and its manufacturing method | |
JP4529024B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2001196549A (en) | Semiconductor device and manufacturing method therefor | |
JPWO2006035503A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US20030111708A1 (en) | Semiconductor devices and methods of fabricating the same | |
US20060063321A1 (en) | Semiconductor device and method of fabricating the same | |
KR100674800B1 (en) | Method for manufacturing semiconductor device | |
US7679144B2 (en) | Semiconductor device and method for manufacturing the same | |
KR100545707B1 (en) | Method of manufacturing a semiconductor device having a floating gate in the boundary region of transistors | |
JPH09321287A (en) | Fabrication of semiconductor device | |
KR20050068564A (en) | Semiconductor device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |