US20060255772A1

US20060255772A1 - High-Q digital active power factor correction device and its IC

Info

Publication number: US20060255772A1
Application number: US11/488,991
Authority: US
Inventors: Weibin Chen
Original assignee: Individual
Current assignee: Individual
Priority date: 2003-01-27
Filing date: 2006-07-18
Publication date: 2006-11-16
Also published as: US20060256588A1; US7551464B2

Abstract

A method for digitally processing high-quality active PFC includes a step of regulating PFC reference signal at a predetermined ending point of each cycle; wherein the cycle is integer multiple of the half cycle of the commercial power, and the ending point of the cycle is synchronized with the edge of the half cycle.

Description

CROSS REFERENCE OF RELATED APPLICATION

This is a Divisional application of a non-provisional application having an application Ser. No. 10/510,198 and filing date of Sep. 29, 2004.

BACKGROUND OF THE PRESENT INVENTION

1. Field of Invention
The present invention relates to switch power supply, and more particularly, relates to a kind of digital high-Q active power factor correcting (i.e. PFC) method, device and its IC.
2. Description of Related Arts
PFC (Power Factor Correction) could be classified into the single phase PFC and three phases PFC, CCM (Continuous Current Mode) PFC, DCM (Discontinuous Current Mode) PFC, boost PFC, boost/buck PFC converter, and flyback PFC converter. Further, there are constant frequency controlling techniques, constant conduction time controlling technique, and equal area control techniques associated with the DCM mode. And there are peak value current controlling technique, average current controlling technique, lag loop current controlling technique, hard switch and soft switch technique associated with the CCM mode.
Regardless what kinds of converter and switching circuits are being used, a PFC device generally comprises a converter circuit having one or more power tubes, a transformer or an induction, and an output circuit. In case of a soft switch is applied, at least one supplemental power tube and a soft switch circuit are employed. And in case of flyback converting mode is used, a transformer would be necessary.
The PFC device further comprises a feedback circuit having a sample circuit, an error amplifier wherein the sample circuit is adapted for sampling the current signal from the output circuit and then sending the sampled current signal to the error amplifier to generate an error signal.
The PFC further comprises a control circuit including an adjustable pulse circuit and a driven circuit, wherein the error signal is send to the adjustable pulse circuit and the driven circuit is adapted for driving the power tube. It is noted that there is a variety of adjustable pulse circuits available depending which kind of converter circuits and the controlling techniques being used. Commonly, the most used control circuits include constant conduction time control circuit (for example, UC3852, after the power tube is conducted, the induction current will be increased and the conduction time will be determined by the error signal outputted by the error amplifier, after the power tube is shut off, the induction current will be decreased; if the induction current is fallen down to zero, the power tube will be conducted again indicating that the circuit is performing at a transition point between DCM and CCM). Some popular control circuits also include average time control circuit (for example, UC3854 comprising a multiplicator, a current error amplifier, PWM, and an oscillator), flyback converter control circuit, soft switching control circuit, and so on.
Finally, the PFC device also comprises a supplemental circuit which is selected from a group consisting of initiating circuit, protective circuit, voltage reference circuit, EMC circuit, alternate rectifying filter circuit. To prevent the PFC outputting voltage being excess the upper limit, designers within the art have to balance the following factors, such as the outputting capacity of the capacitor, power factors, and total harmonic distortion. In other words, users have to sacrifice some factors to achieve a feedback function. For instance, when the circuit is under a heavy load, the power factor will be reduced and the total harmonic distortion will be accordingly increased. However, sacrifice could solve all troubles, in case of the outputting voltage excesses the design value, or the outputting is converted from a heavy load to a light load suddenly, the control circuit sometimes is unaware or unable to judge whether the outputting voltage being over the upper limit. This is due to some inherent factors of voltage error feedback and input voltage filter waves. As a result, there still exist potential risks in conventional PFC circuits.

SUMMARY OF THE PRESENT INVENTION

A primary object of the present invention is to provide a method for digitally processing high quality PFC.
Another object of the present invention is to provide a device for digitally processing high quality PFC as well as its IC.
Another object of the present invention is to provide a digital process and high quality PFC method, wherein a reference circuit and a PFC reference signal are applied for replacing the conventional feedback circuit and error signal. The reference circuit comprises a series of voltage signal sample circuit of the output circuit, voltage signal detection or module converter (A/D) circuit, reference logic circuit and reference output circuit. The reference logic circuit is adapted for digitally processing the voltage signal so as to generate a digital PFC reference signal, and for regulating PFC reference signal at a predetermined ending point of each cycle, wherein during each cycle, PFC reference signal is kept constant. Said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle. Or, said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle. Or, said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC1000-3-2 and IEC1000-3-4 standards.
Accordingly, the present invention further provides a PFC device based on the above digital process and high quality PFC method, comprising:
a converter circuit having one or more power tubes, a transformer or an inductance, and an output circuit;
a reference circuit;
a control circuit having a pulse adjustable circuit and a driven circuit, wherein the PFC reference signal is feed into the pulse adjustable circuit for controlling a generation of a pulse; and
a supplemental circuit selected from a group consisting of initiating circuit, protective circuit, voltage reference circuit, EMC circuit and so on.
According to the present invention, the pulse adjustable circuit comprises a proportional current circuit, a timing circuit, a pulse width adjustable logic circuit, a current amplifier and an oscillator wherein the PFC reference signal is applied as the input of the proportional current circuit, a pair of proportional current of said proportional current circuit are send to said timing circuit, a pair of digital signal of said timing circuit are send to the pulse width adjustable logic circuit which in turn is adapted for outputting a pair of digital signal to said timing circuit, the output signal of the current amplifier is send to the timing circuit, the output signal from the oscillator is send to the pulse width adjustable logic circuit, finally the pulse width adjustable logic circuit will output a pulse signal. The different portion of the pulse adjustable circuit will be discussed in details later.
The PFC device of the present invention utilizes power factor to correct IC which comprises a portion of reference circuit and control circuit.
The digitally processing high quality PFC have distinguished characteristics and effects thus generating advantageous edge and quality, and will ultimately save the costs as well as improve the overall quality.
These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an undefined digital process and high quality PFC according to the preferred embodiment of the present invention.
FIG. 2 is a schematic diagram showing an alternative mode of an undefined digital process and high quality PFC according to the preferred embodiment of the present invention.
FIG. 3 is a schematic diagram showing a simplified digital process and high quality PFC according to the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the FIG. 1, FIG. 2 and FIG. 3, the independent PFC are illustrated wherein IC are circumscribed within the dash line. R3 is adapted for checking PFC induction Lp current, and the PFC current (Lp current) reference output filter capacitor Cir and high power tube Qp could be resided outside or integrated within the IC. UD is commercial power rectifier synchronous input and RV is high voltage, high resistible resistance. Rh, R1 are PFC output voltage signal sample circuit, which is adapted for filtering the high frequency voice of thousands Hz. VA is adapted for checking the voltage signal, having a quad-voltage comparator for outputting a first high voltage Vhh, a second high voltage Vh, a first low voltage Vl and a second low voltage Vll signal, or an Analog/Digital converter. IR0 is a PFC current reference (said PFC reference signal) output accumulator (which is adapted to convert the extra output into capacity Cir voltage for providing a reference for PFC current, and such conversion is a sort of D/A conversion, wherein the capacity Cir voltage is inversely proportioned with respect to IR1); IR1 is a present PFC current reference output register; IR2 is PFC current reference output register; IR3 is major cycle PFC average current reference output register; II is present PFC current reference output register (IR1) major cycle accumulator; CT is a major cycle counter; IR0, IR1, IR2, and IR3 (according to the accuracy) are preferably set with 8 bit or 9 bit; while CT is adapted to be chosen from a relative wide range, preferably 12 bit, since the major circle is suppose to be larger than commercial circle; and II is preferably set at 20 bit or 21 bit.
As shown in FIG. 1, PFC current reference generating logic (IR logic), i.e. a digital processing unit, is adapted to delay time to an extent after power on reset. PFC logic sets a permissive signal to achieve the PFC soft enablement, and at the same time, set the IR2 and IR3 as the half value of its maximum value, and II and CT reset; after a major cycle is accomplished, a major cycle current reference output average value obtained from the II will be feed in the IR3, and then a new major cycle is re-enabled; voltage detecting 0000 (i.e. Vhh=0, Vh=0, Vl=0, Vll=0), IR1 is set to be the maximum value (stf), so as to prevent PFC outputting voltage falling down too much; voltage detection 1111, IR1 is set to 0 (c10), PFC logic is set prohibitive signal so as to prevent output voltage from being excess the upper limit, after the voltage detection is resumed to 0011, PFC logic sets a permissive signal; if voltage detection is non-0000 or non-1111, and PFC logic is set to be permissive, IR2 is sub-classed into IR1; If the voltage detection is from 0000 to 0001 or from 1111 to 0111, IR3 is sub-classed into IR2, and the major cycle average current is set as reference; if voltage detection is from 0111 to 0011 and then 0111, IR2 is down to search the real IR2 value; if voltage detection is from 0011 to 0001 and then 0011, IR2 is up to search the real IR2 value; for those stable load, IR2 is adapted to either up or down, i.e. minus one or add one would be applicable. For those load with a wide range, an adjustable equivalent register would be helpful, if IR2 is detected of continuous variance, the registering volume of the adjustable equivalent register would be correspondingly changed. Therefore, there exists a necessity to enable a limited method for ensuring IR2 bigger than a preset value, so as to guarantee PFC working in a continuous manner.
As shown in FIG. 2, PFC current reference generating logic (IR1 logic) is illustrated. It is quite similar with above mentioned IR logic, wherein the difference is that alternation of the IR2 is synchronized with the edge of UD (namely, UD sync or the half cycle sync of the commercial power); if voltage detection is 0000 to 0001, or 1111 to 0111, UD sync IR3 is sub-classed into the IR2; if voltage detection is 0111, UD sync IR2 would be down; if voltage detection is 0001, UD sync IR2 would be up; if voltage detection is 0011 non-activated. Therefore, PFC current reference would be kept at a constant level under the half cycle of the commercial power.
As shown in FIG. 3, PFC current reference generating logic (IR2 logic) should be delay to an extent after the power on reset, and PFC logic permissive signal is set so as to accomplish the PFC soft enablement procedure; in case of voltage detection 1111, PFC logic set a prohibitive signal; UD sync voltage detection 0111, PFC current reference is set Ri1; UD sync voltage detection 0011, PFC logic set a permissive signal, and PFC current reference is set Ri2; UD sync voltage detection 0001, PFC current reference is set Ri3; In case of UD sync voltage detection is 0000, PFC current reference is set Ri4; current references Ri1, Ri2, Ri3, Ri4 are arranged in a gradually increased manner, for example, 25%, 50%, 75%, 100%; or otherwise 40%, 60%, 80%, and 100%; In response to different version, VA should be correspondingly regulated, and deemed as D/A conversion. As a result, D/A conversion could be designed to 4 bit D/A conversion and IR2 logic could be designed to be more complicated. What is more, PFC current reference value could be accurately calculated based on the voltage detection. It is noted that the variation of PFC current reference should be synchronously mated with UD.
The logic unit generated from PFC current reference shown in FIG. 1, FIG. 2 and FIG. 3 could directly replace the error amplifier of UC3854 IC and the like, so as to form a safer, superb and high quality continuous current mode control IC; or otherwise, the logic units could directly replace the error amplifier of the UC3852 and the like so as to form a safer and reliable non-continuous current mode, constant conductible time control IC.
PFC shown in the FIG. 1, FIG. 2, and FIG. 3 could be embodied as average current mode, which is working under CCM or DCM (for DCM, R3 detected PFC current should be filtered first to be send to −4 amplifier); −4 is PFC current amplifier, and the output of the PFC current amplifier is send to the timing circuit; Imk is a proportional current circuit, comprising three transistor or MOS tubes (MOSFET), one for PFC current reference input, the other two for proportional output. The timing circuit comprises two proportioning capacitors, (shown as 30PF and 15PF, being either disposed within or outside the IC. Here, the two proportioning capacitors are shorten as Ct2 and Ct1), two transistor or MOSFET Ta and Tb adapted for discharging the proportioning capacitors, and two amplifiers Aa and Ab for monitoring the voltages of the two proportioning capacitors, wherein a pair of digital signal are respectively feed into Ta and Tb, and then Aa and Ab will output a pair of digital signals. PFC reference output circuit outputs a current reference via Cir, Ri so as to generate a steady-flow current through Imk for charging a pair of capacitors having a 2:1 capacity ratio; the mechanism of the PFC logic (pulse width adjustable logic circuit) is working synchronously with oscillator, but is subject to the control of the PFC logic permissive signal; if the oscillator is on rising edge, and then PFC enters into a cut-off period, that is to say, the PFC power tube Qp is off, and PFC induction Lp current will be decreased, Ct2 discharging tube Ta is off and steady flow charged; Ct1 discharging tube Tb is kept on and CT1 voltage is kept 0. when the current represented by the Ct2 voltage reach the same level of the PFC induction voltage, i.e. the comparator Ab is on rising edge, Ct1 discharging tube Tb is turned off and steady flow charged. When the Ct1 voltage catches up the Ct2 voltage, that is to say, the comparator Ab is on the rising edge, the PFC enters into an enablement period, PFC power tube Qp is enabled, PFC induction Lp current will be increased; Ct2 discharging tube Ta and Ct1 discharging tube Tb are enabled, Ct1 and Ct2 are discharged to be 0 voltage. Until the rising edge of the next oscillator is close and a new PFC cycle is initiated. It is proven that the controlling method according to the present invention, under a continuous current mode and R3 detection is free of filtration, PFC is a desirable average current mode, and more importantly, when Aa is on the rising edge, Lp current is embodied as average current.
VA voltage signal detection shown in the FIG. 1, FIG. 2 and FIG. 3, could apply four different check output signals, or A/D converter for outputting voltage value. As a result, VA is A/D conversion, and PFC current reference ultimately could be converted into a D/A converter (or reference output circuit). However, the PFC current reference generating logic should be compliable with the following rules: VA input is non-filterable or the high frequency voice is free; preferably, Vhh logic is applicable, when vhh=1. PFC will prevent the PFC output voltage from being excessed the upper limit; and the best option is preferably, Vll logic is applicable, when Vll=0, PFC sets a high or a maximum reference value, so as to prevent PFC outputting voltage from falling too much and to simplify the monitoring process, Vll monitoring signal is preferably be outputted. Even though Vhh and Vll is optional, but the Vhh and Vll PFC is safer and more reliable. When non-Vhh=1 and non-Vll=0 are not guaranteed, PFC could maintain PFC current reference being constant during a major cycle. In other words, whenever a major cycle is initiated or terminated, the current reference would be adjusted. Furthermore, the major cycle should be synchronously mating with the edges of half cycle's integer multiple or far above the commercial power's half cycle. According to the A/D of VA input and D/A conversion's complication, a more accurate PFC current reference logic sounds more reliable. As a result, the PFC techniques according to the present invention could be embodied as single processing unit (MCU) having digital processing logic.
Accordingly, the digital processing PFC control circuit of the present invention has a desirable power factor and an ideal total harmonic distortion, and is deemed as a high quality PFC control circuit.
One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.
It will thus be seen that the objects of the present invention have been fully and effectively accomplished. It embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure form such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.

Claims

1. A method for digitally processing high-quality active PFC, comprising a step for regulating PFC reference signal at a predetermined ending point of each cycle; wherein said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle.

2. The method, as recited in claim 1, wherein said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle.

3. The method, as recited in claim 1, wherein said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC 1000-3-2 and IEC 1000-3-4 standards.

4. A PFC device, comprising:

a converter circuit having one or more power tubes, a transformer or an inductance, and an output circuit;

a control circuit;

a PFC reference signal, regulating PFC reference signal at a predetermined ending point of each cycle; wherein said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle;

a reference circuit, comprising a series of voltage signal sample circuit of an output circuit, a voltage signal detection circuit, a reference logic circuit and a reference output circuit, wherein PFC reference signal of said reference output circuit is send to said control circuit to generate a pulse; and

a supplemental circuit.

5. The PFC device, as recited in claim 4, wherein said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle.

6. The PFC device, as recited in claim 4, wherein said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC 1000-3-2 and IEC 1000-3-4 standards.

7. A PFC IC, comprising:

a PFC reference signal, regulating PFC reference signal at a predetermined ending point of each cycle; wherein said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle; and

a portion of a reference circuit, comprising a voltage signal detection circuit, a reference logic circuit and a reference output circuit, wherein PFC reference signal of said reference output circuit is send to the control circuit to generate a pulse.

8. The PFC IC, as recited in claim 7, wherein said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle.

9. The PFC IC, as recited in claim 7, wherein said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC1000-3-2 and IEC1000-3-4 standards.

10. The PFC IC, as recited in claim 7 or 8 or 9, further comprising a pulse adjustable circuit comprising a proportional current circuit, a timing circuit, a pulse width adjustable logic circuit, a current amplifier and an oscillator wherein the PFC reference signal is applied as the input of the proportional current circuit, a pair of proportional current of said proportional current circuit are send to said timing circuit, a pair of digital signal of said timing circuit are send to the pulse width adjustable logic circuit which in turn is adapted for outputting a pair of digital signal to said timing circuit, the output signal of the current amplifier is send to the timing circuit, the output signal from the oscillator is send to the pulse width adjustable logic circuit, finally the pulse width adjustable logic circuit will output a pulse signal.