US20060190908A1

US20060190908A1 - Coding of FPGA and standard cell logic in a tiling structure

Info

Publication number: US20060190908A1
Application number: US11/375,891
Authority: US
Inventors: Stanislav Bajuk; Jack Smith; Sebastian Ventrone
Original assignee: Individual
Current assignee: GlobalFoundries Inc
Priority date: 2003-06-25
Filing date: 2006-03-15
Publication date: 2006-08-24
Also published as: US20040268288A1; US7080344B2

Abstract

A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

Description

BACKGROUND OF INVENTION

1. Technical Field
The present invention relates in general to a field of logic design, and in particular to the partitioning and synthesis of field programmable gate array (FPGA) and standard cell logic. Still more particularly, the present invention relates to a method and system for dynamically shifting the boundary between FPGA and standard cell logic within a physically placeable block that can simultaneously hold both FPGA and standard cell elements
2. Description of the Related Art
Building computer logic takes many steps before the computer logic is physically manufactured. The logic designer typically uses synthesis tools, such as register transfer languages (RTL) such as Verilog® and VHDL (Very-high-speed-integrated-circuit Hardware Descriptor Language) to describe, design and document electronic circuits. A typical RTL file includes a description of the interfaces to the logic and its behavior.
Two types of devices that can implement logic are FPGA (Field Programmable Gate Arrays) and Standard Cell. FPGAs use a 2-dimensional array of logic cells that are programmable, such that the FPGA functions as a custom integrated circuit (IC) that is modified by program code. Thus, a same FPGA can be alternately programmed to selectively perform the function of many different logic circuits. Typically, the programming of the FPGA is persistent until re-programmed at a later time. The persistent nature may be permanent (e.g., by blowing fuses in gates) or modifiable (by storing the programming code in a programmable memory). Standard cell, on the other hand, is hard-wired logic that is not modifiable after it is manufactured. Although it does not have the flexibility of a FPGA, standard cells is usually much faster than FPGA. Furthermore, FPGAs typically have many more gates and logic components than standard cells, since only a part of the FPGA circuit is typically used in any selected
A tile is a physically placeable block that contains some portion of FPGA (0% to 100%) and another portion of standard cell (0% to 100°%). By having the technology vendor's library offer several variations of tiles, all of which have the same outline size but different portions of FPGA and standard cell, the designer can repartition logic with a tile and replace it during the physical design phase with an alternate tile that represents the new partition. In addition, the library preferably contains tiles of smaller and larger sizes that can be selected to implement the logic in the appropriate amount of area on the IC.
The above, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.

BRIEF DESCRIPTION OF DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, where:
FIG. 1 a depicts a prior art in which separate register transfer language (RTL) files are created and maintained for FPGA and standard cell portions of a design;
FIG. 1 b illustrates a placeable logic tile composed of field programmable gate array (FPGA) logic and standard cell space logic;
FIG. 1 c depicts a complex hierarchical application specific integrated circuit (ASIC) design composed of many FPGA and standard cell files;
FIG. 2 illustrates a register transfer language (RTL) file that targets portions of a design to FPGA and other portions to standard cells as accomplished through the use of the present invention;
FIG. 3 is a table depicting new RTL wire type declarations as taught by the present invention;
FIGS. 4 a-c depict how a portion of a design is repartitioned to move from standard cell to FPGA using the wire types described in the present invention, where FIG. 4 a depicts an initial logic partitioning, FIG. 4 b shows a new partitioning requested by a design tool, and FIG. 4 c illustrates a final partition;
FIGS. 5 a-b illustrate options for partitioning a standard cell wire and an FPGA wire;
FIG. 6 is a flow-chart describing the design flow from initial RTL through synthesis, repartioning the FPGA/Standard Cell boundary to meet design constraints, and updating the RTL to reflect the new boundary; and
FIGS. 7 a-b depict a logic repartitioning step to accomplish either greater speed (with smaller size) or greater flexibility.

DETAILED DESCRIPTION

With reference now to FIG. 1 b, there is depicted a placeable logic tile composed of field programmable gate array (FPGA) 102 logic and standard cell 104 logic, as defined and understood by the teachings of the present invention. Such a placeable logic tile may be highly complex as contemplated by the present invention, as illustrated in FIG. 1 c.
With reference now to FIG. 2, there is depicted a single RTL file array 200 containing logic that is targeted to both FPGA and standard cell. FPGA logic 202 and standard cell logic 204 are able to reside in the same RTL file 200 since they have file extensions, described in detail below, defining the interconnects (“wires”) to each type of logic, thus allowing synthesis tools to recognize and handle each portion appropriately.
Unlike prior art RTL files in which only a single wire type (“wire”) was defined without regard to whether the design was targeted to FPGA or standard cell technology, the present invention defines multiple wire types, as shown in FIG. 3. RTL files under the present invention have extensions defining one of six different types of wires. A wire is defined as an RTL-specific interconnect type, such as an input node, an output node, or an internal connection node in a logic, that carries a logic signal (i.e., is not a power line).
Extension 302 (Swire) describes/defines a standard cell fixed wire, which cannot be modified to become an FPGA wire. Extension 304 (Fwire) describes/defines an FPGA wire, which cannot be modified to become a standard cell wire. Extension 306 (sFwire) describes an intermediate wire type, which, as described in more detail below, is an FPGA wire that can later be modified to become a standard cell wire. Extension 308 (fSwire) describes another intermediate wire type, which, as described below, is a standard cell wire that can later be modified to become an FPGA wire. Extension 310 (Sfwire) describes a standard cell wire, which can be modified to become an FPGA wire. Extension 312 (Fswire) describes an FPGA wire, which can be modified to become a standard cell wire.
With reference now to FIG. 4 a, there is depicted a block diagram of an initial logic partitioning having four example logics and their interconnect wires. Logic 3 is an FPGA logic, and as such has only FPGA type input wires, which as shown are two control lines (cntl1 and cntl2) identified and defined as Fswire's 312 a and 312 b. Also input into logic 3 is an 8-bit inbus identified as Fswire 312 c. Note that only Fswire defined wires are able to be input into an FPGA logic. The output of FPGA logic 3 is shown as node1 which is an Sfwire 310 a. That is, the output of the FPGA logic 3 does not have to be an FPGA wire; only the input to an FPGA logic must be an FPGA wire.
Sfwire 310 a is input into logic 2 a, which is a standard cell logic. Also input into logic 2 a is a control line (cntl3) identified and described as Sfwire 310 b. Analogous to an FPGA logic, a standard cell logic can take only standard cell inputs. Logic 2 a has an output at node2 identified and described as Fswire 312 f, which is one of the inputs to FPGA logic 4. The other input to FPGA logic 4 a is Fswire 312 g, coming from the node3 output of standard cell logic 1. The output from logic 4 is the outbus identified/described as Sfwire 310 c. Also shown in FIG. 4 a is Verilog®pseudo code describing this initial logic partitioning.
As each of the wires shown in FIG. 4 a are adjustable, this indicates that they can be transformed to an FPGA or standard cell wire if the logic to which they are input changes. In a preferred embodiment, however, such a transformation of wires takes two steps, an intermediate step and a final step, in order to allow the logic designer an opportunity to accept or reject the proposed wire changes. Such an intermediate step, along with pseudo code, is illustrated in FIG. 4 b. The only logic to be changed from that shown in FIG. 4 a is logic 2 b, which is now proposed as an FPGA logic cell. Logic 2 b must now have FPGA input wires, which are illustrated as proposed wires fSwire 308 a and fSwire 308 b.
FIG. 4 c illustrates the state of the logic shown in FIGS. 2 a-b after moving logic 2 to FPGA. If proposed fSwires 308 a and 308 b are accepted by the logic designer, then they are designated/defined as final wires Fswire 312 d and Fswire 312 e. Incremental synthesis of logic into FPGA is thus permitted as the inputs are now properly defined.
The process shown in FIGS. 4 a-c is summarized in FIG. 5 a. Sfwire 310 a was originally an input to a standard cell. A tool driven request is then made to move the standard cell into FPGA, resulting in the input to the new FPGA cell to be temporarily defined as fSwire 308 a. If the logic designer accepts the change, then the fSwire 308 a is redefined as Fswire 312 d, which it will remain (as an FPGA wire) unless another request comes in requesting the change it back into a standard cell wire.
FIG. 5 b describes a similar process as shown in FIG. 5 a, except that the process is used to redefine an FPGA wire into a standard wire. Thus, an FPGA Fswire 312, upon a tool driven request to move the logic, to which Fswire 312 is an input, from FPGA to a standard cell, redefines the Fswire 312 to the intermediate definition sFwire 306. If the logic designer accepts the change, then the sFwire 306 is redefined as final standard cell wire Sfwire 310, whose definition will remain unless a new request comes in the change back to FPGA logic.
Referring now to FIG. 6, there is illustrated a flow-chart of a process of utilizing the re-designation of wires to achieve an optimal logic chip. Starting at block 602, the initial coding with signal declarations is performed in the RTL file. That is, an original “layout” of the chip using FPGA and standard logic cells is defined in the RTL file. Using a retrieval process, known as “cone trace,” each portion of RTL code, both for FPGA and standard cells, is retrieved (block 604), and the standard cells and FPGA cells are mapped onto the technology (synthesized), whether that be an FPGA cell (defining code used to program the FPGA cell shown in block 608) or a standard cell (defining the layout of hard logic as shown in block 606). A preliminary decision is made (block 609) as to whether the design meets the overall circuitry requirements as defined by the circuit designer. If so, then the process ends. If not, then there is an incremental synthesis/repartitioning of the logic, as described in block 610, by moving at least a portion of the logic from one logic type to another (FPGA to standard cell or standard cell to FPGA) to meet the design requirements. Change suggestions are then made to reconcile the wire inputs to the newly defined logic partition (block 612), preferably using the fSwire or sFwire designations. If the logic designer accepts the changes (decision block 614) then the RTL file is updated with the new wire designation (Fswire or Sfwire), as described in block 616. If the designer does not accept the suggested change, then the designer can manually change the RTL and resynthesizes as needed to meet the design requirements (block 618).
The iterative process described above allows the logic designer to dynamically change the structure of the logic without manually having to delete wires and constructs from one RTL file (such as an FPGA file) and then re-building the deleted wires/constructs for the new logic in another RTL file (such as a standard cell file). The process described in FIG. 6 thus allows the logic designer to optimize the logic according to the need for flexibility or speed/size. Thus, as shown in FIG. 7 a, if the designer of logic tile 702 wishes to place more logic in standard cells to have a small die size and a faster chip (but at the expense of flexibility), then logic cells and their wires are moved from FPGA 702-F to standard cell space 702-S, resulting in a smaller FPGA 704-F and a slightly larger standard cell space 704-S, resulting in an overall faster and smaller logic tile 704. Similarly, as shown in FIG. 7 b, if the logic designer wishes to make logic tile 706 more flexible, then logic is moved from standard cell space 706-S to

Claims

1-21. (canceled)

22. An array of placeable logic tiles, said array comprising:

a plurality of placeable logic tiles, each of said plurality of placeable logic tiles having a same outline size by a different amount of field programmable gate array (FPGA) and standard cell logic, wherein a first placeable logic tile from said plurality can replace a second placeable logic tile from said plurality to effectively more a boundary between the FPGA and standard cell logic within the tile.

23. A set of placeable logic tiles comprising:

a plurality of placeable logic tiles, each of said plurality of placeable logic tiles having a different outline size and a different amount of field programmable gate array (FPGA) and standard cell logic, wherein a first placeable logic tile can replace a second placeable logic tile of different outline size.