CN100451553C - Wide-voltage range signal shunt based on FPGA - Google Patents
Wide-voltage range signal shunt based on FPGA Download PDFInfo
- Publication number
- CN100451553C CN100451553C CNB2006100197513A CN200610019751A CN100451553C CN 100451553 C CN100451553 C CN 100451553C CN B2006100197513 A CNB2006100197513 A CN B2006100197513A CN 200610019751 A CN200610019751 A CN 200610019751A CN 100451553 C CN100451553 C CN 100451553C
- Authority
- CN
- China
- Prior art keywords
- pin
- resistance
- signal
- comparer
- triode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Electronic Switches (AREA)
- Amplifiers (AREA)
Abstract
A wide pressure range signal shunting-implement based on FPGA program frequency divider, 2-digitization comparator and arithmetic counter by hardware described language VHDL and integrates into one FPGA1. The fan-out to frequency divider of FPGA1 connects with the input-port to 2-digitization comparator and the fan-out to 2-digitization comparator connects with the input-out to arithmetic counter. One end to the wide pressure signal accepting and photoelectric insulation module connects with the +5-+24VDC signal input-port, the other end connects with two or more than two same FPGA. It owns wide press range for +4VDC-+26VDC, and well insulation effect, goo wave quality, easy removing and strong anti-jamming nature. The characteristic is small volume, low cost, short exploitation cycle and suited for abominable industry environmental.
Description
Technical field
The present invention is for belonging to wide-voltage range code device signal tripping device.Relate in particular to a kind of wide-voltage range signal shunt based on FPGA.
Background technology
Scrambler is widely used in the collection of industrial motor parameter.Modern industry often requires the signal of scrambler collection is delivered to more than equipment such as frequency converter, terminal monitor etc.It is often infeasible that an above scrambler is installed on same motor, therefore separates and duplicate for the signal of scrambler collection to seem particularly important.The OPT029-501 of BALDOR company is a kind of code device signal tripping device, but this product has open defect: at first, the signal that this product does not separate needs carries out photoelectricity isolates, and has caused its range of application narrow; Secondly, the input and output voltage of this product all is the 5VDC fixed value, can not adjust in certain voltage range, therefore can not satisfy the requirement of some receiving equipments to input voltage; At last, this product can not be proofreaied and correct and shaping the signal of scrambler collection according to on-site actual situations.
Summary of the invention
The purpose of this invention is to provide and a kind ofly have the input of wide voltage signal, isolate the molded breadth voltage power and drive output, can carry out signal waveform and proofread and correct that shaping, upgrading are convenient, the wide-voltage range signal shunt based on FPGA of strong interference immunity.
For achieving the above object, the technical solution adopted in the present invention is: with Hardware Description Language VHDL programming and be integrated among a slice FPGA, the output terminal of the frequency divider among the FPGA is connected with the input end of binaryzation comparer, the output terminal of binaryzation comparer is connected with the input end of algorithm computation device with frequency divider, binaryzation comparer and algorithm computation device; Wide voltage signal receives and the end and+5 of photoelectric isolation module～+ signal input part of 24VDC is connected, and the other end of wide voltage signal reception and photoelectric isolation module is connected respectively with 2 same FPGA.
A slice FPGA wherein, the input end of the binaryzation comparer among wide voltage signal reception and photoelectric isolation module and the FPGA is connected, the output terminal of the algorithm computation device among the FPGA is connected with the input end of wide voltage power output driver module, and the output terminal of wide voltage power output driver module is connected with terminal device.
Described wide voltage signal receive and photoelectric isolation module in A with the first via circuit of/A phase input signal reception and photoelectric isolating circuit be: the A phase input signal is connected with the pin 2 of comparer U1 through resistance R 1, resistance R 3 dividing potential drops, power supply is connected with the pin 3 of comparer U1 through resistance R 2, resistance R 4 dividing potential drops, / A ground connection GND1, be connected with resistance R 5 between the output terminal of comparer U1 and the power supply, be connected with capacitor C 2 between the pin 3 of comparer U1 and the pin 5, the output terminal of comparer U1 is connected with the pin 2 of photoelectrical coupler U2 through resistance R 6.The pin 3 ground connection GND1 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U2 is connected with 5V power supply+5V-A, the pin 8 of photoelectrical coupler U2 is by capacitor C 3 ground connection GND1, be connected with resistance R 7 between the pin 6 of power supply+5V-A and photoelectrical coupler U2, the pin 6 of photoelectrical coupler U2 is connected with signal output part A11 ', and signal output part A11 ' is connected with the input end SAIN1 of binaryzation comparer.
Wide voltage signal receive and photoelectric isolation module in A with the second road circuit of/A phase input signal reception and photoelectric isolating circuit be: the output terminal of comparer U1 is connected with the pin 2 of photoelectrical coupler U3 through resistance R 8, the pin 8 of photoelectrical coupler U3 is by capacitor C 4 ground connection GND2, be connected to resistance R 9 between the pin 6 of power supply+5V-B and photoelectrical coupler U3, the pin 3 ground connection GND1 of photoelectrical coupler U3, the pin 8 of photoelectrical coupler U3 meets power supply+5V-B, the pin 6 of photoelectrical coupler U3 is connected with signal output part A21, and signal output part A21 is connected with the input end SAIN2 of binaryzation comparer.
For A receive with/A phase input signal and the above circuit of two-way of photoelectric isolating circuit the same.
It is above-mentioned that to be A with/A phase input signal receive and the above circuit of two-way of photoelectric isolating circuit.Wide voltage signal receive and photoelectric isolation module in B with/B, Z and/reception of Z phase input signal and photoelectric isolating circuit and A and/reception of A phase input signal and photoelectric isolating circuit are identical.
The resistance of described resistance R 1 is that the resistance of 24K Ω～36K Ω, resistance R 2 is that the resistance of 91K Ω～110K Ω, resistance R 3 is that the resistance of 6.2K Ω～7.2K Ω, resistance R 4 is 0.91K Ω～1.5K Ω.
The clk end of described frequency divider is connected with binaryzation comparator input terminal CLKIN, wide voltage signal receives and photoelectric isolation module output signal end A11, B11 are connected with SZIN1 with input end SAIN1, the SBIN1 of binaryzation comparer with Z11, and the output terminal SOUT1～SOUT3 of binaryzation comparer is connected with the input end D1～D3 of algorithm computation device; Output terminal DOUT1～the DOUT6 of algorithm computation device is connected with input end A11, A12, B11, B12, Z11, the Z12 of wide voltage power output driver module respectively.
Signal input part A11 in the described wide voltage power output driver module is connected respectively with pin 6 with the pin 1 of driver U5 with A12, the pin 2 of driver U5, pin 7 is connected with 5V power supply+5V_A with pin 8, the pin 8 of driver U5 is by capacitor C 5 ground connection GND1, the pin 5 of driver U5 is connected with the base stage pin 1 of triode Q1, power supply+V1 is connected with triode Q1 collector pin 3, one end of resistance R 10 is connected with the collector pin 3 of triode Q1, the other end of resistance R 10 is connected with the base stage pin 1 of triode Q1, the emitter pin 2 of triode Q1 is connected with output signal end A1, the emitter pin 2 of triode Q1 is by resistance R 11 ground connection GND1, the pin 3 of driver U5 is connected with the base stage 1 of triode Q2, power supply+V1 is connected with triode Q2 collector pin 3, one end of resistance R 12 is connected with the collector pin 3 of triode Q2, the other end of resistance R 12 is connected with the base stage pin 1 of triode Q2, the emitter pin 2 of triode Q2 is connected with output signal end/A1, the emitter pin 2 of triode Q2 is by resistance R 13 ground connection GND1, and capacitor C 5 is+decoupling capacitor of 5V_A.Signal input part B11 in the wide voltage power output driver module is identical with the circuit of signal input part A11 and A12 with the circuit connecting mode of B12, signal input part Z11 and Z12; The circuit of wide voltage power output driver module is identical with wide voltage power output driver module circuit connecting mode; Circuit more than two-way and the two-way is the same.
Owing to adopt technique scheme, the present invention have voltage range wide (+4VDC～+ 26VDC), isolation effect is good, waveform quality is good, upgrading is convenient, the characteristics of strong interference immunity, also has the characteristics that volume is little, cost of development is low, the construction cycle is short, be applicable to various industrial rugged surroundings simultaneously.
Description of drawings
Fig. 1 is a structural representation block diagram of the present invention;
Fig. 2 is that the wide voltage signal among Fig. 1 receives and the circuit diagram of photoelectric isolation module 1;
Fig. 3 is the circuit diagram of the wide voltage power output driver module 5 among Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
A kind of wide-voltage range signal shunt based on FPGA, as shown in Figure 1, with frequency divider 2, binaryzation comparer 3 and the programming of algorithm computation device 4 usefulness Hardware Description Language VHDL and be integrated among a slice FPGA 7, the output terminal of the frequency divider 2 among the FPGA7 is connected with the input end of binaryzation comparer 3, the output terminal of binaryzation comparer 3 is connected with the input end of algorithm computation device 4; Wide voltage signal receives and the end and+5 of photoelectric isolation module 1～+ signal input part of 24VDC is connected, and the other end of wide voltage signal reception and photoelectric isolation module 1 is connected respectively with 3 same FPGA7.
A slice FPGA7 wherein, wide voltage signal receive and photoelectric isolation module 1 and FPGA7 in the input end of binaryzation comparer 3 be connected, the output terminal of the algorithm computation device 4 among the FPGA7 is connected with the input end of wide voltage power output driver module 5, and the output terminal of wide voltage power output driver module 5 is connected with terminal device 6.
For concrete and clear for the purpose of, the same FPGA7 of the 2nd FPGA11 among Fig. 1, wide voltage signal receive and photoelectric isolation module 1 and FPGA11 in the input end of binaryzation comparer 12 be connected, the output terminal of binaryzation comparer 12 is connected with algorithm computation device 10 input ends, the output terminal of algorithm computation device 10 is connected with the input end of wide voltage power output driver module 9, and the output terminal of wide voltage power output driver module 9 is connected with terminal device 8.
Described wide voltage signal receive and photoelectric isolation module 1 in the first via circuit of A and/A phase input signal reception and photoelectric isolating circuit shown in the module among Fig. 2 14: the A phase input signal is connected with the pin 2 of comparer U1 through resistance R 1, resistance R 3 dividing potential drops, power supply is connected with the pin 3 of comparer U1 through resistance R 2, resistance R 4 dividing potential drops, and/A is connected with GND1.Be connected with resistance R 5 between the output terminal of comparer U1 and the power supply, be connected with capacitor C 2 between the pin 3 of comparer U1 and the pin 5, the output terminal of comparer U1 is connected with the pin 2 of photoelectrical coupler U2 through resistance R 6.The pin 3 ground connection GND1 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U2 is connected with 5V power supply+5V-A, the pin 8 of photoelectrical coupler U2 is by capacitor C 3 ground connection GND1, be connected with resistance R 7 between the pin 6 of power supply+5V-A and photoelectrical coupler U2, the pin 6 of photoelectrical coupler U2 is connected with signal output part A11, and signal output part A11 is connected with the input end SAIN1 of binaryzation comparer 3.
Wide voltage signal receive and photoelectric isolation module 1 in A with the second road circuit of/A phase input signal reception and photoelectric isolating circuit be: the output terminal of comparer U1 is connected with the pin 2 of photoelectrical coupler U3 through resistance R 8, the pin 8 of photoelectrical coupler U3 is by capacitor C 4 ground connection GND2, be connected to resistance R 9 between the pin 6 of power supply+5V-B and photoelectrical coupler U3, the pin 3 ground connection GND1 of photoelectrical coupler U3, the pin 8 of photoelectrical coupler U3 meets power supply+5V-B, the pin 6 of photoelectrical coupler U3 is connected with signal output part A21, and signal output part A21 is connected with the input end SAIN2 of binaryzation comparer 12.
For A receives with/A phase input signal and the two-way of photoelectric isolating circuit is above circuit with the second the tunnel.
It is above-mentioned that to be A with/A phase input signal receive and the above circuit of two-way of photoelectric isolating circuit.Wide voltage signal receive and photoelectric isolation module 1 in B with/B15, Z receive with/Z16 phase input signal and photoelectric isolating circuit as with A and/reception of A phase input signal and photoelectric isolating circuit are identical.
The resistance of above-mentioned resistance R 1 is that the resistance of 30K Ω, resistance R 2 is that the resistance of 100K Ω, resistance R 3 is that the resistance of 6.8K Ω, resistance R 4 is 1K Ω.
The clk end of described frequency divider 2 is connected with binaryzation comparer 3 input end CLKIN, wide voltage signal receives and photoelectric isolation module 1 output signal end A11, B11 are connected with SZIN1 with input end SAIN1, the SBIN1 of binaryzation comparer 3 with Z11, and the output terminal SOUT1～SOUT3 of binaryzation comparer 3 is connected with the input end D1～D3 of algorithm computation device 4; Output terminal DOUT1～the DOUT6 of algorithm computation device 4 is connected with input end A11, A12, B11, B12, Z11, the Z12 of wide voltage power output driver module 5 respectively.
As shown in Figure 3, A phase signals output circuit 17 in the wide voltage power output driver module 5 is: signal input part A11 is connected respectively with pin 6 with the pin 1 of driver U5 with A12, the pin 2 of driver U5, pin 7 is connected with 5V power supply+5V_A with pin 8, the pin 8 of driver U5 is by capacitor C 5 ground connection GND1, the pin 5 of driver U5 is connected with the base stage pin 1 of triode Q1, power supply+V1 is connected with triode Q1 collector pin 3, one end of resistance R 10 is connected with the collector pin 3 of triode Q1, the other end of resistance R 10 is connected with the base stage pin 1 of triode Q1, the emitter pin 2 of triode Q1 is connected with output signal end A1, the emitter pin 2 of triode Q1 is by resistance R 11 ground connection GND1, the pin 3 of driver U5 is connected with the base stage 1 of triode Q2, power supply+V1 is connected with triode Q2 collector pin 3, one end of resistance R 12 is connected with the collector pin 3 of triode Q2, the other end of resistance R 12 is connected with the base stage pin 1 of triode Q2, the emitter pin 2 of triode Q2 is connected with output signal end/A1, the emitter pin 2 of triode Q2 is by resistance R 13 ground connection GND1, and capacitor C 5 is+decoupling capacitor of 5V_A.
B phase output circuit 18 in the wide voltage power output driver module 5 is identical with A phase output circuit 17; Z phase output circuit 19 in the wide voltage power output driver module 5 is identical with A phase output circuit 17.The circuit of wide voltage power output driver module 9 is identical with the circuit of wide voltage power output driver module 5.
The circuit of the circuit 20,21,22 in the second tunnel the wide voltage power output driver module 9 is identical with circuit 17 with the circuit that wide voltage power is exported in the driver module 5.
The Third Road circuit is the same.
Present embodiment have voltage range wide (+4VDC～+ 26VDC), isolation effect is good, waveform quality is good, upgrading is convenient, the characteristics of strong interference immunity, also has the characteristics that volume is little, cost of development is low, the construction cycle is short, be applicable to various industrial rugged surroundings simultaneously.
Claims (3)
1, a kind of wide-voltage range signal shunt based on FPGA, with Hardware Description Language VHDL programming and be integrated among a slice FPGA (7), the output terminal of the frequency divider (2) among the FPGA (7) is connected with the input end of binaryzation comparer (3), the output terminal of binaryzation comparer (3) is connected with the input end of algorithm computation device (4) with frequency divider (2), binaryzation comparer (3) and algorithm computation device (4); Wide voltage signal receives and the end and+5 of photoelectric isolation module (1)～+ signal input part of 24VDC is connected, wide voltage signal receives and the other end of photoelectric isolation module (1) is connected respectively with 2 same FPGA (7), it is characterized in that: a slice FPGA (7) wherein, wide voltage signal receive and photoelectric isolation module (1) and FPGA (7) in the input end of binaryzation comparer (3) be connected, the output terminal of the algorithm computation device (4) among the FPGA (7) is connected with the input end of wide voltage power output driver module (5), and the output terminal of wide voltage power output driver module (5) is connected with terminal device (6);
Described wide voltage signal receive and photoelectric isolation module (1) in A with/the A phase input signal receives and the first via circuit of photoelectric isolating circuit is: the A phase input signal is through resistance R 1, resistance R 3 dividing potential drops are connected with the pin 2 of comparer U1, power supply is through resistance R 2, resistance R 4 dividing potential drops are connected with the pin 3 of comparer U1, / A ground connection GND1, be connected with resistance R 5 between the output terminal of comparer U1 and the power supply, be connected with capacitor C 2 between the pin 3 of comparer U1 and the pin 5, the output terminal of comparer U1 is connected with the pin 2 of photoelectrical coupler U2 through resistance R 6, the pin 3 ground connection GND1 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U2 is connected with 5V power supply+5V-A, the pin 8 of photoelectrical coupler U2 is by capacitor C 3 ground connection GND1, be connected with resistance R 7 between the pin 6 of power supply+5V-A and photoelectrical coupler U2, the pin 6 of photoelectrical coupler U2 is connected with signal output part A11 ', and the input end SAIN1 of the binaryzation comparer (3) on signal output part A11 ' and first FPGA is connected;
Wide voltage signal receive and photoelectric isolation module (1) in A with the second road circuit of/A phase input signal reception and photoelectric isolating circuit be: the output terminal of comparer U1 is connected with the pin 2 of photoelectrical coupler U3 through resistance R 8, the pin 8 of photoelectrical coupler U3 is by capacitor C 4 ground connection GND2, be connected to resistance R 9 between the pin 6 of power supply+5V-B and photoelectrical coupler U3, the pin 3 ground connection GND1 of photoelectrical coupler U3, the pin 8 of photoelectrical coupler U3 meets power supply+5V-B, the pin 6 of photoelectrical coupler U3 is connected with signal output part A21, and the input end SAIN2 of the binaryzation comparer (12) on signal output part A21 and second FPGA is connected;
Wide voltage signal receive and photoelectric isolation module (1) in B with/B, Z with/the Z phase input signal receives and photoelectric isolating circuit receives with wide voltage signal respectively and photoelectric isolation module (1) in A and/reception of A phase input signal and photoelectric isolating circuit are identical.
2, the wide-voltage range signal shunt based on FPGA according to claim 1, the resistance that it is characterized in that described resistance R 1 are that the resistance of 24K Ω～36K Ω, resistance R 2 is that the resistance of 91K Ω～110K Ω, resistance R 3 is that the resistance of 6.2K Ω～7.2K Ω, resistance R 4 is 0.91K Ω～1.5K Ω.
3, wide-voltage range signal shunt based on FPGA according to claim 1, it is characterized in that the signal input part A11 in the described wide voltage power output driver module (5) is connected respectively with pin 6 with the pin 1 of driver U5 with A12, the pin 2 of driver U5, pin 7 is connected with 5V power supply+5V-A with pin 8, the pin 8 of driver U5 is by capacitor C 5 ground connection GND1, the pin 5 of driver U5 is connected with the base stage pin 1 of triode Q1, power supply+V1 is connected with triode Q1 collector pin 3, one end of resistance R 10 is connected with the collector pin 3 of triode Q1, the other end of resistance R 10 is connected with the base stage pin 1 of triode Q1, the emitter pin 2 of triode Q1 is connected with output signal end A1, the emitter pin 2 of triode Q1 is by resistance R 11 ground connection GND1, the pin 3 of driver U5 is connected with the base stage 1 of triode Q2, power supply+V1 is connected with triode Q2 collector pin 3, one end of resistance R 12 is connected with the collector pin 3 of triode Q2, the other end of resistance R 12 is connected with the base stage pin 1 of triode Q2, the emitter pin 2 of triode Q2 is connected with output signal end/A1, the emitter pin 2 of triode Q2 is by resistance R 13 ground connection GND1, and capacitor C 5 is+decoupling capacitor of 5V-A;
The circuit connecting mode with signal input part A11 and A12 is identical respectively for signal input part B11 in the wide voltage power output driver module (5) and the circuit connecting mode of B12, signal input part Z11 and Z12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100197513A CN100451553C (en) | 2006-07-28 | 2006-07-28 | Wide-voltage range signal shunt based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100197513A CN100451553C (en) | 2006-07-28 | 2006-07-28 | Wide-voltage range signal shunt based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1888826A CN1888826A (en) | 2007-01-03 |
| CN100451553C true CN100451553C (en) | 2009-01-14 |
Family
ID=37578115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100197513A Expired - Fee Related CN100451553C (en) | 2006-07-28 | 2006-07-28 | Wide-voltage range signal shunt based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100451553C (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1420632A (en) * | 2002-04-17 | 2003-05-28 | 湘潭师范学院 | Virtual signal generator for generating square wave by remainder interpolation comparision |
| CN1746620A (en) * | 2005-10-08 | 2006-03-15 | 武汉科技大学 | Large industrial hock and crane positioning measuring apparatus based on FPGA |
| US7080344B2 (en) * | 2003-06-25 | 2006-07-18 | International Business Machines Corporation | Coding of FPGA and standard cell logic in a tiling structure |
| CN1809040A (en) * | 2006-01-26 | 2006-07-26 | 东南大学 | Programmable device based estimation and balancing apparatus and method for OFDM channels |
-
2006
- 2006-07-28 CN CNB2006100197513A patent/CN100451553C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1420632A (en) * | 2002-04-17 | 2003-05-28 | 湘潭师范学院 | Virtual signal generator for generating square wave by remainder interpolation comparision |
| US7080344B2 (en) * | 2003-06-25 | 2006-07-18 | International Business Machines Corporation | Coding of FPGA and standard cell logic in a tiling structure |
| CN1746620A (en) * | 2005-10-08 | 2006-03-15 | 武汉科技大学 | Large industrial hock and crane positioning measuring apparatus based on FPGA |
| CN1809040A (en) * | 2006-01-26 | 2006-07-26 | 东南大学 | Programmable device based estimation and balancing apparatus and method for OFDM channels |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1888826A (en) | 2007-01-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207352398U (en) | General digital input and output multiplex circuit and input-output control unit | |
| CN101835250A (en) | Device and method for reducing power consumption of terminal | |
| CN101819261B (en) | Three-phase source phase failure and power failure detection circuit | |
| CN2854922Y (en) | Single-phase variable frequency constant-current source | |
| US20140321003A1 (en) | Power supply circuit | |
| CN100451553C (en) | Wide-voltage range signal shunt based on FPGA | |
| CN108205857A (en) | A kind of electrical communication system | |
| CN102539912B (en) | Mains frequency detection method for load monitor | |
| CN103634723A (en) | Audio input circuit and electronic device with audio input | |
| CN200947041Y (en) | FPGA-based signal separation unit of encoder | |
| CN208060027U (en) | A kind of temperature sampling circuit and controller | |
| CN103178483B (en) | A kind of radio-frequency signal source and reverse protection method with reverse protection function | |
| US20140320106A1 (en) | Power supply circuit | |
| CN206339596U (en) | Three-phase multifunctional electric instrument | |
| CN103245904B (en) | A kind of method for test function circuit and device | |
| CN208353322U (en) | A kind of thick film circuit of broadband signal synthesizer | |
| CN207993480U (en) | A kind of DSP tuning systems | |
| US8810313B2 (en) | Multi-band power amplifier | |
| CN100438288C (en) | Method for raizing drive circuit reliability and large power drive circuit | |
| CN205864745U (en) | Asynchronous pair of cave automobile audio Auto-Test System | |
| CN201194412Y (en) | Electric power switching device and signal processing apparatus | |
| US8248148B2 (en) | Power supply switch apparatus | |
| CN211263652U (en) | Line load and fault detection system based on STM32 singlechip | |
| CN204595088U (en) | A kind of device detecting radio-frequency power | |
| CN210742385U (en) | Crystal oscillator frequency measuring system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090114 |