CN200947041Y - FPGA-based signal separation unit of encoder - Google Patents
FPGA-based signal separation unit of encoder Download PDFInfo
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- CN200947041Y CN200947041Y CN 200620098115 CN200620098115U CN200947041Y CN 200947041 Y CN200947041 Y CN 200947041Y CN 200620098115 CN200620098115 CN 200620098115 CN 200620098115 U CN200620098115 U CN 200620098115U CN 200947041 Y CN200947041 Y CN 200947041Y
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Abstract
The utility model relates to a coder signal separating device based on FPGA. Technological proposal of the utility model is that a frequency divider [2], a binaryzation comparator [3] and an arithmetic calculator [4] are programmed and integrated into a FPGA 1[7] through hardware descriptor language VIIDL. Output end of the frequency divider [2] of the FPGA 1[7] is connected with input end of the binaryzation comparator [3], and output end of the binaryzation comparator [3] is connected with input end of the arithmetic calculator [4]. One end of wide voltage signal receiving and photoelectric division module [1] is connected with signal input end of +5 to +24 VDC, and the other end of the wide voltage signal receiving and photoelectric division module [1] is connected with two or more similar FPGA [7]. The utility model has such advantages of wide voltage scope (from +5 VDC to +24 VDC), good separating effect, good waveform quality, easy upgrade, strong anti-jamming property, small cubage, low development cost, short development period and strong adaptability to all severely industrial conditions.
Description
Technical field
The utility model belongs to the code device signal tripping device.Relate in particular to a kind of code device signal tripping device based on FPGA.
Background technology
Scrambler is widely used in the collection of industrial motor parameter.Modern industry often requires the signal of scrambler collection is delivered to more than equipment such as frequency converter, terminal monitor etc.It is often infeasible that an above scrambler is installed on same motor, therefore separates and duplicate for the signal of scrambler collection to seem particularly important.The OPT029-501 of BALDOR company is a kind of code device signal tripping device, but this product has open defect: at first, the signal that this product does not separate needs carries out photoelectricity isolates, and has caused its range of application narrow; Secondly, the input and output voltage of this product all is the 5VDC fixed value, can not adjust in certain voltage range, therefore can not satisfy the requirement of some receiving equipments to input voltage; At last, this product can not be proofreaied and correct and shaping the signal of scrambler collection according to on-site actual situations.
Summary of the invention
The purpose of this utility model provides a kind ofly to be had the input of wide voltage signal, isolates the molded breadth voltage power and drive output, can carry out signal waveform and proofread and correct that shaping, upgrading are convenient, the code device signal tripping device based on FPGA of strong interference immunity.
For achieving the above object, the technical scheme that the utility model adopted is: with Hardware Description Language VHDL programming and be integrated among a slice FPGA, the output terminal of the frequency divider among the FPGA is connected with the input end of binaryzation comparer, the output terminal of binaryzation comparer is connected with the input end of algorithm computation device with frequency divider, binaryzation comparer and algorithm computation device; Wide voltage signal receives and an end of photoelectric isolation module is connected with the input signal end of (+5～+ 24) VDC, and the other end of wide voltage signal reception and photoelectric isolation module is connected with FPGA same more than 2 or 2 respectively.
Wherein, wide voltage signal receives and photoelectric isolation module is connected with the input end of binaryzation comparer among the FPGA respectively, the output terminal of the algorithm computation device among the FPGA is connected with the input end of wide voltage power output driver module, and the output terminal of wide voltage power output driver module is connected with terminal device.
Described wide voltage signal receive and photoelectric isolation module in A with the first via circuit of/A phase input signal reception and photoelectric isolating circuit be: A phase input signal end is connected with the collector pin 3 of triode Q1, the two ends of resistance R 1 are connected with base stage pin 1 with the collector pin 3 of triode Q1 respectively, the two ends of resistance R 2 are connected with the emitter pin 2 of triode Q1 and the pin 2 of photoelectrical coupler U1 respectively, the negative pole of stabilivolt D2 is connected with the base stage pin 1 of triode Q1, and the positive pole of stabilivolt D2 is connected with the pin 3 of photoelectrical coupler U1; The negative pole of diode D1 is connected with/A phase input signal end, the positive pole of diode D1 is connected with the pin 3 of photoelectrical coupler U1, the pin 2 of photoelectrical coupler U1, pin 3 are connected respectively with pin 2, the pin 3 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U1 is connected with 5V power supply+5V_A, power supply+5V_A is connected with the pin 6 of photoelectrical coupler U1 by resistance R 3 by the pin 8 of capacitor C 1 ground connection GND1, photoelectrical coupler U1, the pin 6 of photoelectrical coupler U1 is connected with output signal end A11, and signal output part A11 is connected with the input end SAIN1 of binaryzation comparer.
Wide voltage signal receive and photoelectric isolation module in A with the second road circuit of/A phase input signal reception and photoelectric isolating circuit be: the pin 2 of photoelectrical coupler U1, pin 3 are connected respectively with pin 2, the pin 3 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U2 is connected with 5V power supply+5V_B, power supply+5V_B is connected with the pin 6 of photoelectrical coupler U2 by resistance R 4 by the pin 8 of capacitor C 2 ground connection GND2, photoelectrical coupler U2, the pin 6 of photoelectrical coupler U2 is connected with output signal end A21, and signal output part A21 is connected with the input end SAIN2 of binaryzation comparer; The same for the circuit that A receives with/A phase input signal and the two-way of photoelectric isolating circuit is above; Wide voltage signal receive and photoelectric isolation module in B with/B, Z and/Z phase input signal reception and photoelectric isolating circuit and above-mentioned A and/reception of A phase input signal and photoelectric isolating circuit are identical.
The clk end of the frequency divider among the described FPGA is connected with binaryzation comparator input terminal CLKIN, and the output terminal SOUT1～SOUT3 of binaryzation comparer is connected with the input end D1～D3 of algorithm computation device; Wide voltage signal receives and photoelectric isolation module output signal end A11, B11 are connected with SZIN1 with binaryzation comparator input terminal SAIN1, SBIN1 with Z11, and the output terminal DOUT1～DOUT6 of algorithm computation device is connected with input end A11, A12, B11, B12, Z11, the Z12 of wide voltage power output driver module respectively.
A in the described wide voltage power output driver module with the first via circuit of/A phase input signal reception and photoelectric isolating circuit is: signal input part A11 is connected respectively with pin 6 with the pin 1 of driver U4 with A12, the pin 2 of driver U4, pin 7 is connected with 5V power supply+5V_A with pin 8, the pin 8 of driver U4 is by capacitor C 21 ground connection GND1, the pin 5 of driver U4 is connected with the base stage pin 1 of triode Q2, power supply+V1 is connected with triode Q2 collector pin 3, one end of resistance R 5 is connected with the collector pin 3 of triode Q2, the other end of resistance R 5 is connected with the base stage pin 1 of triode Q2, the emitter pin 2 of triode Q2 is connected with output signal end A1, the emitter pin 2 of triode Q2 is by resistance R 6 ground connection GND1, the pin 3 of driver U4 is connected with the base stage 1 of triode Q3, power supply+V1 is connected with triode Q3 collector pin 3, one end of resistance R 7 is connected with the collector pin 3 of triode Q3, the other end of resistance R 7 is connected with the base stage pin 1 of triode Q3, the emitter pin 2 of triode Q3 is connected with output signal end/A1, the emitter pin 2 of triode Q3 is by resistance R 8 ground connection GND1, and capacitor C 3 is+decoupling capacitor of 5V_A;
Signal input part B11 in the wide voltage power output driver module is identical with the circuit of input signal end A11 and A12 with the circuit of B12, signal input part Z11 and Z12; The circuit of wide voltage power output driver module is identical with wide voltage power output driver module electricity; Circuit more than two-way and the two-way is the same.
Owing to adopt technique scheme, the utlity model has voltage range wide (+5～+ 24) VDC, isolation effect is good, waveform quality is good, upgrading is convenient, the characteristics of strong interference immunity; Also have the characteristics that volume is little, cost of development is low, the construction cycle is short, be applicable to various industrial rugged surroundings simultaneously.
Description of drawings
Fig. 1 is a structural representation block diagram of the present utility model;
Fig. 2 is that the wide voltage signal among Fig. 1 receives and the circuit diagram of photoelectric isolation module [1];
Fig. 3 is the circuit diagram of the wide voltage power output driver module [5] among Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
A kind of code device signal tripping device based on FPGA, as shown in Figure 1, with frequency divider [2], binaryzation comparer [3] and algorithm computation device [4] with Hardware Description Language VHDL programming and be integrated into a slice FPGA[7] in, FPGA[7] in the output terminal of frequency divider [2] be connected with the input end of binaryzation comparer [3], the output terminal of binaryzation comparer [3] is connected with the input end of algorithm computation device [4]; Wide voltage signal receives and an end of photoelectric isolation module [1] is connected with the input signal end of (+5～+ 24) VDC, the other end of wide voltage signal reception and photoelectric isolation module [1] respectively with FPGA[7 same more than 2 or 2] be connected.
Wherein, wide voltage signal receive and photoelectric isolation module [1] respectively with FPGA[7] in the input end of binaryzation comparer [3] be connected, FPGA[7] in the output terminal of algorithm computation device [4] is connected with the input end of wide voltage power output driver module [5], the output terminal that wide voltage power is exported driver module [5] is connected with terminal device [6].
For concrete and clear for the purpose of, the 2nd FPGA[11 among Fig. 1] same FPGA[7], wide voltage signal receives and photoelectric isolation module [1] and FPGA[11] in the input end of binaryzation comparer [12] be connected, the output terminal of binaryzation comparer [12] is connected with algorithm computation device [10] input end, the output terminal of algorithm computation device [10] is connected with the input end of wide voltage power output driver module [9], and the output terminal of wide voltage power output driver module [9] is connected with terminal device [8].
Described wide voltage signal receive and photoelectric isolation module [1] in the first via circuit of A and/A phase input signal reception and photoelectric isolating circuit shown in the module among Fig. 2 [14]: A phase input signal end is connected with the collector pin 3 of triode Q1, the two ends of resistance R 1 are connected with base stage pin 1 with the collector pin 3 of triode Q1 respectively, the two ends of resistance R 2 are connected with the emitter pin 2 of triode Q1 and the pin 2 of photoelectrical coupler U1 respectively, the negative pole of stabilivolt D2 is connected with the base stage pin 1 of triode Q1, and the positive pole of stabilivolt D2 is connected with the pin 3 of photoelectrical coupler U1; The negative pole of diode D1 is connected with/A phase input signal end, the positive pole of diode D1 is connected with the pin 3 of photoelectrical coupler U1, the pin 2 of photoelectrical coupler U1, pin 3 are connected respectively with pin 2, the pin 3 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U1 is connected with 5V power supply+5V_A, power supply+5V_A is connected with the pin 6 of photoelectrical coupler U1 by resistance R 3 by the pin 8 of capacitor C 1 ground connection GND1, photoelectrical coupler U1, the pin 6 of photoelectrical coupler U1 is connected with output signal end A11, and signal output part A11 is connected with the input end SAIN1 of comparer [3].
Wide voltage signal receive and photoelectric isolation module [1] in A with the second road circuit of/A phase input signal reception and photoelectric isolating circuit be: the pin 2 of photoelectrical coupler U1, pin 3 are connected respectively with pin 2, the pin 3 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U2 is connected with 5V power supply+5V_B, power supply+5V_B is connected with the pin 6 of photoelectrical coupler U2 by resistance R 4 by the pin 8 of capacitor C 2 ground connection GND2, photoelectrical coupler U2, the pin 6 of photoelectrical coupler U2 is connected with output signal end A21, and signal output part A21 is connected with the input end SAIN2 of comparer [12].
The same for the circuit that A receives with/A phase input signal and the two-way of photoelectric isolating circuit is above;
Wide voltage signal receive and photoelectric isolation module [1] in B and/B[15], Z and/Z[16] phase input signal reception and photoelectric isolating circuit and above-mentioned A and/reception of A phase input signal and photoelectric isolating circuit are identical.
As shown in Figure 1, FPGA[7] in the clk end of frequency divider [2] be connected with binaryzation comparer [3] input end CLKIN, the output terminal SOUT1～SOUT3 of binaryzation comparer [3] is connected with the input end D1～D3 of algorithm computation device [4]; Wide voltage signal receives and photoelectric isolation module [1] output signal end A11, B11 are connected with SZIN1 with binaryzation comparer [3] input end SAIN1, SBIN1 with Z11, and the output terminal DOUT1～DOUT6 of algorithm computation device [4] is connected with input end A11, A12, B11, B12, Z11, the Z12 of wide voltage power output driver module [5] respectively.
As shown in Figure 3, A phase signals output circuit [17] in the wide voltage power output driver module [5] is: the A in the wide voltage power output driver module [5] with the first via circuit of/A phase input signal reception and photoelectric isolating circuit is: signal input part A11 is connected respectively with pin 6 with the pin 1 of driver U4 with A12, the pin 2 of driver U4, pin 7 is connected with 5V power supply+5V_A with pin 8, the pin 8 of driver U4 is by capacitor C 21 ground connection GND1, the pin 5 of driver U4 is connected with the base stage pin 1 of triode Q2, power supply+V1 is connected with triode Q2 collector pin 3, one end of resistance R 5 is connected with the collector pin 3 of triode Q2, the other end of resistance R 5 is connected with the base stage pin 1 of triode Q2, the emitter pin 2 of triode Q2 is connected with output signal end A1, the emitter pin 2 of triode Q2 is by resistance R 6 ground connection GND1, the pin 3 of driver U4 is connected with the base stage 1 of triode Q3, power supply+V1 is connected with triode Q3 collector pin 3, one end of resistance R 7 is connected with the collector pin 3 of triode Q3, the other end of resistance R 7 is connected with the base stage pin 1 of triode Q3, the emitter pin 2 of triode Q3 is connected with output signal end/A1, the emitter pin 2 of triode Q3 is by resistance R 8 ground connection GND1, and capacitor C 3 is the decoupling capacitor of power supply+5V_A.
B phase output circuit [18] in the wide voltage power output driver module [5] is identical with A phase output circuit [17]; Z phase output circuit [19] in the wide voltage power output driver module [5] is identical with A phase output circuit [17].The circuit of wide voltage power output driver module [9] is identical with the circuit of wide voltage power output driver module [5].
The circuit of the circuit [20] in the second tunnel the wide voltage power output driver module [9], [21], [22] is identical with circuit [17] with the circuit that wide voltage power is exported in the driver module [5].
The Third Road circuit is the same.
Present embodiment have voltage range wide (+5～+ 24VDC), isolation effect is good, waveform quality is good, upgrading is convenient, the characteristics of strong interference immunity, also has the characteristics that volume is little, cost of development is low, the construction cycle is short, be applicable to various industrial rugged surroundings simultaneously.
Claims (4)
1, a kind of code device signal tripping device based on FPGA, it is characterized in that with frequency divider [2], binaryzation comparer [3] and algorithm computation device [4] with Hardware Description Language VHDL programming and be integrated into a slice FPGA[7] in, FPGA[7] in the output terminal of frequency divider [2] be connected with the input end of binaryzation comparer [3], the output terminal of binaryzation comparer [3] is connected with the input end of algorithm computation device [4]; Wide voltage signal receives and an end of photoelectric isolation module [1] is connected with the input signal end of (+5～+ 24) VDC, the other end of wide voltage signal reception and photoelectric isolation module [1] respectively with FPGA[7 same more than 2 or 2] be connected;
Wherein, wide voltage signal receive and photoelectric isolation module [1] respectively with FPGA[7] in the input end of binaryzation comparer [3] be connected, FPGA[7] in the output terminal of algorithm computation device [4] is connected with the input end of wide voltage power output driver module [5], the output terminal that wide voltage power is exported driver module [5] is connected with terminal device [6].
2, code device signal tripping device based on FPGA according to claim 1, it is characterized in that described wide voltage signal receives and photoelectric isolation module [1] in A with/the A phase input signal receives and the first via circuit of photoelectric isolating circuit is, A phase input signal end is connected with the collector pin 3 of triode Q1, the two ends of resistance R 1 are connected with base stage pin 1 with the collector pin 3 of triode Q1 respectively, the two ends of resistance R 2 are connected with the emitter pin 2 of triode Q1 and the pin 2 of photoelectrical coupler U1 respectively, the negative pole of stabilivolt D2 is connected with the base stage pin 1 of triode Q1, and the positive pole of stabilivolt D2 is connected with the pin 3 of photoelectrical coupler U1; The negative pole of diode D1 is connected with/A phase input signal end, the positive pole of diode D1 is connected with the pin 3 of photoelectrical coupler U1, the pin 2 of photoelectrical coupler U1, pin 3 are connected respectively with pin 2, the pin 3 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U1 is connected with 5V power supply+5V_A, power supply+5V_A is connected with the pin 6 of photoelectrical coupler U1 by resistance R 3 by the pin 8 of capacitor C 1 ground connection GND1, photoelectrical coupler U1, the pin 6 of photoelectrical coupler U1 is connected with output signal end A11, and signal output part A11 is connected with the input end SAIN1 of binaryzation comparer [3];
Wide voltage signal receive and photoelectric isolation module [1] in A with the second road circuit of/A phase input signal reception and photoelectric isolating circuit be: the pin 2 of photoelectrical coupler U1, pin 3 are connected respectively with pin 2, the pin 3 of photoelectrical coupler U2, the pin 8 of photoelectrical coupler U2 is connected with 5V power supply+5V_B, power supply+5V_B is connected with the pin 6 of photoelectrical coupler U2 by resistance R 4 by the pin 8 of capacitor C 2 ground connection GND2, photoelectrical coupler U2, the pin 6 of photoelectrical coupler U2 is connected with output signal end A21, and signal output part A21 is connected with the input end SAIN2 of binaryzation comparer [12]; The same for the circuit that A receives with/A phase input signal and the two-way of photoelectric isolating circuit is above;
Wide voltage signal receive and photoelectric isolation module [1] in B with/B, Z and/Z phase input signal reception and photoelectric isolating circuit and above-mentioned A and/reception of A phase input signal and photoelectric isolating circuit are identical.
3, the code device signal tripping device based on FPGA according to claim 1, it is characterized in that described FPGA[7] in the clk end of frequency divider [2] be connected with binaryzation comparer [3] input end CLKIN, the output terminal SOUT1～SOUT3 of binaryzation comparer [3] is connected with the input end D1～D3 of algorithm computation device [4]; Wide voltage signal receives and photoelectric isolation module [1] output signal end A11, B11 are connected with SZIN1 with binaryzation comparator input terminal SAIN1, SBIN1 with Z11, and the output terminal DOUT1～DOUT6 of algorithm computation device [4] is connected with input end A11, A12, B11, B12, Z11, the Z12 of wide voltage power output driver module [5] respectively.
4, code device signal tripping device based on FPGA according to claim 1, it is characterized in that the A in the described wide voltage power output driver module [5] with the first via circuit of/A phase input signal reception and photoelectric isolating circuit is: signal input part A11 is connected respectively with pin 6 with the pin 1 of driver U4 with A12, the pin 2 of driver U4, pin 7 is connected with 5V power supply+5V_A with pin 8, the pin 8 of driver U4 is by capacitor C 21 ground connection GND1, the pin 5 of driver U4 is connected with the base stage pin 1 of triode Q2, power supply+V1 is connected with triode Q2 collector pin 3, one end of resistance R 5 is connected with the collector pin 3 of triode Q2, the other end of resistance R 5 is connected with the base stage pin 1 of triode Q2, the emitter pin 2 of triode Q2 is connected with output signal end A1, the emitter pin 2 of triode Q2 is by resistance R 6 ground connection GND1, the pin 3 of driver U4 is connected with the base stage 1 of triode Q3, power supply+V1 is connected with triode Q3 collector pin 3, one end of resistance R 7 is connected with the collector pin 3 of triode Q3, the other end of resistance R 7 is connected with the base stage pin 1 of triode Q3, the emitter pin 2 of triode Q3 is connected with output signal end/A1, the emitter pin 2 of triode Q3 is by resistance R 8 ground connection GND1, and capacitor C 3 is+decoupling capacitor of 5V_A;
Signal input part B11 in the wide voltage power output driver module [5] is identical with the circuit of input signal end A11 and A12 with the circuit of B12, signal input part Z11 and Z12; The circuit of wide voltage power output driver module [9] is identical with wide voltage power output driver module [5] electricity; Circuit more than two-way and the two-way is the same.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200620098115 CN200947041Y (en) | 2006-07-28 | 2006-07-28 | FPGA-based signal separation unit of encoder |
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| CN 200620098115 CN200947041Y (en) | 2006-07-28 | 2006-07-28 | FPGA-based signal separation unit of encoder |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237836A (en) * | 2010-04-26 | 2011-11-09 | 东元电机股份有限公司 | Servo driver and control method thereof |
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2006
- 2006-07-28 CN CN 200620098115 patent/CN200947041Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237836A (en) * | 2010-04-26 | 2011-11-09 | 东元电机股份有限公司 | Servo driver and control method thereof |
| CN102237836B (en) * | 2010-04-26 | 2013-09-04 | 东元电机股份有限公司 | Servo driver and control method thereof |
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