US20060163701A1 - Scribe-line structures and methods of forming the same - Google Patents
Scribe-line structures and methods of forming the same Download PDFInfo
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- US20060163701A1 US20060163701A1 US11/335,359 US33535906A US2006163701A1 US 20060163701 A1 US20060163701 A1 US 20060163701A1 US 33535906 A US33535906 A US 33535906A US 2006163701 A1 US2006163701 A1 US 2006163701A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
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- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/4363—Adapting the video or multiplex stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F1/16—Constructional details or arrangements
- G06F1/1613—Constructional details or arrangements for portable computers
- G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
- G06F1/1656—Details related to functional adaptations of the enclosure, e.g. to provide protection against EMI, shock, water, or to host detachable peripherals like a mouse or removable expansions units like PCMCIA cards, or to provide access to internal components for maintenance or to removable storage supports like CDs or DVDs, or to mechanically mount accessories
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- H—ELECTRICITY
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- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
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Definitions
- the present invention relates to structures formed on a semiconductor substrate and to methods of forming the same, and more particularly, to scribe-line structures formed on a semiconductor substrate, to substrates having such scribe-line structures, and to methods of forming the same.
- multiple semiconductor devices are formed respectively on predetermined regions of a semiconductor substrate.
- Each of these regions may be defined by a set of intersecting scribe-lines, for example by horizontal and vertical scribe-lines.
- Each such scribe-line has a predetermined width, so that the semiconductor substrate can be easily cut along the scribe-lines so as to separate the individual semiconductor devices from each other and from any unused portions of the semiconductor substrate.
- the semiconductor devices and the scribe-lines are typically covered with a plurality of interlayer insulating layers.
- the interlayer insulating layers protect the semiconductor devices from exterior environment influences while cutting the semiconductor substrate.
- U.S. Pat. No. 6,441,465 to Chi-Fa Lin discloses a scribe line structure for preventing the type of damages as described above that may be induced during fabrication processes.
- the scribe-line structure intentionally includes cavities disposed in a multi-layer structure along a scribe-line. The cavities are disposed on each side of a scribe-line and then disposed in at least two rows.
- the '465 patent teaches that such cavities reduce and relieve internal stress of the scribe lines, which may be created during formation of the scribe-line and thus reduce the tendency for crack formation, peeling, delamination and dielectric fracture of the scribe lines during cutting of the substrate.
- the scribe-line structure taught by the '465 patent also can cause damage to the semiconductor devices because the cavities act as starting points for a crack during performing a cutting process along a scribe-line. Besides, the cavities also act as obstructions while performing the cutting process along the scribe-line, so that the processing time may be made longer than would otherwise be required.
- scribe-line structures on a semiconductor substrate such that during performance of a cutting process on the semiconductor substrate, physical shock and cracking tendencies on the one or more semiconductor devices formed on the substrate can be minimized.
- scribe-line structures such that during performance of a cutting process on a semiconductor substrate having such scribe-line structures thereon, physical shock and cracking tendencies on the semiconductor devices formed on the substrate can be minimized.
- the present invention provides new types of scribe-line structures and methods of forming such scribe-line structures.
- One embodiment of scribe-line structures according to this invention comprises a lower layer disposed on a semiconductor substrate.
- a molding layer having at least one protective contact hole is then disposed on the lower layer.
- a dielectric layer and an upper layer are thereafter disposed in sequence on the molding layer so as to fill the protective contact hole(s).
- On the upper layer protective layer patterns are then disposed so as to be spaced a distance away from each other. The spacing distance between the protective layer patterns should be different in size from a width of the protective contact hole(s).
- the dielectric layer should be formed of a material having a greater mechanical intensity (or strength) than that of the molding layer.
- Another embodiment of scribe-line structures comprises a lower layer disposed on a semiconductor substrate.
- a pad layer and a molding layer having at least one protective contact hole are then disposed on the lower layer in sequence.
- a dielectric layer and an upper layer are thereafter disposed in sequence on the molding layer so as to fill the protective contact hole(s).
- On the upper layer protective layer patterns are then disposed so as to be spaced a distance away from each other. The spacing distance between the protective layer patterns should be different in size from a width of the protective contact hole(s).
- the dielectric layer and the pad layer should be formed of a material or of materials having a greater mechanical intensity (or strength) than that of the molding layer.
- Still another embodiment of scribe-line structures comprises a lower layer and a pad layer disposed in order on a semiconductor substrate.
- a molding layer having at least one protective contact hole is then disposed on the pad layer.
- a dielectric layer and an upper layer are thereafter disposed in sequence on the molding layer so as to fill the protective contact hole(s).
- On the upper layer protective layer patterns are then disposed so as to be spaced a distance away from each other. The spacing distance between the protective layer patterns should be different in size from a width of the protective contact hole(s).
- the dielectric layer and the pad layer should be formed of a material or of materials having a greater mechanical intensity (or strength) than that of the molding layer.
- One embodiment of a method of forming scribe-line structures comprises the initial steps of forming a lower layer and a molding layer on a semiconductor substrate in sequence.
- a photoresist layer is then formed on the molding layer.
- the photoresist layer is formed so as to have at least one opening extending down to the molding layer.
- the molding layer is then etched through the opening(s) using the photoresist layer as an etching mask.
- the etching process forms one or more protective hole(s) in the molding layer to expose the lower layer.
- the photoresist layer is thereafter removed from the semiconductor substrate.
- a dielectric layer, an upper layer, and a set of protective layer patterns are then formed in sequence so as to fill the protective hole(s).
- the dielectric layer should be formed using a material having a greater mechanical intensity (strength) than that of the molding layer.
- Another embodiment of a method of forming scribe-line structures comprises the initial steps of forming a lower layer, a pad layer, and a molding layer on a semiconductor substrate in sequence.
- a photoresist layer is then formed on the molding layer.
- the photoresist layer is formed so as to have at least one opening extending down to the molding layer.
- the molding layer and the pad layer are then etched in sequence through the opening(s) using the photoresist layer as an etching mask.
- the etching process forms one or more protective hole(s) in the pad layer and the molding layer to expose the lower layer.
- the photoresist layer is thereafter removed from the semiconductor substrate.
- a dielectric layer, an upper layer, and a set of protective layer patterns are then formed in sequence so as to fill the protective hole(s).
- the dielectric layer and the pad layer should be formed using a material or materials having a greater mechanical intensity (strength) than that of the molding layer.
- Still another embodiment of a method of forming scribe-line structures comprises the initial steps of forming a lower layer, a pad layer, and a molding layer on a semiconductor substrate in order.
- a photoresist layer is then formed on the molding layer.
- the photoresist layer is formed so as to have at least one opening extending down to the molding layer.
- the molding layer is then etched through the opening(s) using the photoresist layer as an etching mask. The etching process forms one or more protective hole(s) in the molding layer and the pad layer to expose the lower layer.
- the photoresist layer is thereafter removed from the semiconductor substrate.
- a dielectric layer, an upper layer, and a set of protective layer patterns are then formed in sequence so as to fill the protective hole(s).
- the dielectric layer and the pad layer should be formed using a material or materials having a greater mechanical intensity (strength) than that of the molding layer.
- FIG. 1 is a schematic layout diagram illustrating scribe-line structures formed along a face of a semiconductor substrate having at least a semiconductor device thereon, the scribe-line structures being formed according to the present invention
- FIGS. 2 and 3 are two schematic cross-sectional views, each of a different scribe-line structure as seen in FIG. 1 , taken along the section line I-I′ of FIG. 1 , respectively;
- FIGS. 4 to 11 are schematic cross-sectional views, taken along the section line I-I′ of FIG. 1 , illustrating the sequential steps in two methods of forming scribe-line structures according to the present invention.
- FIG. 1 is a schematic layout diagram illustrating scribe-line structures formed along a semiconductor substrate having at least a semiconductor device thereon, the scribe-line structures being formed according to the present invention
- FIGS. 2 and 3 are schematic cross-sectional views of two different scribe-line structures as seen in FIG. 1 taken along the section line I-I′ of FIG. 1 , respectively.
- a lower layer 20 and a pad layer 30 are sequentially disposed on a semiconductor substrate 10 .
- a molding layer 40 is disposed on the pad layer 30 .
- the molding layer 40 has a first protective contact hole 47 (as seen in FIG. 2 ) or alternatively has first and second protective contact holes 48 (as seen in FIG. 3 ), or, as shown in FIG. 1 , both.
- the first protective contact hole 47 and/or the first and second protective contact holes 48 may be surrounded with the molding layer 40 along the sides and the pad layer 30 along the bottom(s) thereof. In some invention embodiments, however, the pad layer 30 may not be disposed between the molding layer 40 and the lower layer 20 .
- the first protective contact hole 47 and/or the first and second protective contact holes 48 may be surrounded with the molding layer 40 along the sides and the lower layer 20 along the bottom(s) thereof. It is desirable that the lower layer 20 consist essentially of a material having a greater mechanical intensity (strength) than that of either the pad layer 30 or the molding layer 40 .
- the lower layer 20 may, for example, be formed of silicon oxide (SiO 2 ).
- the molding layer 40 should preferably consist essentially of a material having a lower mechanical intensity (strength) than that of the pad layer 30 .
- the pad layer 30 be formed of what will herein be called a “low-k material,” for example a material selected from the group consisting of the substances commonly known in the trade as Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto.
- the pad layer 30 and the molding layer 40 may alternatively be formed of what will herein be called a “lower-k material,” for example a material selected from the group consisting of the substances commonly known in the trade as Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto.
- the molding layer 40 may be composed of a compositie of two or more low-k materials.
- the pad layer 30 may also be composed of a compositie of two or more of the previously mentioned low-k materials or of two or more of the previously mentioned lower-k materials.
- a set of the protective hole(s) such as first protective contact hole 47
- the trench has a predetermined contact hole width B.
- a set of the first and second protective contact holes 48 be disposed along the scribe-line 90 of FIG. 1 to form two trenches as shown in FIG. 3 .
- Each of the first and second protective contact holes 48 in FIG. 3 defines a trench with a predetermined contact hole width C.
- a base layer 50 , a buried layer 60 , and an upper layer 70 may be sequentially disposed on the molding layer 40 so as to fill the first protective contact hole 47 ( FIG. 2 ) and/or the first and second protective contact holes 48 ( FIG. 3 ).
- the upper layer 70 be formed of silicon nitride (Si 3 N 4 ).
- the buried layer 60 and the base layer 50 be formed of a material or materials having a lower mechanical intensity (strength) than that of the lower layer 20 .
- the base layer 50 and the buried layer 60 consist essentially of a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, or materials having dielectric constants similar thereto.
- the base layer 50 may be a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, or materials having dielectric constants similar thereto, while the buried layer 60 may be a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, or materials having dielectric constants similar thereto.
- the base layer 50 may be lower-k material comprising Nanoporous silicate, BCB, Flare, ALCAP, LKD, or materials having dielectric constants similar thereto, while the buried layer 60 may be a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, or materials having dielectric constants similar thereto.
- the dielectric layer 65 may comprise either the buried layer 60 or the base layer 50 .
- the dielectric layer 65 may also be composed of two or more low-k materials.
- the dielectric layer 65 may be composed of a combination of two or more low-k materials and also of two or more lower-k materials, said material layers being stacked in turn.
- Protective layer patterns 80 are shown disposed on the upper layer 70 . It is desirable that the protective layer patterns 80 be disposed so as to be spaced a distance away from each other. As seen in FIG. 2 and FIG. 3 respectively, a spacing distance A between the protective layer patterns 80 is different from either the contact hole width B of the first protective contact hole 47 ( FIG. 2 ) or the contact hole width C of each of the first and second protective contact holes 48 ( FIG. 3 ). It is particularly desirable that the protective layer patterns 80 be formed of polyimide.
- FIGS. 4 to 11 are schematic cross-sectional views, taken along the section line I-I′ of FIG. 1 , illustrating sequential steps in two methods according to the present invention of forming scribe-line structures on a semiconductor substrate.
- a lower layer 20 and a pad layer 30 are sequentially formed on a semiconductor substrate 10 .
- a molding layer 40 and a photoresist layer 42 are then formed so as to be sequentially stacked on the pad layer 30 .
- the photoresist layer 42 is formed to have at least one opening, for example the single opening 44 in FIG. 4 and/or the two openings 44 seen in FIG. 5 .
- An etching process 46 is then performed on the molding layer 40 through the one or more openings 44 using the photoresist layer 42 as an etching mask.
- the etching process (represented by the arrows 46 ) forms a first protective contact hole 47 as shown in FIG. 4 or, alternatively, first and second protective contact holes 48 as shown in FIG. 5 , in the molding layer 40 .
- the first protective contact hole 47 or the first and second protective contact holes 48 are formed so as to expose the pad layer 30 .
- the first protective contact hole 47 be formed so as to extend a trench having a predetermined width B along a scribe-line 90 as shown in FIG. 1 .
- the scribe-line 90 may be formed to have the first and second protective contact holes 48 .
- the first and second protective contact holes 48 are preferably formed so as to extend each of two trenches, each having a predetermined width C, along the scribe-line 90 as shown in FIG. 1 .
- the first and second protective contact holes 48 ( FIG. 5 ) or the first protective contact hole 47 ( FIG. 4 ) may be repeatedly formed along a double ( FIG. 5 ) or a single ( FIG. 4 ) line 49 in a linear sequence to penetrate both the molding layer 40 and the underlying pad layer 30 .
- the first protective contact hole 47 or the first and second protective contact holes 48 are formed to a suitable depth so as to expose the lower layer 20 .
- the pad layer 30 may not be formed between the molding layer 40 and the lower layer 20 .
- the first protective contact hole 47 or the first and second protective contact holes 48 are formed to a suitable depth so as to expose the lower layer 20 through the molding layer 40 .
- the lower layer- 20 be formed by using a material having a greater mechanical intensity (strength) than that of either the pad layer 30 or the molding layer 40 .
- the lower layer 20 can be formed using silicon oxide (SiO 2 ).
- the molding layer 40 may be formed by using material having a lower mechanical intensity (strength) than that of the pad layer 30 .
- the pad layer 30 can be formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto.
- the pad layer 30 and the molding layer 40 may both be formed by using a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto.
- the molding layer 40 may also be composed of two or more lower-k materials.
- the pad layer 30 may be formed of two or more of the previously described low-k materials or of two or more of the previously described lower-k materials.
- the photoresist layer 42 is removed from the semiconductor substrate 10 by methods well known in the art.
- a dielectric layer 65 may be formed on the exposed portions of pad layer 30 and on the molding layer 40 so as to fill the first protective contact hole 47 or the first and second protective contact holes 48 . It is often desirable that the dielectric layer 65 be formed by using a base layer 50 and a buried layer 60 which are stacked in sequence. The dielectric 65 may also be formed, however, by only using the base layer 50 or only using the buried layer 60 .
- the buried layer 60 and the base layer 50 are preferably formed by using a material or materials having a greater mechanical intensity (strength) than that of the molding layer 40 . It is also often desirable that the buried layer 60 and the base layer 50 be formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto. In an alternative embodiment, the base layer 50 may be formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto, while the buried layer 60 is formed by using a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto.
- the base layer 50 may be formed by using a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto, while the buried layer 60 is formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto.
- the dielectric layer 65 may also be formed of two or more low-k materials.
- the dielectric layer 65 may additionally be formed of two or more low-k materials and two or more lower-k materials, as described above, stacked in turn.
- the base layer 50 and the buried layer 60 may be formed on the exposed portions of lower layer 20 and on the molding layer 40 so as to fill the first protective contact hole 47 or the first and second protective contact holes 48 .
- the base layer 50 and the buried layer 60 may be formed to have top surfaces as generally indicated by dotted lines 55 and 65 , respectively, as shown in FIGS. 6 and 7 .
- the buried layer 60 and the base layer 50 should have a greater mechanical intensity (strength) than that of the molding layer 40 , so that, during performance of a cutting process on the semiconductor substrate 10 along a scribe-line 90 , physical shock to the molding layer 40 can be minimized.
- the base layer 50 and the buried layer 60 can reduce the number of crack occurrences during cutting along the scribe-line.
- the first and second protective contact holes 48 use the molding layer 40 as a shielding layer against physical shock in a central area of the first protective contact hole 47 , crack transference to a peripheral area of the scribe-line 90 can also be minimized.
- an upper layer 70 may be formed on the dielectric layer 65 .
- the upper layer 70 may be conformally formed along the top surface of the dielectric layer 65 .
- the upper layer 70 may be formed, for example, using silicon nitride (Si 3 N 4 ).
- the upper layer 70 can be conformally formed to have a top surface generally indicated by dotted line 75 of FIG. 8 or FIG. 9 .
- Protective layer patterns 80 may then be formed on the upper layer 70 .
- the protective layer patterns 80 are preferably formed so as to be spaced a distance away from each other. It is desirable that the spacing distance A between the protective layer patterns 80 (as seen in FIG. 10 and FIG. 11 ) is selected so as to be different from either a contact hole width B of the first protective contact hole 47 or a contact hole width C of the first and second protective contact holes 48 .
- the protective layer patterns 80 are formed by using polyimide.
- materials having mechanical intensity (strength) different from one another are formed in or along a scribe-line on a semiconductor substrate to create a scribe-line structure, so that, during performance of a cutting process on a semiconductor substrate, mechanical shock or cracking tendencies to a peripheral area of the scribe-line structure may be minimized.
- the use of scribe-line structures according to this invention enables multiple semiconductor devices formed on the same substrate to be separated from one another and from unused semiconductor substrate while minimizing or eliminating damage to the semiconductor devices.
Abstract
Description
- This patent application claims priority from Korean Patent Application No. 10-2005-0006848, filed Jan. 25, 2005, the contents of which are hereby incorporated by reference in their entirety.
- 1. Field of the Invention
- The present invention relates to structures formed on a semiconductor substrate and to methods of forming the same, and more particularly, to scribe-line structures formed on a semiconductor substrate, to substrates having such scribe-line structures, and to methods of forming the same.
- 2. Description of the Related Art
- Generally, multiple semiconductor devices are formed respectively on predetermined regions of a semiconductor substrate. Each of these regions may be defined by a set of intersecting scribe-lines, for example by horizontal and vertical scribe-lines. Each such scribe-line has a predetermined width, so that the semiconductor substrate can be easily cut along the scribe-lines so as to separate the individual semiconductor devices from each other and from any unused portions of the semiconductor substrate. Before performing the cutting process described above, the semiconductor devices and the scribe-lines are typically covered with a plurality of interlayer insulating layers. The interlayer insulating layers protect the semiconductor devices from exterior environment influences while cutting the semiconductor substrate.
- But, in recent manufacturing operations in this field, it has been found that it is often necessary to replace each of the interlayer insulating layers used to protect the formed semiconductor devices with other materials having lower dielectric constants to avoid interfering with the higher-speed operation of modern semiconductor devices. A common characteristic of such materials having a lower dielectric constant, however, is that the mechanical intensity of these materials is often lower than that of silicon oxide (SiO2). As a result, such materials having a lower dielectric constant are readily subject to physical shock and have a tendency to crack along or adjacent to the semiconductor devices during the step of performing the cutting process along the scribe-lines.
- In one approach to these familiar problems, U.S. Pat. No. 6,441,465 to Chi-Fa Lin (the '465 patent), which is incorporated herein by reference, discloses a scribe line structure for preventing the type of damages as described above that may be induced during fabrication processes. According to the '465 patent, the scribe-line structure intentionally includes cavities disposed in a multi-layer structure along a scribe-line. The cavities are disposed on each side of a scribe-line and then disposed in at least two rows. The '465 patent teaches that such cavities reduce and relieve internal stress of the scribe lines, which may be created during formation of the scribe-line and thus reduce the tendency for crack formation, peeling, delamination and dielectric fracture of the scribe lines during cutting of the substrate.
- However, the scribe-line structure taught by the '465 patent also can cause damage to the semiconductor devices because the cavities act as starting points for a crack during performing a cutting process along a scribe-line. Besides, the cavities also act as obstructions while performing the cutting process along the scribe-line, so that the processing time may be made longer than would otherwise be required.
- These and other problems with or limitations of the prior art techniques in this field are addressed in whole, or at least in part, by the structures and methods of this invention.
- According to one embodiment of the present invention, there are provided scribe-line structures on a semiconductor substrate such that during performance of a cutting process on the semiconductor substrate, physical shock and cracking tendencies on the one or more semiconductor devices formed on the substrate can be minimized.
- According to another embodiment of the present invention, there are provided methods of forming scribe-line structures such that during performance of a cutting process on a semiconductor substrate having such scribe-line structures thereon, physical shock and cracking tendencies on the semiconductor devices formed on the substrate can be minimized.
- To accomplish the objects described above and other related objectives, the present invention provides new types of scribe-line structures and methods of forming such scribe-line structures.
- One embodiment of scribe-line structures according to this invention comprises a lower layer disposed on a semiconductor substrate. A molding layer having at least one protective contact hole is then disposed on the lower layer. A dielectric layer and an upper layer are thereafter disposed in sequence on the molding layer so as to fill the protective contact hole(s). On the upper layer, protective layer patterns are then disposed so as to be spaced a distance away from each other. The spacing distance between the protective layer patterns should be different in size from a width of the protective contact hole(s). Also, the dielectric layer should be formed of a material having a greater mechanical intensity (or strength) than that of the molding layer.
- Another embodiment of scribe-line structures according to this invention comprises a lower layer disposed on a semiconductor substrate. A pad layer and a molding layer having at least one protective contact hole are then disposed on the lower layer in sequence. A dielectric layer and an upper layer are thereafter disposed in sequence on the molding layer so as to fill the protective contact hole(s). On the upper layer, protective layer patterns are then disposed so as to be spaced a distance away from each other. The spacing distance between the protective layer patterns should be different in size from a width of the protective contact hole(s). Also, the dielectric layer and the pad layer should be formed of a material or of materials having a greater mechanical intensity (or strength) than that of the molding layer.
- Still another embodiment of scribe-line structures according to this invention comprises a lower layer and a pad layer disposed in order on a semiconductor substrate. A molding layer having at least one protective contact hole is then disposed on the pad layer. A dielectric layer and an upper layer are thereafter disposed in sequence on the molding layer so as to fill the protective contact hole(s). On the upper layer, protective layer patterns are then disposed so as to be spaced a distance away from each other. The spacing distance between the protective layer patterns should be different in size from a width of the protective contact hole(s). Also, the dielectric layer and the pad layer should be formed of a material or of materials having a greater mechanical intensity (or strength) than that of the molding layer.
- One embodiment of a method of forming scribe-line structures according to this invention comprises the initial steps of forming a lower layer and a molding layer on a semiconductor substrate in sequence. A photoresist layer is then formed on the molding layer. The photoresist layer is formed so as to have at least one opening extending down to the molding layer. The molding layer is then etched through the opening(s) using the photoresist layer as an etching mask. The etching process forms one or more protective hole(s) in the molding layer to expose the lower layer. The photoresist layer is thereafter removed from the semiconductor substrate. On the molding layer, a dielectric layer, an upper layer, and a set of protective layer patterns are then formed in sequence so as to fill the protective hole(s). The dielectric layer should be formed using a material having a greater mechanical intensity (strength) than that of the molding layer.
- Another embodiment of a method of forming scribe-line structures according to this invention comprises the initial steps of forming a lower layer, a pad layer, and a molding layer on a semiconductor substrate in sequence. A photoresist layer is then formed on the molding layer. The photoresist layer is formed so as to have at least one opening extending down to the molding layer. The molding layer and the pad layer are then etched in sequence through the opening(s) using the photoresist layer as an etching mask. The etching process forms one or more protective hole(s) in the pad layer and the molding layer to expose the lower layer. The photoresist layer is thereafter removed from the semiconductor substrate. On the molding layer, a dielectric layer, an upper layer, and a set of protective layer patterns are then formed in sequence so as to fill the protective hole(s). The dielectric layer and the pad layer should be formed using a material or materials having a greater mechanical intensity (strength) than that of the molding layer.
- Still another embodiment of a method of forming scribe-line structures according to this invention comprises the initial steps of forming a lower layer, a pad layer, and a molding layer on a semiconductor substrate in order. A photoresist layer is then formed on the molding layer. The photoresist layer is formed so as to have at least one opening extending down to the molding layer. The molding layer is then etched through the opening(s) using the photoresist layer as an etching mask. The etching process forms one or more protective hole(s) in the molding layer and the pad layer to expose the lower layer. The photoresist layer is thereafter removed from the semiconductor substrate. On the molding layer, a dielectric layer, an upper layer, and a set of protective layer patterns are then formed in sequence so as to fill the protective hole(s). The dielectric layer and the pad layer should be formed using a material or materials having a greater mechanical intensity (strength) than that of the molding layer.
- Exemplary embodiments of the invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows when taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts or elements. In the drawings:
-
FIG. 1 is a schematic layout diagram illustrating scribe-line structures formed along a face of a semiconductor substrate having at least a semiconductor device thereon, the scribe-line structures being formed according to the present invention; -
FIGS. 2 and 3 are two schematic cross-sectional views, each of a different scribe-line structure as seen inFIG. 1 , taken along the section line I-I′ ofFIG. 1 , respectively; and - FIGS. 4 to 11 are schematic cross-sectional views, taken along the section line I-I′ of
FIG. 1 , illustrating the sequential steps in two methods of forming scribe-line structures according to the present invention. -
FIG. 1 is a schematic layout diagram illustrating scribe-line structures formed along a semiconductor substrate having at least a semiconductor device thereon, the scribe-line structures being formed according to the present invention, andFIGS. 2 and 3 are schematic cross-sectional views of two different scribe-line structures as seen inFIG. 1 taken along the section line I-I′ ofFIG. 1 , respectively. - Referring to FIGS. 1 to 3, a
lower layer 20 and apad layer 30 are sequentially disposed on asemiconductor substrate 10. Amolding layer 40 is disposed on thepad layer 30. Themolding layer 40 has a first protective contact hole 47 (as seen inFIG. 2 ) or alternatively has first and second protective contact holes 48 (as seen inFIG. 3 ), or, as shown inFIG. 1 , both. The firstprotective contact hole 47 and/or the first and second protective contact holes 48 may be surrounded with themolding layer 40 along the sides and thepad layer 30 along the bottom(s) thereof. In some invention embodiments, however, thepad layer 30 may not be disposed between themolding layer 40 and thelower layer 20. In this case, the firstprotective contact hole 47 and/or the first and second protective contact holes 48 may be surrounded with themolding layer 40 along the sides and thelower layer 20 along the bottom(s) thereof. It is desirable that thelower layer 20 consist essentially of a material having a greater mechanical intensity (strength) than that of either thepad layer 30 or themolding layer 40. Thelower layer 20 may, for example, be formed of silicon oxide (SiO2). - At the same time, the
molding layer 40 should preferably consist essentially of a material having a lower mechanical intensity (strength) than that of thepad layer 30. It is especially desirable that thepad layer 30 be formed of what will herein be called a “low-k material,” for example a material selected from the group consisting of the substances commonly known in the trade as Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto. For some invention embodiments, thepad layer 30 and themolding layer 40 may alternatively be formed of what will herein be called a “lower-k material,” for example a material selected from the group consisting of the substances commonly known in the trade as Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto. For some invention embodiments, themolding layer 40 may be composed of a compositie of two or more low-k materials. For some invention embodiments, thepad layer 30 may also be composed of a compositie of two or more of the previously mentioned low-k materials or of two or more of the previously mentioned lower-k materials. It is also desirable in accordance with this invention that a set of the protective hole(s), such as firstprotective contact hole 47, be disposed along a scribe-line 90 ofFIG. 1 to form a trench as shown inFIG. 2 . The trench has a predetermined contact hole width B. It is similarly desirable that a set of the first and second protective contact holes 48 be disposed along the scribe-line 90 ofFIG. 1 to form two trenches as shown inFIG. 3 . Each of the first and second protective contact holes 48 inFIG. 3 defines a trench with a predetermined contact hole width C. - A
base layer 50, a buriedlayer 60, and anupper layer 70 may be sequentially disposed on themolding layer 40 so as to fill the first protective contact hole 47 (FIG. 2 ) and/or the first and second protective contact holes 48 (FIG. 3 ). It is particularly desirable that theupper layer 70 be formed of silicon nitride (Si3N4). It is also desirable that the buriedlayer 60 and thebase layer 50 be formed of a material or materials having a lower mechanical intensity (strength) than that of thelower layer 20. It is particularly desirable, for example, that thebase layer 50 and the buriedlayer 60 consist essentially of a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, or materials having dielectric constants similar thereto. In another invention embodiment, thebase layer 50 may be a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, or materials having dielectric constants similar thereto, while the buriedlayer 60 may be a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, or materials having dielectric constants similar thereto. Also, thebase layer 50 may be lower-k material comprising Nanoporous silicate, BCB, Flare, ALCAP, LKD, or materials having dielectric constants similar thereto, while the buriedlayer 60 may be a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, or materials having dielectric constants similar thereto. Hereinafter, the combination ofbase layer 50 and buriedlayer 60, or, if only one is present, the one layer, will be referred to asdielectric layer 65. Thus, thedielectric layer 65 may comprise either the buriedlayer 60 or thebase layer 50. Thedielectric layer 65 may also be composed of two or more low-k materials. Alternatively, thedielectric layer 65 may be composed of a combination of two or more low-k materials and also of two or more lower-k materials, said material layers being stacked in turn. -
Protective layer patterns 80 are shown disposed on theupper layer 70. It is desirable that theprotective layer patterns 80 be disposed so as to be spaced a distance away from each other. As seen inFIG. 2 andFIG. 3 respectively, a spacing distance A between theprotective layer patterns 80 is different from either the contact hole width B of the first protective contact hole 47 (FIG. 2 ) or the contact hole width C of each of the first and second protective contact holes 48 (FIG. 3 ). It is particularly desirable that theprotective layer patterns 80 be formed of polyimide. - FIGS. 4 to 11 are schematic cross-sectional views, taken along the section line I-I′ of
FIG. 1 , illustrating sequential steps in two methods according to the present invention of forming scribe-line structures on a semiconductor substrate. - Referring to
FIGS. 1, 4 , and 5, alower layer 20 and apad layer 30 are sequentially formed on asemiconductor substrate 10. Amolding layer 40 and aphotoresist layer 42 are then formed so as to be sequentially stacked on thepad layer 30. Thephotoresist layer 42 is formed to have at least one opening, for example thesingle opening 44 inFIG. 4 and/or the twoopenings 44 seen inFIG. 5 . Anetching process 46 is then performed on themolding layer 40 through the one ormore openings 44 using thephotoresist layer 42 as an etching mask. The etching process (represented by the arrows 46) forms a firstprotective contact hole 47 as shown inFIG. 4 or, alternatively, first and second protective contact holes 48 as shown inFIG. 5 , in themolding layer 40. The firstprotective contact hole 47 or the first and second protective contact holes 48 are formed so as to expose thepad layer 30. - In accordance with this invention, it is desirable that the first
protective contact hole 47 be formed so as to extend a trench having a predetermined width B along a scribe-line 90 as shown inFIG. 1 . Alternatively (or, additionally), the scribe-line 90 may be formed to have the first and second protective contact holes 48. The first and second protective contact holes 48 are preferably formed so as to extend each of two trenches, each having a predetermined width C, along the scribe-line 90 as shown inFIG. 1 . - The first and second protective contact holes 48 (
FIG. 5 ) or the first protective contact hole 47 (FIG. 4 ) may be repeatedly formed along a double (FIG. 5 ) or a single (FIG. 4 )line 49 in a linear sequence to penetrate both themolding layer 40 and theunderlying pad layer 30. As noted above, the firstprotective contact hole 47 or the first and second protective contact holes 48 are formed to a suitable depth so as to expose thelower layer 20. In some invention embodiments, thepad layer 30 may not be formed between themolding layer 40 and thelower layer 20. In this case, the firstprotective contact hole 47 or the first and second protective contact holes 48 are formed to a suitable depth so as to expose thelower layer 20 through themolding layer 40. - It is desirable that the lower layer-20 be formed by using a material having a greater mechanical intensity (strength) than that of either the
pad layer 30 or themolding layer 40. In one preferred embodiment, thelower layer 20 can be formed using silicon oxide (SiO2). In another preferred embodiment, themolding layer 40 may be formed by using material having a lower mechanical intensity (strength) than that of thepad layer 30. In one invention embodiment, thepad layer 30 can be formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto. In another invention embodiment, thepad layer 30 and themolding layer 40 may both be formed by using a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto. Themolding layer 40 may also be composed of two or more lower-k materials. In yet another embodiment, thepad layer 30 may be formed of two or more of the previously described low-k materials or of two or more of the previously described lower-k materials. - After the formation of the first
protective contact hole 47 and/or of the first and second protective contact holes 48, thephotoresist layer 42 is removed from thesemiconductor substrate 10 by methods well known in the art. - Referring now to
FIGS. 1, 6 , and 7, a portion or portions of thepad layer 30 is (are) exposed through the firstprotective contact hole 47 and/or the first and second protective contact holes 48, adielectric layer 65 may be formed on the exposed portions ofpad layer 30 and on themolding layer 40 so as to fill the firstprotective contact hole 47 or the first and second protective contact holes 48. It is often desirable that thedielectric layer 65 be formed by using abase layer 50 and a buriedlayer 60 which are stacked in sequence. The dielectric 65 may also be formed, however, by only using thebase layer 50 or only using the buriedlayer 60. - The buried
layer 60 and thebase layer 50 are preferably formed by using a material or materials having a greater mechanical intensity (strength) than that of themolding layer 40. It is also often desirable that the buriedlayer 60 and thebase layer 50 be formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto. In an alternative embodiment, thebase layer 50 may be formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto, while the buriedlayer 60 is formed by using a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto. Alternatively, thebase layer 50 may be formed by using a lower-k material selected from the group consisting of Nanoporous silicate, BCB, Flare, ALCAP, LKD, and materials having dielectric constants similar thereto, while the buriedlayer 60 is formed by using a low-k material selected from the group consisting of Black Diamond, Coral, Aurora, and materials having dielectric constants similar thereto. Thedielectric layer 65 may also be formed of two or more low-k materials. Furthermore, thedielectric layer 65 may additionally be formed of two or more low-k materials and two or more lower-k materials, as described above, stacked in turn. - In the case where a portion or portions of the
lower layer 20 is (are) exposed through the firstprotective contact hole 47 or through the first and second protective contact holes 48, thebase layer 50 and the buriedlayer 60 may be formed on the exposed portions oflower layer 20 and on themolding layer 40 so as to fill the firstprotective contact hole 47 or the first and second protective contact holes 48. At this time, thebase layer 50 and the buriedlayer 60 may be formed to have top surfaces as generally indicated bydotted lines FIGS. 6 and 7 . - The buried
layer 60 and thebase layer 50 should have a greater mechanical intensity (strength) than that of themolding layer 40, so that, during performance of a cutting process on thesemiconductor substrate 10 along a scribe-line 90, physical shock to themolding layer 40 can be minimized. As a result, thebase layer 50 and the buriedlayer 60 can reduce the number of crack occurrences during cutting along the scribe-line. Furthermore, because the first and second protective contact holes 48 use themolding layer 40 as a shielding layer against physical shock in a central area of the firstprotective contact hole 47, crack transference to a peripheral area of the scribe-line 90 can also be minimized. - Referring now to
FIGS. 1 and 8 to 11, in the case where thepad layer 30 is exposed through the firstprotective contact hole 47 or through the first and second protective contact holes 48, anupper layer 70 may be formed on thedielectric layer 65. Theupper layer 70 may be conformally formed along the top surface of thedielectric layer 65. Theupper layer 70 may be formed, for example, using silicon nitride (Si3N4). In the case where thelower layer 20 is exposed through the firstprotective contact hole 47 or through the first and second protective contact holes 48, theupper layer 70 can be conformally formed to have a top surface generally indicated by dottedline 75 ofFIG. 8 orFIG. 9 . -
Protective layer patterns 80 may then be formed on theupper layer 70. Theprotective layer patterns 80 are preferably formed so as to be spaced a distance away from each other. It is desirable that the spacing distance A between the protective layer patterns 80 (as seen inFIG. 10 andFIG. 11 ) is selected so as to be different from either a contact hole width B of the firstprotective contact hole 47 or a contact hole width C of the first and second protective contact holes 48. In a preferred invention embodiment, theprotective layer patterns 80 are formed by using polyimide. - According to the present invention described above, materials having mechanical intensity (strength) different from one another are formed in or along a scribe-line on a semiconductor substrate to create a scribe-line structure, so that, during performance of a cutting process on a semiconductor substrate, mechanical shock or cracking tendencies to a peripheral area of the scribe-line structure may be minimized. As a result, through the cutting process performed on the semiconductor substrate, the use of scribe-line structures according to this invention enables multiple semiconductor devices formed on the same substrate to be separated from one another and from unused semiconductor substrate while minimizing or eliminating damage to the semiconductor devices.
- While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (42)
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US12/034,919 US20080142927A1 (en) | 2005-01-25 | 2008-02-21 | Scribe-line structures and methods of forming the same |
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KR10-2005-0006848 | 2005-01-25 | ||
KR1020050006848A KR100641364B1 (en) | 2005-01-25 | 2005-01-25 | Scribe-lines and methods of forming the same |
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US11/335,359 Expired - Fee Related US7358155B2 (en) | 2005-01-25 | 2006-01-19 | Scribe-line structures and methods of forming the same |
US12/034,919 Abandoned US20080142927A1 (en) | 2005-01-25 | 2008-02-21 | Scribe-line structures and methods of forming the same |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108346661A (en) * | 2017-01-24 | 2018-07-31 | 三星电子株式会社 | Semiconductor devices |
US10886234B2 (en) * | 2018-08-24 | 2021-01-05 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package comprising the same |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US9806088B2 (en) | 2016-02-15 | 2017-10-31 | Toshiba Memory Corporation | Semiconductor memory device having memory cells arranged three-dimensionally and method of manufacturing the same |
KR102541563B1 (en) * | 2016-04-27 | 2023-06-08 | 삼성전자주식회사 | Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device |
KR102399356B1 (en) * | 2017-03-10 | 2022-05-19 | 삼성전자주식회사 | Substrate, method of sawing substrate, and semiconductor device |
KR102543869B1 (en) | 2018-08-07 | 2023-06-14 | 삼성전자주식회사 | Semiconductor device and semiconductor package comprising the same |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5686171A (en) * | 1993-12-30 | 1997-11-11 | Vlsi Technology, Inc. | Integrated circuit scribe line structures and methods for making same |
US6335559B1 (en) * | 1998-07-08 | 2002-01-01 | Hewlett-Packard Company | Semiconductor device cleave initiation |
US6383893B1 (en) * | 2000-12-28 | 2002-05-07 | International Business Machines Corporation | Method of forming a crack stop structure and diffusion barrier in integrated circuits |
US6441465B2 (en) * | 1999-02-09 | 2002-08-27 | Winbond Electronics Corp. | Scribe line structure for preventing from damages thereof induced during fabrication |
US6897127B2 (en) * | 2002-10-15 | 2005-05-24 | Seiko Epson Corporation | Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument |
US20050139964A1 (en) * | 2003-12-24 | 2005-06-30 | Elpida Memory, Inc. | Semiconductor wafer and dicing method |
US6939777B2 (en) * | 2003-11-12 | 2005-09-06 | Renesas Technology Corp. | Method for manufacturing semiconductor device |
US20050233549A1 (en) * | 2004-04-19 | 2005-10-20 | Hana Microdisplay Technologies, Inc. | Multi-elevation singulation of device laminates in wafer scale and substrate processing |
US20060141750A1 (en) * | 2002-11-12 | 2006-06-29 | Nobuhiro Suzuki | Semiconductor integrated device and method for manufacturing same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5889841A (en) * | 1981-11-24 | 1983-05-28 | Nec Corp | Manufacture of semiconductor device |
US5094984A (en) * | 1990-10-12 | 1992-03-10 | Hewlett-Packard Company | Suppression of water vapor absorption in glass encapsulation |
KR100267775B1 (en) | 1997-05-30 | 2000-12-01 | 김영환 | Method for fabricating in semiconductor device |
KR19990008510A (en) | 1997-07-01 | 1999-02-05 | 문정환 | Test pattern pad formation method |
KR20040003319A (en) | 2002-07-02 | 2004-01-13 | 삼성전자주식회사 | A semiconductor device of a metal line |
JP4454242B2 (en) * | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
-
2005
- 2005-01-25 KR KR1020050006848A patent/KR100641364B1/en not_active IP Right Cessation
-
2006
- 2006-01-19 US US11/335,359 patent/US7358155B2/en not_active Expired - Fee Related
-
2008
- 2008-02-21 US US12/034,919 patent/US20080142927A1/en not_active Abandoned
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5686171A (en) * | 1993-12-30 | 1997-11-11 | Vlsi Technology, Inc. | Integrated circuit scribe line structures and methods for making same |
US5795815A (en) * | 1993-12-30 | 1998-08-18 | Vlsi Technology, Inc. | Integrated circuit scribe line structures and methods for making same |
US5943591A (en) * | 1993-12-30 | 1999-08-24 | Vlsi Technology | Integrated circuit scribe line structures and methods for making same |
US6335559B1 (en) * | 1998-07-08 | 2002-01-01 | Hewlett-Packard Company | Semiconductor device cleave initiation |
US6441465B2 (en) * | 1999-02-09 | 2002-08-27 | Winbond Electronics Corp. | Scribe line structure for preventing from damages thereof induced during fabrication |
US6383893B1 (en) * | 2000-12-28 | 2002-05-07 | International Business Machines Corporation | Method of forming a crack stop structure and diffusion barrier in integrated circuits |
US6897127B2 (en) * | 2002-10-15 | 2005-05-24 | Seiko Epson Corporation | Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument |
US20060141750A1 (en) * | 2002-11-12 | 2006-06-29 | Nobuhiro Suzuki | Semiconductor integrated device and method for manufacturing same |
US6939777B2 (en) * | 2003-11-12 | 2005-09-06 | Renesas Technology Corp. | Method for manufacturing semiconductor device |
US20050139964A1 (en) * | 2003-12-24 | 2005-06-30 | Elpida Memory, Inc. | Semiconductor wafer and dicing method |
US20050233549A1 (en) * | 2004-04-19 | 2005-10-20 | Hana Microdisplay Technologies, Inc. | Multi-elevation singulation of device laminates in wafer scale and substrate processing |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108346661A (en) * | 2017-01-24 | 2018-07-31 | 三星电子株式会社 | Semiconductor devices |
US10886234B2 (en) * | 2018-08-24 | 2021-01-05 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package comprising the same |
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KR20060086038A (en) | 2006-07-31 |
US20080142927A1 (en) | 2008-06-19 |
KR100641364B1 (en) | 2006-10-31 |
US7358155B2 (en) | 2008-04-15 |
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