US20060155958A1 - Processor architecture - Google Patents

Processor architecture Download PDF

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Publication number
US20060155958A1
US20060155958A1 US11/293,845 US29384505A US2006155958A1 US 20060155958 A1 US20060155958 A1 US 20060155958A1 US 29384505 A US29384505 A US 29384505A US 2006155958 A1 US2006155958 A1 US 2006155958A1
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Prior art keywords
processor
instruction
unit
execution units
groups
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Abandoned
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US11/293,845
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English (en)
Inventor
Andrew Duller
Gajinder Panesar
Peter Claydon
William Robbins
Andrew Kuligowski
Olfat Younis
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Intel Corp
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Picochip Designs Ltd
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Assigned to PICOCHIP DESIGNS LIMITED reassignment PICOCHIP DESIGNS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KULIGOWSKI, ANDREW, ROBBINS, WILLIAM, YOUNIS, OLFAT, DULLER, ANDREW, PANESAR, GAJINDER, CLAYDON, PETER
Publication of US20060155958A1 publication Critical patent/US20060155958A1/en
Assigned to ETV CAPITAL S.A. reassignment ETV CAPITAL S.A. SECURITY AGREEMENT Assignors: PICOCHIP DESIGNS LIMITED
Priority to US11/981,973 priority Critical patent/US9104426B2/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MINDSPEED TECHNOLOGIES, INC., MINDSPEED TECHNOLOGIES U.K., LIMITED, PICOCHIP (BEIJING) TECHNOLOGY COMPANY LIMITED, MINDSPEED TELECOMMUNICATIONS TECHNOLOGIES DEVELOPMENT (SHENSHEN) CO. LTD.
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters

Definitions

  • This invention relates to a processor architecture, and in particular to a processor architecture which is particularly useful in signal processing applications.
  • Modern high-performance wireless communications systems require digital processors which can provide billions of compute operations per second to achieve acceptable performance, for example to carry out operations such as filtering, equalisation and decoding functions.
  • digital processors which can provide billions of compute operations per second to achieve acceptable performance, for example to carry out operations such as filtering, equalisation and decoding functions.
  • ALUs arithmetic logic units
  • multipliers arithmetic logic units
  • address generators etc.
  • LIF Long Instruction Word
  • instructions for each of a number of execution units are concatenated into one “long instruction word” which can be executed in a single processor cycle.
  • a bit field within the long instruction is reserved for an instruction for each of the execution units, regardless of whether a particular execution unit will be active within any one processor cycle. This has the disadvantageous effect that it creates excessively long instruction words, which can contain a lot of redundant information for execution units that are not active.
  • the present invention relates to an alternative implementation of an LIW processor.
  • a processor which comprises multiple execution units.
  • the multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups.
  • the processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor. That is, it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously.
  • execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device.
  • an array comprising a plurality of interconnected processors, wherein each of the processors comprises multiple execution units as defined above.
  • FIG. 1 is a block schematic diagram of a processor array according to an aspect of the present invention
  • FIG. 2 is a block schematic diagram of a processor within the processor array of FIG. 1 , according to another aspect of the present invention
  • FIG. 3 is an overview of the format of an instruction word for use in the processor of FIG. 2 ;
  • FIG. 4 illustrates in more detail the format of a part of the instruction word shown in FIG. 3 ;
  • FIG. 5 illustrates the operation of a second part of the instruction word shown in FIG. 3 ;
  • FIG. 6 illustrates the operation of a third part of the instruction word shown in FIG. 3 .
  • FIG. 1 is a block schematic diagram of a processor array, as generally described in WO02/50624.
  • the array is made up of array elements 20 , which are interconnected by buses and switches.
  • the array architecture includes first bus pairs 30 , shown running horizontally in FIG. 1 , each pair including a respective first bus 32 carrying data from left to right in FIG. 1 and a respective second bus 36 carrying data from right to left.
  • the array architecture includes second bus pairs 40 , shown running vertically in FIG. 1 , each pair including a respective third bus 42 carrying data upwards in FIG. 1 and a respective fourth bus 46 carrying data downwards.
  • each diamond connection 50 represents a switch, which connects an array element 20 to a respective bus 32 , 36 .
  • the array further includes a switch matrix 55 at each intersection of a first and second bus pair 30 , 40 .
  • the data buses, and the switches and switch matrices, therefore allow data to be switched from one array element to another for processing, as required.
  • the array elements 20 take the form of processors, as shown in more detail in FIG. 2 .
  • the processors 20 are adapted to make them particularly suitable for use as array elements, although the invention is also applicable to individual processors.
  • the processor 20 includes a 64 ⁇ 64 bit instruction memory 60 , which contains instructions loaded into the memory to control the operation of the processor.
  • instructions are fetched from the instruction memory 60 , and passed to an instruction decoder 62 , where they are decoded to configure the datapaths and execution units in the processor.
  • the processor comprises six execution units.
  • the first available execution unit is a first Arithmetic Logic Unit (ALU) 64 , which can perform a number of arithmetic and logical operations.
  • ALU Arithmetic Logic Unit
  • the second available execution unit is a communications unit 66 , which is connected to the input communications bus 68 and the output communications bus 70 , and is able to perform “put” and “get” operations to move data to and from the external communications buses 68 , 70 , and is also able to move data to and from the 15 ⁇ 16 bit data registers 84 .
  • the registers 84 are connected to the execution units by means of a data bus 85 .
  • the communications unit 66 is thereby optimised to support the processing performed in the array, whereby data flows from one processor 20 to another, with parts of the processing being performed at each stage.
  • the third available execution unit is a combined Memory Access Unit (MAU)/second ALU 72 , which performs a variety of load and store operations over a bus 74 to a 64 ⁇ 32 bit data memory 76 , and also provides a subset of the ALU operations performed by the first ALU 64 .
  • MAU Memory Access Unit
  • second ALU 72 which performs a variety of load and store operations over a bus 74 to a 64 ⁇ 32 bit data memory 76 , and also provides a subset of the ALU operations performed by the first ALU 64 .
  • the fourth available execution unit is a branch unit 78 , which performs a number of conditional and unconditional branch operations.
  • the fifth available execution unit is a Multiplier Accumulator (MAC) Unit 80 , which performs a variety of multiply and multiply accumulate operations with various bit widths.
  • MAC Multiplier Accumulator
  • this unit may be replaced by a simpler Multiply unit.
  • an Application Specific Unit (ASU) 82 .
  • the ASU 82 is adapted to perform a number of highly specialised operations for wireless signal processing applications, such as complex spread and complex despread, in order to support CDMA transmit and receive functionality.
  • this unit may be omitted.
  • each execution unit is able to perform one operation in one clock cycle.
  • the first ALU 64 is also able to perform a shift operation on the first operand of the basic arithmetic or logical operations.
  • two instructions can effectively execute simultaneously on that one execution unit.
  • the execution units are clustered into three groups, each controlled by a separate instruction in a LIW instruction.
  • the first group 86 includes only the first Arithmetic Logic Unit (ALU) 64 ; the second group 88 is made up of the communications unit 66 , and the combined Memory Access Unit (MAU)/second ALU 72 ; and the third group 90 is made up the branch unit 78 , the Multiplier Accumulator (MAC) Unit 80 , and the Application Specific Unit (ASU) 82 .
  • ALU Arithmetic Logic Unit
  • MAU Memory Access Unit
  • ASU Application Specific Unit
  • the device is then controlled such that any one, any two, or all three of the groups 86 , 88 , 90 can be active at any one time, but such that no more than one of the execution units within a group can be active at any one time.
  • the instruction format is such that this can be achieved efficiently in each case.
  • a long instruction word can include an instruction LIW# 1 for the first group 86 , an instruction LIW# 2 for the second group 88 , and an instruction LIW# 3 for the third group 90 .
  • FIG. 3 shows the basic structure of a long instruction word instruction, which is also explained in more detail in FIGS. 4, 5 and 6 .
  • the long instruction word first contains a short, 3 bit, bit sequence, which indicates whether the first group 86 is active in that processor cycle and, if so, indicates what class of operation is to be performed, so that execution units and datapaths can be configured.
  • the first group 86 is active in that processor cycle and that three bit sequence indicates what operation is to be performed by the first Arithmetic Logic Unit (ALU) 64 .
  • ALU Arithmetic Logic Unit
  • the operation is an ALU operation with three operands, for example adding two values to give a result, with the three operands then being the register addresses of the two values to be added plus the register address in which the result is to be stored.
  • the operation is a load or store operation between the data memory and a nominated register or register pair.
  • the operation is an ALU operation with two operands, one operand, or no operands, for example nop.
  • the fourth bit indicates whether an extension byte is to be used, as will be described in more detail below.
  • the remaining four bits of byte 0 , and the eight bits of byte 1 then indicate the operands or opcode values, depending on the value of the first three bits of byte 0 , as shown in FIG. 4 . More specifically, where FIG. 4 says that four of these bits represent an operand, they define the address, within the registers 84 , from which the first ALU 64 should retrieve the respective operand on which it will perform the defined operation.
  • the fourth bit must be set to “1”, and the extension byte must be used, if either the second group 88 or the third group 90 is active.
  • the first group 86 is not active in that processor cycle, and byte 0 of the long instruction word then contains further short bit sequences, which indicate whether the second group 88 and third group 90 are active and, if so, what class of operation is to be performed.
  • additional bytes LIW# 2 108 provide required information to allow the second group 88 to perform the intended function
  • additional bytes LIW# 3 110 provide required information to allow the third group 90 to perform the intended function.
  • the extension byte In the case where the first three bits of byte 0 are not 000 , and an LIW# 1 instruction or “short” Memory Access operation is to be executed, the extension byte must be used if either or both of the second group 88 and third group 90 is active. If so, the extension byte carries Lcode 2 and Lcode 3 , and additional bytes LIW# 2 108 and LIW# 3 110 contain the required information to allow the relevant group to perform the intended function.
  • the extension byte also carries a 2-bit extension opcode “ex op”, which allows more possible instructions for ALU# 0 .
  • the extension byte also includes a 1 bit flag, S. If set, the flag S indicates the presence of a shift operation on the ALU first operand. In that case, an additional byte following the extension byte is used to define whether the shift is logical or arithmetic, to the left or right, and how many bits are shifted (4-bit value).
  • the instruction set architecture supports the use of short constants (which, in this illustrated embodiment, are 4 bits long) and long constants (which, in this illustrated embodiment, are 16 bits long).
  • operands are generally 4 bits long, and one of these 4-bit operands normally refers to one of the registers 84 , but it can alternatively be used to indicate a 4-bit constant value.
  • the operand value “15” is used to direct the instruction decoder 62 to take the value in the 16-bit field 112 , which in that case appears at the end of the long instruction word instruction, as a 16-bit constant value. No useful information is therefore stored at the register address “15” (R 15 ). Thus, writing to R 15 is used to indicate that an operation result should be discarded.
  • the encoded instruction word is organized on byte boundaries. It can further be seen from FIGS. 3-6 that an individual LIW instruction can be between 1 byte (the special case where none of the groups is active, and there are no LIW# 1 , no LIW# 2 and no LIW# 3 instructions) and 9 bytes in length.
  • the instruction decoder 62 can therefore support any combination of instruction lengths within a single 64-bit instruction word and can tolerate LIW instructions which are contained in successive 64-bit instruction words.
  • the length of any single LIW instruction cannot exceed 8 bytes. However, in other embodiments of the invention, this maximum length can be set to any desired value. This restriction results in a small number of combinations of LIW# 1 , LIW# 2 and LIW# 3 instructions which cannot be supported because they exceed this length. These illegal combinations are trapped by the Instruction Decode block 62 , resulting in the setting of an Illegal Instruction flag.
  • a compiler and assembler operating to support the processor architecture should also intercept disallowed instruction combinations at compile time.
  • the architecture relies on an instruction being decoded every processor cycle and therefore it is necessary that a branch destination is aligned at the beginning of a 64-bit instruction word.
  • the instruction decoder 62 interprets an all-0 byte instruction (equivalent to “no LIW# 1 , no LIW# 2 , no LIW# 3 ”) as a “new line” and will fetch the next 64-bit instruction word.
  • the compiler and assembler can use the “new line” instruction at the end of an instruction sequence immediately prior to a branch destination, in order to ensure 64-bit alignment of the instruction at the branch destination.
  • the long instruction word format therefore has the property that the length LIW inst of the long instruction word is independent of the total number of execution units. Rather, it is determined by the maximum number of execution units which can be active in a single processor cycle. In the illustrated embodiment, a maximum of three execution units out of the six available can be active in a single LIW instruction/processor cycle, and the maximum length of a single LIW instruction is limited to 64 bits.
  • LIW inst of the long instruction word can vary, from one instruction to the next, depending on the number of active execution units within a given cycle. Thus, in many instruction cycles, it is likely that LIW inst will be less than 64 bits.
  • multiple instructions can be packed into the 64 bit wide instruction memory 60 , usually without the need for alignment to word boundaries, and the instructions can overrun a 64-bit instruction word boundary into the following instruction word.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
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US20100185818A1 (en) * 2009-01-21 2010-07-22 Lanping Sheng Resource pool managing system and signal processing method
WO2015035339A1 (en) * 2013-09-06 2015-03-12 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with heterogeneous processors
WO2015035306A1 (en) * 2013-09-06 2015-03-12 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with token-based very long instruction word architecture

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KR100813662B1 (ko) 2006-11-17 2008-03-14 삼성전자주식회사 프로세서 구조 및 응용의 최적화를 위한 프로파일러

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GB0426606D0 (en) 2005-01-05
JP2006164279A (ja) 2006-06-22
JP5112627B2 (ja) 2013-01-09
EP1667016A2 (de) 2006-06-07
GB2420884A (en) 2006-06-07
GB2420884B (en) 2009-04-15
US9104426B2 (en) 2015-08-11
US20080065859A1 (en) 2008-03-13

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