US20060124995A1 - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Semiconductor device and manufacturing method for semiconductor device Download PDF

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US20060124995A1
US20060124995A1 US11/295,458 US29545805A US2006124995A1 US 20060124995 A1 US20060124995 A1 US 20060124995A1 US 29545805 A US29545805 A US 29545805A US 2006124995 A1 US2006124995 A1 US 2006124995A1
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gate electrode
region
semiconductor device
forming
power mosfet
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Hitoshi Ninomiya
Yoshinao Miura
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NEC Electronics Corp
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NEC Electronics Corp
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Publication of US20060124995A1 publication Critical patent/US20060124995A1/en
Priority to US12/503,297 priority Critical patent/US7919374B2/en
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method for the semiconductor device, and more specifically to a power MOSFET of a super-junction structure and a trench-gate structure.
  • Japanese unexamined patent application publication No. 2002-368221 and Japanese unexamined patent application publication No. 2002-373988 disclose a conventional vertical power MOSFET.
  • the vertical power MOSFET adopts the trench-gate structure having a gate electrode formed in a trench for lowering an on-resistance super-junction structure or super-junction structure for realizing both the low on-resistance and high breakdown voltage.
  • Japanese unexamined patent application publication No. 2002-368221 and Japanese unexamined patent application publication No. 2002-373988 disclose a conventional vertical power MOSFET.
  • the vertical power MOSFET adopts the trench-gate structure having a gate electrode formed in a trench for lowering an on-resistance super-junction structure or super-junction structure for realizing both the low on-resistance and high breakdown voltage.
  • 2002-184985 discloses the technique of improving a breakdown voltage of the element by forming the super-junction structure even around the element.
  • the super-junction structure is secured even around the element, so a depletion layer formed around the element expands to increase the breakdown voltage of the element.
  • FIG. 3A and 3B show the element structure of a conventional typical vertical power MOSFET.
  • the vertical power MOSFET has a polysilicon layer 301 for forming a gate electrode on its periphery.
  • a heat treatment step is necessary for forming the gate electrode inclusive of the polysilicon layer 301 .
  • a column region 104 is generally formed through thermal diffusion.
  • the heat treatment for the formation of the gate electrode including the polysilicon layer 301 induces the thermal diffusion of the column region 104 .
  • the element cannot be finely formed.
  • the column region 104 is formed after the formation of the gate electrode including the polysilicon layer 301 .
  • the polysilicon layer 301 and its surrounding areas ion implantation for forming the column region is hindered by the polysilicon layer 301 .
  • the column region 104 cannot be formed with sufficient depth. Therefore, the column region 104 is shallower under the polysilicon layer than other regions. That is, the uniform super-junction structure cannot be formed.
  • the depth of the column region 104 in an element active portion is different from the depth of the column region 104 in the outer peripheral portions.
  • Japanese unexamined patent application publication No. 2002-184985 discloses the structure where the column region has the uniform depth at the element active portion and the outer peripheral portion, but describes no structure for extracting a gate electrode.
  • a semiconductor device having a super-junction structure includes: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal.
  • the power MOSFET according to the present invention is thus structured, so it is unnecessary to form the polysilicon layer necessary for the conventional typical power MOSFET. That is, the column region can be formed under the same conditions at the element active portion and the outer peripheral portion. Consequently, a breakdown voltage of the element can be made higher than the conventional one.
  • FIG. 1A is a top view showing a layout of a power MOSFET according to a first embodiment of the present invention
  • FIG. 1B is a sectional view showing the structure of the power MOSFET according to the first embodiment of the present invention.
  • FIG. 2A is a top view showing a layout of a power MOSFET according to a second embodiment of the present invention.
  • FIG. 2B is a sectional view showing the structure of the power MOSFET according to the second embodiment of the present invention.
  • FIG. 3A is a top view showing a layout of a conventional typical power MOSFET.
  • FIG. 3B is a sectional view showing the structure of the conventional typical power MOSFET.
  • FIGS. 1A and 1B show an element structure of a power MOSFET according to a first embodiment of the present invention.
  • the power MOSFET according to the first embodiment is a vertical power MOSFET.
  • FIG. 1A is a top view showing a layout of the power MOSFET.
  • FIG. 1B is a sectional view taken along the line A-A′.
  • a semiconductor substrate 101 of FIG. 1B is an N+ type semiconductor substrate (of a first conductivity type) made of, for example, silicon.
  • An epitaxial layer 102 is formed over the semiconductor substrate 101 .
  • the epitaxial layer 102 is an N ⁇ type semiconductor (of the first conductivity type), for example, which serves as a drain of the vertical power MOSFET together with the semiconductor substrate 101 .
  • a base region 103 is formed on the epitaxial layer 102 .
  • the base region 103 is a P-type semiconductor region (of a second conductivity type) containing boron, for example.
  • a channel formation region is formed near a gate electrode 106 upon the operation of the vertical power MOSFET.
  • P-type semiconductor regions are formed in a columnar form to define column regions 104 .
  • the column regions 104 are the P-type semiconductor regions containing boron, for example.
  • the structure having the column regions formed in the epitaxial layer 102 is a super-junction structure.
  • a source region 105 is formed between the gate electrodes 106 above the base region 103 .
  • the source region 105 is an N+ type semiconductor region containing arsenic, for example, which serves as a source of the power MOSFET.
  • a trench is formed at a depth beyond the source region 105 and the base region 103 on the semiconductor substrate 101 .
  • a gate oxide film (not shown) is formed to cover the inner surface of the trench.
  • the gate electrode 106 is filled in the trench.
  • the gate electrode 106 is formed of, for example, polysilicon and substantially fills the opening of the trench.
  • the structure having the gate electrode filled in the trench formed on the semiconductor substrate is a trench-gate structure.
  • a given gate electrode out of the gate electrodes formed on the semiconductor substrate 101 constitutes a gate electrode extraction portion 107 .
  • the gate electrode of the gate electrode extraction portion 107 is formed with a larger width than the other gate electrodes 106 for the connection with a gate electrode plug 110 as mentioned below.
  • a LOCOS (local oxidation of silicon) region 108 is formed in a predetermined region on the epitaxial layer 102 .
  • the gate electrodes are formed into a substantially rectangular shape to form island-like element active portions. Formed in the island-like active portion are the base region 103 , the column region 104 , the source region 105 , and a source electrode plug 112 .
  • the semiconductor device of this embodiment has the plural island-like element active portions arranged in line.
  • the base region 103 and the column region 104 are formed outside of the element active portions. Further, the LOCOS regions are selectively formed for element isolation.
  • An interlayer insulation layer 109 is formed throughout the entire upper surface of the semiconductor substrate 101 including the source region 105 , the base region 103 , and the LOCOS regions 108 .
  • the interlayer insulation layer 109 is formed of, for example, BPSG (boron doped phospho-silicate glass).
  • the interlayer insulation layer 109 has plural contact holes.
  • the contact holes may be divided into two types: a gate contact hole formed above the gate electrode extraction portion 107 and a source contact hole formed above the source region 105 .
  • the gate contact hole passes through the interlayer insulating layer 109 on the gate electrode extraction portion 107 and the gate electrode extraction portion 107 is exposed on the surface.
  • the source contact hole passes through the interlayer insulating layer 109 and the source region 105 .
  • the base region 105 is exposed on the surface.
  • the conductive plugs filled in the gate contact hole and source contact hole are referred to as the gate electrode plug 110 and the source electrode plug 112 , respectively.
  • a gate wiring metal file 111 is formed on the gate electrode plug 110 and the interlayer insulating layer 109 .
  • the gate wiring metal 111 is formed by patterning a conductive layer such as an aluminum layer into a given shape.
  • the gate wiring metal 111 is connected with the gate terminal of the power MOSFET.
  • a source wiring metal 113 is formed on the source electrode plug 112 and the interlayer insulating layer 109 .
  • the source wiring metal 113 is formed by patterning a conductive layer such as an aluminum layer into a predetermined shape.
  • the source wiring metal 113 is connected with a source terminal of the power MOSFET.
  • the voltage difference between the gate electrode 106 and the source region 105 is small, so a depletion layer (positive field) is formed at the junction between the drift region 102 and the base region 103 . Further, the depletion layer is also formed at the junction between the drift region 102 and the column region 104 .
  • the column region 104 is defined by forming the P-type semiconductor into a deep columnar structure. Hence, the depletion layer is spread throughout the drift region 102 and the column region 104 . In the power MOSFET, charges are hindered from moving in the source region 105 and the drift region 102 due to the depletion layer, so no current flows to turn off the power MOSFET.
  • the column region 104 of the element active portion has the same depth as that of the column region 104 of the outer peripheral portion, and thus, charges are kept in balance between the element active portion and the outer peripheral portion. That is, the depletion layer of the uniform strength is formed at the element active portion and the outer peripheral portion.
  • a channel (negative field) is formed at the junction between the gate electrode 106 and the base region 103 .
  • charges flow between the source region 103 and the drift region 102 due to the channel, so the current flows to turn on the power MOSFET.
  • a polysilicon layer should be formed for the gate electrode. Therefore, at the time of forming the column region 104 , ions necessary for forming the column region 104 cannot be implanted up to a sufficient depth in inverse proportion to the thickness of the polysilicon layer. As a result, the column region 104 of the outer peripheral portion is shallower than the column region 104 of the element active portion. That is, a uniform super-junction structure cannot be achieved. As a result, the balance of charges between the element active portion and the outer peripheral portion is upset. That is, the thickness is not uniform in the depletion layer, so the element breaks down in the thin portion of the depletion layer. This makes it difficult to improve the breakdown voltage of the power MOSFET.
  • the gate electrode 106 is connected with the gate wiring metal 111 through the gate electrode plug 110 .
  • the power MOSFET of this embodiment dispenses with the polysilicon layer, which means that there is no thickness difference due to the polysilicon layer at the time of forming the column regions 104 .
  • the column region 104 of the element active portion has the same depth as that of the column region 104 of the outer peripheral portion. Since the column region 104 of the element active portion has the same depth as that of the column region 104 of the outer peripheral portion, charges are kept in balance between the element active portion and the outer peripheral portion.
  • the depletion layer is spread with uniform thickness in the element active portion and the outer peripheral portion, so the depletion layer is uniform in thickness.
  • the uniform depletion layer can be formed with a large thickness, so the breakdown voltage of the element improves. As a result, it is possible to improve the breakdown voltage of the power MOSFET.
  • the element breakdown voltage of the power MOSFET having the super-junction structure can be improved.
  • FIGS. 2A and 2B show the structure of a power MOSFET according to a second embodiment of the present invention.
  • the power MOSFET of the second embodiment is a vertical power MOSFET.
  • FIG. 2A is a top view showing the layout of the power MOSFET according to the second embodiment.
  • FIG. 2B is a sectional view taken along the line A-A′ of FIG. 2A .
  • the structure of the power MOSFET of the second embodiment is basically the same as that of the first embodiment.
  • the power MOSFET according to the first embodiment differs from the power MOSFET according to the second embodiment only in terms of the polysilicon layer 201 between the LOCOS region 108 and the interlayer insulating film 109 .
  • the power MOSFET of the second embodiment has a polysilicon layer 201 formed between the LOCOS region 108 and the interlayer insulating film 109 , while the power MOSFET of the first embodiment does not have the polysilicon layer 201 .
  • the polysilicon layer 201 forms a cathode region of a gate protective Zener diode formed on the interlayer insulating film.
  • the operation of the power MOSFET is described according to the second embodiment.
  • the structure of the power MOSFET is basically the same as that of the first embodiment. Therefore, the transistor operation of the power MOSFET of the second embodiment is the same as that of the power MOSFET of the first embodiment.
  • the polysilicon layer 201 formed only in the power MOSFET of the second embodiment forms a cathode region of the gate protective Zener diode between the gate terminal and the source terminal. That is, when abnormal voltage or current is applied/supplied between the gate terminal and the source terminal of the power MOSFET owing to the electrostatic disgorge, the gate protective Zener diode functions to keep the voltage difference between the gate and the source from reaching or exceeding the predetermined voltage. In addition, upon the electrostatic discharge, current as well as a voltage is applied to the gate terminal. The gate protective Zener diode also functions as a bypass circuit for the circuit. In other words, the gate protective Zener diode prevents supply of an excessive voltage or current to the gate terminal so as not to break the gate terminal.
  • the breakdown voltage can be increased similar to the power MOSFET of the first embodiment.
  • the polysilicon layer 201 can be formed between the LOCOS region 108 and the interlayer insulating film 109 of the element, so the gate protective Zener diode can be manufactured concurrently with the element.
  • the element resistance to the abnormal input to the gate terminal can be obtained.
  • the polysilicon region 201 is formed of the same polysilicon as the gate electrode 106 , and thus can be formed in the same step as the gate electrode 106 .
  • the gate electrode can be extracted from an extraction portion at plural portions of the gate electrode of the element active portion.

Abstract

A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and a manufacturing method for the semiconductor device, and more specifically to a power MOSFET of a super-junction structure and a trench-gate structure.
  • 2. Description of Related Art
  • In recent years, power components such as a power MOSFET (metal oxide semiconductor field effect transistor) have required a higher element breakdown voltage. A vertical power MOSFET has been widely used out as the power MOSFET. Japanese unexamined patent application publication No. 2002-368221 and Japanese unexamined patent application publication No. 2002-373988 disclose a conventional vertical power MOSFET. Up to now, the vertical power MOSFET adopts the trench-gate structure having a gate electrode formed in a trench for lowering an on-resistance super-junction structure or super-junction structure for realizing both the low on-resistance and high breakdown voltage. Further, Japanese unexamined patent application publication No. 2002-184985 discloses the technique of improving a breakdown voltage of the element by forming the super-junction structure even around the element. The super-junction structure is secured even around the element, so a depletion layer formed around the element expands to increase the breakdown voltage of the element.
  • FIG. 3A and 3B show the element structure of a conventional typical vertical power MOSFET. In general, the vertical power MOSFET has a polysilicon layer 301 for forming a gate electrode on its periphery. A heat treatment step is necessary for forming the gate electrode inclusive of the polysilicon layer 301. A column region 104 is generally formed through thermal diffusion. Thus, in the case where the column region 104 is formed before the formation of the gate electrode including the polysilicon layer 301, the heat treatment for the formation of the gate electrode including the polysilicon layer 301 induces the thermal diffusion of the column region 104. As a result, the element cannot be finely formed. In order to prevent the thermal diffusion of the column region 104 from proceeding, the column region 104 is formed after the formation of the gate electrode including the polysilicon layer 301. In this case, in the polysilicon layer 301 and its surrounding areas, ion implantation for forming the column region is hindered by the polysilicon layer 301. Hence, the column region 104 cannot be formed with sufficient depth. Therefore, the column region 104 is shallower under the polysilicon layer than other regions. That is, the uniform super-junction structure cannot be formed. The depth of the column region 104 in an element active portion is different from the depth of the column region 104 in the outer peripheral portions. As a result, the balance of charges between the element active portion and the outer peripheral portion is upset, making it difficult to improve the breakdown voltage of the element. Japanese unexamined patent application publication No. 2002-184985 discloses the structure where the column region has the uniform depth at the element active portion and the outer peripheral portion, but describes no structure for extracting a gate electrode.
    • SUMMARY OF THE INVENTION
  • A semiconductor device having a super-junction structure according to an aspect of the invention includes: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal.
  • The power MOSFET according to the present invention is thus structured, so it is unnecessary to form the polysilicon layer necessary for the conventional typical power MOSFET. That is, the column region can be formed under the same conditions at the element active portion and the outer peripheral portion. Consequently, a breakdown voltage of the element can be made higher than the conventional one.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1A is a top view showing a layout of a power MOSFET according to a first embodiment of the present invention;
  • FIG. 1B is a sectional view showing the structure of the power MOSFET according to the first embodiment of the present invention;
  • FIG. 2A is a top view showing a layout of a power MOSFET according to a second embodiment of the present invention;
  • FIG. 2B is a sectional view showing the structure of the power MOSFET according to the second embodiment of the present invention;
  • FIG. 3A is a top view showing a layout of a conventional typical power MOSFET; and
  • FIG. 3B is a sectional view showing the structure of the conventional typical power MOSFET.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.
    • First Embodiment
  • FIGS. 1A and 1B show an element structure of a power MOSFET according to a first embodiment of the present invention. The power MOSFET according to the first embodiment is a vertical power MOSFET. FIG. 1A is a top view showing a layout of the power MOSFET. FIG. 1B is a sectional view taken along the line A-A′. A semiconductor substrate 101 of FIG. 1B is an N+ type semiconductor substrate (of a first conductivity type) made of, for example, silicon. An epitaxial layer 102 is formed over the semiconductor substrate 101. The epitaxial layer 102 is an N− type semiconductor (of the first conductivity type), for example, which serves as a drain of the vertical power MOSFET together with the semiconductor substrate 101. A base region 103 is formed on the epitaxial layer 102. The base region 103 is a P-type semiconductor region (of a second conductivity type) containing boron, for example. In the base region, a channel formation region is formed near a gate electrode 106 upon the operation of the vertical power MOSFET. Further, P-type semiconductor regions are formed in a columnar form to define column regions 104. The column regions 104 are the P-type semiconductor regions containing boron, for example. The structure having the column regions formed in the epitaxial layer 102 is a super-junction structure.
  • A source region 105 is formed between the gate electrodes 106 above the base region 103. The source region 105 is an N+ type semiconductor region containing arsenic, for example, which serves as a source of the power MOSFET. A trench is formed at a depth beyond the source region 105 and the base region 103 on the semiconductor substrate 101. A gate oxide film (not shown) is formed to cover the inner surface of the trench. Further, the gate electrode 106 is filled in the trench. The gate electrode 106 is formed of, for example, polysilicon and substantially fills the opening of the trench. The structure having the gate electrode filled in the trench formed on the semiconductor substrate is a trench-gate structure. A given gate electrode out of the gate electrodes formed on the semiconductor substrate 101 constitutes a gate electrode extraction portion 107. The gate electrode of the gate electrode extraction portion 107 is formed with a larger width than the other gate electrodes 106 for the connection with a gate electrode plug 110 as mentioned below.
  • A LOCOS (local oxidation of silicon) region 108 is formed in a predetermined region on the epitaxial layer 102.
  • As shown in the layout of the power MOSFET as viewed from the above in FIG. 1A, the gate electrodes are formed into a substantially rectangular shape to form island-like element active portions. Formed in the island-like active portion are the base region 103, the column region 104, the source region 105, and a source electrode plug 112. The semiconductor device of this embodiment has the plural island-like element active portions arranged in line. The base region 103 and the column region 104 are formed outside of the element active portions. Further, the LOCOS regions are selectively formed for element isolation.
  • An interlayer insulation layer 109 is formed throughout the entire upper surface of the semiconductor substrate 101 including the source region 105, the base region 103, and the LOCOS regions 108. The interlayer insulation layer 109 is formed of, for example, BPSG (boron doped phospho-silicate glass).
  • The interlayer insulation layer 109 has plural contact holes. The contact holes may be divided into two types: a gate contact hole formed above the gate electrode extraction portion 107 and a source contact hole formed above the source region 105. The gate contact hole passes through the interlayer insulating layer 109 on the gate electrode extraction portion 107 and the gate electrode extraction portion 107 is exposed on the surface. The source contact hole passes through the interlayer insulating layer 109 and the source region 105. The base region 105 is exposed on the surface.
  • Conductive plugs formed of a conductor (tungsten or titanium) fill in the gate contact hole and source contact hole. The conductive plugs filled in the gate contact hole and source contact hole are referred to as the gate electrode plug 110 and the source electrode plug 112, respectively.
  • A gate wiring metal file 111 is formed on the gate electrode plug 110 and the interlayer insulating layer 109. The gate wiring metal 111 is formed by patterning a conductive layer such as an aluminum layer into a given shape. The gate wiring metal 111 is connected with the gate terminal of the power MOSFET.
  • A source wiring metal 113 is formed on the source electrode plug 112 and the interlayer insulating layer 109. The source wiring metal 113 is formed by patterning a conductive layer such as an aluminum layer into a predetermined shape. The source wiring metal 113 is connected with a source terminal of the power MOSFET.
  • An operation of the power MOSFET of the first embodiment is described. First, a description is give of the case where a voltage difference between the gate electrode 106 and the source region 105 of the power MOSFET is not higher than a threshold voltage of the power MOSFET, that is, the power MOSFET is turned off. Since the power MOSFET is turned off, there is a large voltage difference between the source region 105 and a drift region (epitaxial layer 102).
  • The voltage difference between the gate electrode 106 and the source region 105 is small, so a depletion layer (positive field) is formed at the junction between the drift region 102 and the base region 103. Further, the depletion layer is also formed at the junction between the drift region 102 and the column region 104. The column region 104 is defined by forming the P-type semiconductor into a deep columnar structure. Hence, the depletion layer is spread throughout the drift region 102 and the column region 104. In the power MOSFET, charges are hindered from moving in the source region 105 and the drift region 102 due to the depletion layer, so no current flows to turn off the power MOSFET.
  • In addition, the column region 104 of the element active portion has the same depth as that of the column region 104 of the outer peripheral portion, and thus, charges are kept in balance between the element active portion and the outer peripheral portion. That is, the depletion layer of the uniform strength is formed at the element active portion and the outer peripheral portion.
  • Next, a description is given of the case where the voltage difference between the gate electrode 106 and the source region 105 of the power MOSFET is not less than the threshold voltage of the power MOSFET, that is, the power MOSFET is turned on. At this time, the power MOSFET is turned on, so the voltage difference between the source region 105 and the drift region 102 is small.
  • Since the high voltage is applied to the gate electrode 106, a channel (negative field) is formed at the junction between the gate electrode 106 and the base region 103. In the power MOSFET, charges flow between the source region 103 and the drift region 102 due to the channel, so the current flows to turn on the power MOSFET.
  • In the structure of the conventional power MOSFET, a polysilicon layer should be formed for the gate electrode. Therefore, at the time of forming the column region 104, ions necessary for forming the column region 104 cannot be implanted up to a sufficient depth in inverse proportion to the thickness of the polysilicon layer. As a result, the column region 104 of the outer peripheral portion is shallower than the column region 104 of the element active portion. That is, a uniform super-junction structure cannot be achieved. As a result, the balance of charges between the element active portion and the outer peripheral portion is upset. That is, the thickness is not uniform in the depletion layer, so the element breaks down in the thin portion of the depletion layer. This makes it difficult to improve the breakdown voltage of the power MOSFET.
  • However, in the power MOSFET of this embodiment, the gate electrode 106 is connected with the gate wiring metal 111 through the gate electrode plug 110. Hence, the power MOSFET of this embodiment dispenses with the polysilicon layer, which means that there is no thickness difference due to the polysilicon layer at the time of forming the column regions 104. Accordingly, the column region 104 of the element active portion has the same depth as that of the column region 104 of the outer peripheral portion. Since the column region 104 of the element active portion has the same depth as that of the column region 104 of the outer peripheral portion, charges are kept in balance between the element active portion and the outer peripheral portion. Thus, the depletion layer is spread with uniform thickness in the element active portion and the outer peripheral portion, so the depletion layer is uniform in thickness. In other words, the uniform depletion layer can be formed with a large thickness, so the breakdown voltage of the element improves. As a result, it is possible to improve the breakdown voltage of the power MOSFET.
  • According to the structure of the power MOSFET of the first embodiment, the element breakdown voltage of the power MOSFET having the super-junction structure can be improved.
    • Second Embodiment
  • FIGS. 2A and 2B show the structure of a power MOSFET according to a second embodiment of the present invention. The power MOSFET of the second embodiment is a vertical power MOSFET. FIG. 2A is a top view showing the layout of the power MOSFET according to the second embodiment. Further, FIG. 2B is a sectional view taken along the line A-A′ of FIG. 2A. As apparent from the sectional structure of FIG. 2B, the structure of the power MOSFET of the second embodiment is basically the same as that of the first embodiment. The power MOSFET according to the first embodiment differs from the power MOSFET according to the second embodiment only in terms of the polysilicon layer 201 between the LOCOS region 108 and the interlayer insulating film 109. The power MOSFET of the second embodiment has a polysilicon layer 201 formed between the LOCOS region 108 and the interlayer insulating film 109, while the power MOSFET of the first embodiment does not have the polysilicon layer 201. The polysilicon layer 201 forms a cathode region of a gate protective Zener diode formed on the interlayer insulating film.
  • The operation of the power MOSFET is described according to the second embodiment. The structure of the power MOSFET is basically the same as that of the first embodiment. Therefore, the transistor operation of the power MOSFET of the second embodiment is the same as that of the power MOSFET of the first embodiment.
  • The polysilicon layer 201 formed only in the power MOSFET of the second embodiment forms a cathode region of the gate protective Zener diode between the gate terminal and the source terminal. That is, when abnormal voltage or current is applied/supplied between the gate terminal and the source terminal of the power MOSFET owing to the electrostatic disgorge, the gate protective Zener diode functions to keep the voltage difference between the gate and the source from reaching or exceeding the predetermined voltage. In addition, upon the electrostatic discharge, current as well as a voltage is applied to the gate terminal. The gate protective Zener diode also functions as a bypass circuit for the circuit. In other words, the gate protective Zener diode prevents supply of an excessive voltage or current to the gate terminal so as not to break the gate terminal.
  • According to the power MOSFET of the second embodiment, the breakdown voltage can be increased similar to the power MOSFET of the first embodiment. In addition, the polysilicon layer 201 can be formed between the LOCOS region 108 and the interlayer insulating film 109 of the element, so the gate protective Zener diode can be manufactured concurrently with the element. Thus, the element resistance to the abnormal input to the gate terminal can be obtained.
  • Further, the polysilicon region 201 is formed of the same polysilicon as the gate electrode 106, and thus can be formed in the same step as the gate electrode 106.
  • The present invention is not limited to the above embodiments but allows various modifications. For example, the gate electrode can be extracted from an extraction portion at plural portions of the gate electrode of the element active portion.
  • It is apparent that the present invention is not limited to the above embodiment that may be modified and changed without departing from the scope and spirit of the invention.

Claims (12)

1. A semiconductor device having a super-junction structure, comprising:
a gate electrode filled in a trench formed on a semiconductor substrate;
a gate wiring metal forming a surface layer; and
a gate electrode plug connecting between the gate electrode and the gate wiring metal.
2. The semiconductor device according to claim 1, wherein a column region of an element active portion as an active portion of an element has substantially the same depth as a column region of an outer peripheral portion as an outer periphery of the element active portion.
3. The semiconductor device according to claim 2, further comprising:
an element isolation region for element isolation;
an interlayer insulating layer formed on the element isolation region; and
a polysilicon layer formed between the element isolation region and the interlayer insulating layer.
4. The semiconductor device according to claim 3, wherein the polysilicon layer is used as a Zener diode.
5. The semiconductor device according to claim 4, wherein the gate electrode filled in the trench formed on the semiconductor substrate is made of the same polysilicon as the polysilicon layer.
6. The semiconductor device according to claim 1, further comprising:
an element isolation region for element isolation;
an interlayer insulating layer formed on the element isolation region; and
a polysilicon layer formed between the element isolation region and the interlayer insulating layer.
7. The semiconductor device according to claim 6, wherein the polysilicon layer is used as a Zener diode.
8. The semiconductor device according to claim 7, wherein the gate electrode filled in the trench formed on the semiconductor substrate is made of the same polysilicon as the polysilicon layer.
9. A manufacturing method for a semiconductor device, comprising:
forming an epitaxial layer of a first conductivity type on a semiconductor substrate of the first conductivity type;
forming an element isolation region in a predetermined region on the epitaxial layer;
forming a gate electrode filled in a trench formed on the epitaxial layer;
forming a column region of a second conductivity type in the epitaxial layer;
forming a base region of a second conductivity type on the epitaxial layer;
forming a source region of the first conductivity type in a predetermined region on the base region;
forming an interlayer insulating film throughout an entire surface of the semiconductor substrate;
forming a contact hole passing through the interlayer insulating film to expose the gate electrode on a surface;
forming a gate electrode plug using a conductor filled in the contact hole; and
forming a gate wiring metal connected with the gate wiring metal on the interlayer insulating film.
10. The manufacturing method for a semiconductor device according to claim 9, wherein a polysilicon layer is formed on the element isolation region concurrently with the formation of the gate electrode.
11. The manufacturing method for a semiconductor device according to claim 10, wherein a portion of the gate electrode serving as an electrode extraction portion is formed with a larger width than a width of the other portion of the gate electrode.
12. The manufacturing method for a semiconductor device according to claim 9, wherein a portion of the gate electrode serving as an electrode extraction portion is formed with a larger width than a width of the other portion of the gate electrode.
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