US20060118922A1 - Selectively growing a polymeric material on a semiconductor substrate - Google Patents

Selectively growing a polymeric material on a semiconductor substrate Download PDF

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US20060118922A1
US20060118922A1 US11/325,874 US32587406A US2006118922A1 US 20060118922 A1 US20060118922 A1 US 20060118922A1 US 32587406 A US32587406 A US 32587406A US 2006118922 A1 US2006118922 A1 US 2006118922A1
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region
regions
exposed
polymer
selectively
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US11/325,874
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Michael Goodner
Grant Kloster
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/165—Monolayers, e.g. Langmuir-Blodgett
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Abstract

A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.

Description

  • This application is a divisional of U.S. patent application Ser. No. 10/284,722, filed on Oct. 31, 2002.
    • BACKGROUND
  • This invention relates generally to processes for manufacturing semiconductor integrated circuits.
  • In some instances during the manufacturing process, a semiconductor integrated circuit may have two exposed surface regions. The two surface regions may have different characteristics. It may be desirable to form materials onto one of the regions and not the other of them.
  • Typically, providing a selective coating on a substrate involves depositing a polymeric coating on the entire substrate and selectively removing the polymeric coating, using standard lithographic and etching patterning, from the regions where the coating is not desired. However, these techniques require tight alignment to leave the coating only on the desired portions of the substrate.
  • Thus, there is a need for better ways to selectively form materials on semiconductor structures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic depiction of a precursor material in accordance with one embodiment of the present invention;
  • FIG. 2 is a schematic depiction of a subsequent precursor material in accordance with one embodiment of the present invention;
  • FIG. 3 is a schematic representation of a subsequent precursor material in accordance with one embodiment of the present invention;
  • FIG. 4 is a schematic depiction of a grafted polymer in accordance with one embodiment of the present invention;
  • FIG. 5 is a schematic depiction of a precursor material in accordance with another embodiment of the present invention;
  • FIG. 6 is a schematic depiction of a grafted polymer in accordance with one embodiment of the present invention;
  • FIG. 7 is an enlarged cross-sectional view of one embodiment of the present invention; and
  • FIG. 8 is an enlarged cross-sectional view of the embodiment shown in FIG. 7 at a subsequent stage of manufacture.
    • DETAILED DESCRIPTION
  • In accordance with various embodiments of the present invention, a semiconductor wafer may include a semiconductor substrate having a dielectric material 10, such as an interlayer dielectric (ILD), formed thereon. The material 10 may be exposed on an upper surface. Also exposed thereon is a disparate material 12, such as a metal material, as indicated in FIG. 1. Thus, it may be desirable to have a polymer formed selectively only over the material 10 and not over the material 12.
  • Through surface grafting, polymers may be caused to attach to materials with abstractable hydrogen. These materials with easily abstractable hydrogen may be known as proton donors and examples include organic materials or materials with organic moieties. Conversely, materials, such as a metal, have no such easily abstractable hydrogen and, therefore, will not be subject to induced photografting or polymerization.
  • As a result, the polymerization can be caused to occur selectively on the surface where easily abstractable hydrogen is available. In regions without such abstractable hydrogen, no such polymerization will occur. As a result, the polymer may be formed selectively on the surface in some regions and not in others. In some embodiments this may avoid unnecessary photo etching and masking steps, decreasing the cost of the semiconductor processing.
  • A variety of techniques may be utilized to induce surface grafting and polymerization. For example, photo induced graft polymerization may be achieved using benzophenone moieties. Other examples include radical photopolymerization, hydrogen abstraction on organic surfaces with molecules other than benzophenone, cationic and anionic polymerizations, and azide functionalization, to mention a few examples. In general, it is desirable to induce polymerization on regions that are polymerizable while avoiding polymerization on regions, such as metals, that are not polymerizable.
  • In accordance with one embodiment of the present invention, photo induced graft polymerization may be implemented using benzophenone. Referring to FIG. 1, a material 10, that has abstactable hydrogen, may have a surface chemistry including hydrogen (H), and organic molecules, in any of a variety of forms. The material 10 may be coated with a solution of benzophenone and irradiated using ultraviolet radiation at 340 nanometers, in accordance with one embodiment of the present invention. Other wavelengths may also be used such as 365 nm. Ultraviolet radiation breaks down the double bond between the carbon and the oxygen forming a benzophenone derivative reactable with a variety of other organic moieties. Thus, as shown in FIG. 2, as a result of the breakdown of the benzophenone solution, ketal moieties 16 may be attached in place of some of the hydrogen moieties (H) previously present on the surface of the material 10.
  • Advantageously, the benzophenone solution is provided in a solvent with poor proton donor activity such as benzene. In addition, the solvent is advantageously transparent at the illumination intensities that are utilized.
  • Of course, the material 12 surface does not react with the benzophenone via the ultraviolet induced hydrogen abstraction mechanism. Only the organic materials or materials with an abstractable hydrogen are functionalized. The wafer may then be washed with an appropriate rinse solution, such as acetone or methanol, to mention a few examples, to remove excess benzophenone.
  • Next, as shown in FIGS. 3 and 4, a coating material that is susceptible to free radical polymerization is coated over the wafer and the wafer is, again, exposed to ultraviolet light. The free radical benzophenone ketal moieties 16 then serve as a surface photoinitiator, causing in situ polymerization of the coating material. The coating material may include, as examples, simple vinyl monomers such as methyl methacrylate or vinyl functionalized engineering polymers, such as an acrylate endcapped polyimide, such as Amoco Ultradel 7501. The methyl methacrylate may form poly(methyl methacrylate).
  • A solvent rinse after exposure removes any unreacted coating material. A polymer coating 14 is selectively grown on the material 10 as shown in FIG. 4.
  • In general, a compound having a double bond that is susceptible to polymerization, such as free radical polymerization, as an example, may be utilized to form the polymer coating 14 and to replace the ketal moieties 16 shown in FIG. 3.
  • As another example, shown in FIGS. 5 and 6, a single step method may be utilized to selectively grow polymer coatings selectively on the material 10. The material 10 is functionalized with moieties 18, such as benzophenone or azide moieties, coated on the wafer, and patterned with metal lines 12 a to form a mixed substrate as shown in FIG. 5.
  • The wafer may then be coated with a precursor material and exposed to ultraviolet light. The precursor material may be, for example, vinyl monomers or vinyl functionalized engineering polymers, as described previously. The polymerization may occur in the same manner to grow the polymeric coating 20 selectively on the organic portions of the exposed substrate as shown in FIG. 6.
  • Alternatively, the precursor material may consist of an engineering polymer that has abstractable hydrogen. The coating may be grown through hydrogen abstraction by benzophenone moieties. A solvent may be utilized to remove unreactive material, leaving the polymer coating 20 over the organic portions of the substrate, as shown in FIG. 6.
  • As an example of an application of the technology described herein, an air gap interconnect structure may use the selective formation of polymers on an exposed surface. In some embodiments it is possible to create an unlanded via. A landed via is a via which has a bottom end completely adjacent to a metal structure below. An unlanded via is a via with the bottom end only partially adjacent to underlying metal structures, allowing possible overlap onto underlying dielectric structures such as ILD or sacrificial material. Unlanded vias are preferred for some integrated circuit manufacture design rules, as they allow relaxed alignments and tolerances for expensive processing steps such as photolithography. However, in some processing schemes, landed vias are necessary to provide a feasible fabrication technique.
  • In the case of air gap structures, some processing schemes require landed vias, as the material surrounding the metal structures on the substrate is air, after a sacrificial material has been removed to form the air gap; etching of subsequent unlanded via holes would punch through the overlying dielectric material, allowing subsequently applied materials to fill the air gap. Process flows using patterned etch stop materials avoid punch-through, but the etch stop must be perfectly aligned to the underlying metal structures.
  • Referring to FIG. 7, a semiconductor substrate 100 may be covered by a porous hard mask 101. A via level dielectric 102 may be positioned over the hard mask 101 and a sacrificial material 103, such as a thermally decomposing layer, may be provided over the dielectric 102. Formed through the layers 101, 102, and 103 are a plurality of L-shaped metal lines, vias, or feature 104. Over the metal feature 104 and the sacrificial material 103, the polymer material 105 may be selectively deposited.
  • The material 105 may be deposited over the dielectric 103 and not over the metal feature 104 using the techniques described herein. Subsequently, the porous hard mask 101 may be formed over the metal via 104 and the surface polymerized etch stop material 105.
  • As shown in FIG. 8, a plurality of layers may be formed over the etch stop material 105. Another via level dielectric 102 a and an additional sacrificial material 103 a may be formed. Then a metal line and via 104 a may be formed completely through the upper layers 103 a, 102 a, 101 a, and 105 to connect to the metal line 104 in the lower layers. In this case, the surface polymerized etch stop material 105 enables the formation of an unlanded via 104 a.
  • In one embodiment, after the layer 102 a is formed, an opening may be etched using suitable masking techniques. The opening would extend straight down and into the region 103 but for the imposition of the etch stop material 105. Thus, the structure may be formed after the sacrificial layer 103 has been removed (as illustrated in FIG. 8) without being affected by the etch, due to the protection afforded by the etch stop material 105. Since the etch stop material 105 can be formed selectively over the non-metallic surfaces using the techniques described herein, it is possible to easily provide the needed masking to enable unlanded vias to be formed.
  • While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (8)

1. A semiconductor structure comprising:
a surface including an exposed polymerizable region and an exposed unpolymerizable region; and
a polymer selectively attached to said polymerizable region to form a surface coating that selectively covers said polymerizable region.
2. The structure of claim 1 wherein said unpolymerizable region is metal.
3. The structure of claim 1 wherein said polymerizable region is a dielectric.
4. The structure of claim 1 wherein said polymer is derived from benzophenone.
5. A semiconductor structure comprising:
a surface including an exposed region with extractable hydrogen and an exposed region without extractable hydrogen; and
a polymer selectively attached to said exposed region with extractable hydrogen to form a surface coating that selectively covers said exposed region with extractable hydrogen.
6. The structure of claim 5 wherein said surface includes a metal region that is without extractable hydrogen.
7. The structure of claim 1 wherein said region with extractable hydrogen is a dielectric.
8. The structure of claim 5 wherein said polymer is derived from benzophenone.
US11/325,874 2002-10-31 2006-01-05 Selectively growing a polymeric material on a semiconductor substrate Abandoned US20060118922A1 (en)

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Publication number Priority date Publication date Assignee Title
US7238604B2 (en) * 2003-04-24 2007-07-03 Intel Corporation Forming thin hard mask over air gap or porous dielectric
DE602005023925D1 (en) * 2004-03-25 2010-11-18 Fujifilm Corp Method for producing a pattern and a conductive pattern
US7071091B2 (en) * 2004-04-20 2006-07-04 Intel Corporation Method of forming air gaps in a dielectric material using a sacrificial film
US20080014530A1 (en) * 2004-05-31 2008-01-17 Fujifilm Corporation Graft Pattern-Forming Method, Graft Pattern Material, Lithography Method, Conductive Pattern - Forming Method, Conductive Pattern, Color Filter Producing Method, Color Filter, and Mircrolens Producing Method
CN100544551C (en) * 2004-08-26 2009-09-23 富士胶片株式会社 The manufacture method of conductive pattern material
US8154121B2 (en) * 2008-02-26 2012-04-10 Intel Corporation Polymer interlayer dielectric and passivation materials for a microelectronic device
CN106206252B (en) * 2016-06-30 2019-06-21 上海交通大学 In the method for surface of semiconductor substrates one-step method chemical graft organic film
US11502001B2 (en) * 2018-10-31 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned vias
KR20210049604A (en) 2019-10-25 2021-05-06 삼성전자주식회사 Integrated circuit device and method of manufacturing the same
WO2023190750A1 (en) * 2022-03-31 2023-10-05 日産化学株式会社 Polymer film-forming composition and selective polymer film-forming method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077085A (en) * 1987-03-06 1991-12-31 Schnur Joel M High resolution metal patterning of ultra-thin films on solid substrates
US5948232A (en) * 1995-06-19 1999-09-07 Lynntech, Inc. Method of manufacturing passive elements using conductive polypyrrole formulations
US6156393A (en) * 1997-11-12 2000-12-05 John C. Polanyi Method of molecular-scale pattern imprinting at surfaces
US6200646B1 (en) * 1999-08-25 2001-03-13 Spectra Group Limited, Inc. Method for forming polymeric patterns, relief images and colored polymeric bodies using digital light processing technology

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670286B1 (en) * 2002-02-13 2003-12-30 The Regents Of The University Of California Photopolymerization-based fabrication of chemical sensing films

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077085A (en) * 1987-03-06 1991-12-31 Schnur Joel M High resolution metal patterning of ultra-thin films on solid substrates
US5948232A (en) * 1995-06-19 1999-09-07 Lynntech, Inc. Method of manufacturing passive elements using conductive polypyrrole formulations
US6156393A (en) * 1997-11-12 2000-12-05 John C. Polanyi Method of molecular-scale pattern imprinting at surfaces
US6200646B1 (en) * 1999-08-25 2001-03-13 Spectra Group Limited, Inc. Method for forming polymeric patterns, relief images and colored polymeric bodies using digital light processing technology

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