US20060097345A1 - Gate dielectric antifuse circuits and methods for operating same - Google Patents
Gate dielectric antifuse circuits and methods for operating same Download PDFInfo
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- US20060097345A1 US20060097345A1 US11/292,653 US29265305A US2006097345A1 US 20060097345 A1 US20060097345 A1 US 20060097345A1 US 29265305 A US29265305 A US 29265305A US 2006097345 A1 US2006097345 A1 US 2006097345A1
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims description 142
- 239000000758 substrate Substances 0.000 claims description 105
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 41
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 230000008878 coupling Effects 0.000 claims description 31
- 238000010168 coupling process Methods 0.000 claims description 31
- 238000005859 coupling reaction Methods 0.000 claims description 31
- 125000001475 halogen functional group Chemical group 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 230000000630 rising effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 23
- 229910021332 silicide Inorganic materials 0.000 description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 20
- 229910021341 titanium silicide Inorganic materials 0.000 description 20
- 239000007943 implant Substances 0.000 description 19
- 239000012212 insulator Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 239000010941 cobalt Substances 0.000 description 10
- 229910017052 cobalt Inorganic materials 0.000 description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 10
- PWPJGUXAGUPAHP-UHFFFAOYSA-N lufenuron Chemical compound C1=C(Cl)C(OC(F)(F)C(C(F)(F)F)F)=CC(Cl)=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F PWPJGUXAGUPAHP-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000000717 retained effect Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 230000002441 reversible effect Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000000700 radioactive tracer Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the present invention relates generally to integrated circuits, and more particularly, to antifuse circuits and methods for operating them.
- Integrated circuits are interconnected networks of electrical components fabricated on a common foundation called a substrate.
- the electrical components are typically fabricated on a wafer of semiconductor material that serves as a substrate.
- Various fabrication techniques such as layering, doping, masking, and etching, are used to build millions of resistors, transistors, and other electrical components on the wafer.
- the components are then wired together, or interconnected, to define a specific electrical circuit, such as a processor or a memory device.
- Fusible elements are employed in integrated circuits to permit changes in the configuration of the integrated circuits after fabrication. For example, fusible elements may be used to replace defective circuits with redundant circuits. Memory devices are typically fabricated with redundant memory cells. The redundant memory cells may be enabled with fusible elements after fabrication to replace defective memory cells found during a test of fabricated memory devices. Fusible elements are also used to customize the configuration of a generic integrated circuit after it is fabricated, or to identify an integrated circuit.
- the polysilicon fuse comprises a polysilicon conductor fabricated to conduct electrical current on an integrated circuit. A portion of the polysilicon fuse may be evaporated or opened by a laser beam to create an open circuit between terminals of the polysilicon fuse. The laser beam may be used to open selected polysilicon fuses in an integrated circuit to change its configuration.
- the use of polysilicon fuses is attended by several disadvantages. Polysilicon fuses must be spaced apart from each other in an integrated circuit such that when one of them is being opened by a laser beam the other polysilicon fuses are not damaged. A bank of polysilicon fuses therefore occupies a substantial area of an integrated circuit. In addition, polysilicon fuses cannot be opened once an integrated circuit is placed in an integrated circuit package, or is encapsulated in any manner.
- An antifuse comprises two conductive terminals separated by an insulator or a dielectric, and is fabricated as an open circuit. The antifuse is programmed by applying a high voltage across its terminals to rupture the insulator and form an electrical path between the terminals.
- Antifuses have several advantages that are not available with fuses.
- a bank of antifuses takes up much less area of an integrated circuit because they are programmed by a voltage difference that can be supplied on wires connected to the terminals of each of the antifuses.
- the antifuses may be placed close together in the bank, and adjacent antifuses are not at risk when one is being programmed.
- Antifuses may also be programmed after an integrated circuit is placed in an integrated circuit package, or encapsulated, by applying appropriate signals to pins of the package. This is a significant advantage for several reasons.
- an integrated circuit may be tested after it is in a package, and may then be repaired by replacing defective circuits with redundant circuits by programming selected antifuses.
- a generic integrated circuit may be tested and placed in a package before it is configured to meet the specifications of a customer. This reduces the delay between a customer order and shipment.
- the use of antifuses to customize generic integrated circuits also improves the production yield for integrated circuits because the same generic integrated circuit may be produced to meet the needs of a wide variety of
- an external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode.
- An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse.
- the program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed.
- the program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor.
- a read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode.
- the common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit.
- the common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode.
- the read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode.
- a floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.
- the embodiments of the present invention support the programming and reading of antifuses in an integrated circuit, and facilitate all the advantages associated with the use of antifuses in integrated circuits. Other advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description.
- FIG. 1 is a cross-sectional view of an antifuse according to an embodiment of the present invention.
- FIG. 1A is a cross-sectional view of an antifuse according to an embodiment of the present invention.
- FIG. 1B is a cross-sectional view of an antifuse according to an embodiment of the present invention.
- FIG. 2 is a cross-sectional view of an antifuse according to an embodiment of the present invention.
- FIG. 2A is a cross-sectional view of an antifuse according to an embodiment of the present invention.
- FIG. 3 is an electrical schematic diagram of a portion of an integrated circuit according to an embodiment of the present invention.
- FIG. 4 is an electrical schematic diagram of an antifuse bank according to an embodiment of the present invention.
- FIG. 5 is a block diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.
- FIG. 7 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.
- FIG. 8 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.
- FIG. 8A is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.
- FIG. 9 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.
- FIG. 10 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 11 is a cross-sectional view of an n-channel transistor according to an embodiment of the present invention.
- FIG. 12 is a cross-sectional view of a diode according to an embodiment of the present invention.
- FIG. 13 is a cross-sectional view of a diode according to an embodiment of the present invention.
- FIG. 14 is a cross-sectional view of a diode according to an embodiment of the present invention.
- FIG. 15 is a cross-sectional view of a diode according to an embodiment of the present invention.
- FIG. 16 is a cross-sectional view of a diode according to an embodiment of the present invention.
- FIG. 17 is a cross-sectional view of a p-channel transistor according to an embodiment of the present invention.
- FIG. 18 is an electrical schematic diagram of an integrated circuit with a common bus line driver circuit according to an embodiment of the present invention.
- FIG. 19 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 20 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 21 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 22 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 23 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 24 is an electrical schematic diagram of an integrated circuit with a common bus line driver circuit according to an embodiment of the present invention.
- FIG. 25 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 26 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 27 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.
- FIG. 28 is a block diagram of a static random access memory device according to an embodiment of the present invention.
- FIG. 29 is an electrical schematic diagram of an integrated circuit package according to an embodiment of the present invention.
- FIG. 30 is a block diagram of an information-handling system according to an embodiment of the present invention.
- wafer and substrate may be used in the following description and include any structure having an exposed surface with which to form an integrated circuit (IC) according to embodiments of the present invention.
- substrate is understood to include semiconductor wafers.
- substrate is also used to refer to semiconductor structures during fabrication, and may include other layers that have been fabricated thereupon.
- substrate includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor, or semiconductor layers supported by an insulator, as well as other semiconductor structures well known to one skilled in the art.
- insulator is defined to include any material that is less electrically conductive than materials generally referred to as conductors by those skilled in the art.
- horizontal as used in this application is defined as a plane substantially parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate.
- vertical refers to a direction substantially perpendicular to the horizonal as defined above. Prepositions, such as “on,” “upper,” “side” (as in “sidewall”), “higher,” “lower,” “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
- Antifuses and transistors described herein according to embodiments of the present invention may have wells that may be formed in other wells or tanks rather than substrates. Such wells or tanks may be situated with other wells or tanks, or within other wells or tanks, in a larger substrate. The wells or tanks may also be situated in a silicon-on-insulator (SOI) device.
- SOI silicon-on-insulator
- source/drain refers generally to the terminals or diffusion regions of a field effect transistor.
- a terminal or a diffusion region may be more specifically described as a “source” or a “drain” on the basis of a voltage applied to it when the field effect transistor is in operation.
- n-type conductivity is conductivity associated with holes in a semiconductor material
- n-type conductivity is conductivity associated with electrons in a semiconductor material.
- n+ refers to semiconductor material that is heavily doped n-type semiconductor material, e.g., monocrystalline silicon or polycrystalline silicon.
- p+ refers to semiconductor material that is heavily doped p-type semiconductor material.
- n ⁇ and p ⁇ refer to lightly doped n and p-type semiconductor materials, respectively.
- a transistor is described as being activated or switched on when it is rendered conductive by a control gate voltage that is separated from its source voltage by at least its threshold voltage.
- the transistor is described as being in an inactive state or switched off when the control gate voltage is separated from its source voltage by less than the threshold voltage and the transistor is rendered non-conductive.
- a digital signal of 1 may be called a high signal and a digital signal of 0 may be called a low signal.
- Embodiments of the present invention described herein may be coupled to receive a power supply voltage Vcc which is within approximately 1 to 5 volts. By way of example in this description, and not by way of limitation, Vcc is approximately 3 volts.
- VccX and VccR Two supply voltages, VccX and VccR, may be used in an integrated circuit to improve the noise margin of the embodiments of the invention described herein.
- VccX is an external supply voltage coupled to the integrated circuit.
- VccR is a regulated supply voltage generated inside the integrated circuit, and is often less than VccX.
- VccX is approximately 3 volts
- VccR is between 2 volts and 3 volts.
- Embodiments of the present invention described herein may also be coupled to receive a ground voltage reference Vss, and a bulk node voltage Vbb.
- the voltage Vbb may be approximately equal to Vss, or may be slightly less than Vss such as approximately minus 1 to minus 2 volts.
- Vbb is often coupled to p-type wells and p-type substrates in integrated circuits described herein.
- Vcc, VccX, VccR, Vss, and Vbb are received directly or are generated by circuits that are not shown for purposes of brevity, but are known to those skilled in the art.
- FIG. 1 A cross-sectional view of an antifuse 100 according to an embodiment of the present invention is shown in FIG. 1 .
- An n-type well 110 is formed in a p-type substrate 112 , and an n+-type source diffusion region 114 and an n+-type drain diffusion region 116 are formed in the well 110 .
- Each of the n+-type diffusion regions 114 , 116 provide an ohmic contact for the well 110 .
- a p-type gate electrode 120 is formed over a layer of gate dielectric 122 which is formed over the well 110 between the source diffusion region 114 and the drain diffusion region 116 .
- One or more spacers 123 are formed on the sides of the gate dielectric 122 and the gate electrode 120 .
- the gate electrode 120 is connected to a first terminal 124 of the antifuse 100 , and a second terminal 126 is connected to each of the n+-type diffusion regions 114 , 116 .
- the gate electrode 120 comprises polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 122 may be oxide, oxynitride, or nitrided oxide.
- a p+-type diffusion region 130 is formed in the substrate 112 to provide an ohmic contact coupling the substrate 112 to Vbb.
- Two separate circuits in an integrated circuit may be connected respectively to the first and second terminals 124 , 126 of the antifuse 100 .
- the antifuse 100 is an open circuit between the terminals until it is programmed in the following manner.
- the p-type substrate 112 is coupled to Vbb and the first terminal 124 attached to the p-type gate electrode 120 is coupled to a low voltage.
- the second terminal 126 is coupled to bring the well 110 to a positive elevated voltage, such as approximately 15 volts. A voltage drop between the well 110 and the p-type gate electrode 120 is enough to rupture the gate dielectric 122 .
- the antifuse 100 When programmed the antifuse 100 has a conductive connection between the first and second terminals 124 , 126 which may be biased appropriately such that the p-n junction between the p-type gate electrode 120 and the well 110 allows current to flow.
- the programmed antifuse 100 is an impedance element similar to a diode between the circuits.
- FIG. 1A A cross-sectional view of an antifuse 140 according to an embodiment of the present invention is shown in FIG. 1A .
- the antifuse 140 is similar to the antifuse 100 shown in FIG. 1 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity.
- the antifuse 140 is one-sided because it has only a single n+-type diffusion region 142 .
- the n+-type diffusion region 142 takes the place of the n+-type diffusion regions 114 , 116 in the antifuse 100 , and is connected to the second terminal 126 .
- the antifuse 140 is programmed and functions in a manner similar to the antifuse 100 .
- FIG. 1B A cross-sectional view of an antifuse 150 according to an embodiment of the present invention is shown in FIG. 1B .
- the antifuse 150 is similar to the antifuse 100 shown in FIG. 1 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity.
- the antifuse 150 is offset because it has an n+-type diffusion region 152 that is offset from the gate electrode 120 and the spacers 123 .
- the n+-type diffusion region 152 takes the place of the n+-type diffusion regions 114 , 116 in the antifuse 100 , and is connected to the second terminal 126 .
- the antifuse 150 is programmed and functions in a manner similar to the antifuse 100 .
- FIG. 2 A cross-sectional view of an antifuse 200 according to another embodiment of the present invention is shown in FIG. 2 .
- An n-type well 210 is formed in a p-type substrate 212 , and an n+-type source diffusion region 214 and an n+-type drain diffusion region 216 are formed in the well 210 .
- Each of the n+-type diffusion regions 214 , 216 provide an ohmic contact for the well 210 .
- An n-type gate electrode 220 is formed over a layer of gate dielectric 222 which is formed over the well 210 between the source diffusion region 214 and the drain diffusion region 216 .
- One or more spacers 223 are formed on the sides of the gate dielectric 222 and the gate electrode 220 .
- the gate electrode 220 is connected to a first terminal 224 of the antifuse 200 , and a second terminal 226 is connected to each of the n+-type diffusion regions 214 , 216 .
- the gate electrode 220 comprises polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 222 may be oxide, oxynitride, or nitrided oxide.
- a p+-type diffusion region 230 is formed in the substrate 212 to provide an ohmic contact coupling the substrate 212 to Vbb.
- the antifuse 200 is an open circuit between the first and second terminals 224 , 226 until it is programmed in a manner similar to the programming of the antifuse 100 described above.
- the antifuse 200 is an impedance element similar to a resistor between the first and second terminals 224 , 226 .
- FIG. 2A A cross-sectional view of an antifuse 250 according to an embodiment of the present invention is shown in FIG. 2A .
- the antifuse 250 is similar to the antifuse 200 shown in FIG. 2 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity.
- the antifuse 250 has a metal gate electrode 260 instead of the gate electrode 220 shown in FIG. 2 .
- the antifuse 250 is programmed and functions in a manner similar to the antifuse 200 . Once the antifuse 250 is programmed the metal gate electrode 260 forms a schottky barrier with the n-type well 210 .
- a conductive connection between the first and second terminals 224 , 226 in the programmed antifuse 250 may be biased appropriately to allow current to flow through the schottky barrier.
- the antifuses 100 , 200 may have only one of the n+-type diffusion regions 114 , 116 , 214 , 216 similar to the antifuse 140 .
- the n+-type diffusion regions 114 , 116 , 214 , 216 may be self-aligned with the respective spacers 123 , 223 , or may be offset from and not self aligned with the spacers 123 , 223 similar to the n+-type diffusion region 152 in the antifuse 150 .
- the gate dielectrics 122 and 222 may be fabricated to be thinner than gate dielectrics in conventional field effect transistors to reduce the voltage drop necessary to rupture them.
- Antifuses 100 , 140 , 150 , 200 , and 250 with thinner gate dielectrics 122 and 222 , respectively, would be programmable with a lower elevated voltage, and thus reduce the effects of the elevated voltage on neighboring circuits which will be described below.
- the antifuses 100 , 140 , 150 , 200 , and 250 may also be formed in a semiconductor layer formed over an insulator according to alternate embodiments of the present invention.
- the antifuses 100 , 140 , 150 , 200 , and 250 described above with reference to FIGS. 1, 1A , 1 B, 2 , and 2 A may be used for a variety of purposes in an integrated circuit.
- the antifuses 100 , 140 , 150 , 200 , and 250 may be programmed to provide a coupling to redundant circuits, to change a configuration of the integrated circuit, to tie a line to a voltage or to Vss, or to provide identification for the integrated circuit.
- An electrical schematic diagram of a portion of an integrated circuit 300 is shown in FIG. 3 according to an embodiment of the present invention.
- the integrated circuit 300 may be a memory device, a processor, or any other type of integrated circuit device by way of example and not by way of limitation.
- the integrated circuit 300 includes a number of circuits 310 , 312 , 314 , 316 , 318 , and 320 coupled together by a number of direct connections 330 , 332 , and 334 and a number of antifuses 340 , 342 , 344 , and 346 .
- the antifuses 340 - 346 are represented by triangles inscribed with the letter A.
- One or more of the antifuses 340 - 346 has the structure and the operational method of one of the antifuses shown in FIGS. 1, 1A , 1 B, 2 , and 2 A described above.
- One or more of the antifuses 340 - 346 is programmed according to the methods discussed above to provide electrically conductive couplings between two or more of the circuits 310 - 320 to change the configuration of the integrated circuit 300 .
- the circuits 310 - 320 may be separate components or devices as well as circuits, and the integrated circuit 300 could include more or less circuits, devices, components, and antifuses according to alternate embodiments of the present invention.
- the antifuses 100 , 140 , 150 , 200 , and 250 described above with reference to FIGS. 1, 1A , 1 B, 2 , and 2 A may be arranged in banks of antifuses in an integrated circuit, and an antifuse bank 400 is shown in FIG. 4 according to an embodiment of the present invention.
- the bank 400 includes four antifuses 410 , 412 , 414 , and 416 , one or more having the structure and the operational method of one of the antifuses 100 , 140 , 150 , 200 , or 250 described above with respect to FIGS. 1, 1A , 1 B, 2 , and 2 A.
- the bank 400 may have more or less than four antifuses according to alternate embodiments of the present invention.
- the antifuses 410 - 416 are coupled in parallel to a programming logic circuit 420 , and each of the antifuses 410 - 416 may be programmed in a similar manner.
- the antifuse 410 has a first terminal coupled to the programming logic circuit 420 and a second terminal coupled to an external pin 430 and a bias circuit 440 through a common bus line 442 .
- the first and second terminals correspond to the terminals of one of the antifuses 100 , 140 , 150 , 200 , and 250 .
- the external pin 430 is external to an integrated circuit including the bank 400 , and will be more fully described hereinbelow.
- the bias circuit 440 may be a transistor, a group of transistors coupled together, or a high breakdown voltage resistor.
- the second terminal is also coupled to an electro-static discharge (ESD) device 450 , 452 through the common bus line 442 .
- ESD electro-static discharge
- the bank 400 is operated on one of three modes: a programming mode, an active mode, and a sleep mode.
- the antifuses 410 - 416 are programmed in the programming mode, and the active and sleep modes will be described hereinbelow.
- the programming mode an elevated voltage is applied to the external pin 430 and the common bus line 442 that exceeds Vcc of the integrated circuit by a substantial amount.
- the elevated voltage provides the potential necessary to rupture the gate dielectrics of the antifuses 410 - 416 selected to be programmed.
- the elevated voltage is removed from the external pin 430 during the active and sleep modes and the integrated circuit operates from Vcc.
- the external pin 430 may be allowed to float, or it may be coupled to a reference voltage such as Vss.
- the use of the external pin 430 to couple the elevated voltage to the antifuses 410 - 416 in the programming mode substantially protects other portions of the integrated circuit from damage that may be caused by the elevated voltage.
- One of the antifuses 410 - 416 may be similar to the antifuse 100 shown in FIG. 1 , and a programming of the antifuse 100 in the bank 400 will now be described.
- the p-type substrate 112 is coupled to Vbb and an elevated voltage, such as approximately 15 volts, is coupled to the well 110 from the external pin 430 through the common bus line 442 , the second terminal 126 , and the diffusion regions 114 , 116 .
- the antifuse 100 is selected to be programmed by the programming logic circuit 420 which couples a sufficiently low potential to the p-type gate electrode 120 to rupture the gate dielectric 122 in the antifuse 100 .
- the programming logic circuit 420 may prevent others of the antifuses 410 - 416 from being programmed by raising a potential of the p-type gate electrodes 120 to prevent the gate dielectrics 122 from being ruptured. The operation of the programming logic circuit 420 will be more fully described hereinbelow according to embodiments of the present invention.
- One of the antifuses 410 - 416 may be similar to one of the antifuses 140 , 150 , 200 , or 250 shown in FIGS. 1A, 1B , 2 , and 2 A and a programming of one of the antifuses 140 , 150 , or 200 in the bank 400 will be similar to the programming of the antifuse 100 described above.
- Those skilled in the art having the benefit of this description will recognize that the voltage levels recited herein may be changed depending on characteristics of the antifuses 410 - 416 in the bank 400 .
- Additional support circuits 500 in the programming logic circuit 420 are shown in a block diagram in FIG. 5 according to an embodiment of the present invention.
- the circuits 500 are for programming and reading the antifuses 410 - 416 in the bank 400 , and are shown for programming and reading a single antifuse 510 for purposes of brevity. Additional, similar circuits may be used to program and read a larger number of antifuses.
- the antifuse 510 has the structure and operational method of one of the antifuses 100 , 140 , 150 , 200 , or 250 described above with reference to FIGS. 1, 1A , 1 B, 2 , and 2 A.
- the antifuse 510 has a first terminal coupled to an external pin 520 through a common bus line 530 , and a second terminal coupled to a program driver circuit 542 .
- the external pin 520 corresponds to the external pin 430 shown in FIG. 4 .
- the program driver circuit 542 is used to select the antifuse 510 to be programmed.
- a read circuit 544 is coupled to the antifuse 510 through the program driver circuit 542 to read a state of the antifuse 510 during the active and sleep modes, and a floating well driver logic circuit 550 is coupled to the read circuit 544 .
- the antifuse 510 is one of several antifuses in a bank (not shown), and the floating well driver logic circuit 550 is also coupled to a read circuit for each of the other antifuses in the bank.
- the floating well driver logic circuit 550 is also coupled to a read circuit for each of the other antifuses in the bank.
- an elevated voltage is applied to the common bus line 530 through the external pin 520 to program the antifuse 510 .
- a common bus line driver circuit 560 is coupled to the common bus line 530 to drive the common bus line 530 to a reference voltage such as Vss when the antifuse 510 is being read by the read circuit 544 .
- the floating well driver logic circuit 550 or the common bus line driver circuit 560 may not be needed or included in the circuits 500 .
- the common bus line driver circuit 560 and the program driver circuit 542 each include a high-voltage transistor (HVT).
- HVT high-voltage transistor
- One example of such a HVT is an n-well drain transistor 600 , a cross-sectional view of which is shown in FIG. 6 according to an embodiment of the present invention.
- An n-type well 610 is formed in a p-type substrate 612 , and an n+-type drain diffusion region 616 is formed in the well 610 .
- An n+-type source diffusion region 618 is formed in the substrate 612 .
- a gate electrode 620 is formed over a layer of gate dielectric 622 which is formed over the substrate 612 between the source and drain diffusion regions 618 and 616 .
- the gate electrode 620 is connected to a gate terminal 624 .
- a drain terminal 626 is connected to the n+-type drain diffusion region 616 and a source terminal 628 is connected to the n+-type source diffusion region 618 .
- the gate electrode 620 comprises metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 622 may be oxide, oxynitride, or nitrided oxide.
- a p+-type diffusion region 640 is formed in the substrate 612 to provide an ohmic contact coupling the substrate 612 to Vbb.
- the n-well drain transistor 600 has a high drain breakdown voltage.
- the substrate 612 is coupled to Vbb and the drain terminal 626 is coupled to a line with a high positive voltage, such as the common bus line 530 shown in FIG. 5 during the programming mode.
- the n-well drain transistor 600 will break down and allow current to flow between the drain terminal 626 and the substrate 612 when a critical electric field intensity (E) is reached across a boundary between the n-type well 610 and the p-type substrate 612 .
- E may be approximated as the voltage drop across the boundary divided by a width of a depletion region at the boundary of the n-type well 610 and the p-type substrate 612 .
- Dopant concentrations in the n-type well 610 and the p-type substrate 612 are relatively low such that the width of the depletion region between the two is relatively large.
- the boundary will not break down even under a very large voltage drop across the boundary because the E is less than the critical E.
- the n-well drain transistor 600 will not break down even if the voltage on the drain terminal 626 is relatively high.
- an ordinary n-channel transistor does not have the n-type well 610 , and there is a boundary between a p-type substrate and an n+-type drain diffusion region with a very high dopant concentration. A depletion region at this boundary is not very wide, and as a consequence it will break down under a smaller voltage.
- FIG. 7 A cross-sectional view of an n-well drain transistor 700 is shown in FIG. 7 according to another embodiment of the present invention.
- An n-type well 710 is formed in a drain side of a p-type substrate 712
- a p-type halo implant 714 is formed in a source side of the substrate 712 .
- An n-type lightly doped drain (LDD) 716 is implanted inside the halo implant 714 .
- a gate 720 is formed over a layer of gate dielectric 722 which is formed over the substrate 712 between the n-type well 710 and the halo implant 714 .
- An electrode 724 is formed over the gate 720 .
- LDD lightly doped drain
- gate may comprise polysilicon and the electrode 724 may comprise a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 722 may be oxide, oxynitride, or nitrided oxide.
- the gate 720 and the electrode 724 may also comprise metal.
- One or more spacers 726 are then formed on the sides of the gate dielectric 722 , the gate 720 , and the electrode 724 .
- An n+-type source diffusion region 730 is implanted inside the LDD 716 and the halo implant 714 .
- an n+-type drain diffusion region 732 is implanted in the n-type well 710 .
- the drain diffusion region 732 is not surrounded by LDD or halo implants which are blocked from the drain side of the substrate 712 .
- a source terminal 740 is connected to the source diffusion region 730
- a gate terminal 742 is connected to the electrode 724
- a drain terminal 744 is connected to the drain diffusion region 732 .
- a p+-type diffusion region 760 is formed in the substrate 712 to provide an ohmic contact coupling the substrate 712 to Vbb.
- the n-well drain transistor 700 has a high drain breakdown voltage for reasons analogous to those recited in the description of the n-well drain transistor 600 shown in FIG. 6 .
- FIG. 8 A cross-sectional view of an n-channel transistor 800 is shown in FIG. 8 which is a HVT according to an embodiment of the present invention.
- a p-type halo implant 810 is formed in a source side of a p-type substrate 812 .
- An n-type lightly doped drain (LDD) 816 is implanted inside the halo implant 810 .
- a gate 820 is formed over a layer of gate dielectric 822 which is formed over the substrate 812 .
- An electrode 824 is formed over the gate 820 .
- LDD lightly doped drain
- the gate 820 comprises polysilicon and the electrode 824 may comprise a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate 820 and the electrode 824 may comprise metal.
- the gate dielectric 822 may be oxide, oxynitride, or nitrided oxide.
- One or more spacers 826 are then formed on the sides of the gate dielectric 822 , the gate 820 , and the electrode 824 .
- An n+-type source diffusion region 830 is implanted inside the LDD 816 and the halo implant 810 .
- an n+-type drain diffusion region 832 is implanted in the substrate 812 .
- the drain diffusion region 832 is not surrounded by LDD or halo implants which are blocked from a drain side of the substrate 812 .
- a source terminal 840 is connected to the source diffusion region 830
- a gate terminal 842 is connected to the electrode 824
- a drain terminal 844 is connected to the drain diffusion region 832 .
- the drain diffusion region 832 and the source diffusion region 830 are self-aligned with the spacers 826 .
- a p+-type diffusion region 860 is formed in the substrate 812 to provide an ohmic contact coupling the substrate 812 to Vbb.
- the n-channel transistor 800 has a high drain breakdown voltage and may be used in embodiments of the present invention described above in place of the n-well drain transistor 600 shown in FIG. 6 .
- FIG. 8A is a HVT according to an embodiment of the present invention.
- the transistor 860 is similar to the transistor 800 shown in FIG. 8 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity.
- the LDD implant is not blocked, and an n-type LDD 862 is implanted in a drain side of the p-type substrate 812 .
- An n+-type drain diffusion region 864 is implanted inside the LDD 862 in place of the drain diffusion region 832 of the transistor 800 .
- the transistor 860 functions in a manner similar to the transistor 800 .
- the transistors 600 , 700 , 800 , and 860 shown in FIGS. 6, 7 , 8 , and 8 A may be fabricated according to process steps used to fabricate field-effect transistors in an integrated circuit, and do not require extra process steps.
- an added mask and implant could be applied to the drain diffusion region 832 to customize the high drain breakdown voltage of the transistor 800 .
- FIG. 9 is a HVT according to another embodiment of the present invention.
- An n-type well 910 is formed in a drain side of a p-type substrate 912
- a p-type halo implant 914 is formed in a source side of the substrate 912 and blocked from the drain side.
- Two n-type lightly doped drains (LDD) 916 and 917 are implanted inside the halo implant 914 and the n-type well 910 .
- a gate 920 is formed over a layer of gate dielectric 922 which is formed over the substrate 912 between the n-type well 910 and the halo implant 914 .
- LDD lightly doped drains
- An electrode 924 is formed over the gate 920 .
- the gate 920 comprises polysilicon and the electrode 924 may comprise a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 922 may be oxide, oxynitride, or nitrided oxide.
- the gate 920 and the electrode 924 may comprise metal.
- One or more spacers 926 are then formed on the sides of the gate dielectric 922 , the gate 920 , and the electrode 924 .
- An n+-type source diffusion region 930 is implanted inside the LDD 916 and the halo implant 914 .
- an n+-type drain diffusion region 932 is implanted in the LDD 917 and the n-type well 910 .
- the drain diffusion region 932 in the LDD 917 is not surrounded by a halo implant which was blocked.
- a source terminal 940 is connected to the source diffusion region 930
- a gate terminal 942 is connected to the electrode 924
- a drain terminal 944 is connected to the drain diffusion region 932 .
- the drain diffusion region 932 and the source diffusion region 930 are self-aligned with the spacers 926 .
- a p+-type diffusion region 960 is formed in the substrate 912 to provide an ohmic contact coupling the substrate 912 to Vbb.
- the n-well drain transistor 900 has a high drain breakdown voltage for reasons analogous to those recited in the description of the n-well drain transistor 600 shown in FIG. 6 .
- FIG. 10 An electrical schematic diagram of several support circuits 1000 for programming and reading antifuses is shown in FIG. 10 according to an embodiment of the present invention.
- the circuits 1000 are located in the programming logic circuit 420 shown in FIG. 4 , and include a program driver circuit 1010 , a read circuit 1011 , and a floating well driver logic circuit 1012 .
- the program driver circuit 1010 is coupled to a gate electrode 1014 of an antifuse 1016 , and a well 1018 of the antifuse 1016 is coupled through a common bus line 1020 to an external pin 1022 .
- the antifuse 1016 is similar in structure and operation to the antifuse 100 shown in FIG. 1 .
- the program driver circuit 1010 includes a HVT 1024 having a drain terminal 1026 , a source terminal 1028 , and a gate terminal 1030 .
- the HVT 1024 is similar in structure and operating characteristics to the n-well drain transistor 600 shown in FIG. 6 .
- the drain terminal 1026 is coupled to the gate electrode 1014 of the antifuse 1016 .
- the gate terminal 1030 is coupled to a cathode 1033 of a diode 1034 , and an anode 1038 of the diode 1034 is coupled to Vcc.
- the diode 1034 is forward biased as long as Vcc exceeds a voltage at the gate terminal 1030 .
- the gate terminal 1030 is coupled to a cathode 1040 of a diode 1042 .
- An anode 1044 of the diode 1042 is coupled to Vbb.
- the diodes 1034 and 1042 maintain the gate terminal 1030 at a voltage slightly less than Vcc, or higher. Current will flow through the HVT 1024 as long as the other elements of the circuits 1000 allow current to flow, as will be described hereinbelow.
- the program driver circuit 1010 also includes a first n-channel transistor 1045 and a second n-channel transistor 1046 coupled in cascode between the source terminal 1028 and Vss.
- a gate terminal of the transistor 1045 is coupled to Vcc, and the transistor 1045 is switched on as long as Vcc exceeds a voltage at its source terminal by a threshold voltage V T of the transistor 1045 .
- a gate terminal of the transistor 1046 is coupled to a logic circuit 1048 which controls the program driver circuit 1010 during the programming, active, and sleep modes.
- a body terminal of the transistor 1046 is coupled to Vbb.
- the transistor 1046 is switched off by the logic circuit 1048 in each of the programming, active, and sleep modes, and is switched on for a short period to program the antifuse 1016 in the programming mode.
- the active mode current may flow from the read circuit 1011 through the HVT 1024 and the antifuse 1016 to the common bus line 1020 .
- a more detailed description of the active mode is recited below. No substantial current passes through the transistors 1045 and 1046 in the active mode or in the sleep mode which will also be described below.
- the common bus line 1020 is coupled to receive an elevated voltage in the programming mode, for example 15 volts, through the external pin 1022 .
- the elevated voltage on the common bus line 1020 is distributed across the antifuse 1016 , the transistors 1024 , 1045 , and 1046 , and the diodes 1034 and 1042 which are non-linear elements.
- the distribution of the elevated voltage is non-linear and may vary over time.
- the antifuse 1016 is programmed it is an impedance element and the distribution of the elevated voltage changes.
- the transistor 1046 is switched off and no current path exists through the read circuit 1011 in the programming mode so no substantial current passes through the HVT 1024 . Voltages along the program driver circuit 1010 rise as a result, and the elevated voltage is distributed across the transistors 1024 , 1045 , and 1046 and the diodes 1034 and 1042 in a manner described hereinbelow.
- the antifuse 1016 may be selected to be programmed by the logic circuit 1048 by switching on the transistor 1046 and conduct current from the common bus line 1020 through to Vss.
- the transistor 1046 is switched on for a short period of time to allow the elevated voltage on the common bus line 1020 to rupture a gate dielectric in the antifuse 1016 , and is then switched off.
- the two transistors 1045 and 1046 are coupled in cascode to substantially prevent the occurrence of a snap-back condition when the transistor 1046 is switched off.
- Snap-back occurs when there is current flowing between a source terminal and a drain terminal of a transistor that cannot be shut off by a voltage at a gate terminal of the transistor. Snap-back may start if the transistor is switched on by a high voltage at the gate terminal, a voltage at the drain terminal is very high, and a substantial current is passing through the transistor. If the voltage at the gate terminal is reduced to a low voltage the transistor may not switch off if the voltage at the drain terminal is too high and there is too much current conducting through the transistor.
- Snap-back may occur in the transistor 1046 as the antifuse 1016 is programmed and the logic circuit 1048 attempts to switch off the transistor 1046 with a low voltage on its gate terminal.
- the elevated voltage on the common bus line 1020 and the current passing through the antifuse 1016 may be high enough to cause snap-back in the transistor 1046 .
- One way of reducing snap back is to lower the voltage on the common bus line 1020 after an antifuse is programmed. This method substantially slows the programming of a sequence of antifuses because the voltage must be lowered after each antifuse is programmed.
- snap-back is substantially prevented in the transistor 1046 by the transistor 1045 which is placed to reduce the voltage on the drain terminal of the transistor 1046 .
- the transistor 1045 reduces the voltage on the drain terminal of the transistor 1046 to approximately Vcc less a threshold voltage of the transistor 1045 , which is enough to substantially prevent snap-back.
- the transistors 1045 and 1046 comprise a cascode configuration.
- the transistor 1045 is also employed to reduce current leakage through the antifuse 1016 . If the antifuse 1016 is unprogrammed, any current leakage through it will degrade its gate dielectric. It is therefore advantageous to reduce sources of current leakage in the program driver circuit 1010 as much as possible.
- One source of current leakage in the program driver circuit 1010 is the transistor 1046 .
- Current may leak through the transistor 1046 due to drain induced barrier lowering (DIBL).
- the transistor 1046 is an n-channel transistor and is switched on to conduct current between its drain and source terminals when the voltage at its gate terminal exceeds the voltage at its source terminal by a threshold voltage V T of the transistor 1046 .
- V T threshold voltage
- V GS The difference between the voltage at the gate terminal and the voltage at the source terminal.
- DIBL leakage current flows between the drain terminal and the source terminal at a subthreshold V GS , when V GS is less than V T of the transistor 1046 .
- DIBL leakage current therefore occurs when the transistor 1046 is switched off, and this current can damage the antifuse 1016 when it is unprogrammed.
- the subthreshold V GS is lowered as the voltage at the drain terminal of the transistor 1046 increases, and the DIBL leakage current will therefore occur at lower and lower values of V GS . If the voltage at the drain terminal is high enough, DIBL leakage current will occur when V GS is zero.
- the transistor 1045 reduces DIBL leakage current by reducing the voltage at the drain terminal of the transistor 1046 , and therefore reduces leakage current through the antifuse 1016 .
- the transistor 1046 is similar to a conventional n-channel transistor and has n+-type source and drain regions separated by a channel region in a p-type substrate that is coupled to Vbb. A thin layer of oxide separates the channel region from a gate electrode. The source and drain regions and the gate electrode are connected to the corresponding terminals described above, the n+-type drain region being coupled to the transistor 1045 .
- the n+-type drain region and the p-type substrate comprise a parasitic diode which is reverse biased with a positive voltage on the drain terminal of the transistor 1046 .
- GIDL current leaks across the reverse biased parasitic diode, and increases with an increase of an electric field intensity (E) near the drain region which is increased due to the proximity of the gate electrode.
- E electric field intensity
- GIDL current increases with a rising voltage on the drain terminal of the transistor 1046 which raises E near the drain region.
- the transistor 1045 reduces GIDL current by reducing the voltage at the drain terminal of the transistor 1046 , and therefore reduces leakage current through the antifuse 1016 .
- Snap-back and the DIBL and GIDL leakage current described above may be substantially prevented without the use of the transistor 1045 according to alternate embodiments of the present invention.
- the cascode configuration of the transistors 1045 and 1046 is replaced by the single transistor 1046 .
- DIBL leakage current may flow in the transistor 1046 even if the voltage at its drain terminal is not elevated due to process conditions in which the transistor 1046 is fabricated.
- a method that may be used to reduce DIBL leakage current is to adjust an implant for the transistor 1046 , or to add a masked implant step to raise the threshold voltage of the transistor 1046 .
- Another method is to lower Vbb, the voltage coupled to the body terminal of the transistor 1046 , to raise its threshold voltage.
- the read circuit 1011 includes elements used to read a state of the antifuse 1016 , and these elements will now be described.
- the read circuit 1011 includes a first p-channel transistor 1050 and a second p-channel transistor 1052 .
- the transistor 1052 is switched on by a bias voltage BIAS applied to its gate terminal, and its source terminal is coupled to Vcc.
- the voltage BIAS is generated by a current mirror (not shown) and is approximately equal to Vcc less an amount selected to control current through the transistor 1052 .
- a drain terminal of the transistor 1052 is coupled to a source terminal of the transistor 1050 , and the drain terminal of the transistor 1050 is coupled to the source terminal 1028 of the HVT 1024 .
- the gate terminal of the transistor 1050 is coupled to a signal TZZ 1 which is low when the programming logic circuit 420 is in the active mode to read the antifuse 1016 as will be described hereinbelow.
- the transistor 1050 is therefore switched on to read the antifuse 1016 .
- An inverter 1054 is coupled to the source terminal 1028 and generates an output signal OUTPUT at an output indicating the state of the antifuse 1016 .
- the common bus line 1020 is coupled to Vss and the impedance of the antifuse 1016 is compared with the impedance of the transistor 1052 that is switched on by the voltage BIAS.
- the transistor 1052 may be replaced by a resistor or other load device in alternate embodiments of the present invention.
- the transistor 1050 is switched on to create a current path from Vcc through the transistors 1052 , 1050 , 1024 , and the antifuse 1016 to the common bus line 1020 . If the antifuse is programmed and has a low impedance a very low voltage will occur at the source terminal 1028 that is inverted by the inverter 1054 into a high OUTPUT signal indicating the antifuse 1016 is programmed.
- the antifuse 1016 If the antifuse 1016 is unprogrammed it will have a very high impedance and the voltage at the source terminal 1028 will be close to Vcc. The inverter 1054 will invert this high voltage into a low OUTPUT signal indicating that the antifuse 1016 is unprogrammed.
- the circuits 1000 include several features to substantially eliminate current flow from the common bus line 1020 through the antifuse 1016 , and these features will now be described.
- the HVT 1024 is a possible source of current flow from the common bus line 1020 during the programming mode when the common bus line 1020 is at the elevated voltage and the antifuse 1016 is programmed.
- the elevated voltage may induce breakdown current in the HVT 1024 , and this does not occur through its substrate because of the high drain breakdown voltage of the HVT 1024 .
- the elevated voltage is distributed across the transistors 1024 , 1045 , and 1046 and the diodes 1034 and 1042 as described below.
- the diode 1034 and the diode 1042 substantially prevent breakdown current across the gate dielectric in the following manner.
- the drain terminal 1026 is connected to the drain diffusion region 616
- the gate terminal 1030 is connected to the gate electrode 620
- the source terminal 1028 is connected to the source diffusion region 618 .
- the voltage at the gate electrode 620 is insulated from the voltage at the drain diffusion region 616 by the gate dielectric 622 .
- current will flow across the gate dielectric 622 if a voltage differential between the drain diffusion region 616 and the gate electrode 620 is large.
- the gate dielectric 622 may even break down and become a resistive element if the voltage differential is large enough.
- the diode 1034 and the diode 1042 hold charge at the gate terminal 1030 such that its voltage rises as current passes across the gate dielectric 622 .
- the diode 1034 allows the voltage at the gate terminal 1030 to rise above Vcc until the voltage difference across the gate dielectric 622 is too small to induce further current flow to the gate electrode 620 .
- the voltage at the gate terminal 1030 will not rise above a breakdown voltage of the diode 1042 .
- the elevated voltage at the drain terminal 1026 is divided into two portions, a first portion held across the gate dielectric 622 , and a second portion held across a depletion region in the diode 1042 .
- the coupling of the diode 1034 and the diode 1042 thereby reduces damage to the gate dielectric 622 by bearing a portion of the elevated voltage and reducing the voltage drop across the gate dielectric 622 when the antifuse 1016 is programmed and the common bus line 1020 is at the elevated voltage. If the gate terminal 1030 were held at Vcc then the large voltage differential would cause continuous current and damage the gate dielectric 622 when the drain terminal 1026 was at the elevated voltage.
- the structure including the HVT 1024 and the diodes 1034 and 1042 described above give the program driver circuit 1010 the following operating characteristics. Current will flow through the HVT 1024 as long as the antifuse 1016 is programmed and either the transistors 1045 and 1046 or the read circuit 1011 allow current to flow. If current ceases in the HVT 1024 in the active or sleep modes, then the voltage at the source terminal 1028 rises to approximately a voltage at the gate terminal 1030 less a threshold voltage V T of the HVT 1024 . If the elevated voltage is on the common bus line 1020 then a first portion of it is held across the gate dielectric 622 , and a second portion of it is held across a depletion region in the diode 1042 .
- This voltage distribution is non-linear, and is determined by the reverse bias characteristics of the diode 1042 and the characteristics of the gate dielectric 622 .
- the voltage distribution may vary over time.
- the reverse bias characteristics of the diode 1042 may be modified during the operation of the circuits 1000 , particularly in the programming mode, by modulating Vbb.
- Vbb may be tied to Vss, or raised or lowered by 1 or 2 volts from Vss to change the voltage distribution across the gate dielectric 622 and the diode 1042 .
- the diodes 1034 and 1042 may be fabricated as a single n-channel transistor 1100 shown in FIG. 11 according to an embodiment of the present invention.
- the transistor 1100 is formed in a p-type well 1110 in a substrate, a surrounding well, or tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- An n+-type drain diffusion region 1112 and an n+-type source diffusion region 1114 are formed in the well 1110 .
- a p+-type well tie diffusion region 1116 is also formed in the well 1110 to provide an ohmic contact to bias the well 1110 .
- a gate electrode 1120 is formed over a layer of gate dielectric 1122 which is formed over the well 1110 between the drain diffusion region 1112 and the source diffusion region 1114 .
- the gate electrode 1120 may be formed by metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 1122 may be oxide, oxynitride, or nitrided oxide.
- the gate electrode 1120 and the drain diffusion region 1112 comprise the anode 1038 and are connected to Vcc.
- the source diffusion region 1114 comprises the cathodes 1033 and 1040 and is connected to the gate terminal 1030 .
- the well 1110 and the diffusion region 1116 comprise the anode 1044 and are coupled to Vbb.
- the diode 1034 may be fabricated as a p+-type diode 1200 shown in FIG. 12 according to an embodiment of the present invention.
- the diode 1200 is formed in an n-type well 1210 in a substrate, a surrounding well, or tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- An n+-type diffusion region 1212 and a p+-type diffusion region 1214 are formed in the well 1210 .
- the n+-type diffusion region 1212 comprises the cathode 1033 and is connected to the gate terminal 1030
- the p+-type diffusion region 1214 comprises the anode 1038 and is connected to Vcc.
- the diode 1034 may be fabricated as a p-type well diode 1300 shown in FIG. 13 according to an embodiment of the present invention.
- An n-type triple well 1306 is formed in a substrate, a surrounding well, or tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- An n-type isolation region 1308 is also formed in the substrate above the triple well 1306 .
- the diode 1300 is formed in a p-type well 1310 formed between the triple well 1306 and the isolation region 1308 .
- An n+-type diffusion region 1312 and a p+-type diffusion region 1314 are formed in the well 1310 .
- the n+-type diffusion region 1312 comprises the cathode 1033 and is connected to the gate terminal 1030
- the p+-type diffusion region 1314 comprises the anode 1038 and is connected to Vcc.
- the diode 1042 may be fabricated as the p+-type diode 1200 shown in FIG. 12 according to an embodiment of the present invention.
- the n+-type diffusion region 1212 comprises the cathode 1040 and is connected to the gate terminal 1030
- the p+-type diffusion region 1214 comprises the anode 1044 and is connected to Vbb instead of Vcc as shown in FIG. 12 .
- the diode 1042 may be fabricated as an n+diode 1400 shown in FIG. 14 according to an embodiment of the present invention.
- the diode 1400 is formed in a p-type well 1410 in a substrate, a surrounding well, or tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- An n+-type diffusion region 1412 is formed in the well 1410 between regions of shallow trench isolation oxide 1414 .
- a p+-type diffusion region 1416 is formed in the well 1410 to provide an ohmic contact coupled to Vbb.
- the n+-type diffusion region 1412 comprises the cathode 1040 and is connected to the gate terminal 1030 , and the p+-type diffusion region 1416 and the well 1410 comprise the anode 1044 coupled to Vbb.
- the diode 1042 may be fabricated as an n+-type gated diode 1500 shown in FIG. 15 according to an embodiment of the present invention.
- the diode 1500 is formed in a p-type well 1510 in a substrate, a surrounding well, or tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- a gate electrode 1512 is formed over a layer of gate dielectric 1514 which is formed over the well 1510 .
- the gate electrode 1512 is connected to Vss.
- the gate electrode 1512 may comprise metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 1514 may be oxide, oxynitride, or nitrided oxide.
- An n+-type diffusion region 1516 is formed in the well 1510 to comprise the cathode 1040 of the diode 1042 , and is connected to the gate terminal 1030 .
- a p+-type diffusion region 1518 is formed in the well 1510 to provide an ohmic contact comprising the anode 1044 of the diode 1042 coupled to Vbb.
- the gate dielectric 1514 is formed near the region 1516 and the gate electrode 1512 modulates the performance of the diode 1042 with a strong electric field.
- the diode 1042 may be fabricated as a p+-type gated diode 1600 shown in FIG. 16 according to an embodiment of the present invention.
- the diode 1600 is formed in an n-type well 1610 in a substrate, a surrounding well, or tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- a gate electrode 1612 is formed over a layer of gate dielectric 1614 which is formed over the well 1610 .
- the gate electrode 1612 comprises metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 1614 may be oxide, oxynitride, or nitrided oxide.
- An n+-type diffusion region 1616 is formed in the well 1610 to comprise the cathode 1040 of the diode 1042 , and is connected to the gate electrode 1612 and to the gate terminal 1030 .
- a p+-type diffusion region 1618 is formed in the well 1610 to comprise the anode 1044 of the diode 1042 coupled to Vbb.
- the gate dielectric 1614 is formed near the region 1618 and the gate electrode 1612 modulates the performance of the diode 1042 with a strong electric field.
- the diodes 1034 and 1042 described above with reference to FIGS. 12-16 may be modified by adding or subtracting implants and mask steps to change their reverse bias characteristics.
- the read circuit 1011 also includes elements that are possible sources of current flow from the common bus line 1020 .
- the read circuit 1011 has several p-channel transistors which are favored over n-channel transistors because p-channel transistors provide a better noise margin by not sustaining a threshold voltage drop from Vcc when the antifuse 1016 is read as described above.
- the programming logic circuit 420 is in the programming mode and there is an elevated voltage on the common bus line 1020 , the p-channel transistors provide a path for current from the common bus line 1020 . This will be described with reference to a cross-sectional view of a p-channel transistor 1700 shown in FIG. 17 according to an embodiment of the present invention.
- the transistors 1050 and 1052 are similar to the p-channel transistor 1700 .
- the p-channel transistor 1700 is formed in an n-type well 1710 in a substrate, a surrounding well, or a tank (not shown).
- the substrate may be a silicon substrate or a semiconductor layer formed over an insulator.
- a p+-type source diffusion region 1712 and a p+-type drain diffusion region 1714 are formed in the well 1710 .
- An n+-type well tie diffusion region 1716 is also formed in the well 1710 to provide an ohmic contact to bias the well 1710 with a reference voltage.
- a gate electrode 1720 is formed over a layer of gate dielectric 1722 which is formed over the well 1710 between the source diffusion region 1712 and the drain diffusion region 1714 .
- the gate electrode 1720 may comprise metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi x ), titanium silicide (TiSi 2 ), or cobalt silicide (CoSi 2 ).
- the gate dielectric 1722 may be oxide, oxynitride, or nitrided oxide.
- the gate electrode 1720 is connected to a gate terminal 1730 .
- a source terminal 1732 is connected to the source diffusion region 1712
- a drain terminal 1734 is connected to the drain diffusion region 1714 .
- a reference terminal 1736 is connected to the well tie diffusion region 1716 .
- the drain terminal 1734 is coupled to the source terminal 1028 of the HVT 1024 . If the antifuse 1016 is programmed and the elevated voltage is on the common bus line 1020 in the programming mode, a voltage at the source terminal 1028 will rise.
- the p-channel transistor 1700 may be switched on because the voltage of the drain terminal 1734 rises substantially above Vcc at the gate terminal 1730 .
- device current will pass between the source terminal 1732 and the drain terminal 1734 to Vcc.
- current may be induced through a parasitic diode comprising the drain diffusion region 1714 and the well 1710 coupled to Vcc through the well tie diffusion region 1716 . This current is substantially eliminated by the logic circuit 1012 .
- the logic circuit 1012 switches off p-channel transistors in the read circuit 1011 when the programming logic circuit 420 is in the programming mode and an elevated voltage is on the common bus line 1020 .
- the logic circuit 1012 switches off the p-channel transistors by raising the voltage potential of the wells 1710 by coupling them to an n-well voltage (NWV).
- NWV n-well voltage
- the NWV rises as the voltage at the source terminal 1028 rises.
- the p-channel transistors are not switched on and no current flows through the parasitic diode in each p-channel transistor. This reduces current flow from the common bus line 1020 through the HVT 1024 and the read circuit 1011 to Vcc in the programming mode.
- the structure and operation of the logic circuit 1012 will now be described.
- the logic circuit 1012 is coupled to receive three signals labeled PROGRAM, ZZ 1 , and ZZ 2 , which select one of the programming mode, the active mode, and the sleep mode.
- the signals PROGRAM, ZZ 1 , and ZZ 2 are defined in Table 1: TABLE 1 MODE PROGRAM ZZ1 ZZ2 PROGRAMMING HIGH LOW LOW ACTIVE LOW HIGH LOW SLEEP LOW LOW HIGH
- the signals PROGRAM, ZZ 1 , and ZZ 2 can be generated by any appropriate circuit known to those skilled in the art to indicate the mode of operation of the programming logic circuit 420 .
- the common bus line 1020 When the programming logic circuit 420 is in the active mode the common bus line 1020 is coupled to Vss, and the state of the antifuse 1016 is read as the transistors 1050 and 1052 are switched on and the OUTPUT signal is generated by the inverter 1054 . A substantial amount of current is dissipated through the common bus line 1020 during the active mode if the antifuse 1016 is programmed.
- the transistor 1052 is switched on by the voltage BIAS, and the transistor 1050 is switched on in the following manner.
- the PROGRAM signal is low, the signal ZZ 1 is high and the signal ZZ 2 is low in the active mode.
- the low PROGRAM signal is provided from a circuit 1056 to force NWV to Vcc as it is coupled to an input of a first inverter 1058 and a source of an n-channel transistor 1060 .
- An output of the inverter 1058 generates a high signal that is coupled to a gate terminal of a p-channel transistor 1062 to switch it off.
- a gate terminal of the transistor 1060 is coupled to Vcc such that the transistor 1060 is rendered conductive, and the low PROGRAM signal is coupled through the transistor 1060 to switch on a p-channel transistor 1064 at its gate terminal and couple Vcc to an NWV line 1066 that is coupled to the well tie diffusion region 1716 in each p-channel transistor in the read circuit 1011 .
- the NWV is approximately Vcc.
- the NWV line 1066 thereby couples the NWV to the wells 1710 of p-channel transistors in the read circuit 1011 .
- the logic circuit 1012 includes a second inverter comprising a p-channel transistor 1068 , an n-channel transistor 1070 , and a terminal between the two to generate a signal TZZ 1 .
- a gate terminal of each of the transistors 1068 and 1070 is coupled to receive the signal ZZ 1 which is high.
- the transistor 1068 is switched off and the transistor 1070 is switched on to generate a low signal TZZ 1 which is coupled to the gate terminal of the transistor 1050 to switch it on.
- the logic circuit 1012 also includes a third inverter comprising a p-channel transistor 1072 , an n-channel transistor 1074 , and a terminal between the two to generate a signal TZZ 2 .
- a gate terminal of each of the transistors 1072 and 1074 is coupled to receive the signal ZZ 2 which is low.
- the transistor 1072 is switched on and the transistor 1074 is switched off to generate the signal TZZ 2 to be high, or approximately Vcc.
- the high signal TZZ 2 is coupled to the read circuit 1011 as will now be described.
- the read circuit 1011 includes a third p-channel transistor 1076 , a fourth p-channel transistor 1078 , and a fifth p-channel transistor 1080 .
- Each of the transistors 1076 , 1078 , and 1080 is similar to the p-channel transistor 1700 shown in FIG. 17 .
- the gate terminal of the transistor 1076 is coupled to Vcc, and its reference terminal is coupled to its drain terminal and the NWV line 1066 .
- the transistors 1078 and 1080 are coupled in series between Vcc and the inverter 1054 .
- the high signal TZZ 2 is coupled to a gate terminal of the transistor 1078 to switch it off so that the transistors 1078 and 1080 to not add to the current used to read the antifuse 1016 . Additional features of the read circuit 1011 will be described hereinbelow.
- the programming logic circuit 420 When the programming logic circuit 420 is in the programming mode the common bus line 1020 is coupled to an elevated voltage. If the antifuse 1016 is programmed, it is an impedance element between the elevated voltage and the rest of the elements in the program driver circuit 1010 and the read circuit 1011 .
- the logic circuit 1012 substantially eliminates current flow in the p-channel transistors in the read circuit 1011 in the following manner.
- the PROGRAM signal In the programming mode the PROGRAM signal is high and is coupled to a drain of the transistor 1060 to switch it off. Inverter 1058 generates a low signal to switch on the transistor 1062 .
- the NWV on the NWV line 1066 will rise, for reasons described below, and the high NWV is coupled to the gate terminal of the transistor 1064 to switch it off. With the transistors 1060 and 1064 both switched off, the NWV line 1066 is isolated from both the PROGRAM signal and Vcc.
- the source terminal 1028 may rise above Vcc in the programming mode when the elevated voltage is on the common bus line 1020 and the antifuse 1016 is programmed.
- the transistor 1076 will be switched on because its gate terminal is held at Vcc, and the rising voltage at the source terminal 1028 is coupled to the NWV line 1066 to raise the NWV.
- the NWV line 1066 is coupled to the wells of each of the transistors 1050 , 1052 , 1076 , 1078 , and 1080 which comprise a capacitive load that absorbs charge as the NWV rises.
- both of the signals ZZ 1 and ZZ 2 are low such that the p-channel transistors 1068 and 1072 are switched on and the n-channel transistors 1070 and 1074 are switched off and both of the signals TZZ 1 and TZZ 2 rise with the NWV.
- the signal TZZ 1 is coupled to a gate terminal of the transistor 1050
- the signal TZZ 2 is coupled to a gate terminal of the transistor 1078 .
- the rise in NWV reduces current being passed through the parasitic diodes in the transistors 1050 , 1052 , 1076 , 1078 , and 1080 because the wells 1010 of those transistors have nearly the same voltage potential as the source terminal 1028 , and there is not enough voltage potential to forward bias the parasitic diodes.
- the gate terminals of the transistors 1050 and 1078 are also coupled to the NWV to prevent them from being switched on by the voltage at the source terminal 1028 . Substantial device current is thereby reduced in the transistors 1050 , 1052 , 1078 , and 1080 .
- the floating well driver logic circuit 1012 prevents substantial current in the p-channel transistors 1050 , 1052 , 1076 , 1078 , and 1080 in the programming mode when the elevated voltage is on the common bus line 1020 and an antifuse is to be programmed.
- the inverter 1054 and the transistors 1078 and 1080 in the read circuit 1011 are part of a latch circuit used to latch a state of the antifuse 1016 when the programming logic circuit 420 is in the sleep mode.
- the programming logic circuit 420 is receiving power and operating in both the active and sleep modes. However, in the sleep mode the programming logic circuit 420 shuts down some operations to reduce power dissipation. As mentioned above, a substantial amount of current is dissipated through the common bus line 1020 in the active mode if the antifuse 1016 is programmed. This current is substantially eliminated in the sleep mode.
- the latch circuit is used in the sleep mode to latch the state of the antifuse 1016 to indicate correctly the state of the antifuse 1016 in the sleep mode.
- the latch circuit also includes a first n-channel transistor 1082 and a second n-channel transistor 1084 .
- the transistors 1082 and 1084 are similar to n-channel transistors known to those skilled in the art, and will not be shown in more detail for purposes of brevity.
- a drain terminal of the transistor 1082 is coupled to a drain terminal of the transistor 1078 and an input of the inverter 1054 .
- a gate terminal of the transistor 1082 is coupled with the gate terminal of the transistor 1050 to receive the signal TZZ 1 from the logic circuit 1012 .
- a source terminal of the transistor 1082 is coupled to a drain terminal of the transistor 1084 , and a source terminal of the transistor 1084 is coupled to Vss.
- a gate terminal of the transistor 1084 is coupled to the output of the inverter 1054 , as is a gate terminal of the transistor 1080 .
- the gate terminal of the transistor 1078 is coupled to receive the signal TZZ 2 from the logic circuit 1012 .
- the latch circuit is disabled in the active mode described above when the signal ZZ 1 is high and the signal ZZ 2 is low.
- the resulting signal TZZ 1 is low to switch the transistor 1050 on while switching off the transistor 1082 .
- the signal TZZ 2 is high to switch off the transistor 1078 . Thus no substantial current passes through the transistors 1078 and 1082 while the antifuse 1016 is being read in the active mode.
- the PROGRAM signal In the sleep mode the PROGRAM signal is low so that the NWV line 1066 is coupled to Vcc.
- the signal ZZ 1 is low so the signal TZZ 1 is high to switch off the transistor 1050 and block current from the transistor 1052 .
- the high signal TZZ 1 also enables the transistor 1082 to be switched on depending on a voltage between the transistors 1082 and 1084 .
- the signal ZZ 2 is high so the signal TZZ 2 is low to enable the transistor 1078 to be switched on depending on a voltage between the transistors 1078 and 1080 .
- the source terminal 1028 will retain its voltage potential, near either Vcc or Vss, after being read in the active mode.
- the output of the inverter 1054 will be low to switch off the transistor 1084 and enable the transistor 1080 to be switched on.
- the high voltage on the source terminal 1028 causes the transistors 1078 and 1080 to be switched on to couple the source terminal 1028 to Vcc and latch the output of the inverter 1054 low.
- the output of the inverter 1054 will be high to switch off the transistor 1080 and enable the transistor 1084 to be switched on.
- the low voltage at the source terminal 1028 causes the transistors 1082 and 1084 to be switched on to couple the source terminal 1028 to Vss and latch the output of the inverter 1054 high.
- the latch including the transistors 1078 , 1080 , 1082 , and 1084 , and the inverter 1054 , is used to latch a state of the antifuse 1016 only in the sleep mode because the state of the latch is unknown when the programming logic circuit 420 first receives power after being in a power-down mode.
- the latch will indicate the correct state of the antifuse 1016 only after it has been read in the active mode.
- One advantage of the sleep mode is that the transistor 1050 is switched off to reduce the dissipation of current from Vcc through the transistors 1052 , 1050 , 1024 , and the antifuse 1016 to the common bus line 1020 .
- the antifuse 1016 may be read only intermittently during the operation of an integrated circuit and then its state may be latched the rest of the time according to an alternate embodiment of the present invention.
- the state of the antifuse is read as it is in the active mode described above in response to a signal such as a power-up signal or a wake-up signal for the integrated circuit that initiates the read.
- the power-up or wake-up signal sets TZZ 1 low and TZZ 2 high for a period of time to read the antifuse 1016 and allow the inverter 1054 to generate a settled OUTPUT signal. As the period of time ends TZZ 1 is set high and TZZ 2 is set low to latch the state of the antifuse 1016 as described above.
- the NWV line 1066 is coupled not only to the transistors shown in FIG. 10 , but transistors associated with other antifuses in the bank 400 . If all of the antifuses in the bank 400 are unprogrammed, then the capacitive load of the NWV line 1066 will be charged from current passed through one or more of them and which will damage the antifuses.
- One way of preventing this damage is to short at least one antifuse in each bank, such as the antifuse 410 in the bank 400 , with metal such that a current path exists to charge the capacitive load of the NWV line 1066 and its transistors.
- the shorted antifuse may also be used in a test mode.
- the transistors 1070 , 1074 , and 1084 shown in FIG. 10 may each be replaced by an upper transistor and a lower transistor of similar types coupled in cascode to manage high voltages.
- the upper transistor has a gate terminal coupled to Vcc and the lower transistor has a gate terminal connected in a manner similar to the corresponding original transistor 1070 , 1074 , and 1084 .
- FIG. 18 An electrical schematic diagram of an integrated circuit 1800 with a common bus line driver circuit 1802 is shown in FIG. 18 according to an embodiment of the present invention.
- the integrated circuit 1800 includes three banks 1810 , 1812 , and 1814 of antifuses coupled to a common bus line 1820 .
- the banks 1810 , 1812 , and 1814 may be similar to the bank 400 shown in FIG. 4 .
- Integrated circuits according to other embodiments of the present invention may include more or fewer banks of antifuses.
- the common bus line 1820 is coupled to an ESD device 1822 , 1824 , and an external pin 1826 of the integrated circuit 1800 .
- the external pin 1826 is similar to the external pin 430 shown in FIG. 4 .
- the common bus line driver circuit 1802 is coupled to provide a path to Vss for the common bus line 1820 .
- the common bus line driver circuit 1802 includes a HVT 1830 having a drain terminal 1832 , a source terminal 1834 , and a gate terminal 1836 .
- the HVT 1830 is similar in structure and operating characteristics to the n-well drain transistor 600 shown in FIG. 6 .
- the gate terminal 1836 is coupled to a cathode 1841 of a diode 1842 , and an anode 1846 of the diode 1842 is coupled to Vcc.
- the diode 1842 is forward biased as long as Vcc exceeds a voltage at the gate terminal 1836 .
- the gate terminal 1836 is also coupled to a cathode 1850 of a diode 1852 .
- An anode 1854 of the diode 1852 is coupled to Vbb.
- the diodes 1842 and 1852 maintain the gate terminal 1836 at a voltage slightly less than Vcc, or higher.
- a first n-channel transistor 1860 and a second n-channel transistor 1870 are coupled in cascode between the source terminal 1834 and Vss.
- a gate terminal of the transistor 1860 is coupled to Vcc, and a gate terminal of the transistor 1870 is coupled to a logic circuit 1872 which controls current in the common bus line driver circuit 1802 .
- a body terminal of the transistor 1870 is coupled to Vbb.
- the logic circuit 1872 switches on the transistor 1870 such that current on the common bus line 1820 is given a path to Vss.
- the current flows from the antifuses in the banks 1810 , 1812 , and 1814 through the HVT 1830 and the transistors 1860 , 1870 to Vss as they are read in the active mode according to the description of FIG. 10 recited above.
- the transistors 1830 , 1860 , and 1870 are sized to accommodate current from all of these antifuses while maintaining the common bus line 1820 near Vss.
- the logic circuit 1872 switches off the transistor 1870 to prevent substantial current flow. This is done to maintain an elevated voltage on the common bus line 1820 , and to minimize current flow from the common bus line 1820 . Voltages along the common bus line driver circuit 1802 rise when the transistor 1870 is switched off to substantially end current flow, and the voltage rises on the common bus line 1820 .
- the transistor 1830 and the diodes 1842 and 1852 function in a manner similar to the transistor 1024 and the diodes 1034 and 1042 described with reference to FIG. 10 .
- the program driver circuit 1010 shown in FIG. 10 and the common bus line driver circuit 1802 may be different in alternate embodiments of the present invention.
- the two circuits 1010 and 1802 may have different HVTs, or one may have a cascode coupling of transistors and the other may have only a single corresponding transistor.
- the two circuits 1010 and 1802 may also have different combinations of diodes such as those described with reference to FIGS. 11-16 .
- the logic circuit 1872 may also switch off the transistor 1870 during a test mode to permit an analog characterization of the impedance of each programmed antifuse in the banks 1810 , 1812 , and 1814 .
- the current/voltage characteristics of each programmed antifuse are tested with a test apparatus such as a curve tracer coupled to the external pin 1826 .
- Current passes through the programmed antifuse, and other current sources coupled to the common bus line 1820 must be substantially blocked during the test mode.
- Another test mode permits a modulation of the voltage BIAS to modulate the impedance of the transistor 1052 .
- a noise margin for the circuits 1000 may be quantified by determining an impedance of the transistor 1052 at which the inverter 1054 changes the OUTPUT signal. A wider noise margin will allow for more variability in the impedance of the antifuse over the operating lifetime of the circuits 1000 without impairing performance.
- the common bus line driver circuit 1802 is not included in the integrated circuit 1800 because a programming of its antifuses takes place during its manufacture, and the external pin 1826 is coupled to Vss during its operation. This is called supply stealing.
- the common bus line 1820 is then always coupled to Vss during operation, and the common bus line driver circuit 1802 is not needed.
- the read circuit 1011 shown in FIG. 10 may be modified to read the antifuse 1016 as it is read in the active mode all of the time.
- a set of support circuits 1900 including a modified read circuit 1910 are shown in FIG. 19 according to an embodiment of the present invention. All of the other elements of the support circuits 1900 are similar to the support circuits 1000 shown in FIG. 10 , have been given the same reference numerals, and will not be further described for purposes of brevity.
- the state of the antifuse 1016 is never latched by the read circuit 1900 .
- the read circuit 1910 retains only two of the transistors, 1052 and 1076 , from the read circuit 1011 , the remaining transistors not being necessary or included in the read circuit 1910 .
- the transistor 1052 may be replaced by a resistor or other load device in alternate embodiments of the present invention.
- the operation of the transistor 1076 is the same as described above for the read circuit 1011 .
- the antifuse 1016 is read by comparing the impedance of the transistor 1052 with the impedance of the antifuse 1016 with current flow from Vcc through the transistors 1052 and 1024 and the antifuse 1016 .
- the resulting OUTPUT signal is the same as described above for the read circuit 1011 .
- the antifuse 510 may be similar to the antifuse 200 shown in FIG. 2 , in which case the programmed antifuse 510 will be similar to a resistor and include a ruptured gate dielectric 222 between the n-type well 210 and the n-type gate electrode 220 .
- the antifuse 510 may then be read with Vcc on the common bus line 530 using a read circuit similar to the read circuit 1011 shown in FIG. 10 .
- a set of support circuits 2000 including an example of such a read circuit are shown in FIG. 20 according to an embodiment of the present invention.
- the circuits 2000 include a programmed antifuse 2008 similar to the antifuse 200 having a first terminal coupled to a common bus line 2010 .
- the common bus line 2010 is coupled to Vcc, and this may be called supply stealing for Vcc if it is supplied from a source external to the circuits 2000 .
- a second terminal of the antifuse 2008 is coupled to a program driver circuit 2012 having the same elements as the program driver circuit 1010 shown in FIG. 10 . Also shown is the floating well driver logic circuit 1012 . The same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- a read circuit 2020 is coupled to the program driver circuit 2012 at the source terminal 1028 of the HVT 1024 and includes elements similar to the elements of the read circuit 1011 shown in FIG. 10 . The similar elements have been given the same reference numerals and will not be further described for purposes of brevity.
- the read circuit 2020 does not include the transistors 1050 and 1052 shown in FIG. 10 . Instead, a first n-channel transistor 2030 and a second n-channel transistor 2032 are coupled in series between the source terminal 1028 and Vss. The transistor 2032 is switched on by a bias voltage BIAS applied to its gate terminal, and the voltage BIAS is generated by a current mirror (not shown) to control current through the transistor 2032 to Vss at its source terminal.
- a drain terminal of the transistor 2032 is coupled to a source terminal of the transistor 2030 , and the drain terminal of the transistor 2030 is coupled to the source terminal 1028 .
- the gate terminal of the transistor 2030 is coupled to the signal TZZ 2 which is high to switch on the transistor 2030 when the programming logic circuit 420 is in the active mode to read the antifuse 2008 .
- the antifuse 2008 When the antifuse 2008 is read current flows from the common bus line 1020 at Vcc through the antifuse 2008 and the transistors 1024 , 2030 , and 2032 to Vss.
- the impedance of the antifuse 2008 is compared with the impedance of the transistor 2032 when it is switched on. If the antifuse 2008 is programmed and has a low impedance then a voltage at the source terminal 1028 will be close to Vcc less the threshold voltages of the diode 1034 and the HVT 1024 .
- the inverter will invert this high voltage into a low OUTPUT signal indicating that the antifuse 2008 is programmed.
- the transistor 2032 is a long-L n-channel transistor or a long-L p-channel transistor, or it may be replaced by a resistor.
- the transistor 2032 may also be replaced by an upper transistor and a lower transistor of a similar type coupled in cascode to manage high voltages.
- the upper transistor has a gate terminal coupled to Vcc and the lower transistor has a gate terminal connected in a manner similar to the corresponding original transistor 2032 .
- the logic circuit 1012 shown in FIG. 10 may not be necessary to reduce current flow in the read circuit 1011 for many reasons. For example, process parameters may result in an integrated circuit that minimizes this current, or the HVT 1024 may have characteristics which minimize this current.
- a pass-gate device may also reduce the need for the logic circuit 1012 .
- a set of support circuits 2100 including a pass-gate device are shown in FIG. 21 according to an embodiment of the present invention.
- the circuits 2100 include elements similar to the elements of the support circuits 1000 shown in FIG. 10 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- the program driver circuit 1010 is coupled to a read circuit 2120 through an n-channel pass-gate transistor 2130 according to an embodiment of the present invention.
- a drain of the pass-gate transistor 2130 is coupled to the source of the HVT 1024 , and a source of the pass-gate transistor 2130 is coupled to the transistor 1050 .
- Vcc is coupled to a gate of the pass-gate transistor 2130 .
- Both of the signals ZZ 1 and ZZ 2 are low during the programming mode such that Vcc is coupled to the source of the pass-gate transistor 2130 to ensure that it is not conductive and substantially prevents current flow from the common bus line 1020 .
- the voltage at the source of the pass-gate transistor 2130 will vary during the active and sleep modes.
- the use of the pass-gate transistor 2130 to reduce current flow in the read circuit 2120 may also permit the use of n-channel transistors instead of the p-channel transistors in the read circuit 2120 .
- a set of support circuits 2200 are shown in FIG. 22 according to an embodiment of the present invention.
- the circuits 2200 include elements similar to the elements of the support circuits 2100 shown in FIG. 21 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- the program driver circuit 1010 is coupled to a read circuit 2220 through an n-channel pass-gate transistor 2130 having Vcc coupled to its gate.
- the pass-gate transistor 2130 substantially prevents current flow from the common bus line 1020 .
- the read circuit 2220 includes elements similar to the elements of the read circuit 2120 shown in FIG. 21 , and further includes n-channel transistors 2230 , 2232 , 2240 , and 2242 in place of the p-channel transistors 1050 , 1052 , 1078 , and 1080 shown in FIG. 21 .
- the signal ZZ 1 is coupled to a gate of the transistor 2230 while the signal ZZ 2 is coupled to gates of the transistors 1082 and 2240 .
- An inverted signal OUTPUT is coupled to a gate of the transistor 2242 , being inverted by an inverter 2254 .
- the read circuit 2220 operates in a manner substantially similar to the read circuit 2120 .
- the pass-gate transistor 2130 shown in FIGS. 21 and 22 eliminates the need for the logic circuit 1012 , but it also reduces the noise margin of the read circuits 2120 and 2220 during a read of the antifuse 1016 .
- the noise margin is improved by using the external supply voltage VccX and the regulated supply voltage VccR described above to supply power to the read circuits 2120 and 2220 .
- a set of support circuits 2300 are shown in FIG. 23 according to an embodiment of the present invention. Most of the elements of the circuits 2300 are similar to the elements of the support circuits 2100 shown in FIG. 21 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- the read circuit 2120 is coupled to receive VccR on the sources of the transistors 1052 and 1080 while the gate of the pass-gate transistor 2130 is coupled to VccX. Either VccX or VccR is coupled to the anode of the diode 1034 .
- VccR is regulated to be less than VccX to improve the noise margin of the read circuit 2120 .
- VccR is raised to be approximately equal to VccX.
- a similar use of VccR and VccX would also improve the noise margin of the circuits 2200 shown in FIG. 22 .
- the common bus line 2010 in the circuits 2000 shown in FIG. 20 is coupled to Vcc. This may be replaced by a driver circuit driven by both of the supply voltages VccX and VccR.
- An electrical schematic diagram of an integrated circuit 2400 with a common bus line driver circuit 2402 is shown in FIG. 24 according to an embodiment of the present invention.
- the integrated circuit 2400 includes three banks 2410 , 2412 , and 2414 of antifuses coupled to a common bus line 2420 .
- the banks 2410 , 2412 , and 2414 may be similar to the bank 400 shown in FIG. 4 .
- Integrated circuits according to other embodiments of the present invention may include more or fewer banks of antifuses.
- the common bus line 2420 is coupled to an ESD device 2422 , 2424 , and an external pin 2426 of the integrated circuit 2400 .
- the external pin 2426 is similar to the external pin 430 shown in FIG. 4 .
- the common bus line driver circuit 2402 couples the common bus line 2420 to VccR when necessary.
- the common bus line driver circuit 2402 includes a HVT 2430 having a drain terminal 2432 , a source terminal 2434 , and a gate terminal 2436 .
- the HVT 2430 is similar in structure and operating characteristics to the n-well drain transistor 600 shown in FIG. 6 .
- the gate terminal 2436 is coupled to a cathode 2441 of a diode 2442 , and an anode 2446 of the diode 2442 is coupled to VccX.
- the diode 2442 is forward biased as long as VccX exceeds a voltage at the gate terminal 2436 .
- the gate terminal 2436 is also coupled to a cathode 2450 of a diode 2452 .
- An anode 2454 of the diode 2452 is coupled to Vss.
- the diodes 2442 and 2452 maintain the gate terminal 2436 at a voltage slightly less than VccX, or higher.
- a first n-channel transistor 2460 and a second n-channel transistor 2470 are coupled in cascode between the source terminal 2434 and VccR.
- a body terminal of the transistor 2470 is coupled to Vbb.
- a gate terminal of the transistor 2460 is coupled to VccX, and a gate terminal of the transistor 2470 is coupled to a logic circuit 2472 which controls current in the common bus line driver circuit 2402 .
- the logic circuit 2472 is coupled to receive VccX as its supply voltage.
- the logic circuit 2472 switches on the transistor 2470 such that the common bus line 2420 is coupled to VccR.
- the current flows from VccR to the antifuses in the banks 2410 , 2412 , and 2414 as they are read in the active mode according to the description of FIG. 10 recited above.
- the transistors 2430 , 2460 , and 2470 are sized to accommodate current drawn by all of these antifuses while maintaining the common bus line 2420 near VccR.
- the logic circuit 2472 switches off the transistor 2470 to prevent substantial current flow. This is done to maintain an elevated voltage on the common bus line 2420 , and to minimize current flow from the common bus line 2420 . Voltages along the common bus line driver circuit 2402 rise when the transistor 2470 is switched off to substantially end current flow, and the voltage rises on the common bus line 2420 .
- the transistor 2430 and the diodes 2442 and 2452 function in a manner similar to the transistor 1024 and the diodes 1034 and 1042 described with reference to FIG. 10 .
- the program driver circuit 1010 shown in FIG. 10 and the common bus line driver circuits 1802 and 2402 may be different in alternate embodiments of the present invention.
- the circuits 1010 , 1802 , and 2402 may have different HVTs, or one may have a cascode coupling of transistors and the other may have only a single corresponding transistor.
- the circuits 1010 , 1802 , and 2402 may also have different combinations of diodes such as those described with reference to FIGS. 11-16 .
- FIG. 10 With reference to the circuits 1000 shown in FIG. 10 , another possible source of unwanted current in the antifuse 1016 exists through the transistors 1082 and 1084 . If the voltage at the source 1028 of the HVT 1024 is low, then the OUTPUT signal is high and the transistor 1084 is switched on. If this condition occurs during the programming mode the transistors 1082 , 1084 may draw current through the antifuse 1016 causing damage if it is unprogrammed.
- a set of support circuits 2500 are shown in FIG. 25 according to an embodiment of the present invention. Most of the elements of the circuits 2500 are similar to the elements of the support circuits 1000 shown in FIG. 10 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- the circuits 2500 include a read circuit 2520 that has, in addition to the elements shown in FIG. 10 , elements that substantially prevent current through the transistors 1082 , 1084 in the programming mode.
- the inverter 1054 comprises a p-channel transistor 2530 and an n-channel transistor 2532 connected in series, with drains of the transistors 2530 and 2532 connected together to form the output of the inverter 1054 .
- Gates of the transistors 2530 and 2532 are connected together to the source 1028 of the HVT 1024 .
- a source of the transistor 2532 is coupled to Vss, and a p-channel transistor 2534 is coupled between a source of the transistor 2530 and Vcc.
- an n-channel transistor 2536 is coupled between the output of the inverter 1054 and Vss.
- the output of the inverter 1054 remains connected to the gate of the transistor 1084 .
- Gates of the transistors 2534 and 2536 are coupled to receive a signal SW, which is shown in the following Table 2: TABLE 2 MODE SW PROGRAMMING HIGH ACTIVE LOW SLEEP LOW
- the signal SW is high to switch off the transistor 2534 and substantially block current to the inverter 1054 .
- the high SW signal also switches on the transistor 2536 to couple the output of the inverter 1054 to Vss and thus ensure that the transistor 1084 is switched off to substantially prevent unwanted current in the antifuse 1016 .
- the signal SW is low to decouple the output of the inverter 1054 from Vss and switch on the transistor 2534 .
- the inverter 1054 is thereby coupled to Vcc and the read circuit 2520 operates similarly to the read circuit 1011 shown in FIG. 10 to read a state of the antifuse 1016 .
- the antifuses 100 , 140 , 150 , 200 , and 250 shown in FIGS. 1, 1A , 1 B, 2 , and 2 A, the transistors 600 , 700 , 800 , 860 , 900 , 1100 , and 1700 shown in FIGS. 6, 7 , 8 , 8 A, 9 , 11 , and 17 , and the diodes 1200 , 1300 , 1400 , 1500 , and 1600 shown in FIGS. 12, 13 , 14 , 15 , and 16 according to embodiments of the present invention may be formed in wells within other wells or tanks rather than the substrates shown. Such wells or tanks may be situated with other wells or tanks, or within other wells or tanks, in a larger substrate. The wells or tanks may also be situated in a silicon-on-insulator (SOI) device.
- SOI silicon-on-insulator
- An integrated circuit fabricated with one or more of the antifuses and circuits described above may be tested in a test mode.
- an integrated circuit having a bank of antifuses is prestressed by applying a prestress voltage that is less than the elevated voltage used to program the antifuses.
- the antifuses are exposed to the prestress voltage and weaker antifuses are programmed as a result.
- the antifuses are then read to indicate the antifuses that have been programmed.
- the antifuses may be read by determining their analog resistances, by detecting a digital output of an addressed antifuse, or by detecting digital output from an addressed antifuse compared with several different load elements.
- the logic circuit 1012 shown in FIG. 10 may not be necessary to reduce current flow in the read circuit 1011 for many reasons. For example, process parameters may result in an integrated circuit that minimizes this current, or the HVT 1024 may have characteristics which minimize this current.
- a set of support circuits 2600 are shown in FIG. 26 according to an embodiment of the present invention.
- the circuits 2600 include elements similar to the elements of the circuits 1000 shown in FIG. 10 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- the logic circuit 1012 , the transistor 1076 , and the connections to the NWV line 1066 shown in FIG. 10 are not included in the circuits 2600 .
- the circuits 2600 operate in a manner similar to the circuits 1000 without the above-listed elements.
- the pass-gate transistor 2130 shown in FIG. 22 may not be necessary to reduce current flow in the read circuit 2220 for the reasons mentioned above.
- a set of support circuits 2700 are shown in FIG. 27 according to an embodiment of the present invention.
- the circuits 2700 include elements similar to the elements of the circuits 2200 shown in FIG. 22 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.
- the pass-gate transistor 2130 shown in FIG. 22 is not included in the circuits 2700 .
- the circuits 2700 operate in a manner similar to the circuits 2200 without the pass-gate transistor 2130 .
- FIG. 28 A block diagram of a static random access memory device (SRAM) 2800 is shown in FIG. 28 according to an embodiment of the present invention.
- the SRAM 2800 may include one or more of the circuits and devices described above with respect to FIGS. 1-25 according to embodiments of the present invention.
- the SRAM 2800 has an array 2810 of memory cells that are accessed according to address signals provided to the SRAM 2800 at a number of address inputs A 0 -A 16 .
- An address decoder 2820 decodes the address signals and accesses memory cells in the array 2810 according to the address signals. Data is written to the memory cells in the array 2810 when a write enable signal WE* and a chip enable signal CE* coupled to the SRAM 2800 are both low.
- the data is received by the SRAM 2800 over eight data input/output (I/O) paths DQ 1 -DQ 8 .
- the data is coupled to the memory cells in the array 2810 from the I/O paths DQ 1 -DQ 8 through an I/O control circuit 2830 .
- Data is read from the memory cells in the array 2810 when the write enable signal WE* is high and an output enable signal OE* coupled to the SRAM 2800 and the chip enable signal CE* are both low.
- a power down circuit 2840 controls the SRAM 2800 during a power-down mode.
- the circuits and devices described above with respect to FIGS. 1-25 according to embodiments of the present invention may be included in other types of memory devices such as DRAMs, programmable logic devices, PROMs, EPROMs, and EEPROMs.
- FIG. 29 An integrated circuit package 2900 of a 32 k ⁇ 36 SRAM memory device is shown in FIG. 29 according to an embodiment of the present invention.
- the SRAM may include one or more of the circuits and devices described above with respect to FIGS. 1-25 according to embodiments of the present invention.
- One of the external pins 430 , 520 , 1022 , 1826 , or 2426 described above is one of several pins 16 , 38 , 39 , 42 , 43 , or 66 in the package 2900 .
- the pins 16 , 38 , 39 , 42 , 43 , or 66 are non-reserved pins, one of which is used as one of the external pins 430 , 520 , 1022 , 1826 , or 2426 .
- the pin selected as one of the external pins 430 , 520 , 1022 , 1826 , or 2426 will receive an elevated voltage if an antifuse in the SRAM is to be programmed.
- the selected pin may be left floating, or may be coupled to Vss during a normal operation of the SRAM.
- one of the external pins 430 , 520 , 1022 , or 1826 described above is one of several pins 17 , 40 , 67 , or 90 coupled to Vss during the operation of the SRAM.
- the external pin 2426 is one of several pins 14 , 15 , 41 , 65 , or 91 coupled to Vcc during the operation of the SRAM. This is called supply stealing, and is described above with reference to the external pin 1826 shown in FIG. 18 .
- FIG. 30 A block diagram of an information-handling system 3000 is shown in FIG. 30 according to an embodiment of the present invention.
- the information-handling system 3000 includes a memory system 3008 , a processor 3010 , a display unit 3020 , and an input/output (I/O) subsystem 3030 .
- the processor 3010 may be, for example, a microprocessor.
- One or more of the memory system 3008 , the processor 3010 , the display unit 3020 , and the I/O subsystem 3030 may include one or more of the circuits and devices described above with respect to FIGS. 1-25 according to embodiments of the present invention.
- the processor 3010 , the display unit 3020 , the I/O subsystem 3030 , and the memory system 3008 are coupled together by a suitable communication line or bus 3040 .
- the processor 3010 and the memory system 3008 may be integrated circuits formed on a single substrate.
- the information-handling system 3000 is a computer system (such as, for example, a video game, a hand-held calculator, a television set-top box, a fixed-screen telephone, a smart mobile phone, a personal digital assistant (PDA), a network computer (NC), a hand-held computer, a personal computer, or a multi-processor supercomputer), an information appliance (such as, for example, a cellular telephone or any wireless device, a pager, or a daily planner or organizer), an information component (such as, for example, a magnetic disk drive or telecommunications modem), or other appliance (such as, for example, a hearing aid, washing machine or microwave oven having an electronic controller).
- a computer system such as, for example, a video game, a hand-held calculator, a television set-top box, a fixed-screen telephone, a smart mobile phone, a personal digital assistant (PDA), a network computer (NC), a hand-held computer, a personal computer, or a multi-processor supercomputer
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Abstract
A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.
Description
- This application is a divisional of U.S. application Ser. No. 10/680,481 filed on Oct. 6, 2003, which is a divisional of U.S. application Ser. No. 09/652,429 filed on Aug. 31, 2000, now U.S. Pat. No. 6,630,724, which applications are incorporated herein by reference.
- The present invention relates generally to integrated circuits, and more particularly, to antifuse circuits and methods for operating them.
- Integrated circuits are interconnected networks of electrical components fabricated on a common foundation called a substrate. The electrical components are typically fabricated on a wafer of semiconductor material that serves as a substrate. Various fabrication techniques, such as layering, doping, masking, and etching, are used to build millions of resistors, transistors, and other electrical components on the wafer. The components are then wired together, or interconnected, to define a specific electrical circuit, such as a processor or a memory device.
- Fusible elements are employed in integrated circuits to permit changes in the configuration of the integrated circuits after fabrication. For example, fusible elements may be used to replace defective circuits with redundant circuits. Memory devices are typically fabricated with redundant memory cells. The redundant memory cells may be enabled with fusible elements after fabrication to replace defective memory cells found during a test of fabricated memory devices. Fusible elements are also used to customize the configuration of a generic integrated circuit after it is fabricated, or to identify an integrated circuit.
- One type of fusible element is a polysilicon fuse. The polysilicon fuse comprises a polysilicon conductor fabricated to conduct electrical current on an integrated circuit. A portion of the polysilicon fuse may be evaporated or opened by a laser beam to create an open circuit between terminals of the polysilicon fuse. The laser beam may be used to open selected polysilicon fuses in an integrated circuit to change its configuration. The use of polysilicon fuses is attended by several disadvantages. Polysilicon fuses must be spaced apart from each other in an integrated circuit such that when one of them is being opened by a laser beam the other polysilicon fuses are not damaged. A bank of polysilicon fuses therefore occupies a substantial area of an integrated circuit. In addition, polysilicon fuses cannot be opened once an integrated circuit is placed in an integrated circuit package, or is encapsulated in any manner.
- Another type of fusible element is an antifuse. An antifuse comprises two conductive terminals separated by an insulator or a dielectric, and is fabricated as an open circuit. The antifuse is programmed by applying a high voltage across its terminals to rupture the insulator and form an electrical path between the terminals.
- Antifuses have several advantages that are not available with fuses. A bank of antifuses takes up much less area of an integrated circuit because they are programmed by a voltage difference that can be supplied on wires connected to the terminals of each of the antifuses. The antifuses may be placed close together in the bank, and adjacent antifuses are not at risk when one is being programmed. Antifuses may also be programmed after an integrated circuit is placed in an integrated circuit package, or encapsulated, by applying appropriate signals to pins of the package. This is a significant advantage for several reasons. First, an integrated circuit may be tested after it is in a package, and may then be repaired by replacing defective circuits with redundant circuits by programming selected antifuses. A generic integrated circuit may be tested and placed in a package before it is configured to meet the specifications of a customer. This reduces the delay between a customer order and shipment. The use of antifuses to customize generic integrated circuits also improves the production yield for integrated circuits because the same generic integrated circuit may be produced to meet the needs of a wide variety of customers.
- Despite their advantages, the use of antifuses in integrated circuits is limited by a lack of adequate circuitry to support the programming and reading of the antifuses. There exists a need for improved circuits and methods for programming and reading antifuses in integrated circuits.
- The above mentioned and other deficiencies are addressed in the following detailed description. According to embodiments of the present invention several support circuits have elements to program and read antifuses. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.
- The embodiments of the present invention support the programming and reading of antifuses in an integrated circuit, and facilitate all the advantages associated with the use of antifuses in integrated circuits. Other advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description.
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FIG. 1 is a cross-sectional view of an antifuse according to an embodiment of the present invention. -
FIG. 1A is a cross-sectional view of an antifuse according to an embodiment of the present invention. -
FIG. 1B is a cross-sectional view of an antifuse according to an embodiment of the present invention. -
FIG. 2 is a cross-sectional view of an antifuse according to an embodiment of the present invention. -
FIG. 2A is a cross-sectional view of an antifuse according to an embodiment of the present invention. -
FIG. 3 is an electrical schematic diagram of a portion of an integrated circuit according to an embodiment of the present invention. -
FIG. 4 is an electrical schematic diagram of an antifuse bank according to an embodiment of the present invention. -
FIG. 5 is a block diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 6 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention. -
FIG. 7 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention. -
FIG. 8 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention. -
FIG. 8A is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention. -
FIG. 9 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention. -
FIG. 10 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 11 is a cross-sectional view of an n-channel transistor according to an embodiment of the present invention. -
FIG. 12 is a cross-sectional view of a diode according to an embodiment of the present invention. -
FIG. 13 is a cross-sectional view of a diode according to an embodiment of the present invention. -
FIG. 14 is a cross-sectional view of a diode according to an embodiment of the present invention. -
FIG. 15 is a cross-sectional view of a diode according to an embodiment of the present invention. -
FIG. 16 is a cross-sectional view of a diode according to an embodiment of the present invention. -
FIG. 17 is a cross-sectional view of a p-channel transistor according to an embodiment of the present invention. -
FIG. 18 is an electrical schematic diagram of an integrated circuit with a common bus line driver circuit according to an embodiment of the present invention. -
FIG. 19 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 20 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 21 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 22 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 23 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 24 is an electrical schematic diagram of an integrated circuit with a common bus line driver circuit according to an embodiment of the present invention. -
FIG. 25 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 26 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 27 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention. -
FIG. 28 is a block diagram of a static random access memory device according to an embodiment of the present invention. -
FIG. 29 is an electrical schematic diagram of an integrated circuit package according to an embodiment of the present invention. -
FIG. 30 is a block diagram of an information-handling system according to an embodiment of the present invention. - In the following detailed description of exemplary embodiments of the present invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.
- The terms wafer and substrate may be used in the following description and include any structure having an exposed surface with which to form an integrated circuit (IC) according to embodiments of the present invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during fabrication, and may include other layers that have been fabricated thereupon. The term substrate includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor, or semiconductor layers supported by an insulator, as well as other semiconductor structures well known to one skilled in the art. The term insulator is defined to include any material that is less electrically conductive than materials generally referred to as conductors by those skilled in the art.
- The term “horizontal” as used in this application is defined as a plane substantially parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction substantially perpendicular to the horizonal as defined above. Prepositions, such as “on,” “upper,” “side” (as in “sidewall”), “higher,” “lower,” “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
- Antifuses and transistors described herein according to embodiments of the present invention may have wells that may be formed in other wells or tanks rather than substrates. Such wells or tanks may be situated with other wells or tanks, or within other wells or tanks, in a larger substrate. The wells or tanks may also be situated in a silicon-on-insulator (SOI) device.
- The term “source/drain” refers generally to the terminals or diffusion regions of a field effect transistor. A terminal or a diffusion region may be more specifically described as a “source” or a “drain” on the basis of a voltage applied to it when the field effect transistor is in operation.
- P-type conductivity is conductivity associated with holes in a semiconductor material, and n-type conductivity is conductivity associated with electrons in a semiconductor material. Throughout this specification the designation “n+” refers to semiconductor material that is heavily doped n-type semiconductor material, e.g., monocrystalline silicon or polycrystalline silicon. Similarly, the designation “p+” refers to semiconductor material that is heavily doped p-type semiconductor material. The designations “n−” and “p−” refer to lightly doped n and p-type semiconductor materials, respectively.
- In this description a transistor is described as being activated or switched on when it is rendered conductive by a control gate voltage that is separated from its source voltage by at least its threshold voltage. The transistor is described as being in an inactive state or switched off when the control gate voltage is separated from its source voltage by less than the threshold voltage and the transistor is rendered non-conductive. A digital signal of 1 may be called a high signal and a digital signal of 0 may be called a low signal. Embodiments of the present invention described herein may be coupled to receive a power supply voltage Vcc which is within approximately 1 to 5 volts. By way of example in this description, and not by way of limitation, Vcc is approximately 3 volts. Two supply voltages, VccX and VccR, may be used in an integrated circuit to improve the noise margin of the embodiments of the invention described herein. VccX is an external supply voltage coupled to the integrated circuit. VccR is a regulated supply voltage generated inside the integrated circuit, and is often less than VccX. By way of example in this description, and not by way of limitation, VccX is approximately 3 volts, and VccR is between 2 volts and 3 volts. Embodiments of the present invention described herein may also be coupled to receive a ground voltage reference Vss, and a bulk node voltage Vbb. The voltage Vbb may be approximately equal to Vss, or may be slightly less than Vss such as approximately minus 1 to
minus 2 volts. Vbb is often coupled to p-type wells and p-type substrates in integrated circuits described herein. Vcc, VccX, VccR, Vss, and Vbb are received directly or are generated by circuits that are not shown for purposes of brevity, but are known to those skilled in the art. - A cross-sectional view of an
antifuse 100 according to an embodiment of the present invention is shown inFIG. 1 . An n-type well 110 is formed in a p-type substrate 112, and an n+-typesource diffusion region 114 and an n+-typedrain diffusion region 116 are formed in thewell 110. Each of the n+-type diffusion regions well 110. A p-type gate electrode 120 is formed over a layer of gate dielectric 122 which is formed over the well 110 between thesource diffusion region 114 and thedrain diffusion region 116. One ormore spacers 123 are formed on the sides of thegate dielectric 122 and thegate electrode 120. Thegate electrode 120 is connected to afirst terminal 124 of theantifuse 100, and asecond terminal 126 is connected to each of the n+-type diffusion regions gate electrode 120 comprises polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 122 may be oxide, oxynitride, or nitrided oxide. A p+-type diffusion region 130 is formed in thesubstrate 112 to provide an ohmic contact coupling thesubstrate 112 to Vbb. - Two separate circuits in an integrated circuit may be connected respectively to the first and
second terminals antifuse 100. Theantifuse 100 is an open circuit between the terminals until it is programmed in the following manner. The p-type substrate 112 is coupled to Vbb and thefirst terminal 124 attached to the p-type gate electrode 120 is coupled to a low voltage. Thesecond terminal 126 is coupled to bring the well 110 to a positive elevated voltage, such as approximately 15 volts. A voltage drop between the well 110 and the p-type gate electrode 120 is enough to rupture thegate dielectric 122. When programmed theantifuse 100 has a conductive connection between the first andsecond terminals type gate electrode 120 and the well 110 allows current to flow. The programmed antifuse 100 is an impedance element similar to a diode between the circuits. - A cross-sectional view of an
antifuse 140 according to an embodiment of the present invention is shown inFIG. 1A . Theantifuse 140 is similar to theantifuse 100 shown inFIG. 1 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theantifuse 140 is one-sided because it has only a single n+-type diffusion region 142. The n+-type diffusion region 142 takes the place of the n+-type diffusion regions antifuse 100, and is connected to thesecond terminal 126. Theantifuse 140 is programmed and functions in a manner similar to theantifuse 100. - A cross-sectional view of an
antifuse 150 according to an embodiment of the present invention is shown inFIG. 1B . Theantifuse 150 is similar to theantifuse 100 shown inFIG. 1 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theantifuse 150 is offset because it has an n+-type diffusion region 152 that is offset from thegate electrode 120 and thespacers 123. The n+-type diffusion region 152 takes the place of the n+-type diffusion regions antifuse 100, and is connected to thesecond terminal 126. Theantifuse 150 is programmed and functions in a manner similar to theantifuse 100. - A cross-sectional view of an
antifuse 200 according to another embodiment of the present invention is shown inFIG. 2 . An n-type well 210 is formed in a p-type substrate 212, and an n+-typesource diffusion region 214 and an n+-typedrain diffusion region 216 are formed in thewell 210. Each of the n+-type diffusion regions well 210. An n-type gate electrode 220 is formed over a layer of gate dielectric 222 which is formed over the well 210 between thesource diffusion region 214 and thedrain diffusion region 216. One ormore spacers 223 are formed on the sides of thegate dielectric 222 and thegate electrode 220. Thegate electrode 220 is connected to afirst terminal 224 of theantifuse 200, and asecond terminal 226 is connected to each of the n+-type diffusion regions gate electrode 220 comprises polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 222 may be oxide, oxynitride, or nitrided oxide. A p+-type diffusion region 230 is formed in thesubstrate 212 to provide an ohmic contact coupling thesubstrate 212 to Vbb. - The
antifuse 200 is an open circuit between the first andsecond terminals antifuse 100 described above. When programmed theantifuse 200 is an impedance element similar to a resistor between the first andsecond terminals - A cross-sectional view of an
antifuse 250 according to an embodiment of the present invention is shown inFIG. 2A . Theantifuse 250 is similar to theantifuse 200 shown inFIG. 2 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theantifuse 250 has ametal gate electrode 260 instead of thegate electrode 220 shown inFIG. 2 . Theantifuse 250 is programmed and functions in a manner similar to theantifuse 200. Once theantifuse 250 is programmed themetal gate electrode 260 forms a schottky barrier with the n-type well 210. A conductive connection between the first andsecond terminals - In alternate embodiments of the present invention the
antifuses type diffusion regions antifuse 140. The n+-type diffusion regions respective spacers spacers type diffusion region 152 in theantifuse 150. - The
gate dielectrics Antifuses thinner gate dielectrics - The
antifuses - The
antifuses FIGS. 1, 1A , 1B, 2, and 2A may be used for a variety of purposes in an integrated circuit. For example, theantifuses integrated circuit 300 is shown inFIG. 3 according to an embodiment of the present invention. Theintegrated circuit 300 may be a memory device, a processor, or any other type of integrated circuit device by way of example and not by way of limitation. Theintegrated circuit 300 includes a number ofcircuits direct connections antifuses FIGS. 1, 1A , 1B, 2, and 2A described above. One or more of the antifuses 340-346 is programmed according to the methods discussed above to provide electrically conductive couplings between two or more of the circuits 310-320 to change the configuration of theintegrated circuit 300. The circuits 310-320 may be separate components or devices as well as circuits, and theintegrated circuit 300 could include more or less circuits, devices, components, and antifuses according to alternate embodiments of the present invention. - The
antifuses FIGS. 1, 1A , 1B, 2, and 2A may be arranged in banks of antifuses in an integrated circuit, and anantifuse bank 400 is shown inFIG. 4 according to an embodiment of the present invention. Thebank 400 includes fourantifuses antifuses FIGS. 1, 1A , 1B, 2, and 2A. Thebank 400 may have more or less than four antifuses according to alternate embodiments of the present invention. The antifuses 410-416 are coupled in parallel to aprogramming logic circuit 420, and each of the antifuses 410-416 may be programmed in a similar manner. For example, theantifuse 410 has a first terminal coupled to theprogramming logic circuit 420 and a second terminal coupled to anexternal pin 430 and abias circuit 440 through acommon bus line 442. The first and second terminals correspond to the terminals of one of theantifuses external pin 430 is external to an integrated circuit including thebank 400, and will be more fully described hereinbelow. Thebias circuit 440 may be a transistor, a group of transistors coupled together, or a high breakdown voltage resistor. The second terminal is also coupled to an electro-static discharge (ESD)device common bus line 442. - The
bank 400 is operated on one of three modes: a programming mode, an active mode, and a sleep mode. The antifuses 410-416 are programmed in the programming mode, and the active and sleep modes will be described hereinbelow. In the programming mode, an elevated voltage is applied to theexternal pin 430 and thecommon bus line 442 that exceeds Vcc of the integrated circuit by a substantial amount. The elevated voltage provides the potential necessary to rupture the gate dielectrics of the antifuses 410-416 selected to be programmed. The elevated voltage is removed from theexternal pin 430 during the active and sleep modes and the integrated circuit operates from Vcc. In the active and sleep modes theexternal pin 430 may be allowed to float, or it may be coupled to a reference voltage such as Vss. The use of theexternal pin 430 to couple the elevated voltage to the antifuses 410-416 in the programming mode substantially protects other portions of the integrated circuit from damage that may be caused by the elevated voltage. - One of the antifuses 410-416 may be similar to the
antifuse 100 shown inFIG. 1 , and a programming of theantifuse 100 in thebank 400 will now be described. In the programming mode the p-type substrate 112 is coupled to Vbb and an elevated voltage, such as approximately 15 volts, is coupled to the well 110 from theexternal pin 430 through thecommon bus line 442, thesecond terminal 126, and thediffusion regions antifuse 100 is selected to be programmed by theprogramming logic circuit 420 which couples a sufficiently low potential to the p-type gate electrode 120 to rupture thegate dielectric 122 in theantifuse 100. Theprogramming logic circuit 420 may prevent others of the antifuses 410-416 from being programmed by raising a potential of the p-type gate electrodes 120 to prevent thegate dielectrics 122 from being ruptured. The operation of theprogramming logic circuit 420 will be more fully described hereinbelow according to embodiments of the present invention. - One of the antifuses 410-416 may be similar to one of the
antifuses FIGS. 1A, 1B , 2, and 2A and a programming of one of theantifuses bank 400 will be similar to the programming of theantifuse 100 described above. Those skilled in the art having the benefit of this description will recognize that the voltage levels recited herein may be changed depending on characteristics of the antifuses 410-416 in thebank 400. -
Additional support circuits 500 in theprogramming logic circuit 420 are shown in a block diagram inFIG. 5 according to an embodiment of the present invention. Thecircuits 500 are for programming and reading the antifuses 410-416 in thebank 400, and are shown for programming and reading asingle antifuse 510 for purposes of brevity. Additional, similar circuits may be used to program and read a larger number of antifuses. Theantifuse 510 has the structure and operational method of one of theantifuses FIGS. 1, 1A , 1B, 2, and 2A. Theantifuse 510 has a first terminal coupled to anexternal pin 520 through acommon bus line 530, and a second terminal coupled to aprogram driver circuit 542. Theexternal pin 520 corresponds to theexternal pin 430 shown inFIG. 4 . Theprogram driver circuit 542 is used to select theantifuse 510 to be programmed. Aread circuit 544 is coupled to theantifuse 510 through theprogram driver circuit 542 to read a state of theantifuse 510 during the active and sleep modes, and a floating welldriver logic circuit 550 is coupled to theread circuit 544. Theantifuse 510 is one of several antifuses in a bank (not shown), and the floating welldriver logic circuit 550 is also coupled to a read circuit for each of the other antifuses in the bank. In the programming mode an elevated voltage is applied to thecommon bus line 530 through theexternal pin 520 to program theantifuse 510. A common busline driver circuit 560 is coupled to thecommon bus line 530 to drive thecommon bus line 530 to a reference voltage such as Vss when theantifuse 510 is being read by theread circuit 544. In other embodiments of the present invention the floating welldriver logic circuit 550 or the common busline driver circuit 560 may not be needed or included in thecircuits 500. - The common bus
line driver circuit 560 and theprogram driver circuit 542 each include a high-voltage transistor (HVT). One example of such a HVT is an n-well drain transistor 600, a cross-sectional view of which is shown inFIG. 6 according to an embodiment of the present invention. An n-type well 610 is formed in a p-type substrate 612, and an n+-typedrain diffusion region 616 is formed in thewell 610. An n+-typesource diffusion region 618 is formed in thesubstrate 612. Agate electrode 620 is formed over a layer of gate dielectric 622 which is formed over thesubstrate 612 between the source and draindiffusion regions gate electrode 620 is connected to a gate terminal 624. Likewise, adrain terminal 626 is connected to the n+-typedrain diffusion region 616 and asource terminal 628 is connected to the n+-typesource diffusion region 618. In alternate embodiments of the present invention thegate electrode 620 comprises metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 622 may be oxide, oxynitride, or nitrided oxide. A p+-type diffusion region 640 is formed in thesubstrate 612 to provide an ohmic contact coupling thesubstrate 612 to Vbb. - The n-
well drain transistor 600 has a high drain breakdown voltage. In operation thesubstrate 612 is coupled to Vbb and thedrain terminal 626 is coupled to a line with a high positive voltage, such as thecommon bus line 530 shown inFIG. 5 during the programming mode. The n-well drain transistor 600 will break down and allow current to flow between thedrain terminal 626 and thesubstrate 612 when a critical electric field intensity (E) is reached across a boundary between the n-type well 610 and the p-type substrate 612. E may be approximated as the voltage drop across the boundary divided by a width of a depletion region at the boundary of the n-type well 610 and the p-type substrate 612. Dopant concentrations in the n-type well 610 and the p-type substrate 612 are relatively low such that the width of the depletion region between the two is relatively large. The boundary will not break down even under a very large voltage drop across the boundary because the E is less than the critical E. As a result, the n-well drain transistor 600 will not break down even if the voltage on thedrain terminal 626 is relatively high. In contrast, an ordinary n-channel transistor does not have the n-type well 610, and there is a boundary between a p-type substrate and an n+-type drain diffusion region with a very high dopant concentration. A depletion region at this boundary is not very wide, and as a consequence it will break down under a smaller voltage. - Other examples of a HVT will now be described. A cross-sectional view of an n-
well drain transistor 700 is shown inFIG. 7 according to another embodiment of the present invention. An n-type well 710 is formed in a drain side of a p-type substrate 712, and a p-type halo implant 714 is formed in a source side of thesubstrate 712. An n-type lightly doped drain (LDD) 716 is implanted inside thehalo implant 714. Agate 720 is formed over a layer of gate dielectric 722 which is formed over thesubstrate 712 between the n-type well 710 and thehalo implant 714. Anelectrode 724 is formed over thegate 720. In alternate embodiments of the present invention gate may comprise polysilicon and theelectrode 724 may comprise a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 722 may be oxide, oxynitride, or nitrided oxide. Thegate 720 and theelectrode 724 may also comprise metal. One ormore spacers 726 are then formed on the sides of thegate dielectric 722, thegate 720, and theelectrode 724. An n+-typesource diffusion region 730 is implanted inside theLDD 716 and thehalo implant 714. Also, an n+-typedrain diffusion region 732 is implanted in the n-type well 710. Thedrain diffusion region 732 is not surrounded by LDD or halo implants which are blocked from the drain side of thesubstrate 712. Asource terminal 740 is connected to thesource diffusion region 730, agate terminal 742 is connected to theelectrode 724, and adrain terminal 744 is connected to thedrain diffusion region 732. A p+-type diffusion region 760 is formed in thesubstrate 712 to provide an ohmic contact coupling thesubstrate 712 to Vbb. The n-well drain transistor 700 has a high drain breakdown voltage for reasons analogous to those recited in the description of the n-well drain transistor 600 shown inFIG. 6 . - A cross-sectional view of an n-
channel transistor 800 is shown inFIG. 8 which is a HVT according to an embodiment of the present invention. A p-type halo implant 810 is formed in a source side of a p-type substrate 812. An n-type lightly doped drain (LDD) 816 is implanted inside thehalo implant 810. Agate 820 is formed over a layer of gate dielectric 822 which is formed over thesubstrate 812. Anelectrode 824 is formed over thegate 820. In alternate embodiments of the present invention thegate 820 comprises polysilicon and theelectrode 824 may comprise a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate 820 and theelectrode 824 may comprise metal. Thegate dielectric 822 may be oxide, oxynitride, or nitrided oxide. One ormore spacers 826 are then formed on the sides of thegate dielectric 822, thegate 820, and theelectrode 824. An n+-typesource diffusion region 830 is implanted inside theLDD 816 and thehalo implant 810. Also, an n+-typedrain diffusion region 832 is implanted in thesubstrate 812. Thedrain diffusion region 832 is not surrounded by LDD or halo implants which are blocked from a drain side of thesubstrate 812. Asource terminal 840 is connected to thesource diffusion region 830, agate terminal 842 is connected to theelectrode 824, and adrain terminal 844 is connected to thedrain diffusion region 832. Thedrain diffusion region 832 and thesource diffusion region 830 are self-aligned with thespacers 826. A p+-type diffusion region 860 is formed in thesubstrate 812 to provide an ohmic contact coupling thesubstrate 812 to Vbb. The n-channel transistor 800 has a high drain breakdown voltage and may be used in embodiments of the present invention described above in place of the n-well drain transistor 600 shown inFIG. 6 . - A cross-sectional view of an n-
channel transistor 860 is shown inFIG. 8A which is a HVT according to an embodiment of the present invention. Thetransistor 860 is similar to thetransistor 800 shown inFIG. 8 , and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. In addition to the elements of thetransistor 800, the LDD implant is not blocked, and an n-type LDD 862 is implanted in a drain side of the p-type substrate 812. An n+-typedrain diffusion region 864 is implanted inside theLDD 862 in place of thedrain diffusion region 832 of thetransistor 800. Thetransistor 860 functions in a manner similar to thetransistor 800. - The
transistors FIGS. 6, 7 , 8, and 8A may be fabricated according to process steps used to fabricate field-effect transistors in an integrated circuit, and do not require extra process steps. In another embodiment of the present invention, an added mask and implant could be applied to thedrain diffusion region 832 to customize the high drain breakdown voltage of thetransistor 800. - A cross-sectional view of an n-
well drain transistor 900 is shown inFIG. 9 which is a HVT according to another embodiment of the present invention. An n-type well 910 is formed in a drain side of a p-type substrate 912, and a p-type halo implant 914 is formed in a source side of thesubstrate 912 and blocked from the drain side. Two n-type lightly doped drains (LDD) 916 and 917 are implanted inside thehalo implant 914 and the n-type well 910. Agate 920 is formed over a layer of gate dielectric 922 which is formed over thesubstrate 912 between the n-type well 910 and thehalo implant 914. Anelectrode 924 is formed over thegate 920. In alternate embodiments of the present invention thegate 920 comprises polysilicon and theelectrode 924 may comprise a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 922 may be oxide, oxynitride, or nitrided oxide. Thegate 920 and theelectrode 924 may comprise metal. One ormore spacers 926 are then formed on the sides of thegate dielectric 922, thegate 920, and theelectrode 924. An n+-typesource diffusion region 930 is implanted inside theLDD 916 and thehalo implant 914. Also, an n+-typedrain diffusion region 932 is implanted in theLDD 917 and the n-type well 910. Thedrain diffusion region 932 in theLDD 917 is not surrounded by a halo implant which was blocked. Asource terminal 940 is connected to thesource diffusion region 930, agate terminal 942 is connected to theelectrode 924, and adrain terminal 944 is connected to thedrain diffusion region 932. Thedrain diffusion region 932 and thesource diffusion region 930 are self-aligned with thespacers 926. A p+-type diffusion region 960 is formed in thesubstrate 912 to provide an ohmic contact coupling thesubstrate 912 to Vbb. The n-well drain transistor 900 has a high drain breakdown voltage for reasons analogous to those recited in the description of the n-well drain transistor 600 shown inFIG. 6 . - Several of the
circuits 500 shown inFIG. 5 are shown in greater detail inFIG. 10 . An electrical schematic diagram ofseveral support circuits 1000 for programming and reading antifuses is shown inFIG. 10 according to an embodiment of the present invention. Thecircuits 1000 are located in theprogramming logic circuit 420 shown inFIG. 4 , and include aprogram driver circuit 1010, aread circuit 1011, and a floating welldriver logic circuit 1012. Theprogram driver circuit 1010 is coupled to agate electrode 1014 of anantifuse 1016, and a well 1018 of theantifuse 1016 is coupled through acommon bus line 1020 to anexternal pin 1022. Theantifuse 1016 is similar in structure and operation to theantifuse 100 shown inFIG. 1 . - The
program driver circuit 1010 includes aHVT 1024 having adrain terminal 1026, asource terminal 1028, and agate terminal 1030. TheHVT 1024 is similar in structure and operating characteristics to the n-well drain transistor 600 shown inFIG. 6 . Thedrain terminal 1026 is coupled to thegate electrode 1014 of theantifuse 1016. Thegate terminal 1030 is coupled to acathode 1033 of adiode 1034, and ananode 1038 of thediode 1034 is coupled to Vcc. Thediode 1034 is forward biased as long as Vcc exceeds a voltage at thegate terminal 1030. Thegate terminal 1030 is coupled to acathode 1040 of adiode 1042. Ananode 1044 of thediode 1042 is coupled to Vbb. Thediodes gate terminal 1030 at a voltage slightly less than Vcc, or higher. Current will flow through theHVT 1024 as long as the other elements of thecircuits 1000 allow current to flow, as will be described hereinbelow. - The
program driver circuit 1010 also includes a first n-channel transistor 1045 and a second n-channel transistor 1046 coupled in cascode between thesource terminal 1028 and Vss. A gate terminal of thetransistor 1045 is coupled to Vcc, and thetransistor 1045 is switched on as long as Vcc exceeds a voltage at its source terminal by a threshold voltage VT of thetransistor 1045. A gate terminal of thetransistor 1046 is coupled to alogic circuit 1048 which controls theprogram driver circuit 1010 during the programming, active, and sleep modes. A body terminal of thetransistor 1046 is coupled to Vbb. - The
transistor 1046 is switched off by thelogic circuit 1048 in each of the programming, active, and sleep modes, and is switched on for a short period to program theantifuse 1016 in the programming mode. In the active mode, current may flow from theread circuit 1011 through theHVT 1024 and theantifuse 1016 to thecommon bus line 1020. A more detailed description of the active mode is recited below. No substantial current passes through thetransistors - The
common bus line 1020 is coupled to receive an elevated voltage in the programming mode, for example 15 volts, through theexternal pin 1022. Before it is programmed the elevated voltage on thecommon bus line 1020 is distributed across theantifuse 1016, thetransistors diodes antifuse 1016 is programmed it is an impedance element and the distribution of the elevated voltage changes. Thetransistor 1046 is switched off and no current path exists through theread circuit 1011 in the programming mode so no substantial current passes through theHVT 1024. Voltages along theprogram driver circuit 1010 rise as a result, and the elevated voltage is distributed across thetransistors diodes - The
antifuse 1016 may be selected to be programmed by thelogic circuit 1048 by switching on thetransistor 1046 and conduct current from thecommon bus line 1020 through to Vss. Thetransistor 1046 is switched on for a short period of time to allow the elevated voltage on thecommon bus line 1020 to rupture a gate dielectric in theantifuse 1016, and is then switched off. - The two
transistors transistor 1046 is switched off. Snap-back occurs when there is current flowing between a source terminal and a drain terminal of a transistor that cannot be shut off by a voltage at a gate terminal of the transistor. Snap-back may start if the transistor is switched on by a high voltage at the gate terminal, a voltage at the drain terminal is very high, and a substantial current is passing through the transistor. If the voltage at the gate terminal is reduced to a low voltage the transistor may not switch off if the voltage at the drain terminal is too high and there is too much current conducting through the transistor. Snap-back may occur in thetransistor 1046 as theantifuse 1016 is programmed and thelogic circuit 1048 attempts to switch off thetransistor 1046 with a low voltage on its gate terminal. The elevated voltage on thecommon bus line 1020 and the current passing through theantifuse 1016 may be high enough to cause snap-back in thetransistor 1046. - One way of reducing snap back is to lower the voltage on the
common bus line 1020 after an antifuse is programmed. This method substantially slows the programming of a sequence of antifuses because the voltage must be lowered after each antifuse is programmed. In theprogram driver circuit 1010, snap-back is substantially prevented in thetransistor 1046 by thetransistor 1045 which is placed to reduce the voltage on the drain terminal of thetransistor 1046. Thetransistor 1045 reduces the voltage on the drain terminal of thetransistor 1046 to approximately Vcc less a threshold voltage of thetransistor 1045, which is enough to substantially prevent snap-back. Thetransistors - The
transistor 1045 is also employed to reduce current leakage through theantifuse 1016. If theantifuse 1016 is unprogrammed, any current leakage through it will degrade its gate dielectric. It is therefore advantageous to reduce sources of current leakage in theprogram driver circuit 1010 as much as possible. - One source of current leakage in the
program driver circuit 1010 is thetransistor 1046. Current may leak through thetransistor 1046 due to drain induced barrier lowering (DIBL). Thetransistor 1046 is an n-channel transistor and is switched on to conduct current between its drain and source terminals when the voltage at its gate terminal exceeds the voltage at its source terminal by a threshold voltage VT of thetransistor 1046. The difference between the voltage at the gate terminal and the voltage at the source terminal is called VGS. DIBL leakage current flows between the drain terminal and the source terminal at a subthreshold VGS, when VGS is less than VT of thetransistor 1046. DIBL leakage current therefore occurs when thetransistor 1046 is switched off, and this current can damage theantifuse 1016 when it is unprogrammed. The subthreshold VGS is lowered as the voltage at the drain terminal of thetransistor 1046 increases, and the DIBL leakage current will therefore occur at lower and lower values of VGS. If the voltage at the drain terminal is high enough, DIBL leakage current will occur when VGS is zero. Thetransistor 1045 reduces DIBL leakage current by reducing the voltage at the drain terminal of thetransistor 1046, and therefore reduces leakage current through theantifuse 1016. - Current may also leak through the
transistor 1046 due to gate induced drain leakage (GIDL). Thetransistor 1046 is similar to a conventional n-channel transistor and has n+-type source and drain regions separated by a channel region in a p-type substrate that is coupled to Vbb. A thin layer of oxide separates the channel region from a gate electrode. The source and drain regions and the gate electrode are connected to the corresponding terminals described above, the n+-type drain region being coupled to thetransistor 1045. The n+-type drain region and the p-type substrate comprise a parasitic diode which is reverse biased with a positive voltage on the drain terminal of thetransistor 1046. GIDL current leaks across the reverse biased parasitic diode, and increases with an increase of an electric field intensity (E) near the drain region which is increased due to the proximity of the gate electrode. GIDL current increases with a rising voltage on the drain terminal of thetransistor 1046 which raises E near the drain region. Thetransistor 1045 reduces GIDL current by reducing the voltage at the drain terminal of thetransistor 1046, and therefore reduces leakage current through theantifuse 1016. - Snap-back and the DIBL and GIDL leakage current described above may be substantially prevented without the use of the
transistor 1045 according to alternate embodiments of the present invention. In an alternate embodiment of the present invention, the cascode configuration of thetransistors single transistor 1046. - For example, DIBL leakage current may flow in the
transistor 1046 even if the voltage at its drain terminal is not elevated due to process conditions in which thetransistor 1046 is fabricated. A method that may be used to reduce DIBL leakage current is to adjust an implant for thetransistor 1046, or to add a masked implant step to raise the threshold voltage of thetransistor 1046. Another method is to lower Vbb, the voltage coupled to the body terminal of thetransistor 1046, to raise its threshold voltage. These methods may be used if thetransistor 1046 is employed alone or as part of the cascode configuration with thetransistor 1045. - The
read circuit 1011 includes elements used to read a state of theantifuse 1016, and these elements will now be described. Theread circuit 1011 includes a first p-channel transistor 1050 and a second p-channel transistor 1052. Thetransistor 1052 is switched on by a bias voltage BIAS applied to its gate terminal, and its source terminal is coupled to Vcc. The voltage BIAS is generated by a current mirror (not shown) and is approximately equal to Vcc less an amount selected to control current through thetransistor 1052. A drain terminal of thetransistor 1052 is coupled to a source terminal of thetransistor 1050, and the drain terminal of thetransistor 1050 is coupled to thesource terminal 1028 of theHVT 1024. The gate terminal of thetransistor 1050 is coupled to a signal TZZ1 which is low when theprogramming logic circuit 420 is in the active mode to read theantifuse 1016 as will be described hereinbelow. Thetransistor 1050 is therefore switched on to read theantifuse 1016. Aninverter 1054 is coupled to thesource terminal 1028 and generates an output signal OUTPUT at an output indicating the state of theantifuse 1016. - When the
antifuse 1016 is read thecommon bus line 1020 is coupled to Vss and the impedance of theantifuse 1016 is compared with the impedance of thetransistor 1052 that is switched on by the voltage BIAS. Thetransistor 1052 may be replaced by a resistor or other load device in alternate embodiments of the present invention. Thetransistor 1050 is switched on to create a current path from Vcc through thetransistors antifuse 1016 to thecommon bus line 1020. If the antifuse is programmed and has a low impedance a very low voltage will occur at thesource terminal 1028 that is inverted by theinverter 1054 into a high OUTPUT signal indicating theantifuse 1016 is programmed. If theantifuse 1016 is unprogrammed it will have a very high impedance and the voltage at thesource terminal 1028 will be close to Vcc. Theinverter 1054 will invert this high voltage into a low OUTPUT signal indicating that theantifuse 1016 is unprogrammed. - With reference to the
bank 400 shown inFIG. 4 , once one of the antifuses 410416 in thebank 400 is programmed, it is an impedance element similar to a diode or a resistor, and provides a possible current path for current on thecommon bus line 442. It is desirable to limit current on thecommon bus line 442, and therefore additional sources of current on thecommon bus line 442 are to be substantially eliminated as far as is possible. For this reason, thecircuits 1000 include several features to substantially eliminate current flow from thecommon bus line 1020 through theantifuse 1016, and these features will now be described. - The
HVT 1024 is a possible source of current flow from thecommon bus line 1020 during the programming mode when thecommon bus line 1020 is at the elevated voltage and theantifuse 1016 is programmed. The elevated voltage may induce breakdown current in theHVT 1024, and this does not occur through its substrate because of the high drain breakdown voltage of theHVT 1024. The elevated voltage is distributed across thetransistors diodes - The
diode 1034 and thediode 1042 substantially prevent breakdown current across the gate dielectric in the following manner. With reference to bothFIGS. 6 and 10 , thedrain terminal 1026 is connected to thedrain diffusion region 616, thegate terminal 1030 is connected to thegate electrode 620, and thesource terminal 1028 is connected to thesource diffusion region 618. The voltage at thegate electrode 620 is insulated from the voltage at thedrain diffusion region 616 by thegate dielectric 622. However, current will flow across thegate dielectric 622 if a voltage differential between thedrain diffusion region 616 and thegate electrode 620 is large. Thegate dielectric 622 may even break down and become a resistive element if the voltage differential is large enough. Thediode 1034 and thediode 1042 hold charge at thegate terminal 1030 such that its voltage rises as current passes across thegate dielectric 622. Thediode 1034 allows the voltage at thegate terminal 1030 to rise above Vcc until the voltage difference across thegate dielectric 622 is too small to induce further current flow to thegate electrode 620. The voltage at thegate terminal 1030 will not rise above a breakdown voltage of thediode 1042. The elevated voltage at thedrain terminal 1026 is divided into two portions, a first portion held across thegate dielectric 622, and a second portion held across a depletion region in thediode 1042. The coupling of thediode 1034 and thediode 1042 thereby reduces damage to thegate dielectric 622 by bearing a portion of the elevated voltage and reducing the voltage drop across thegate dielectric 622 when theantifuse 1016 is programmed and thecommon bus line 1020 is at the elevated voltage. If thegate terminal 1030 were held at Vcc then the large voltage differential would cause continuous current and damage thegate dielectric 622 when thedrain terminal 1026 was at the elevated voltage. - The structure including the
HVT 1024 and thediodes program driver circuit 1010 the following operating characteristics. Current will flow through theHVT 1024 as long as theantifuse 1016 is programmed and either thetransistors read circuit 1011 allow current to flow. If current ceases in theHVT 1024 in the active or sleep modes, then the voltage at thesource terminal 1028 rises to approximately a voltage at thegate terminal 1030 less a threshold voltage VT of theHVT 1024. If the elevated voltage is on thecommon bus line 1020 then a first portion of it is held across thegate dielectric 622, and a second portion of it is held across a depletion region in thediode 1042. This voltage distribution is non-linear, and is determined by the reverse bias characteristics of thediode 1042 and the characteristics of thegate dielectric 622. The voltage distribution may vary over time. The reverse bias characteristics of thediode 1042 may be modified during the operation of thecircuits 1000, particularly in the programming mode, by modulating Vbb. For example, Vbb may be tied to Vss, or raised or lowered by 1 or 2 volts from Vss to change the voltage distribution across thegate dielectric 622 and thediode 1042. - The
diodes channel transistor 1100 shown inFIG. 11 according to an embodiment of the present invention. Thetransistor 1100 is formed in a p-type well 1110 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n+-typedrain diffusion region 1112 and an n+-typesource diffusion region 1114 are formed in thewell 1110. A p+-type welltie diffusion region 1116 is also formed in the well 1110 to provide an ohmic contact to bias thewell 1110. Agate electrode 1120 is formed over a layer of gate dielectric 1122 which is formed over the well 1110 between thedrain diffusion region 1112 and thesource diffusion region 1114. In alternate embodiments of the present invention thegate electrode 1120 may be formed by metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 1122 may be oxide, oxynitride, or nitrided oxide. Thegate electrode 1120 and thedrain diffusion region 1112 comprise theanode 1038 and are connected to Vcc. Thesource diffusion region 1114 comprises thecathodes gate terminal 1030. Thewell 1110 and thediffusion region 1116 comprise theanode 1044 and are coupled to Vbb. - The
diode 1034 may be fabricated as a p+-type diode 1200 shown inFIG. 12 according to an embodiment of the present invention. Thediode 1200 is formed in an n-type well 1210 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n+-type diffusion region 1212 and a p+-type diffusion region 1214 are formed in thewell 1210. The n+-type diffusion region 1212 comprises thecathode 1033 and is connected to thegate terminal 1030, and the p+-type diffusion region 1214 comprises theanode 1038 and is connected to Vcc. - The
diode 1034 may be fabricated as a p-type well diode 1300 shown inFIG. 13 according to an embodiment of the present invention. An n-type triple well 1306 is formed in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n-type isolation region 1308 is also formed in the substrate above the triple well 1306. Thediode 1300 is formed in a p-type well 1310 formed between the triple well 1306 and theisolation region 1308. An n+-type diffusion region 1312 and a p+-type diffusion region 1314 are formed in thewell 1310. The n+-type diffusion region 1312 comprises thecathode 1033 and is connected to thegate terminal 1030, and the p+-type diffusion region 1314 comprises theanode 1038 and is connected to Vcc. - The
diode 1042 may be fabricated as the p+-type diode 1200 shown inFIG. 12 according to an embodiment of the present invention. The n+-type diffusion region 1212 comprises thecathode 1040 and is connected to thegate terminal 1030, and the p+-type diffusion region 1214 comprises theanode 1044 and is connected to Vbb instead of Vcc as shown inFIG. 12 . - The
diode 1042 may be fabricated as an n+diode 1400 shown inFIG. 14 according to an embodiment of the present invention. Thediode 1400 is formed in a p-type well 1410 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n+-type diffusion region 1412 is formed in the well 1410 between regions of shallowtrench isolation oxide 1414. A p+-type diffusion region 1416 is formed in the well 1410 to provide an ohmic contact coupled to Vbb. The n+-type diffusion region 1412 comprises thecathode 1040 and is connected to thegate terminal 1030, and the p+-type diffusion region 1416 and the well 1410 comprise theanode 1044 coupled to Vbb. - The
diode 1042 may be fabricated as an n+-typegated diode 1500 shown inFIG. 15 according to an embodiment of the present invention. Thediode 1500 is formed in a p-type well 1510 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. Agate electrode 1512 is formed over a layer of gate dielectric 1514 which is formed over thewell 1510. Thegate electrode 1512 is connected to Vss. In alternate embodiments of the present invention thegate electrode 1512 may comprise metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 1514 may be oxide, oxynitride, or nitrided oxide. An n+-type diffusion region 1516 is formed in the well 1510 to comprise thecathode 1040 of thediode 1042, and is connected to thegate terminal 1030. A p+-type diffusion region 1518 is formed in the well 1510 to provide an ohmic contact comprising theanode 1044 of thediode 1042 coupled to Vbb. Thegate dielectric 1514 is formed near theregion 1516 and thegate electrode 1512 modulates the performance of thediode 1042 with a strong electric field. - The
diode 1042 may be fabricated as a p+-typegated diode 1600 shown inFIG. 16 according to an embodiment of the present invention. Thediode 1600 is formed in an n-type well 1610 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. Agate electrode 1612 is formed over a layer of gate dielectric 1614 which is formed over thewell 1610. In alternate embodiments of the present invention thegate electrode 1612 comprises metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 1614 may be oxide, oxynitride, or nitrided oxide. An n+-type diffusion region 1616 is formed in the well 1610 to comprise thecathode 1040 of thediode 1042, and is connected to thegate electrode 1612 and to thegate terminal 1030. A p+-type diffusion region 1618 is formed in the well 1610 to comprise theanode 1044 of thediode 1042 coupled to Vbb. Thegate dielectric 1614 is formed near theregion 1618 and thegate electrode 1612 modulates the performance of thediode 1042 with a strong electric field. - The
diodes FIGS. 12-16 may be modified by adding or subtracting implants and mask steps to change their reverse bias characteristics. - The
read circuit 1011 also includes elements that are possible sources of current flow from thecommon bus line 1020. Theread circuit 1011 has several p-channel transistors which are favored over n-channel transistors because p-channel transistors provide a better noise margin by not sustaining a threshold voltage drop from Vcc when theantifuse 1016 is read as described above. However, when theprogramming logic circuit 420 is in the programming mode and there is an elevated voltage on thecommon bus line 1020, the p-channel transistors provide a path for current from thecommon bus line 1020. This will be described with reference to a cross-sectional view of a p-channel transistor 1700 shown inFIG. 17 according to an embodiment of the present invention. Thetransistors channel transistor 1700. - The p-
channel transistor 1700 is formed in an n-type well 1710 in a substrate, a surrounding well, or a tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. A p+-typesource diffusion region 1712 and a p+-typedrain diffusion region 1714 are formed in thewell 1710. An n+-type welltie diffusion region 1716 is also formed in the well 1710 to provide an ohmic contact to bias the well 1710 with a reference voltage. Agate electrode 1720 is formed over a layer of gate dielectric 1722 which is formed over the well 1710 between thesource diffusion region 1712 and thedrain diffusion region 1714. In alternate embodiments of the present invention thegate electrode 1720 may comprise metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2). Thegate dielectric 1722 may be oxide, oxynitride, or nitrided oxide. Thegate electrode 1720 is connected to agate terminal 1730. Asource terminal 1732 is connected to thesource diffusion region 1712, and adrain terminal 1734 is connected to thedrain diffusion region 1714. Finally, areference terminal 1736 is connected to the welltie diffusion region 1716. - As an example for illustrative purposes only, if the p-
channel transistor 1700 is connected in theread circuit 1011 in a manner similar to thetransistor 1050, and if both thegate terminal 1730 and thereference terminal 1736 are coupled to Vcc during the programming mode, then unwanted current may flow in thetransistor 1700 for the following reasons. According to the example, thedrain terminal 1734 is coupled to thesource terminal 1028 of theHVT 1024. If theantifuse 1016 is programmed and the elevated voltage is on thecommon bus line 1020 in the programming mode, a voltage at thesource terminal 1028 will rise. With thegate terminal 1730 and thereference terminal 1736 are both coupled to Vcc, the p-channel transistor 1700 may be switched on because the voltage of thedrain terminal 1734 rises substantially above Vcc at thegate terminal 1730. As a result, device current will pass between thesource terminal 1732 and thedrain terminal 1734 to Vcc. In addition, current may be induced through a parasitic diode comprising thedrain diffusion region 1714 and the well 1710 coupled to Vcc through the welltie diffusion region 1716. This current is substantially eliminated by thelogic circuit 1012. - The
logic circuit 1012 switches off p-channel transistors in theread circuit 1011 when theprogramming logic circuit 420 is in the programming mode and an elevated voltage is on thecommon bus line 1020. Thelogic circuit 1012 switches off the p-channel transistors by raising the voltage potential of thewells 1710 by coupling them to an n-well voltage (NWV). The NWV rises as the voltage at thesource terminal 1028 rises. As a result, the p-channel transistors are not switched on and no current flows through the parasitic diode in each p-channel transistor. This reduces current flow from thecommon bus line 1020 through theHVT 1024 and theread circuit 1011 to Vcc in the programming mode. The structure and operation of thelogic circuit 1012 will now be described. - The
logic circuit 1012 is coupled to receive three signals labeled PROGRAM, ZZ1, and ZZ2, which select one of the programming mode, the active mode, and the sleep mode. The signals PROGRAM, ZZ1, and ZZ2 are defined in Table 1:TABLE 1 MODE PROGRAM ZZ1 ZZ2 PROGRAMMING HIGH LOW LOW ACTIVE LOW HIGH LOW SLEEP LOW LOW HIGH - The signals PROGRAM, ZZ1, and ZZ2 can be generated by any appropriate circuit known to those skilled in the art to indicate the mode of operation of the
programming logic circuit 420. - When the
programming logic circuit 420 is in the active mode thecommon bus line 1020 is coupled to Vss, and the state of theantifuse 1016 is read as thetransistors inverter 1054. A substantial amount of current is dissipated through thecommon bus line 1020 during the active mode if theantifuse 1016 is programmed. - The
transistor 1052 is switched on by the voltage BIAS, and thetransistor 1050 is switched on in the following manner. The PROGRAM signal is low, the signal ZZ1 is high and the signal ZZ2 is low in the active mode. The low PROGRAM signal is provided from acircuit 1056 to force NWV to Vcc as it is coupled to an input of afirst inverter 1058 and a source of an n-channel transistor 1060. An output of theinverter 1058 generates a high signal that is coupled to a gate terminal of a p-channel transistor 1062 to switch it off. A gate terminal of thetransistor 1060 is coupled to Vcc such that thetransistor 1060 is rendered conductive, and the low PROGRAM signal is coupled through thetransistor 1060 to switch on a p-channel transistor 1064 at its gate terminal and couple Vcc to anNWV line 1066 that is coupled to the welltie diffusion region 1716 in each p-channel transistor in theread circuit 1011. In the active mode, the NWV is approximately Vcc. TheNWV line 1066 thereby couples the NWV to thewells 1710 of p-channel transistors in theread circuit 1011. - The
logic circuit 1012 includes a second inverter comprising a p-channel transistor 1068, an n-channel transistor 1070, and a terminal between the two to generate a signal TZZ1. A gate terminal of each of thetransistors transistor 1068 is switched off and thetransistor 1070 is switched on to generate a low signal TZZ1 which is coupled to the gate terminal of thetransistor 1050 to switch it on. - The
logic circuit 1012 also includes a third inverter comprising a p-channel transistor 1072, an n-channel transistor 1074, and a terminal between the two to generate a signal TZZ2. A gate terminal of each of thetransistors transistor 1072 is switched on and thetransistor 1074 is switched off to generate the signal TZZ2 to be high, or approximately Vcc. The high signal TZZ2 is coupled to theread circuit 1011 as will now be described. - In addition to the elements described above, the
read circuit 1011 includes a third p-channel transistor 1076, a fourth p-channel transistor 1078, and a fifth p-channel transistor 1080. Each of thetransistors channel transistor 1700 shown inFIG. 17 . The gate terminal of thetransistor 1076 is coupled to Vcc, and its reference terminal is coupled to its drain terminal and theNWV line 1066. Thetransistors inverter 1054. The high signal TZZ2 is coupled to a gate terminal of thetransistor 1078 to switch it off so that thetransistors antifuse 1016. Additional features of theread circuit 1011 will be described hereinbelow. - When the
programming logic circuit 420 is in the programming mode thecommon bus line 1020 is coupled to an elevated voltage. If theantifuse 1016 is programmed, it is an impedance element between the elevated voltage and the rest of the elements in theprogram driver circuit 1010 and theread circuit 1011. Thelogic circuit 1012 substantially eliminates current flow in the p-channel transistors in theread circuit 1011 in the following manner. - In the programming mode the PROGRAM signal is high and is coupled to a drain of the
transistor 1060 to switch it off.Inverter 1058 generates a low signal to switch on thetransistor 1062. The NWV on theNWV line 1066 will rise, for reasons described below, and the high NWV is coupled to the gate terminal of thetransistor 1064 to switch it off. With thetransistors NWV line 1066 is isolated from both the PROGRAM signal and Vcc. Thesource terminal 1028 may rise above Vcc in the programming mode when the elevated voltage is on thecommon bus line 1020 and theantifuse 1016 is programmed. When this happens thetransistor 1076 will be switched on because its gate terminal is held at Vcc, and the rising voltage at thesource terminal 1028 is coupled to theNWV line 1066 to raise the NWV. TheNWV line 1066 is coupled to the wells of each of thetransistors - In the programming mode, both of the signals ZZ1 and ZZ2 are low such that the p-
channel transistors channel transistors transistor 1050, and the signal TZZ2 is coupled to a gate terminal of thetransistor 1078. The rise in NWV reduces current being passed through the parasitic diodes in thetransistors wells 1010 of those transistors have nearly the same voltage potential as thesource terminal 1028, and there is not enough voltage potential to forward bias the parasitic diodes. In addition, the gate terminals of thetransistors source terminal 1028. Substantial device current is thereby reduced in thetransistors driver logic circuit 1012 prevents substantial current in the p-channel transistors common bus line 1020 and an antifuse is to be programmed. - The
inverter 1054 and thetransistors read circuit 1011 are part of a latch circuit used to latch a state of theantifuse 1016 when theprogramming logic circuit 420 is in the sleep mode. Theprogramming logic circuit 420 is receiving power and operating in both the active and sleep modes. However, in the sleep mode theprogramming logic circuit 420 shuts down some operations to reduce power dissipation. As mentioned above, a substantial amount of current is dissipated through thecommon bus line 1020 in the active mode if theantifuse 1016 is programmed. This current is substantially eliminated in the sleep mode. - The latch circuit is used in the sleep mode to latch the state of the
antifuse 1016 to indicate correctly the state of theantifuse 1016 in the sleep mode. The latch circuit also includes a first n-channel transistor 1082 and a second n-channel transistor 1084. Thetransistors transistor 1082 is coupled to a drain terminal of thetransistor 1078 and an input of theinverter 1054. A gate terminal of thetransistor 1082 is coupled with the gate terminal of thetransistor 1050 to receive the signal TZZ1 from thelogic circuit 1012. A source terminal of thetransistor 1082 is coupled to a drain terminal of thetransistor 1084, and a source terminal of thetransistor 1084 is coupled to Vss. A gate terminal of thetransistor 1084 is coupled to the output of theinverter 1054, as is a gate terminal of thetransistor 1080. The gate terminal of thetransistor 1078 is coupled to receive the signal TZZ2 from thelogic circuit 1012. - The latch circuit is disabled in the active mode described above when the signal ZZ1 is high and the signal ZZ2 is low. The resulting signal TZZ1 is low to switch the
transistor 1050 on while switching off thetransistor 1082. The signal TZZ2 is high to switch off thetransistor 1078. Thus no substantial current passes through thetransistors antifuse 1016 is being read in the active mode. - In the sleep mode the PROGRAM signal is low so that the
NWV line 1066 is coupled to Vcc. The signal ZZ1 is low so the signal TZZ1 is high to switch off thetransistor 1050 and block current from thetransistor 1052. The high signal TZZ1 also enables thetransistor 1082 to be switched on depending on a voltage between thetransistors transistor 1078 to be switched on depending on a voltage between thetransistors source terminal 1028 will retain its voltage potential, near either Vcc or Vss, after being read in the active mode. If thesource terminal 1028 is high, or is close to or above Vcc, the output of theinverter 1054 will be low to switch off thetransistor 1084 and enable thetransistor 1080 to be switched on. The high voltage on thesource terminal 1028 causes thetransistors source terminal 1028 to Vcc and latch the output of theinverter 1054 low. If thesource terminal 1028 is low the output of theinverter 1054 will be high to switch off thetransistor 1080 and enable thetransistor 1084 to be switched on. The low voltage at thesource terminal 1028 causes thetransistors source terminal 1028 to Vss and latch the output of theinverter 1054 high. - The latch including the
transistors inverter 1054, is used to latch a state of theantifuse 1016 only in the sleep mode because the state of the latch is unknown when theprogramming logic circuit 420 first receives power after being in a power-down mode. The latch will indicate the correct state of theantifuse 1016 only after it has been read in the active mode. One advantage of the sleep mode is that thetransistor 1050 is switched off to reduce the dissipation of current from Vcc through thetransistors antifuse 1016 to thecommon bus line 1020. - The
antifuse 1016 may be read only intermittently during the operation of an integrated circuit and then its state may be latched the rest of the time according to an alternate embodiment of the present invention. In this embodiment of the invention, the state of the antifuse is read as it is in the active mode described above in response to a signal such as a power-up signal or a wake-up signal for the integrated circuit that initiates the read. The power-up or wake-up signal sets TZZ1 low and TZZ2 high for a period of time to read theantifuse 1016 and allow theinverter 1054 to generate a settled OUTPUT signal. As the period of time ends TZZ1 is set high and TZZ2 is set low to latch the state of theantifuse 1016 as described above. - The capacitance of the
NWV line 1066 and the wells of the transistors it is coupled to absorbs charge as the NWV rises. TheNWV line 1066 is coupled not only to the transistors shown inFIG. 10 , but transistors associated with other antifuses in thebank 400. If all of the antifuses in thebank 400 are unprogrammed, then the capacitive load of theNWV line 1066 will be charged from current passed through one or more of them and which will damage the antifuses. One way of preventing this damage is to short at least one antifuse in each bank, such as theantifuse 410 in thebank 400, with metal such that a current path exists to charge the capacitive load of theNWV line 1066 and its transistors. The shorted antifuse may also be used in a test mode. - The
transistors FIG. 10 may each be replaced by an upper transistor and a lower transistor of similar types coupled in cascode to manage high voltages. The upper transistor has a gate terminal coupled to Vcc and the lower transistor has a gate terminal connected in a manner similar to the correspondingoriginal transistor - An electrical schematic diagram of an
integrated circuit 1800 with a common busline driver circuit 1802 is shown inFIG. 18 according to an embodiment of the present invention. Theintegrated circuit 1800 includes threebanks 1810, 1812, and 1814 of antifuses coupled to acommon bus line 1820. Thebanks 1810, 1812, and 1814 may be similar to thebank 400 shown inFIG. 4 . Integrated circuits according to other embodiments of the present invention may include more or fewer banks of antifuses. Thecommon bus line 1820 is coupled to anESD device external pin 1826 of theintegrated circuit 1800. Theexternal pin 1826 is similar to theexternal pin 430 shown inFIG. 4 . - The common bus
line driver circuit 1802 is coupled to provide a path to Vss for thecommon bus line 1820. The common busline driver circuit 1802 includes aHVT 1830 having adrain terminal 1832, asource terminal 1834, and agate terminal 1836. TheHVT 1830 is similar in structure and operating characteristics to the n-well drain transistor 600 shown inFIG. 6 . Thegate terminal 1836 is coupled to acathode 1841 of adiode 1842, and ananode 1846 of thediode 1842 is coupled to Vcc. Thediode 1842 is forward biased as long as Vcc exceeds a voltage at thegate terminal 1836. Thegate terminal 1836 is also coupled to acathode 1850 of adiode 1852. Ananode 1854 of thediode 1852 is coupled to Vbb. Thediodes gate terminal 1836 at a voltage slightly less than Vcc, or higher. - A first n-
channel transistor 1860 and a second n-channel transistor 1870 are coupled in cascode between thesource terminal 1834 and Vss. A gate terminal of thetransistor 1860 is coupled to Vcc, and a gate terminal of thetransistor 1870 is coupled to alogic circuit 1872 which controls current in the common busline driver circuit 1802. A body terminal of thetransistor 1870 is coupled to Vbb. - In the active mode the
logic circuit 1872 switches on thetransistor 1870 such that current on thecommon bus line 1820 is given a path to Vss. The current flows from the antifuses in thebanks 1810, 1812, and 1814 through theHVT 1830 and thetransistors FIG. 10 recited above. Thetransistors common bus line 1820 near Vss. - In the programming mode the
logic circuit 1872 switches off thetransistor 1870 to prevent substantial current flow. This is done to maintain an elevated voltage on thecommon bus line 1820, and to minimize current flow from thecommon bus line 1820. Voltages along the common busline driver circuit 1802 rise when thetransistor 1870 is switched off to substantially end current flow, and the voltage rises on thecommon bus line 1820. Thetransistor 1830 and thediodes transistor 1024 and thediodes FIG. 10 . - The
program driver circuit 1010 shown inFIG. 10 and the common busline driver circuit 1802 may be different in alternate embodiments of the present invention. For example, the twocircuits circuits FIGS. 11-16 . - The
logic circuit 1872 may also switch off thetransistor 1870 during a test mode to permit an analog characterization of the impedance of each programmed antifuse in thebanks 1810, 1812, and 1814. The current/voltage characteristics of each programmed antifuse are tested with a test apparatus such as a curve tracer coupled to theexternal pin 1826. Current passes through the programmed antifuse, and other current sources coupled to thecommon bus line 1820 must be substantially blocked during the test mode. Another test mode permits a modulation of the voltage BIAS to modulate the impedance of thetransistor 1052. A noise margin for thecircuits 1000 may be quantified by determining an impedance of thetransistor 1052 at which theinverter 1054 changes the OUTPUT signal. A wider noise margin will allow for more variability in the impedance of the antifuse over the operating lifetime of thecircuits 1000 without impairing performance. - In alternate embodiments of the present invention the common bus
line driver circuit 1802 is not included in theintegrated circuit 1800 because a programming of its antifuses takes place during its manufacture, and theexternal pin 1826 is coupled to Vss during its operation. This is called supply stealing. Thecommon bus line 1820 is then always coupled to Vss during operation, and the common busline driver circuit 1802 is not needed. - The
read circuit 1011 shown inFIG. 10 may be modified to read theantifuse 1016 as it is read in the active mode all of the time. A set ofsupport circuits 1900 including a modifiedread circuit 1910 are shown inFIG. 19 according to an embodiment of the present invention. All of the other elements of thesupport circuits 1900 are similar to thesupport circuits 1000 shown inFIG. 10 , have been given the same reference numerals, and will not be further described for purposes of brevity. The state of theantifuse 1016 is never latched by theread circuit 1900. - The
read circuit 1910 retains only two of the transistors, 1052 and 1076, from theread circuit 1011, the remaining transistors not being necessary or included in theread circuit 1910. Thetransistor 1052 may be replaced by a resistor or other load device in alternate embodiments of the present invention. The operation of thetransistor 1076 is the same as described above for theread circuit 1011. Theantifuse 1016 is read by comparing the impedance of thetransistor 1052 with the impedance of theantifuse 1016 with current flow from Vcc through thetransistors antifuse 1016. The resulting OUTPUT signal is the same as described above for theread circuit 1011. - The
antifuse 510 may be similar to theantifuse 200 shown inFIG. 2 , in which case the programmed antifuse 510 will be similar to a resistor and include aruptured gate dielectric 222 between the n-type well 210 and the n-type gate electrode 220. Theantifuse 510 may then be read with Vcc on thecommon bus line 530 using a read circuit similar to theread circuit 1011 shown inFIG. 10 . A set ofsupport circuits 2000 including an example of such a read circuit are shown inFIG. 20 according to an embodiment of the present invention. Thecircuits 2000 include a programmed antifuse 2008 similar to theantifuse 200 having a first terminal coupled to acommon bus line 2010. Thecommon bus line 2010 is coupled to Vcc, and this may be called supply stealing for Vcc if it is supplied from a source external to thecircuits 2000. A second terminal of theantifuse 2008 is coupled to aprogram driver circuit 2012 having the same elements as theprogram driver circuit 1010 shown inFIG. 10 . Also shown is the floating welldriver logic circuit 1012. The same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. - A
read circuit 2020 is coupled to theprogram driver circuit 2012 at thesource terminal 1028 of theHVT 1024 and includes elements similar to the elements of theread circuit 1011 shown inFIG. 10 . The similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theread circuit 2020 does not include thetransistors FIG. 10 . Instead, a first n-channel transistor 2030 and a second n-channel transistor 2032 are coupled in series between thesource terminal 1028 and Vss. Thetransistor 2032 is switched on by a bias voltage BIAS applied to its gate terminal, and the voltage BIAS is generated by a current mirror (not shown) to control current through thetransistor 2032 to Vss at its source terminal. A drain terminal of thetransistor 2032 is coupled to a source terminal of thetransistor 2030, and the drain terminal of thetransistor 2030 is coupled to thesource terminal 1028. The gate terminal of thetransistor 2030 is coupled to the signal TZZ2 which is high to switch on thetransistor 2030 when theprogramming logic circuit 420 is in the active mode to read theantifuse 2008. - When the
antifuse 2008 is read current flows from thecommon bus line 1020 at Vcc through theantifuse 2008 and thetransistors antifuse 2008 is compared with the impedance of thetransistor 2032 when it is switched on. If theantifuse 2008 is programmed and has a low impedance then a voltage at thesource terminal 1028 will be close to Vcc less the threshold voltages of thediode 1034 and theHVT 1024. The inverter will invert this high voltage into a low OUTPUT signal indicating that theantifuse 2008 is programmed. If theantifuse 2008 is unprogrammed it will have a very high impedance and the voltage at thesource terminal 1028 will be slightly above Vss. Theinverter 1054 will invert this low voltage into a high OUTPUT signal indicating theantifuse 1016 is unprogrammed. Thetransistor 2032 is a long-L n-channel transistor or a long-L p-channel transistor, or it may be replaced by a resistor. Thetransistor 2032 may also be replaced by an upper transistor and a lower transistor of a similar type coupled in cascode to manage high voltages. The upper transistor has a gate terminal coupled to Vcc and the lower transistor has a gate terminal connected in a manner similar to the correspondingoriginal transistor 2032. - The
logic circuit 1012 shown inFIG. 10 may not be necessary to reduce current flow in theread circuit 1011 for many reasons. For example, process parameters may result in an integrated circuit that minimizes this current, or theHVT 1024 may have characteristics which minimize this current. A pass-gate device may also reduce the need for thelogic circuit 1012. A set ofsupport circuits 2100 including a pass-gate device are shown inFIG. 21 according to an embodiment of the present invention. Thecircuits 2100 include elements similar to the elements of thesupport circuits 1000 shown inFIG. 10 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. - The
program driver circuit 1010 is coupled to aread circuit 2120 through an n-channel pass-gate transistor 2130 according to an embodiment of the present invention. A drain of thepass-gate transistor 2130 is coupled to the source of theHVT 1024, and a source of thepass-gate transistor 2130 is coupled to thetransistor 1050. Vcc is coupled to a gate of thepass-gate transistor 2130. Both of the signals ZZ1 and ZZ2 are low during the programming mode such that Vcc is coupled to the source of thepass-gate transistor 2130 to ensure that it is not conductive and substantially prevents current flow from thecommon bus line 1020. The voltage at the source of thepass-gate transistor 2130 will vary during the active and sleep modes. - The use of the
pass-gate transistor 2130 to reduce current flow in theread circuit 2120 may also permit the use of n-channel transistors instead of the p-channel transistors in theread circuit 2120. A set ofsupport circuits 2200 are shown inFIG. 22 according to an embodiment of the present invention. Thecircuits 2200 include elements similar to the elements of thesupport circuits 2100 shown inFIG. 21 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Theprogram driver circuit 1010 is coupled to aread circuit 2220 through an n-channel pass-gate transistor 2130 having Vcc coupled to its gate. Thepass-gate transistor 2130 substantially prevents current flow from thecommon bus line 1020. Theread circuit 2220 includes elements similar to the elements of theread circuit 2120 shown inFIG. 21 , and further includes n-channel transistors channel transistors FIG. 21 . The signal ZZ1 is coupled to a gate of thetransistor 2230 while the signal ZZ2 is coupled to gates of thetransistors transistor 2242, being inverted by aninverter 2254. Theread circuit 2220 operates in a manner substantially similar to theread circuit 2120. - The
pass-gate transistor 2130 shown inFIGS. 21 and 22 eliminates the need for thelogic circuit 1012, but it also reduces the noise margin of theread circuits antifuse 1016. The noise margin is improved by using the external supply voltage VccX and the regulated supply voltage VccR described above to supply power to theread circuits support circuits 2300 are shown inFIG. 23 according to an embodiment of the present invention. Most of the elements of thecircuits 2300 are similar to the elements of thesupport circuits 2100 shown inFIG. 21 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Theread circuit 2120 is coupled to receive VccR on the sources of thetransistors pass-gate transistor 2130 is coupled to VccX. Either VccX or VccR is coupled to the anode of thediode 1034. During a read of theantifuse 1016 VccR is regulated to be less than VccX to improve the noise margin of theread circuit 2120. However, when antifuses such as theantifuse 1016 are being programmed, VccR is raised to be approximately equal to VccX. A similar use of VccR and VccX would also improve the noise margin of thecircuits 2200 shown inFIG. 22 . - The
common bus line 2010 in thecircuits 2000 shown inFIG. 20 is coupled to Vcc. This may be replaced by a driver circuit driven by both of the supply voltages VccX and VccR. An electrical schematic diagram of anintegrated circuit 2400 with a common busline driver circuit 2402 is shown inFIG. 24 according to an embodiment of the present invention. Theintegrated circuit 2400 includes threebanks common bus line 2420. Thebanks bank 400 shown inFIG. 4 . Integrated circuits according to other embodiments of the present invention may include more or fewer banks of antifuses. Thecommon bus line 2420 is coupled to anESD device external pin 2426 of theintegrated circuit 2400. Theexternal pin 2426 is similar to theexternal pin 430 shown inFIG. 4 . - The common bus
line driver circuit 2402 couples thecommon bus line 2420 to VccR when necessary. The common busline driver circuit 2402 includes aHVT 2430 having adrain terminal 2432, asource terminal 2434, and agate terminal 2436. TheHVT 2430 is similar in structure and operating characteristics to the n-well drain transistor 600 shown inFIG. 6 . Thegate terminal 2436 is coupled to acathode 2441 of adiode 2442, and ananode 2446 of thediode 2442 is coupled to VccX. Thediode 2442 is forward biased as long as VccX exceeds a voltage at thegate terminal 2436. Thegate terminal 2436 is also coupled to a cathode 2450 of adiode 2452. Ananode 2454 of thediode 2452 is coupled to Vss. Thediodes gate terminal 2436 at a voltage slightly less than VccX, or higher. - A first n-
channel transistor 2460 and a second n-channel transistor 2470 are coupled in cascode between thesource terminal 2434 and VccR. A body terminal of thetransistor 2470 is coupled to Vbb. A gate terminal of thetransistor 2460 is coupled to VccX, and a gate terminal of thetransistor 2470 is coupled to alogic circuit 2472 which controls current in the common busline driver circuit 2402. Thelogic circuit 2472 is coupled to receive VccX as its supply voltage. - In the active mode the
logic circuit 2472 switches on thetransistor 2470 such that thecommon bus line 2420 is coupled to VccR. The current flows from VccR to the antifuses in thebanks FIG. 10 recited above. Thetransistors common bus line 2420 near VccR. - In the programming mode the
logic circuit 2472 switches off thetransistor 2470 to prevent substantial current flow. This is done to maintain an elevated voltage on thecommon bus line 2420, and to minimize current flow from thecommon bus line 2420. Voltages along the common busline driver circuit 2402 rise when thetransistor 2470 is switched off to substantially end current flow, and the voltage rises on thecommon bus line 2420. Thetransistor 2430 and thediodes transistor 1024 and thediodes FIG. 10 . - The
program driver circuit 1010 shown inFIG. 10 and the common busline driver circuits circuits circuits FIGS. 11-16 . - With reference to the
circuits 1000 shown inFIG. 10 , another possible source of unwanted current in theantifuse 1016 exists through thetransistors source 1028 of theHVT 1024 is low, then the OUTPUT signal is high and thetransistor 1084 is switched on. If this condition occurs during the programming mode thetransistors antifuse 1016 causing damage if it is unprogrammed. A set ofsupport circuits 2500 are shown inFIG. 25 according to an embodiment of the present invention. Most of the elements of thecircuits 2500 are similar to the elements of thesupport circuits 1000 shown inFIG. 10 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Thecircuits 2500 include aread circuit 2520 that has, in addition to the elements shown inFIG. 10 , elements that substantially prevent current through thetransistors inverter 1054 comprises a p-channel transistor 2530 and an n-channel transistor 2532 connected in series, with drains of thetransistors inverter 1054. Gates of thetransistors source 1028 of theHVT 1024. A source of thetransistor 2532 is coupled to Vss, and a p-channel transistor 2534 is coupled between a source of thetransistor 2530 and Vcc. In addition, an n-channel transistor 2536 is coupled between the output of theinverter 1054 and Vss. The output of theinverter 1054 remains connected to the gate of thetransistor 1084. Gates of thetransistors TABLE 2 MODE SW PROGRAMMING HIGH ACTIVE LOW SLEEP LOW
In the programming mode the signal SW is high to switch off thetransistor 2534 and substantially block current to theinverter 1054. The high SW signal also switches on thetransistor 2536 to couple the output of theinverter 1054 to Vss and thus ensure that thetransistor 1084 is switched off to substantially prevent unwanted current in theantifuse 1016. In the active and sleep modes the signal SW is low to decouple the output of theinverter 1054 from Vss and switch on thetransistor 2534. Theinverter 1054 is thereby coupled to Vcc and theread circuit 2520 operates similarly to theread circuit 1011 shown inFIG. 10 to read a state of theantifuse 1016. - The
antifuses FIGS. 1, 1A , 1B, 2, and 2A, thetransistors FIGS. 6, 7 , 8, 8A, 9, 11, and 17, and thediodes FIGS. 12, 13 , 14, 15, and 16 according to embodiments of the present invention may be formed in wells within other wells or tanks rather than the substrates shown. Such wells or tanks may be situated with other wells or tanks, or within other wells or tanks, in a larger substrate. The wells or tanks may also be situated in a silicon-on-insulator (SOI) device. - An integrated circuit fabricated with one or more of the antifuses and circuits described above may be tested in a test mode. For example, an integrated circuit having a bank of antifuses is prestressed by applying a prestress voltage that is less than the elevated voltage used to program the antifuses. The antifuses are exposed to the prestress voltage and weaker antifuses are programmed as a result. The antifuses are then read to indicate the antifuses that have been programmed. The antifuses may be read by determining their analog resistances, by detecting a digital output of an addressed antifuse, or by detecting digital output from an addressed antifuse compared with several different load elements.
- The
logic circuit 1012 shown inFIG. 10 may not be necessary to reduce current flow in theread circuit 1011 for many reasons. For example, process parameters may result in an integrated circuit that minimizes this current, or theHVT 1024 may have characteristics which minimize this current. A set ofsupport circuits 2600 are shown inFIG. 26 according to an embodiment of the present invention. Thecircuits 2600 include elements similar to the elements of thecircuits 1000 shown inFIG. 10 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Thelogic circuit 1012, thetransistor 1076, and the connections to theNWV line 1066 shown inFIG. 10 are not included in thecircuits 2600. Thecircuits 2600 operate in a manner similar to thecircuits 1000 without the above-listed elements. - The
pass-gate transistor 2130 shown inFIG. 22 may not be necessary to reduce current flow in theread circuit 2220 for the reasons mentioned above. A set ofsupport circuits 2700 are shown inFIG. 27 according to an embodiment of the present invention. Thecircuits 2700 include elements similar to the elements of thecircuits 2200 shown inFIG. 22 , and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Thepass-gate transistor 2130 shown inFIG. 22 is not included in thecircuits 2700. Thecircuits 2700 operate in a manner similar to thecircuits 2200 without thepass-gate transistor 2130. - A block diagram of a static random access memory device (SRAM) 2800 is shown in
FIG. 28 according to an embodiment of the present invention. TheSRAM 2800 may include one or more of the circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention. TheSRAM 2800 has anarray 2810 of memory cells that are accessed according to address signals provided to theSRAM 2800 at a number of address inputs A0-A16. Anaddress decoder 2820 decodes the address signals and accesses memory cells in thearray 2810 according to the address signals. Data is written to the memory cells in thearray 2810 when a write enable signal WE* and a chip enable signal CE* coupled to theSRAM 2800 are both low. The data is received by theSRAM 2800 over eight data input/output (I/O) paths DQ1-DQ8. The data is coupled to the memory cells in thearray 2810 from the I/O paths DQ1-DQ8 through an I/O control circuit 2830. Data is read from the memory cells in thearray 2810 when the write enable signal WE* is high and an output enable signal OE* coupled to theSRAM 2800 and the chip enable signal CE* are both low. A power downcircuit 2840 controls theSRAM 2800 during a power-down mode. The circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention may be included in other types of memory devices such as DRAMs, programmable logic devices, PROMs, EPROMs, and EEPROMs. - An
integrated circuit package 2900 of a 32 k×36 SRAM memory device is shown inFIG. 29 according to an embodiment of the present invention. The SRAM may include one or more of the circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention. One of theexternal pins several pins package 2900. Thepins external pins external pins external pins several pins external pin 2426 is one ofseveral pins external pin 1826 shown inFIG. 18 . - A block diagram of an information-
handling system 3000 is shown inFIG. 30 according to an embodiment of the present invention. The information-handling system 3000 includes amemory system 3008, aprocessor 3010, adisplay unit 3020, and an input/output (I/O)subsystem 3030. Theprocessor 3010 may be, for example, a microprocessor. One or more of thememory system 3008, theprocessor 3010, thedisplay unit 3020, and the I/O subsystem 3030 may include one or more of the circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention. Theprocessor 3010, thedisplay unit 3020, the I/O subsystem 3030, and thememory system 3008 are coupled together by a suitable communication line orbus 3040. Theprocessor 3010 and thememory system 3008 may be integrated circuits formed on a single substrate. - In various embodiments of the present invention, the information-
handling system 3000 is a computer system (such as, for example, a video game, a hand-held calculator, a television set-top box, a fixed-screen telephone, a smart mobile phone, a personal digital assistant (PDA), a network computer (NC), a hand-held computer, a personal computer, or a multi-processor supercomputer), an information appliance (such as, for example, a cellular telephone or any wireless device, a pager, or a daily planner or organizer), an information component (such as, for example, a magnetic disk drive or telecommunications modem), or other appliance (such as, for example, a hearing aid, washing machine or microwave oven having an electronic controller). - Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art having the benefit of this description that any equivalent arrangement may be substituted for the specific embodiments shown. For example, specific memory devices have been described and shown in the Figures. One skilled in the art having the benefit of this description will recognize that the invention may be employed in other types of memory devices and in other types of integrated circuit devices. The voltage Vbb described above may be approximately equal to Vss, or may be negative. In addition, in alternate embodiments of the present invention, the common bus line is sized to provide a programming current for more than one antifuse at the same time. The present invention is therefore limited only by the claims and equivalents thereof.
Claims (28)
1. A transistor comprising:
a p-type halo in a source side of a p-type substrate;
an n-type lightly doped drain in the halo;
an n+-type source diffusion region in the lightly doped drain; and
an n+-type drain diffusion region in a drain side of the substrate.
2. The transistor of claim 1 , further including:
a drain terminal connected to the drain diffusion region;
a source terminal connected to the source diffusion region;
a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;
a polysilicon gate over the layer of gate dielectric;
an electrode over the polysilicon gate;
a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and
a gate terminal connected to the electrode.
3. A method of forming a transistor comprising:
forming a p-type halo in a source side of a p-type substrate;
forming an n-type lightly doped drain in the halo;
forming an n+-type source diffusion region in the lightly doped drain; and
forming an n+-type drain diffusion region in a drain side of the substrate.
4. The method of claim 3 , further including:
connecting a drain terminal to the drain diffusion region;
connecting a source terminal to the source diffusion region;
forming a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;
forming a polysilicon gate over the layer of gate dielectric;
forming an electrode over the polysilicon gate;
forming a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and
connecting a gate terminal to the electrode.
5. A transistor comprising:
an n-type well in a drain side of a p-type substrate;
an n+-type drain diffusion region in the well;
a p-type halo in a source side of the substrate;
an n-type lightly doped drain in the halo; and
an n+-type source diffusion region in the lightly doped drain.
6. The transistor of claim 5 , further including:
a drain terminal connected to the drain diffusion region;
a source terminal connected to the source diffusion region;
a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;
a polysilicon gate over the layer of gate dielectric;
an electrode over the polysilicon gate;
a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and
a gate terminal connected to the electrode.
7. A method of forming a transistor comprising:
forming an n-type well in a drain side of a p-type substrate;
forming an n+-type drain diffusion region in the well;
forming a p-type halo in a source side of the substrate;
forming an n-type lightly doped drain in the halo; and
forming an n+-type source diffusion region in the lightly doped drain.
8. The method of claim 7 , further including:
connecting a drain terminal to the drain diffusion region;
connecting a source terminal to the source diffusion region;
forming a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;
forming a polysilicon gate over the layer of gate dielectric;
forming an electrode over the polysilicon gate;
forming a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and
connecting a gate terminal to the electrode.
9. An integrated circuit comprising:
an external pin;
a common bus line coupled to the external pin;
an antifuse bank coupled to the common bus line, the antifuse bank including a plurality of antifuses; and
a common bus line driver circuit including:
a high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal;
a diode coupled between the control terminal and a reference voltage; and
a control transistor coupled between the second terminal and a voltage reference.
10. The integrated circuit of claim 9 , wherein:
the high-voltage transistor includes an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to the diode, and a source terminal coupled to the control transistor;
the diode includes:
a first diode including an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor; and
a second diode including a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a voltage reference to withstand a high voltage on the control terminal of the n-well drain transistor;
the control transistor is coupled between the second terminal and a reference voltage and further includes a control circuit to switch on the control transistor to couple the common bus line to the ground voltage reference and to switch off the control transistor to permit an elevated voltage on the common bus line.
11. A method of operating an integrated circuit comprising:
coupling an elevated voltage through an external pin to a common bus line in the integrated circuit to program an antifuse coupled to the common bus line;
switching off a control transistor in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line;
bearing a portion of the elevated voltage across a high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal coupled to the control transistor;
bearing a portion of the elevated voltage between a diode and the control terminal of the high-voltage transistor; and
switching on the control transistor to couple the common bus line to the voltage reference to read the antifuse.
12. The method of claim 11 , wherein:
switching off a control transistor includes switching off a control transistor with a control circuit in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line;
bearing a portion of the elevated voltage across a high-voltage transistor includes bearing a portion of the elevated voltage across an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to a diode, and a source terminal coupled to the control transistor;
bearing a portion of the elevated voltage between a diode and the control terminal includes bearing a portion of the elevated voltage between the control terminal of the n-well drain transistor, a first diode including an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor, and a second diode including a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a reference voltage; and
switching on the control transistor includes switching on the control transistor with the control circuit to couple the common bus line to the voltage reference to read the antifuse.
13. A circuit comprising:
a high-voltage transistor including:
a well of a first conductivity type in a substrate of a second conductivity type;
a drain diffusion region of the first conductivity type in the well, the drain diffusion region being coupled to an elevated voltage source;
a source diffusion region of the first conductivity type in the substrate;
a layer of gate dielectric over the substrate; and
a gate electrode over the gate dielectric;
a diode coupled between the gate electrode and a reference voltage to hold a voltage on the gate electrode caused by a charge transfer across the gate dielectric due to the elevated voltage source;
a support circuit coupled to the source diffusion region.
14. The circuit of claim 13 , wherein:
the substrate includes a p-type substrate;
the well includes an n-type well in the p-type substrate;
the drain diffusion region includes an n+-type drain diffusion region in the n-type well;
the source diffusion region includes an n+-type source diffusion region in the p-type substrate;
the gate dielectric includes a layer of oxide;
the gate electrode includes a gate electrode over the layer of oxide;
the diode includes:
a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode of the high-voltage transistor to switch on the high-voltage transistor; and
a second diode including a cathode coupled to the gate electrode of the high-voltage transistor and an anode coupled to a reference voltage to withstand a high voltage on the gate electrode; and
the support circuit includes a control transistor is coupled between the source diffusion region and a ground voltage reference and further includes a control circuit to switch on the control transistor to couple the elevated voltage source to the ground voltage reference and to switch off the control transistor to permit the circuit to bear the elevated voltage.
15. A method comprising:
coupling an elevated voltage to a drain of a high-voltage transistor;
allowing charge to transfer from the drain across a layer of gate dielectric to a gate electrode of the high-voltage transistor; and
allowing the charge to accumulate in the gate electrode to raise a voltage of the gate electrode to a balanced voltage to reduce further charge transfer across the layer of gate dielectric.
16. The method of claim 15 , wherein:
coupling an elevated voltage to a drain includes coupling an elevated voltage to an n+-type drain diffusion region in an n-type well in a p-type substrate of a high-voltage transistor;
allowing charge to transfer from the drain includes allowing charge to transfer from the n+-type drain diffusion region across a layer of gate oxide to a gate electrode of the high-voltage transistor; and
allowing the charge to accumulate includes holding the charge in the gate electrode with a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode and a second diode including an cathode coupled to the gate electrode and an anode coupled to a reference voltage to raise a voltage of the gate electrode to a balanced voltage to reduce further charge transfer across the layer of oxide.
17. An antifuse circuit comprising:
an antifuse having a first terminal coupled to a programming voltage supply and a second terminal;
a high-voltage transistor including:
a well of a first conductivity type in a substrate of a second conductivity type;
a drain diffusion region of the first conductivity type in the well, the drain diffusion region being coupled to the second terminal of the antifuse;
a source diffusion region of the first conductivity type in the substrate;
a layer of gate dielectric over the substrate; and
a gate electrode over the gate dielectric;
a diode coupled between the gate electrode and a first reference voltage to hold a voltage on the gate electrode caused by a charge transfer across the gate dielectric due to the programming voltage;
an impedance transistor having a first terminal coupled to the source diffusion region of the antifuse and a second terminal; and
a control transistor having a first terminal coupled to the second terminal of the impedance transistor, a second terminal coupled to a second reference voltage, and a control terminal coupled to a control circuit to switch the control transistor on to couple the second terminal of the anti fuse to the second reference voltage to program the antifuse, and to switch the control transistor off when the antifuse is not being programmed.
18. The antifuse circuit of claim 17 , wherein:
the substrate includes a p-type substrate;
the well includes an n-type well in the p-type substrate;
the drain diffusion region includes an n+-type drain diffusion region in the n-type well;
the source diffusion region includes an n+-type source diffusion region in the p-type substrate;
the gate dielectric includes a layer of oxide;
the gate electrode includes a gate electrode over the layer of oxide;
the diode includes:
a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode of the high-voltage transistor to switch on the high-voltage transistor; and
a second diode including a cathode coupled to the gate electrode of the high-voltage transistor and an anode coupled to a reference voltage to withstand a high voltage on the gate electrode;
the control transistor includes an n-channel transistor; and
the impedance transistor includes an n-channel transistor including a gate terminal coupled to the voltage supply.
19. A method of operating an antifuse circuit comprising:
coupling an elevated voltage to a first terminal of an antifuse from a common bus line;
coupling a second terminal of the antifuse to a reference voltage through a control transistor to program the antifuse with current from the common bus line;
switching off the control transistor to uncouple the second terminal of the antifuse from the reference voltage after the antifuse is programmed; and
reducing a voltage on a terminal of the control transistor with an impedance transistor coupled between the second terminal of the antifuse and the terminal of the control transistor to reduce a probability of snap-back in the control transistor.
20. The method of claim 19 , wherein:
coupling an elevated voltage includes coupling an elevated voltage from an external pin to a first terminal of an antifuse through a common bus line;
coupling a second terminal of the antifuse includes coupling a second terminal of the antifuse to a ground reference voltage through an n-channel control transistor to program the antifuse with current from the common bus line;
switching off the control transistor includes switching off the n-channel control transistor with a control circuit to uncouple the second terminal of the antifuse from the ground reference voltage after the antifuse is programmed; and
reducing a voltage includes reducing a voltage on a drain terminal of the n-channel control transistor with an n-channel impedance transistor that is switched on and coupled between the second terminal of the antifuse and the drain terminal of the control transistor to reduce a probability of snap-back in the control transistor.
21. A method of operating an antifuse circuit including:
coupling an elevated voltage to a first terminal of an unprogrammed antifuse from a common bus line;
separating a second terminal of the antifuse from a reference voltage with a control transistor that is switched off; and
reducing a voltage on a terminal of the control transistor with an impedance transistor coupled between the second terminal of the antifuse and the terminal of the control transistor to reduce leakage current in the control transistor.
22. The method of claim 21 , wherein:
coupling an elevated voltage includes coupling an elevated voltage from an external pin to a first terminal of an antifuse through a common bus line;
separating a second terminal of the antifuse includes separating a second terminal of the antifuse from a ground reference voltage with an n-channel control transistor that is switched off; and
reducing a voltage includes reducing a voltage on a drain terminal of the n-channel control transistor with an n-channel impedance transistor that is switched on and coupled between the second terminal of the antifuse and the drain terminal of the control transistor to reduce leakage current in the control transistor.
23. An antifuse circuit comprising:
an antifuse having a first terminal coupled to an elevated voltage in a programming mode and a reference voltage in an active mode;
a read circuit including a p-channel transistor coupled between a read voltage source and a second terminal of the antifuse to couple the read voltage source to the antifuse to read the antifuse in the active mode; and
a floating well driver logic circuit coupled to a gate terminal and a well of the p-channel transistor to raise a voltage of the gate terminal and the well in the programming mode to substantially prevent current in the p-channel transistor.
24. The antifuse circuit of claim 23 , wherein:
the antifuse includes an antifuse having a first terminal coupled to a common bus line, the common bus line being coupled to the elevated voltage in the programming mode and to a ground reference voltage in the active mode;
the read circuit further includes a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit; and
the floating well driver logic circuit further includes a voltage source coupled to a gate terminal and a well of selected ones of the p-channel transistors in the read circuit to raise a voltage of the gate terminals and the wells in the programming mode to substantially prevent current in the selected p-channel transistors.
25. A method of operating an antifuse circuit, comprising:
coupling an elevated voltage to a first terminal of an antifuse in a programming mode and coupling a reference voltage to the first terminal in an active mode;
reading the antifuse in the active mode with a p-channel transistor coupled between a read voltage source and a second terminal of the antifuse; and
raising a voltage of a gate terminal and a well of the p-channel transistor in the programming mode to substantially prevent current in the p-channel transistor.
26. The method of claim 25 , wherein:
coupling a reference voltage includes coupling a ground reference voltage to the first terminal in the active mode;
reading the antifuse further includes:
coupling the read voltage source to the second terminal of the antifuse; and
detecting a voltage on the second terminal of the antifuse with an inverter in a read circuit; and
raising a voltage includes:
coupling a rising voltage on the second terminal of the antifuse to a gate terminal and a well of each of a plurality of p-channel transistors in the read circuit.
27. An integrated memory device comprising:
an array of memory cells;
an address decoder;
a plurality of input/output paths;
an input/output control circuit; and
an antifuse circuit including:
an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;
a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;
a common bus line driver circuit to couple the common bus line to a reference voltage during an active mode;
a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;
a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and
a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.
28. An integrated circuit comprising:
an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;
a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;
a common bus line driver circuit to couple the common bus line to a reference voltage during an active mode;
means for reading the antifuse during the active mode;
a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and
means for switching off transistors in the latch circuit and in the means for reading the antifuse during the programming mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/292,653 US20060097345A1 (en) | 2000-08-31 | 2005-12-02 | Gate dielectric antifuse circuits and methods for operating same |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US09/652,429 US6630724B1 (en) | 2000-08-31 | 2000-08-31 | Gate dielectric antifuse circuits and methods for operating same |
US10/680,481 US7030458B2 (en) | 2000-08-31 | 2003-10-06 | Gate dielectric antifuse circuits and methods for operating same |
US11/292,653 US20060097345A1 (en) | 2000-08-31 | 2005-12-02 | Gate dielectric antifuse circuits and methods for operating same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/680,481 Division US7030458B2 (en) | 2000-08-31 | 2003-10-06 | Gate dielectric antifuse circuits and methods for operating same |
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US20060097345A1 true US20060097345A1 (en) | 2006-05-11 |
Family
ID=28675747
Family Applications (3)
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US09/652,429 Expired - Lifetime US6630724B1 (en) | 2000-08-31 | 2000-08-31 | Gate dielectric antifuse circuits and methods for operating same |
US10/680,481 Expired - Fee Related US7030458B2 (en) | 2000-08-31 | 2003-10-06 | Gate dielectric antifuse circuits and methods for operating same |
US11/292,653 Abandoned US20060097345A1 (en) | 2000-08-31 | 2005-12-02 | Gate dielectric antifuse circuits and methods for operating same |
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US09/652,429 Expired - Lifetime US6630724B1 (en) | 2000-08-31 | 2000-08-31 | Gate dielectric antifuse circuits and methods for operating same |
US10/680,481 Expired - Fee Related US7030458B2 (en) | 2000-08-31 | 2003-10-06 | Gate dielectric antifuse circuits and methods for operating same |
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US6630724B1 (en) | 2003-10-07 |
US7030458B2 (en) | 2006-04-18 |
US20040065941A1 (en) | 2004-04-08 |
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