US20050263400A1 - Method of applying cladding material on conductive lines of MRAM devices - Google Patents
Method of applying cladding material on conductive lines of MRAM devices Download PDFInfo
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- US20050263400A1 US20050263400A1 US11/139,143 US13914305A US2005263400A1 US 20050263400 A1 US20050263400 A1 US 20050263400A1 US 13914305 A US13914305 A US 13914305A US 2005263400 A1 US2005263400 A1 US 2005263400A1
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- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
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- 229910052759 nickel Inorganic materials 0.000 claims description 7
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims 1
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
Definitions
- This invention relates to semiconductor memory devices.
- the present invention relates to improved methods of fabricating semiconductor random access memory devices that utilize a magnetic field.
- a magnetic memory device has a structure which includes ferromagnetic layers separated by a non-magnetic layer. Information is stored as directions of magnetization vectors in magnetic layers. Magnetic vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions which are called “Parallel” and “Anti-parallel”-states, respectively. In response to parallel and anti-parallel states, the magnetic memory device represents two different resistances. The resistance indicates minimum and maximum values when the magnetization vectors of two magnetic layers point in substantially the same and opposite directions, respectively. Accordingly, a detection of changes in resistance allows a magnetic memory device to provide stored information.
- MRAM magnetoresistive random access memory
- the memory cells are programmed by magnetic fields induced by a current carrying conductor such as a copper interconnect.
- a current carrying conductor such as a copper interconnect.
- two interconnects are employed, with one positioned above (generally referred to as the bit line) the MRAM device and the second positioned below (generally referred to as the digit line) the MRAM device.
- the term “conductive line or lines” will be used to generally identify either or both lines hereinafter.
- the purpose of the electrically conductive lines is to provide magnetic fields for programming the MRAM device.
- a problem with prior semiconductor processing of conductive lines for MRAM devices is that it involves using a number of expensive and complicated vacuum deposition tools and complex processing steps which increase the cycle time and cost.
- the preferred method of forming the conductive lines is to form copper interconnects by a damascene or inlaid process wherein the conductive line is typically covered with a flux concentrating layer.
- the flux concentrating layer functions to focus the magnetic field around the conductive line toward the MRAM cell or bit, and, consequently, reduces the required programming current by a factor of approximately two.
- the steps involved in forming the flux concentrating material require the use of several vacuum deposition and etching tools, as well as photolayers.
- RIE reactive ion etching
- an improved method of fabricating a flux concentrating region for use in a MRAM device involves forming a flux concentrating region positioned on a conductive line by using electrochemical deposition.
- the conductive line includes conductive material, such as copper, aluminum, or similar metals.
- the novel method of fabricating the flux concentrating layer involves immersing the conductive line in a bath containing dissolved metal ions of a metal more noble than the metal that constitutes the conductive line.
- the bath may comprise palladium, platinum, ruthenium, or rhodium.
- the dissolved metal ions are more noble than the conductive line, a process known as displacement plating occurs only on the conductive line and nowhere else.
- the process forms a barrier layer on the conductive line.
- the barrier layer is then immersed in an electrolessly plating bath to form a flux concentrating layer positioned on the barrier layer.
- the flux concentrating layer includes NiFe, but other electrolessly plating magnetic materials could be used as well.
- the flux concentrating layer is immersed in a second displacement plating bath containing dissolved metal ions.
- the dissolved metal ions in the second bath form a second barrier layer on the flux concentrating layer through displacement plating.
- the first barrier layer, flux concentrating layer, and second barrier layer cooperate to form a cladding or flux concentrating region that increases the magnetic field proximate to the conductive bit or digit line.
- the thickness of the first outside layer, flux concentrating layer, and second barrier layer can be controlled by the immersion time in the various baths.
- FIGS. 1 through 5 are simplified sectional views illustrating several steps in a method of fabricating a magnetoresistive random access memory device with a damascene conductive bit line in accordance with the present invention.
- FIGS. 6 through 10 are simplified sectional views illustrating several steps in a method of fabricating a magnetoresistive random access memory device with a self aligned conductive bit line in accordance with the present invention.
- FIGS. 1 through 5 several sequential steps are illustrated in the fabrication of a MRAM device 10 with a cladded conductive line, in accordance with the present invention.
- the conductive line includes copper.
- the conductive line can include other conductive materials, such as aluminum, tungsten, titanium, and stacks thereof where, in general, the fabrication steps or materials might vary slightly.
- FIG. 1 a first step in the fabrication of a conductive line for MRAM device 10 is illustrated. It will be understood that this is a simplified view, generally showing the areas of interest, and in particular a conductive line region. Also, for ease of discussion, the fabrication of the conductive line in electrical contact with MRAM device 10 is discussed in reference to FIGS. 1 through 5 . However, it should be understood that it is also anticipated by this disclosure to form a conductive bit line that is adjacent to and not in electrical contact with MRAM device 10 .
- MRAM device 10 is a standard MRAM bit or cell formed according to well-known practices in the art. While a standard MRAM bit is illustrated herein for convenience, it will be understood by those skilled in the art that many other types of memory devices could be provided. Also, while a single MRAM bit is illustrated for convenience, it should be understood that a complete array of devices or control/driver circuits around the periphery of an array of magnetic memory bits may be formed.
- a typical damascene conductive line is formed in proximity to MRAM device 10 generally incorporating the following steps.
- a dielectric layer 12 is formed on a surface of MRAM device 10 and any surrounding material. In some specific embodiments layer 12 may be formed around MRAM device 10 during the fabrication of MRAM device 10 .
- a nitride (any nitride, such as a metal nitride) layer 14 is positioned on layer 12 and generally operates as an etch stop layer.
- a second oxide layer 16 is formed on nitride layer 14 .
- a trench is then formed through layers 12 , 14 , and 16 in alignment with MRAM device 10 in any well known process.
- a thin barrier layer 18 of tantalum, tantalum nitride, or the like, is deposited on the surface of the trench and surrounding layers 12 , 14 , 16 .
- a thin seed layer (not shown) of copper is deposited on barrier layer 18 .
- barrier layer 18 is generally referred to as a barrier/copper seed layer.
- a thick copper layer 20 is then electroplated onto barrier/copper seed layer 18 .
- Copper layer 20 and barrier/copper seed layer 18 are partially removed by any well known process (e.g. chemical mechanical polishing or a similar technique) and oxide layer 16 is removed by etching (nitride layer 14 may or may not be removed during the etching process) to provide conductive line 22 , as illustrated in FIG. 2 .
- conductive line 22 includes copper, but it will be understood that it could include other conductive materials, such as aluminum, tungsten, etc.
- copper is generally used in advanced semiconductor processing to form conductive interconnects. Accordingly, it is intended that the method described herein be applicable to both a copper damascene process and other metal damascene or non-damascene processes wherein the materials and fabrication steps are adjusted accordingly for the chosen metal process. More information as to cladding a MRAM device can be found in U.S. Pat. No. 6,211,090, entitled “Method of Fabricating Flux Concentrating Layer for use with Magnetoresistive Random Access Memories”, issued on Apr. 3, 2001, and incorporated herein by reference.
- a first barrier layer 25 is formed on conductive line 22 as follows.
- Conductive line 22 is immersed in a bath containing dissolved ions of a selected metal to form a barrier layer 25 with a thickness sufficient to provide good barrier properties.
- the metal ion bath includes dissolved ions that are more noble than the metal included in conductive line 22 (e.g. copper) so that displacement plating occurs.
- Suitable metal ions in the first bath include platinum, palladium, ruthenium, or rhodium, but other materials may be used and will depend on the composition of conductive line 22 .
- the thickness of barrier layer 25 can generally be controlled by changing the amount of time conductive line 22 is immersed in the metal ion bath.
- Barrier layer 25 acts as a diffusion barrier to fast diffusing elements, such as copper, and nickel-iron alloys.
- barrier layer 25 is immersed in an electroless plating bath to form a flux concentrating layer 27 with a thickness sufficient to provide good flux concentrating properties. Further, changing the amount of time that barrier layer 25 is immersed in the electroless plating bath generally controls the thickness of flux concentrating layer 27 .
- Flux concentrating layer 27 is formed of a high permeability magnetic material and has the characteristic of concentrating magnetic flux produced by the current flowing in conductive line 22 , therefore, reducing the amount of current required to produce the desired action.
- the electroless plating bath may, for example, include one or more of Ni/B, Ni/P, Co/P, Fe/Ni/P, Fe/Ni/B, Ni/Fe/B/P, or Ni/Fe/Co/P, but it will be understood that other material systems may be used in specific applications.
- Flux concentrating layer 27 is also an electrically conducting magnetic material, such as nickel iron, or any suitable material having sufficiently high permeability to concentrate the magnetic flux in the desired area and be metallurgically compatible with the remaining material structure.
- flux concentrating layer 27 is immersed in a second bath containing dissolved ions of a second metal to form a second barrier layer 29 .
- Suitable metal ions for use in the second bath include platinum, palladium, ruthenium, or rhodium, but it will be understood that other materials may be used.
- Changing the amount of time that flux concentrating layer 27 is immersed in the second metal ion bath generally controls the thickness of barrier layer 29 . It will be understood that in some embodiments, the formation of barrier layer 29 may not be desired and is included in the preferred embodiment for illustrative purposes only.
- Barrier layer 25 , flux concentrating layer 27 , and barrier layer 29 cooperate to form a cladding region 30 .
- the layers of cladding region 30 are deposited by using immersion or electroless plating, as described above, which eliminates the need to pattern and etch the cladding materials. Eliminating the pattern and etch steps substantially improves the process (e.g. simpler processing steps, at a reduced cost, and with a reduced cycle time) and produces a much more reliable product (e.g. not as subject to shorting and similar problems).
- a MRAM cell or device 40 is formed in any well known manner and at least partially encapsulated in material 42 so as to provide a smooth upper surface 41 .
- Sidewall spacers 45 are formed in the trench by any of the well known methods (see for example, U.S. Pat. No. 5,940,319, included herein by reference).
- spacers 45 are formed of cladding or flux concentrating materials, and, optionally barrier materials, that aid in concentrating or directing magnetic flux toward MRAM device 40 .
- the trench is then filled with a conductive material, such as copper, titanium, aluminum, etc., to form a conductive line 47 .
- conductive line 47 is immersed in a bath containing dissolved ions of a selected metal to form a barrier layer 49 .
- the metal ion bath includes dissolved ions that are more noble than the metal included in conductive line 47 (e.g. copper) so that displacement plating occurs.
- Suitable metal ions in the first bath include platinum, palladium, ruthenium, or rhodium, but other materials may be used and will depend on the composition of conductive line 47 .
- the thickness of barrier layer 49 can generally be controlled by changing the amount of time conductive line 47 is immersed in the metal ion bath.
- Barrier layer 49 acts as a diffusion barrier to fast diffusing elements, such as copper, and nickel-iron alloys.
- displacement plating occurs only in conjunction with conductive line 47 and, therefore, barrier layer 49 is self-aligned with conductive line 47 .
- barrier layer 49 is immersed in an electroless plating bath to form a flux concentrating layer 50 with a thickness sufficient to provide good flux concentrating properties. Changing the amount of time that barrier layer 49 is immersed in the electroless plating bath generally controls the thickness of flux concentrating layer 50 .
- Flux concentrating layer 50 is formed of a high permeability magnetic material and has the characteristic of concentrating magnetic flux produced by the current flowing in conductive line 47 , therefore, reducing the amount of current required to produce the desired action.
- the electroless plating bath may, for example, include one or more of Ni/B, Ni/P, Co/P, Fe/Ni/P, Fe/Ni/B, Ni/Fe/B/P, or Ni/Fe/Co/P, but it will be understood that other material systems may be used in specific applications.
- Flux concentrating layer 50 is also an electrically conducting magnetic material, such as nickel iron, or any suitable material having sufficiently high permeability to concentrate the magnetic flux in the desired area and be metallurgically compatible with the remaining material structure. Again it should be noted that plating occurs only in conjunction with barrier layer 49 and, therefore, flux concentrating layer 50 is self-aligned with barrier layer 49 and conductive line 47 .
- flux concentrating layer 50 is immersed in a second bath containing dissolved ions of a second metal to form a second barrier layer 52 .
- Suitable metal ions for use in the second bath include platinum, palladium, ruthenium, or rhodium, but it will be understood that other materials may be used.
- Changing the amount of time that flux concentrating layer 50 is immersed in the second metal ion bath generally controls the thickness of barrier layer 52 . It will be understood that in some embodiments, the formation of barrier layer 52 may not be desired and is included in the preferred embodiment for illustrative purposes only.
- Barrier layer 49 , flux concentrating layer 50 , and barrier layer 52 are generally referred to as cladding region 55 .
- a layer 60 of dielectric material (e.g. oxides, nitrides, or the like) is deposited on layer 44 around cladding region 55 .
- layer 60 can be deposited and patterned prior to the formation of cladding region 55 or it can be deposited subsequently, as described above, depending upon the specific application and the processes used in other areas of the structure.
- flux concentrating layer 50 and barrier layer 52 may extend slightly over the edges of a previously formed layer (e.g. barrier layer 49 and flux concentrating layer 50 , respectively). When this additional material is undesirable, (e.g. because of adjacent components or MRAM devices) the formation can be limited through the use of layer 60 .
- the method of fabricating cladding region 30 in FIG. 5 and cladding region 55 in FIG. 10 involves using electrochemical deposition, such as immersion or electroless plating, to form the necessary layers.
- Electrochemical deposition improves the fabrication sequence because it eliminates a photolayer. Thus, the processing steps are simpler and less expensive.
- electrochemical deposition to form cladding regions 30 and 55 , no photo-steps are needed and the cycle time to fabricate MRAM devices is reduced.
- electrochemical deposition the shorting problem associated with using subtractive patterning is avoided and the number of expensive photolayers is decreased.
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Abstract
Description
- This invention relates to semiconductor memory devices.
- More particularly, the present invention relates to improved methods of fabricating semiconductor random access memory devices that utilize a magnetic field.
- A magnetic memory device has a structure which includes ferromagnetic layers separated by a non-magnetic layer. Information is stored as directions of magnetization vectors in magnetic layers. Magnetic vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions which are called “Parallel” and “Anti-parallel”-states, respectively. In response to parallel and anti-parallel states, the magnetic memory device represents two different resistances. The resistance indicates minimum and maximum values when the magnetization vectors of two magnetic layers point in substantially the same and opposite directions, respectively. Accordingly, a detection of changes in resistance allows a magnetic memory device to provide stored information.
- In magnetoresistive random access memory (hereinafter referred to as “MRAM”) devices, the memory cells are programmed by magnetic fields induced by a current carrying conductor such as a copper interconnect. Typically, two interconnects are employed, with one positioned above (generally referred to as the bit line) the MRAM device and the second positioned below (generally referred to as the digit line) the MRAM device. Because the name and position of the lines may be altered in various applications, the term “conductive line or lines” will be used to generally identify either or both lines hereinafter. The purpose of the electrically conductive lines is to provide magnetic fields for programming the MRAM device.
- A problem with prior semiconductor processing of conductive lines for MRAM devices is that it involves using a number of expensive and complicated vacuum deposition tools and complex processing steps which increase the cycle time and cost. For example, the preferred method of forming the conductive lines is to form copper interconnects by a damascene or inlaid process wherein the conductive line is typically covered with a flux concentrating layer. The flux concentrating layer functions to focus the magnetic field around the conductive line toward the MRAM cell or bit, and, consequently, reduces the required programming current by a factor of approximately two. However, the steps involved in forming the flux concentrating material require the use of several vacuum deposition and etching tools, as well as photolayers. For example, reactive ion etching (hereinafter referred to as “RIE”) is typically used to remove the evaporated layers from unwanted areas. Unfortunately, RIE can over-etch the layers, which can cause shorting. Also, photolayers are an expensive step in device fabrication, so the cost can be reduced by utilizing alternative techniques.
- It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
- To achieve the objects and advantages specified above and others, an improved method of fabricating a flux concentrating region for use in a MRAM device is disclosed. The method involves forming a flux concentrating region positioned on a conductive line by using electrochemical deposition. In the preferred embodiment, the conductive line includes conductive material, such as copper, aluminum, or similar metals. The novel method of fabricating the flux concentrating layer involves immersing the conductive line in a bath containing dissolved metal ions of a metal more noble than the metal that constitutes the conductive line. For example, if copper is the conductive line, the bath may comprise palladium, platinum, ruthenium, or rhodium. Because the dissolved metal ions are more noble than the conductive line, a process known as displacement plating occurs only on the conductive line and nowhere else. The process forms a barrier layer on the conductive line. The barrier layer is then immersed in an electrolessly plating bath to form a flux concentrating layer positioned on the barrier layer. In a preferred embodiment, the flux concentrating layer includes NiFe, but other electrolessly plating magnetic materials could be used as well.
- In an additional and optional processing step, the flux concentrating layer is immersed in a second displacement plating bath containing dissolved metal ions. The dissolved metal ions in the second bath form a second barrier layer on the flux concentrating layer through displacement plating. The first barrier layer, flux concentrating layer, and second barrier layer cooperate to form a cladding or flux concentrating region that increases the magnetic field proximate to the conductive bit or digit line. Also, the thickness of the first outside layer, flux concentrating layer, and second barrier layer can be controlled by the immersion time in the various baths.
- The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings:
-
FIGS. 1 through 5 are simplified sectional views illustrating several steps in a method of fabricating a magnetoresistive random access memory device with a damascene conductive bit line in accordance with the present invention; and -
FIGS. 6 through 10 are simplified sectional views illustrating several steps in a method of fabricating a magnetoresistive random access memory device with a self aligned conductive bit line in accordance with the present invention. - Several embodiments of cladded conductive lines in magnetic proximity to MRAM devices are discussed in conjunction with the drawings in order to illustrate the preferred method of forming cladding material on MRAM device conductive lines. Turning now to
FIGS. 1 through 5 , several sequential steps are illustrated in the fabrication of aMRAM device 10 with a cladded conductive line, in accordance with the present invention. In the preferred embodiment, the conductive line includes copper. However, it will be understood that the conductive line can include other conductive materials, such as aluminum, tungsten, titanium, and stacks thereof where, in general, the fabrication steps or materials might vary slightly. - Referring specifically to
FIG. 1 , a first step in the fabrication of a conductive line forMRAM device 10 is illustrated. It will be understood that this is a simplified view, generally showing the areas of interest, and in particular a conductive line region. Also, for ease of discussion, the fabrication of the conductive line in electrical contact withMRAM device 10 is discussed in reference toFIGS. 1 through 5 . However, it should be understood that it is also anticipated by this disclosure to form a conductive bit line that is adjacent to and not in electrical contact withMRAM device 10. - Further, in this specific embodiment,
MRAM device 10 is a standard MRAM bit or cell formed according to well-known practices in the art. While a standard MRAM bit is illustrated herein for convenience, it will be understood by those skilled in the art that many other types of memory devices could be provided. Also, while a single MRAM bit is illustrated for convenience, it should be understood that a complete array of devices or control/driver circuits around the periphery of an array of magnetic memory bits may be formed. - A typical damascene conductive line is formed in proximity to
MRAM device 10 generally incorporating the following steps. Adielectric layer 12 is formed on a surface ofMRAM device 10 and any surrounding material. In somespecific embodiments layer 12 may be formed aroundMRAM device 10 during the fabrication ofMRAM device 10. A nitride (any nitride, such as a metal nitride)layer 14 is positioned onlayer 12 and generally operates as an etch stop layer. Asecond oxide layer 16 is formed onnitride layer 14. A trench is then formed throughlayers MRAM device 10 in any well known process. Athin barrier layer 18, of tantalum, tantalum nitride, or the like, is deposited on the surface of the trench and surroundinglayers barrier layer 18. For convenience,barrier layer 18 is generally referred to as a barrier/copper seed layer. Athick copper layer 20 is then electroplated onto barrier/copper seed layer 18.Copper layer 20 and barrier/copper seed layer 18, are partially removed by any well known process (e.g. chemical mechanical polishing or a similar technique) andoxide layer 16 is removed by etching (nitride layer 14 may or may not be removed during the etching process) to provideconductive line 22, as illustrated inFIG. 2 . - In the preferred embodiment,
conductive line 22 includes copper, but it will be understood that it could include other conductive materials, such as aluminum, tungsten, etc. However, it is well known in the art that copper is generally used in advanced semiconductor processing to form conductive interconnects. Accordingly, it is intended that the method described herein be applicable to both a copper damascene process and other metal damascene or non-damascene processes wherein the materials and fabrication steps are adjusted accordingly for the chosen metal process. More information as to cladding a MRAM device can be found in U.S. Pat. No. 6,211,090, entitled “Method of Fabricating Flux Concentrating Layer for use with Magnetoresistive Random Access Memories”, issued on Apr. 3, 2001, and incorporated herein by reference. - Turning now to
FIG. 3 , afirst barrier layer 25 is formed onconductive line 22 as follows.Conductive line 22 is immersed in a bath containing dissolved ions of a selected metal to form abarrier layer 25 with a thickness sufficient to provide good barrier properties. The metal ion bath includes dissolved ions that are more noble than the metal included in conductive line 22 (e.g. copper) so that displacement plating occurs. Suitable metal ions in the first bath include platinum, palladium, ruthenium, or rhodium, but other materials may be used and will depend on the composition ofconductive line 22. The thickness ofbarrier layer 25 can generally be controlled by changing the amount of timeconductive line 22 is immersed in the metal ion bath.Barrier layer 25 acts as a diffusion barrier to fast diffusing elements, such as copper, and nickel-iron alloys. - Referring additionally to
FIG. 4 ,barrier layer 25 is immersed in an electroless plating bath to form aflux concentrating layer 27 with a thickness sufficient to provide good flux concentrating properties. Further, changing the amount of time thatbarrier layer 25 is immersed in the electroless plating bath generally controls the thickness offlux concentrating layer 27.Flux concentrating layer 27 is formed of a high permeability magnetic material and has the characteristic of concentrating magnetic flux produced by the current flowing inconductive line 22, therefore, reducing the amount of current required to produce the desired action. The electroless plating bath may, for example, include one or more of Ni/B, Ni/P, Co/P, Fe/Ni/P, Fe/Ni/B, Ni/Fe/B/P, or Ni/Fe/Co/P, but it will be understood that other material systems may be used in specific applications.Flux concentrating layer 27 is also an electrically conducting magnetic material, such as nickel iron, or any suitable material having sufficiently high permeability to concentrate the magnetic flux in the desired area and be metallurgically compatible with the remaining material structure. - Referring additionally to
FIG. 5 ,flux concentrating layer 27 is immersed in a second bath containing dissolved ions of a second metal to form asecond barrier layer 29. Suitable metal ions for use in the second bath include platinum, palladium, ruthenium, or rhodium, but it will be understood that other materials may be used. Changing the amount of time thatflux concentrating layer 27 is immersed in the second metal ion bath generally controls the thickness ofbarrier layer 29. It will be understood that in some embodiments, the formation ofbarrier layer 29 may not be desired and is included in the preferred embodiment for illustrative purposes only. -
Barrier layer 25,flux concentrating layer 27, andbarrier layer 29 cooperate to form acladding region 30. The layers ofcladding region 30 are deposited by using immersion or electroless plating, as described above, which eliminates the need to pattern and etch the cladding materials. Eliminating the pattern and etch steps substantially improves the process (e.g. simpler processing steps, at a reduced cost, and with a reduced cycle time) and produces a much more reliable product (e.g. not as subject to shorting and similar problems). - Turning now to
FIGS. 6 through 10 , a process is illustrated for fabricating a self-aligned flux concentrating region in conjunction with a conductive line, in accordance with the present invention. Referring specifically toFIG. 6 , a MRAM cell ordevice 40 is formed in any well known manner and at least partially encapsulated inmaterial 42 so as to provide a smoothupper surface 41. Alayer 44 of dielectric material, e.g. oxide, nitride, or the like, is deposited onsurface 41 and patterned to provide a trench in alignment withMRAM device 40.Sidewall spacers 45 are formed in the trench by any of the well known methods (see for example, U.S. Pat. No. 5,940,319, included herein by reference). In this embodiment, spacers 45 are formed of cladding or flux concentrating materials, and, optionally barrier materials, that aid in concentrating or directing magnetic flux towardMRAM device 40. The trench is then filled with a conductive material, such as copper, titanium, aluminum, etc., to form aconductive line 47. - Referring additionally to
FIG. 7 ,conductive line 47 is immersed in a bath containing dissolved ions of a selected metal to form abarrier layer 49. As explained above, the metal ion bath includes dissolved ions that are more noble than the metal included in conductive line 47 (e.g. copper) so that displacement plating occurs. Suitable metal ions in the first bath include platinum, palladium, ruthenium, or rhodium, but other materials may be used and will depend on the composition ofconductive line 47. The thickness ofbarrier layer 49 can generally be controlled by changing the amount of timeconductive line 47 is immersed in the metal ion bath.Barrier layer 49 acts as a diffusion barrier to fast diffusing elements, such as copper, and nickel-iron alloys. Here it should be noted that displacement plating occurs only in conjunction withconductive line 47 and, therefore,barrier layer 49 is self-aligned withconductive line 47. - Referring additionally to
FIG. 8 ,barrier layer 49 is immersed in an electroless plating bath to form aflux concentrating layer 50 with a thickness sufficient to provide good flux concentrating properties. Changing the amount of time thatbarrier layer 49 is immersed in the electroless plating bath generally controls the thickness offlux concentrating layer 50.Flux concentrating layer 50 is formed of a high permeability magnetic material and has the characteristic of concentrating magnetic flux produced by the current flowing inconductive line 47, therefore, reducing the amount of current required to produce the desired action. The electroless plating bath may, for example, include one or more of Ni/B, Ni/P, Co/P, Fe/Ni/P, Fe/Ni/B, Ni/Fe/B/P, or Ni/Fe/Co/P, but it will be understood that other material systems may be used in specific applications.Flux concentrating layer 50 is also an electrically conducting magnetic material, such as nickel iron, or any suitable material having sufficiently high permeability to concentrate the magnetic flux in the desired area and be metallurgically compatible with the remaining material structure. Again it should be noted that plating occurs only in conjunction withbarrier layer 49 and, therefore,flux concentrating layer 50 is self-aligned withbarrier layer 49 andconductive line 47. - Referring additionally to
FIG. 9 ,flux concentrating layer 50 is immersed in a second bath containing dissolved ions of a second metal to form asecond barrier layer 52. Suitable metal ions for use in the second bath include platinum, palladium, ruthenium, or rhodium, but it will be understood that other materials may be used. Changing the amount of time thatflux concentrating layer 50 is immersed in the second metal ion bath generally controls the thickness ofbarrier layer 52. It will be understood that in some embodiments, the formation ofbarrier layer 52 may not be desired and is included in the preferred embodiment for illustrative purposes only.Barrier layer 49,flux concentrating layer 50, and barrier layer 52 (if included) are generally referred to ascladding region 55. - Turning now to
FIG. 10 , alayer 60 of dielectric material (e.g. oxides, nitrides, or the like) is deposited onlayer 44 aroundcladding region 55. Here it should be understood thatlayer 60 can be deposited and patterned prior to the formation ofcladding region 55 or it can be deposited subsequently, as described above, depending upon the specific application and the processes used in other areas of the structure. In some processes, for example,flux concentrating layer 50 andbarrier layer 52 may extend slightly over the edges of a previously formed layer (e.g. barrier layer 49 andflux concentrating layer 50, respectively). When this additional material is undesirable, (e.g. because of adjacent components or MRAM devices) the formation can be limited through the use oflayer 60. - Thus, the method of fabricating
cladding region 30 inFIG. 5 andcladding region 55 inFIG. 10 involves using electrochemical deposition, such as immersion or electroless plating, to form the necessary layers. Electrochemical deposition improves the fabrication sequence because it eliminates a photolayer. Thus, the processing steps are simpler and less expensive. However, by using electrochemical deposition to formcladding regions - Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
Claims (10)
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US11/139,143 US7402529B2 (en) | 2002-03-08 | 2005-05-26 | Method of applying cladding material on conductive lines of MRAM devices |
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US10/093,909 US6927072B2 (en) | 2002-03-08 | 2002-03-08 | Method of applying cladding material on conductive lines of MRAM devices |
US11/139,143 US7402529B2 (en) | 2002-03-08 | 2005-05-26 | Method of applying cladding material on conductive lines of MRAM devices |
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Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6740947B1 (en) * | 2002-11-13 | 2004-05-25 | Hewlett-Packard Development Company, L.P. | MRAM with asymmetric cladded conductor |
US6885074B2 (en) * | 2002-11-27 | 2005-04-26 | Freescale Semiconductor, Inc. | Cladded conductor for use in a magnetoelectronics device and method for fabricating the same |
US6952364B2 (en) * | 2003-03-03 | 2005-10-04 | Samsung Electronics Co., Ltd. | Magnetic tunnel junction structures and methods of fabrication |
KR100615600B1 (en) * | 2004-08-09 | 2006-08-25 | 삼성전자주식회사 | High density magnetic random access memory device and method of fabricating the smae |
US20060034012A1 (en) * | 2003-08-29 | 2006-02-16 | Lam Terence T | Self-aligned coil process in magnetic recording heads |
US7369428B2 (en) * | 2003-09-29 | 2008-05-06 | Samsung Electronics Co., Ltd. | Methods of operating a magnetic random access memory device and related devices and structures |
KR100615089B1 (en) * | 2004-07-14 | 2006-08-23 | 삼성전자주식회사 | Magnetic random access memory with low switching current |
KR100835275B1 (en) * | 2004-08-12 | 2008-06-05 | 삼성전자주식회사 | Methods of operating a magnetic random access memory device using a spin injection mechanism |
US7372722B2 (en) * | 2003-09-29 | 2008-05-13 | Samsung Electronics Co., Ltd. | Methods of operating magnetic random access memory devices including heat-generating structures |
KR100568512B1 (en) * | 2003-09-29 | 2006-04-07 | 삼성전자주식회사 | Magnetic thermal random access memory cells having a heat-generating layer and methods of operating the same |
US20050095855A1 (en) * | 2003-11-05 | 2005-05-05 | D'urso John J. | Compositions and methods for the electroless deposition of NiFe on a work piece |
US6925000B2 (en) | 2003-12-12 | 2005-08-02 | Maglabs, Inc. | Method and apparatus for a high density magnetic random access memory (MRAM) with stackable architecture |
US7061037B2 (en) * | 2004-07-06 | 2006-06-13 | Maglabs, Inc. | Magnetic random access memory with multiple memory layers and improved memory cell selectivity |
KR100660539B1 (en) * | 2004-07-29 | 2006-12-22 | 삼성전자주식회사 | Magnetic memory devices and methods of forming the same |
US20060022286A1 (en) * | 2004-07-30 | 2006-02-02 | Rainer Leuschner | Ferromagnetic liner for conductive lines of magnetic memory cells |
US7075818B2 (en) * | 2004-08-23 | 2006-07-11 | Maglabs, Inc. | Magnetic random access memory with stacked memory layers having access lines for writing and reading |
US7411816B2 (en) * | 2006-01-19 | 2008-08-12 | Honeywell International Inc. | Enhanced MRAM reference bit programming structure |
TW200905679A (en) * | 2007-07-31 | 2009-02-01 | Ind Tech Res Inst | Structure of magnetic random access memory and fabrication method thereof |
US7800471B2 (en) | 2008-04-04 | 2010-09-21 | Cedar Ridge Research, Llc | Field emission system and method |
US8816805B2 (en) | 2008-04-04 | 2014-08-26 | Correlated Magnetics Research, Llc. | Magnetic structure production |
US8373527B2 (en) | 2008-04-04 | 2013-02-12 | Correlated Magnetics Research, Llc | Magnetic attachment system |
US8279032B1 (en) | 2011-03-24 | 2012-10-02 | Correlated Magnetics Research, Llc. | System for detachment of correlated magnetic structures |
US8174347B2 (en) | 2010-07-12 | 2012-05-08 | Correlated Magnetics Research, Llc | Multilevel correlated magnetic system and method for using the same |
US8576036B2 (en) | 2010-12-10 | 2013-11-05 | Correlated Magnetics Research, Llc | System and method for affecting flux of multi-pole magnetic structures |
US9202616B2 (en) | 2009-06-02 | 2015-12-01 | Correlated Magnetics Research, Llc | Intelligent magnetic system |
US8779879B2 (en) | 2008-04-04 | 2014-07-15 | Correlated Magnetics Research LLC | System and method for positioning a multi-pole magnetic structure |
US9105380B2 (en) | 2008-04-04 | 2015-08-11 | Correlated Magnetics Research, Llc. | Magnetic attachment system |
US8760250B2 (en) | 2009-06-02 | 2014-06-24 | Correlated Magnetics Rsearch, LLC. | System and method for energy generation |
US8760251B2 (en) | 2010-09-27 | 2014-06-24 | Correlated Magnetics Research, Llc | System and method for producing stacked field emission structures |
US8179219B2 (en) | 2008-04-04 | 2012-05-15 | Correlated Magnetics Research, Llc | Field emission system and method |
US8368495B2 (en) | 2008-04-04 | 2013-02-05 | Correlated Magnetics Research LLC | System and method for defining magnetic structures |
US9371923B2 (en) | 2008-04-04 | 2016-06-21 | Correlated Magnetics Research, Llc | Magnetic valve assembly |
JP5300428B2 (en) | 2008-11-13 | 2013-09-25 | ルネサスエレクトロニクス株式会社 | Arithmetic apparatus and arithmetic processing method |
US8917154B2 (en) | 2012-12-10 | 2014-12-23 | Correlated Magnetics Research, Llc. | System for concentrating magnetic flux |
US8937521B2 (en) | 2012-12-10 | 2015-01-20 | Correlated Magnetics Research, Llc. | System for concentrating magnetic flux of a multi-pole magnetic structure |
US20140111296A1 (en) * | 2012-10-24 | 2014-04-24 | Correlated Magnetics Research, Llc | System and method for producing magnetic structures |
US9275783B2 (en) | 2012-10-15 | 2016-03-01 | Correlated Magnetics Research, Llc. | System and method for demagnetization of a magnetic structure region |
US9404776B2 (en) | 2009-06-02 | 2016-08-02 | Correlated Magnetics Research, Llc. | System and method for tailoring polarity transitions of magnetic structures |
US9257219B2 (en) | 2012-08-06 | 2016-02-09 | Correlated Magnetics Research, Llc. | System and method for magnetization |
US8704626B2 (en) | 2010-05-10 | 2014-04-22 | Correlated Magnetics Research, Llc | System and method for moving an object |
US8169816B2 (en) * | 2009-09-15 | 2012-05-01 | Magic Technologies, Inc. | Fabrication methods of partial cladded write line to enhance write margin for magnetic random access memory |
US9711268B2 (en) | 2009-09-22 | 2017-07-18 | Correlated Magnetics Research, Llc | System and method for tailoring magnetic forces |
JP2011166015A (en) * | 2010-02-12 | 2011-08-25 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
US8638016B2 (en) | 2010-09-17 | 2014-01-28 | Correlated Magnetics Research, Llc | Electromagnetic structure having a core element that extends magnetic coupling around opposing surfaces of a circular magnetic structure |
JP2012069630A (en) * | 2010-09-22 | 2012-04-05 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
US8702437B2 (en) | 2011-03-24 | 2014-04-22 | Correlated Magnetics Research, Llc | Electrical adapter system |
US9330825B2 (en) | 2011-04-12 | 2016-05-03 | Mohammad Sarai | Magnetic configurations |
US8963380B2 (en) | 2011-07-11 | 2015-02-24 | Correlated Magnetics Research LLC. | System and method for power generation system |
KR20130016827A (en) * | 2011-08-09 | 2013-02-19 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same |
US9219403B2 (en) | 2011-09-06 | 2015-12-22 | Correlated Magnetics Research, Llc | Magnetic shear force transfer device |
US8848973B2 (en) | 2011-09-22 | 2014-09-30 | Correlated Magnetics Research LLC | System and method for authenticating an optical pattern |
WO2013130667A2 (en) | 2012-02-28 | 2013-09-06 | Correlated Magnetics Research, Llc. | System for detaching a magnetic structure from a ferromagnetic material |
US9245677B2 (en) | 2012-08-06 | 2016-01-26 | Correlated Magnetics Research, Llc. | System for concentrating and controlling magnetic flux of a multi-pole magnetic structure |
ITTO20121080A1 (en) | 2012-12-14 | 2014-06-15 | St Microelectronics Srl | SEMICONDUCTOR DEVICE WITH INTEGRATED MAGNETIC ELEMENT PROVIDED WITH A METALLIC CONTAMINATION BARRIER STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE |
US9298281B2 (en) | 2012-12-27 | 2016-03-29 | Correlated Magnetics Research, Llc. | Magnetic vector sensor positioning and communications system |
US9449874B1 (en) | 2015-06-30 | 2016-09-20 | International Business Machines Corporation | Self-forming barrier for subtractive copper |
CN113571521B (en) * | 2021-07-26 | 2023-09-26 | 长鑫存储技术有限公司 | Bit line structure, semiconductor structure and manufacturing method of bit line structure |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622469A (en) * | 1968-07-10 | 1971-11-23 | Ibm | Method for edge-plating coupled film devices |
US6211090B1 (en) * | 2000-03-21 | 2001-04-03 | Motorola, Inc. | Method of fabricating flux concentrating layer for use with magnetoresistive random access memories |
US6501144B1 (en) * | 2001-11-13 | 2002-12-31 | Motorola, Inc. | Conductive line with multiple turns for programming a MRAM device |
US6559511B1 (en) * | 2001-11-13 | 2003-05-06 | Motorola, Inc. | Narrow gap cladding field enhancement for low power programming of a MRAM device |
US20030089933A1 (en) * | 2001-11-13 | 2003-05-15 | Janesky Jason Allen | Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers |
US20040050859A1 (en) * | 2002-09-16 | 2004-03-18 | Roger Lee Greene | Elevating dispenser for canister |
US6812040B2 (en) * | 2002-03-12 | 2004-11-02 | Freescale Semiconductor, Inc. | Method of fabricating a self-aligned via contact for a magnetic memory element |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1052646A (en) * | ||||
US621090A (en) * | 1899-03-14 | Elastic-tread horseshoe | ||
DE19836567C2 (en) | 1998-08-12 | 2000-12-07 | Siemens Ag | Memory cell arrangement with memory elements with a magnetoresistive effect and method for their production |
EP1052646B1 (en) | 1999-05-11 | 2004-07-14 | Fujitsu Limited | Non-volatile semiconductor memory device permitting data-read operation performed during data-write/erase operation |
US6555858B1 (en) | 2000-11-15 | 2003-04-29 | Motorola, Inc. | Self-aligned magnetic clad write line and its method of formation |
-
2002
- 2002-03-08 US US10/093,909 patent/US6927072B2/en not_active Expired - Fee Related
-
2003
- 2003-02-27 EP EP03709387A patent/EP1483762A2/en not_active Withdrawn
- 2003-02-27 JP JP2003575387A patent/JP2005519482A/en active Pending
- 2003-02-27 CN CNB038054922A patent/CN100530419C/en not_active Expired - Fee Related
- 2003-02-27 AU AU2003212447A patent/AU2003212447A1/en not_active Abandoned
- 2003-02-27 KR KR1020047014056A patent/KR100698803B1/en not_active IP Right Cessation
- 2003-02-27 WO PCT/US2003/006020 patent/WO2003077258A2/en active Application Filing
- 2003-03-07 TW TW092104917A patent/TWI283885B/en not_active IP Right Cessation
-
2005
- 2005-05-26 US US11/139,143 patent/US7402529B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622469A (en) * | 1968-07-10 | 1971-11-23 | Ibm | Method for edge-plating coupled film devices |
US6211090B1 (en) * | 2000-03-21 | 2001-04-03 | Motorola, Inc. | Method of fabricating flux concentrating layer for use with magnetoresistive random access memories |
US6501144B1 (en) * | 2001-11-13 | 2002-12-31 | Motorola, Inc. | Conductive line with multiple turns for programming a MRAM device |
US6559511B1 (en) * | 2001-11-13 | 2003-05-06 | Motorola, Inc. | Narrow gap cladding field enhancement for low power programming of a MRAM device |
US20030089933A1 (en) * | 2001-11-13 | 2003-05-15 | Janesky Jason Allen | Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers |
US6812040B2 (en) * | 2002-03-12 | 2004-11-02 | Freescale Semiconductor, Inc. | Method of fabricating a self-aligned via contact for a magnetic memory element |
US20040050859A1 (en) * | 2002-09-16 | 2004-03-18 | Roger Lee Greene | Elevating dispenser for canister |
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TWI283885B (en) | 2007-07-11 |
TW200304666A (en) | 2003-10-01 |
US7402529B2 (en) | 2008-07-22 |
US6927072B2 (en) | 2005-08-09 |
AU2003212447A1 (en) | 2003-09-22 |
CN100530419C (en) | 2009-08-19 |
AU2003212447A8 (en) | 2003-09-22 |
US20030170976A1 (en) | 2003-09-11 |
KR20040091703A (en) | 2004-10-28 |
CN1781156A (en) | 2006-05-31 |
JP2005519482A (en) | 2005-06-30 |
EP1483762A2 (en) | 2004-12-08 |
KR100698803B1 (en) | 2007-03-26 |
WO2003077258A3 (en) | 2003-12-31 |
WO2003077258A2 (en) | 2003-09-18 |
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