US20050231889A1 - Capacitor-embedded substrate - Google Patents

Capacitor-embedded substrate Download PDF

Info

Publication number
US20050231889A1
US20050231889A1 US11/100,827 US10082705A US2005231889A1 US 20050231889 A1 US20050231889 A1 US 20050231889A1 US 10082705 A US10082705 A US 10082705A US 2005231889 A1 US2005231889 A1 US 2005231889A1
Authority
US
United States
Prior art keywords
capacitor
layer
power source
embedded substrate
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/100,827
Other versions
US7046501B2 (en
Inventor
Yoshiomi Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Assigned to ALPS ELECTRIC CO., LTD. reassignment ALPS ELECTRIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSUJI, YOSHIOMI
Publication of US20050231889A1 publication Critical patent/US20050231889A1/en
Application granted granted Critical
Publication of US7046501B2 publication Critical patent/US7046501B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718—Clearance holes

Definitions

  • the present invention relates to a capacitor-embedded substrate having a decoupling capacitor embedded in order to reliably compensate for fluctuation of a power source voltage.
  • a capacitor substrate having a surface on which a decoupling capacitor for preventing malfunction of a semiconductor device due to fluctuation of a power source voltage is formed (for example, see Japanese Patent Application Publication No. 6-318672).
  • the decoupling capacitor is coupled to a power supply terminal and so on through wiring lines in the unit of mm in a horizontal direction perpendicular to a thickness direction. Accordingly, since the decoupling capacitor is affected by the length of the wiring lines in the high frequency band of, particularly, more than GHz, inductive components due to the length of the wiring lines cannot be ignored. Such inductive components make the decoupling capacitor difficult or even impossible to fulfill its function. Accordingly, the conventional capacitor-embedded substrate has a problem in that the fluctuation of the power source voltage cannot be reliably compensated for.
  • the present invention has been finalized in view of the problem inherent in the conventional capacitor-embedded substrate, and it is an object of the present invention to provide a capacitor-embedded substrate in which the fluctuation of the power source voltage can be reliably compensated for.
  • the present invention provides a capacitor-embedded substrate disposed between a mount substrate and a semiconductor device, having a decoupling capacitor formed between an input side electrode layer and an output side electrode layer via an interlayer insulating layer, the decoupling capacitor including a pair of internal electrode layers composed of a ground layer and a power source layer, and a dielectric layer formed between the pair of internal electrode layers, wherein a plurality of power supply terminals used for power supply to the semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via used for interlayer connection.
  • the decoupling capacitor is disposed immediately below the plurality of power supply terminals, power is supplied to each of the plurality of power supply terminals from a horizontal direction perpendicular to a thickness direction of the output side electrode layer, and the length of a wiring line of the capacitor via is less than 100 ⁇ m.
  • the dielectric layer is disposed to form the decoupling capacitor on an approximately entire surface of the ground layer.
  • capacitance of the decoupling capacitor is more than 1 nF/mm 2 , and the capacitance of the decoupling capacitor can be varied depending on an area of the ground layer and a film thickness of the dielectric layer.
  • the capacitor via is formed of copper or its alloy, and the capacitor via and the power source layer are metallically coupled to each other in a thickness direction of the power source layer.
  • the dielectric layer is formed of silicon nitride and a film thickness of the dielectric layer is less than 1 ⁇ m, or the dielectric layer is formed of titanium oxide and a film thickness of the dielectric layer is less than 1 ⁇ m.
  • FIG. 1 is a simplified schematic view illustrating a configuration of a main portion of a capacitor-embedded substrate in a mounted state, according to a first embodiment of the present invention
  • FIG. 2 is an enlarged sectional view illustrating a main portion of the capacitor-embedded substrate of FIG. 1 ;
  • FIG. 3 is a perspective view illustrating an example of a structure of an interconnection between an output side power source terminal using a wiring line pattern and a plurality of power supply terminals;
  • FIG. 4 is a graphical view illustrating a relationship between an impedance and a frequency depending on a length of a wiring line
  • FIG. 5 is a simplified schematic view illustrating a configuration of a main portion of a capacitor-embedded substrate in a mounted state, according to a second embodiment of the present invention.
  • FIG. 6 is an enlarged sectional view illustrating a main portion of the capacitor-embedded substrate of FIG. 5 .
  • FIG. 1 is a simplified schematic view illustrating a configuration of a main portion of a capacitor-embedded substrate in a mounted state, according to a first embodiment of the present invention.
  • a capacitor-embedded substrate 1 of this embodiment is of an interposer type, that is, is disposed between a mount substrate 2 such as a print wiring substrate and a semiconductor device 3 such as a CPU.
  • a mount substrate 2 such as a print wiring substrate
  • a semiconductor device 3 such as a CPU.
  • a plurality of terminals 4 which is electrically connected to corresponding terminals 5 , which are formed on the bottom of the capacitor-embedded substrate 1 , via a bonding member such as solder.
  • a plurality of terminals 6 which is electrically connected to corresponding terminals 7 , which are formed on the bottom of the semiconductor device 3 , via a bonding member such as solder.
  • a decoupling capacitor 8 to which power source is supplied from the top of the capacitor-embedded substrate 1 .
  • the capacitor-embedded substrate 1 of this embodiment will be now described in detail with reference to the enlarged sectional view of FIG. 2 .
  • an input side power terminal 9 As shown in FIG. 2 , on the bottom of the capacitor-embedded substrate 1 of this embodiment are formed an input side power terminal 9 , an input side signal terminal 10 and an input side ground terminal 11 as the plurality of terminals 5 corresponding to the plurality of terminals 4 of the mount substrate 2 .
  • the input side power terminal 9 , the input side signal terminal 10 and the input side ground terminal 11 are formed by patterning an input side electrode layer S 1 formed of a metal film having conductivity, such as copper or its alloy having the thickness of 12 ⁇ m or so, into a predetermined pattern, using a photolithography method, and are supported and fixed by a rectangular input side solder resist 12 serving as an insulating protective film.
  • a lower power source via 13 is connected to the top of the input side power terminal 9
  • the bottom of a lower signal via 14 is connected to the top of the input side signal terminal 10
  • the bottom of a lower ground via 15 is connected to the top of the input side ground terminal 11 .
  • the lower power source via 13 , the lower signal via 14 and the lower ground via 15 are formed of conductive metal wirings, such as copper or its alloy, whose length in a thickness direction (vertical direction in FIG. 2 , the same will apply hereinafter) is, for example, 25 ⁇ m or so.
  • a lower interlayer insulating layer 16 formed of an insulating material, such as polyimide or glass epoxy, and having a film thickness of 25 ⁇ m or so, such that the lower interlayer insulating layer 16 covers circumferences of the lower power source via 13 , the lower signal via 14 and the lower ground via 15 .
  • the top of the lower interlayer insulating layer 16 has the same height as the tops of the lower power source via 13 , the lower signal via 14 and the lower ground via 15 .
  • the ground layer 17 is formed by forming a conductive metal film, such as copper or its alloy, having a thickness of 2 to 5 ⁇ m, on the lower interlayer insulating layer 16 , and patterning the metal film into a predetermined pattern using a photolithography method.
  • the top of the lower ground via 15 is connected to a position of the bottom of the ground layer 17 corresponding to the input side ground terminal 11 .
  • an upper ground via 18 is connected to the top of the ground layer 17 at a predetermined position, for example, a position corresponding to the top of the lower ground via 15 .
  • the upper ground via 18 is formed of a conductive metal wiring, such as copper or its alloy, whose length in a thickness direction is, for example, 25 ⁇ m or so.
  • a power source connecting portion 19 and a signal connecting portion 20 which are respectively connected to the tops of the lower power source via 13 and the lower signal via 14 .
  • the power source connecting portion 19 and the signal connecting portion 20 are respectively formed to have a shape of an island, which is separate from the ground layer 17 , at positions opposite to the tops of the lower power source via 13 and the lower signal via 14 , by patterning the ground layer 17 into a predetermined pattern using a photolithography method.
  • the top of the lower power source via 13 is connected to the bottom of the power source connecting portion 19 and the bottom of an upper power source via 21 is connected to the top of the power source connecting portion 19 .
  • top of the lower signal via 14 is connected to the bottom of the signal connecting portion 20 and the bottom of an upper signal via 22 is connected to the top of the signal connecting portion 20 .
  • an intermediate interlayer insulating layer 23 for securing insulating property is disposed around each of the power source connecting portion 19 and the signal connecting portion 20 .
  • the tops of the upper power source via 21 and the upper signal via 22 are formed on the same plane as the top of the upper ground via 18 .
  • the upper power source via 21 and the upper signal via 22 are formed of conductive metal wirings, such as copper or its alloy, whose length in a thickness direction is, for example, 25 ⁇ m or so.
  • a dielectric layer 24 On the top of the ground layer 17 is laminated a dielectric layer 24 forming a part of the decoupling capacitor 8 .
  • a dielectric layer 24 On the dielectric layer 24 is formed of a material such as silicon nitride or titanium oxide having a film thickness of 1 ⁇ m or so.
  • a film thickness of the dielectric layer 24 may be 0.1 to 3.0 ⁇ m, preferably, 0.1 to 1.0 ⁇ m. If the film thickness exceeds this thickness range, capacitance may not become large, and if the film thickness is less than this thickness range, the insulating property may not be secured.
  • the dielectric layer 24 is formed on an approximately entire surface of the ground layer 17 , more specifically, an entire surface of the ground layer 17 except for an interconnecting portion between the top of the ground layer 17 and the upper ground via 18 .
  • the dielectric layer 24 is not formed on the tops of the power connecting portion 19 and the signal connecting portion 20 , which are formed separate from the ground layer 17 .
  • the power source layer 25 is formed by forming a conductive metal film, such as copper or its alloy, having a thickness of 2 to 5 ⁇ m, on the dielectric layer 24 , and patterning the metal film into a predetermined pattern using a photolithography method.
  • the bottom of a capacitor via 26 formed of copper or its alloy for supplying power to the decoupling capacitor 8 is connected to the top of the power source layer 25 , by a metal coupling, to a predetermined position on the top of the power source layer 25 , more specifically, a position corresponding to a plurality of terminals for power supply of the semiconductor device 3 . That is, the decoupling capacitor 8 is formed immediately below the plurality of terminals for power supply of the semiconductor device 3 .
  • the decoupling capacitor 8 has capacitance of 3 nF/mm 2 or so by forming the dielectric layer 24 with a titanium oxide having a film thickness of 500 mm or so.
  • the capacitance of the decoupling capacitor 8 is preferably more than 1 nF/mm 2 .
  • the capacitance of the decoupling capacitor 8 may be varied depending on an area of the ground layer 17 , that is, a mount area which is an area of a plane of the capacitor-embedded substrate 1 .
  • the decoupling capacitor 8 of this embodiment has the configuration where the dielectric layer 24 is interposed between the ground layer 17 and the power source layer 25 , a plurality of dielectric layers 24 may be configured according to the design concept. In this case, it is important to form intermediate electrode layers between the plurality of dielectric layers 24 .
  • the length of a wiring line in a thickness direction of the capacitor via 26 is 20 ⁇ m or so.
  • the length of the wiring line of the capacitor via 26 is less than 100 ⁇ m, preferably, 10 to 50 ⁇ m. If the length exceeds this range, it may be difficult for the capacitor 26 to function as a capacitor due to increase of an inductance component. If the length is less than this range, an electrical property of interlayer insulating resin may be unstable.
  • the length of the wiring line in the thickness direction of the capacitor via 26 becomes the length of the wiring line of the decoupling capacitor 8 and it is easy to set the length of the wiring line of the decoupling capacitor 8 to be shorter than 100 ⁇ m.
  • an upper interlayer insulating layer 27 formed of an insulating material, such as polyimide or glass epoxy, and having a film thickness of 25 ⁇ m or so at maximum.
  • the upper interlayer insulating layer 27 covers circumferences of the upper power source via 21 , the upper signal via 22 , the upper ground via 18 and the capacitor via 26 .
  • the top of the upper interlayer insulating layer 27 has the same height as the tops of the upper power source via 21 , the upper signal via 22 , the upper ground via 18 and the capacitor via 26 .
  • VCC power supply terminals
  • the power supply terminals 28 , the output side signal terminal 29 , the output side ground terminal 30 , the output side power source terminal 31 , and the wiring line pattern 32 are formed by forming an output side electrode layer S 2 formed of a conductive metal film, such as copper or its alloy, having a thickness of 12 ⁇ m or so, on the top of the upper interlayer insulating layer 27 , and patterning the output side electrode layer S 2 into a predetermined pattern using a photolithography method.
  • a conductive metal film such as copper or its alloy
  • the wiring line pattern 32 is disposed such that it does not short with the output side signal terminal 29 and the output side ground terminal 30 .
  • the power supply terminals 28 , the output side signal terminal 29 , the output side ground terminal 30 , the output side power source terminal 31 , and the wiring line pattern 32 are supported and fixed by an output side solder resist 33 serving as an insulating protective film.
  • an output side solder resist 33 serving as an insulating protective film.
  • upper parts of the output side signal terminal 29 , the output side ground terminal 30 and the power supply terminals 28 have respective openings. In external exposure portions of the respective openings is formed a gold/nickel pad (not shown) consisting of a lower nickel plating layer and an upper gold plating layer, as known in the prior art.
  • surfaces of the output side power source terminal 31 and the wiring line pattern 32 are coated with the output side solder resist 33 .
  • the top of the capacitor via 26 is connected to the bottoms of the power supply terminals 28 and the top of the upper signal via 22 is connected to the bottom of the output side signal terminal 29 .
  • the top of the upper ground via 18 is connected to the bottom of the output side ground terminal 30 and the top of the upper power source via 21 is connected to the bottom of the output side power source terminal 31 .
  • the wiring line pattern 32 has one end connected to a side of the output side power source terminal 31 and the other end branched and connected to sides of the plurality of power supply terminals 28 .
  • each power supply terminal 28 is formed to be branches for supply of power to the semiconductor device 3 and the decoupling capacitor 8 .
  • the decoupling capacitor 8 is disposed immediately below each power supply terminal 28 , power is supplied to each power supply terminal 28 by the wiring line pattern 32 from a horizontal direction perpendicular to a thickness direction of the output side electrode layer S 2 , and the length of the wiring line of the capacitor via is less than 100 ⁇ m.
  • FIG. 3 illustrates an example of a structure of an interconnection between the output side power source terminal 31 using the wiring line pattern 32 and the plurality of power supply terminals 28 .
  • an adhesive agent or a chemical adsorptive film such as triazinethiol may be used.
  • a triazinethiol-containing organic material including carbon and nitrogen and having permittivity ⁇ of more than 60 may be used as material of the dielectric layer 24 .
  • a high-permittivity material made by dispersing metal particles having a size of an order of nanometer into a polymeric resin may be used as the material of the dielectric layer 24 (nanomaterial).
  • Such organic materials can attain capacitance of several tens to several hundreds nF/mm 2 .
  • the decoupling capacitor 8 for compensating for the power source voltage of the semiconductor device 3 can be connected to only the capacitor via 26 in the longitudinal direction of the wiring line.
  • the decoupling capacitor 8 can sufficiently function as a capacitor even in a high frequency band of more than GHz.
  • FIG. 4 shows a result of a simulation for a relationship between an impedance and a frequency depending on the length of the wiring line.
  • the capacitance of the decoupling capacitor 8 is 3.5 nF/mm 2
  • an article where the length of the power source wiring line to the decoupling capacitor 8 in a direct-below form by only the capacitor via 26 is 100 ⁇ m is taken as the present article
  • an article where the wiring line length by the prior power source wiring is 1 mm is taken as prior article 1
  • an article where the wiring line length by the prior power source wiring is 3 mm is taken as prior article 2
  • an article where the wiring line length by the prior power source wiring is 9 mm is taken as prior article 3 .
  • FIG. 4 it can be confirmed that the impedance can become lower in a wide frequency band as the wiring line length becomes shorter.
  • the capacitor-embedded substrate 1 of this embodiment the fluctuation of the power source voltage can be reliably compensated for.
  • the capacitor-embedded substrate 1 of this embodiment since the power supply terminals 28 are connected to the power source layer 25 of the decoupling capacitor 8 by only the capacitor via 26 used for interlayer connection, a path of power supply to the decoupling capacitor 8 can be simply minimized. As a result, since the capacitor-embedded substrate 1 can be obtained by a simple manufacturing process, productivity of the substrate can be improved and product costs can be lowered.
  • the dielectric may be formed by printing methods including an offset printing method, a screen printing method, etc.
  • the electrodes may be formed by plating using a semi-additive method or a full additive method.
  • the decoupling capacitor 8 is disposed immediately below the plurality of power supply terminals 28 , power is supplied to each power supply terminal 28 by the wiring line pattern 32 from a horizontal direction perpendicular to a thickness direction of the output side electrode layer S 2 , and the length of the wiring line of the capacitor via 26 is less than 100 ⁇ m, a manufacturing process can be further simplified.
  • the decoupling capacitor 8 can sufficiently function as a capacitor even in a high frequency band of more than GHz.
  • the capacitor-embedded substrate 1 of this embodiment since the decoupling capacitor 8 is disposed on the approximately entire surface of the ground layer 17 , the capacitor-embedded substrate 1 itself may be used as the decoupling capacitor 8 . As a result, large capacitance of the decoupling capacitor 8 and low impedance in a wide frequency band can be easily attained.
  • the capacitance of the decoupling capacitor 8 is more than 1 nF/mm 2 , and the capacitance of the decoupling capacitor 8 may be varied depending on an area of the ground layer 17 , that is, a mount area of the capacitor-embedded substrate 1 , large capacitance of the decoupling capacitor 8 can be easily attained.
  • the capacitor via 26 is formed of copper or its alloy and the capacitor via 26 and the power source layer 25 are metallically coupled to each other in a thickness direction of the power source layer 25 , an interlayer connection can be attained with low resistance, at low costs, and high reliability, unlike a conventional connection between metals of different kinds.
  • the dielectric layer 24 is formed of the silicon nitride or the titanium oxide having the film thickness less than 1 ⁇ m, large capacitance of the decoupling capacitor 8 can be reliably and easily attained.
  • FIGS. 5 and 6 illustrate a capacitor-embedded substrate according to a second embodiment of the present invention.
  • FIG. 5 is a simplified schematic view illustrating a configuration of a main portion of the capacitor-embedded substrate in a mounted state
  • FIG. 6 is an enlarged sectional view illustrating a main portion of the capacitor-embedded substrate.
  • the same or equivalent components as the capacitor-embedded substrate 1 of the first embodiment are denoted by the same reference numerals.
  • a capacitor-embedded substrate 1 A of this embodiment is of a socket type, that is, is disposed between a mount substrate 2 such as a print wiring substrate and an interposer 41 on which a semiconductor device 3 is mounted.
  • a mount substrate 2 such as a print wiring substrate
  • an interposer 41 on which a semiconductor device 3 is mounted.
  • a plurality of terminals 4 which is electrically connected to corresponding terminals 5 , which are formed on the bottom of the capacitor-embedded substrate 1 A, via a bonding member such as solder.
  • a plurality of terminals 6 which is electrically connected to corresponding terminals 7 A, which are formed on the bottom of the interposer 41 , via a bonding member such as solder.
  • a decoupling capacitor 8 to which power source is supplied from the top of the capacitor-embedded substrate 1 A, as shown in FIGS. 5 and 6 .
  • a plurality of input side power source terminals (only one terminal is shown in FIG. 6 ) 9 is connected, via an input side wiring line pattern 35 , to one input side power source terminal 36 , which is not directly connected to the terminals 4 of the mount substrate 2 , and the bottom of a lower power source via 13 is connected to the top of the input side power source terminal 36 .
  • the input side wiring line pattern 35 has one end connected to a side of the input side power source terminal 36 and the other end branched and connected to sides of a plurality of input side power source terminal 36 .
  • the input side wiring line pattern 35 and the input side power source terminals 36 are formed by patterning an input side electrode layer S 1 into a predetermined pattern using a photolithography method, at the same time of forming the input side power source terminals 9 , an input side signal terminal 10 and an input side ground terminal 11 .
  • the configuration where the plurality of input side power source terminals 9 is connected, via the input side wiring line pattern 35 , to one input side power source terminal 36 , and the bottom of the lower power source via 13 is connected to the top of the input side power source terminal 36 may be used in the capacitor-embedded substrate 1 of the first embodiment.
  • the capacitor-embedded substrate 1 A has the same configuration as the capacitor-embedded substrate 1 of the first embodiment, and therefore, detailed explanation thereof will be omitted.
  • the capacitor-embedded substrate 1 A of the second embodiment as configured above has the same effect as the capacitor-embedded substrate 1 of the first embodiment.
  • the present invention is not limited to the above-described embodiments, and may be modified in various ways if necessary.
  • the capacitor-embedded substrate according to the invention has a remarkable effect that the fluctuation of the power source voltage can be reliably compensated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

A capacitor-embedded substrate for reliably compensating for fluctuation of a power source voltage is provided. A decoupling capacitor is formed between an input side electrode layer and an output side electrode layer via interlayer insulating layers, the decoupling capacitor includes a ground layer, a power source layer, and a dielectric layer interposed therebetween. A plurality of power supply terminals used for power supply to a semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a capacitor-embedded substrate having a decoupling capacitor embedded in order to reliably compensate for fluctuation of a power source voltage.
  • 2. Description of the Related Art
  • Conventionally, when semiconductor devices of the form of a chip, such as ICs, LSIs, super LSIs, and CPUs using these devices, are mounted on a mounting substrate such as a printed wiring substrate, there has been known to use, as the mounting substrate, a capacitor substrate having a surface on which a decoupling capacitor for preventing malfunction of a semiconductor device due to fluctuation of a power source voltage is formed (for example, see Japanese Patent Application Publication No. 6-318672).
  • In addition, there has been proposed an interposer-typed capacitor-embedded substrate having a high capacitive decoupling capacitor embedded therein, which is provided between a mounting substrate and a semiconductor element (for example, see Japanese Patent Application Publication No. 2001-358248).
  • Recently, as one of various high performance components, a high performance capacitor-embedded substrate in which the fluctuation of the power source voltage can be reliably compensated for has been demanded.
  • In recent semiconductor devices, efforts to achieve high density and high speed in addition to downsizing and high performance have been made. According to the downsizing and the high performance of the semiconductor device, higher operational frequencies, for example, a high frequency band of more than GHz, have been used.
  • However, in the conventional capacitor-embedded substrate, the decoupling capacitor is coupled to a power supply terminal and so on through wiring lines in the unit of mm in a horizontal direction perpendicular to a thickness direction. Accordingly, since the decoupling capacitor is affected by the length of the wiring lines in the high frequency band of, particularly, more than GHz, inductive components due to the length of the wiring lines cannot be ignored. Such inductive components make the decoupling capacitor difficult or even impossible to fulfill its function. Accordingly, the conventional capacitor-embedded substrate has a problem in that the fluctuation of the power source voltage cannot be reliably compensated for.
    • SUMMARY OF THE INVENTION
  • The present invention has been finalized in view of the problem inherent in the conventional capacitor-embedded substrate, and it is an object of the present invention to provide a capacitor-embedded substrate in which the fluctuation of the power source voltage can be reliably compensated for.
  • To achieve the above object, the present invention provides a capacitor-embedded substrate disposed between a mount substrate and a semiconductor device, having a decoupling capacitor formed between an input side electrode layer and an output side electrode layer via an interlayer insulating layer, the decoupling capacitor including a pair of internal electrode layers composed of a ground layer and a power source layer, and a dielectric layer formed between the pair of internal electrode layers, wherein a plurality of power supply terminals used for power supply to the semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via used for interlayer connection.
  • In the capacitor-embedded substrate according to the present invention, preferably, the decoupling capacitor is disposed immediately below the plurality of power supply terminals, power is supplied to each of the plurality of power supply terminals from a horizontal direction perpendicular to a thickness direction of the output side electrode layer, and the length of a wiring line of the capacitor via is less than 100 μm.
  • In the capacitor-embedded substrate according to the present invention, preferably, the dielectric layer is disposed to form the decoupling capacitor on an approximately entire surface of the ground layer.
  • In the capacitor-embedded substrate according to the present invention, preferably, capacitance of the decoupling capacitor is more than 1 nF/mm2, and the capacitance of the decoupling capacitor can be varied depending on an area of the ground layer and a film thickness of the dielectric layer.
  • In the capacitor-embedded substrate according to the present invention, preferably, the capacitor via is formed of copper or its alloy, and the capacitor via and the power source layer are metallically coupled to each other in a thickness direction of the power source layer.
  • In the capacitor-embedded substrate according to the present invention, preferably, the dielectric layer is formed of silicon nitride and a film thickness of the dielectric layer is less than 1 μm, or the dielectric layer is formed of titanium oxide and a film thickness of the dielectric layer is less than 1 μm.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a simplified schematic view illustrating a configuration of a main portion of a capacitor-embedded substrate in a mounted state, according to a first embodiment of the present invention;
  • FIG. 2 is an enlarged sectional view illustrating a main portion of the capacitor-embedded substrate of FIG. 1;
  • FIG. 3 is a perspective view illustrating an example of a structure of an interconnection between an output side power source terminal using a wiring line pattern and a plurality of power supply terminals;
  • FIG. 4 is a graphical view illustrating a relationship between an impedance and a frequency depending on a length of a wiring line;
  • FIG. 5 is a simplified schematic view illustrating a configuration of a main portion of a capacitor-embedded substrate in a mounted state, according to a second embodiment of the present invention; and
  • FIG. 6 is an enlarged sectional view illustrating a main portion of the capacitor-embedded substrate of FIG. 5.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.
  • FIG. 1 is a simplified schematic view illustrating a configuration of a main portion of a capacitor-embedded substrate in a mounted state, according to a first embodiment of the present invention.
  • As shown in FIG. 1, a capacitor-embedded substrate 1 of this embodiment is of an interposer type, that is, is disposed between a mount substrate 2 such as a print wiring substrate and a semiconductor device 3 such as a CPU. In addition, on the top of the mount substrate 2 is formed a plurality of terminals 4 which is electrically connected to corresponding terminals 5, which are formed on the bottom of the capacitor-embedded substrate 1, via a bonding member such as solder. In addition, on the top of the capacitor-embedded substrate 1 is formed a plurality of terminals 6 which is electrically connected to corresponding terminals 7, which are formed on the bottom of the semiconductor device 3, via a bonding member such as solder. In addition, inside the capacitor-embedded substrate 1 is formed a decoupling capacitor 8 to which power source is supplied from the top of the capacitor-embedded substrate 1.
  • The capacitor-embedded substrate 1 of this embodiment will be now described in detail with reference to the enlarged sectional view of FIG. 2.
  • As shown in FIG. 2, on the bottom of the capacitor-embedded substrate 1 of this embodiment are formed an input side power terminal 9, an input side signal terminal 10 and an input side ground terminal 11 as the plurality of terminals 5 corresponding to the plurality of terminals 4 of the mount substrate 2. For example, the input side power terminal 9, the input side signal terminal 10 and the input side ground terminal 11 are formed by patterning an input side electrode layer S1 formed of a metal film having conductivity, such as copper or its alloy having the thickness of 12 μm or so, into a predetermined pattern, using a photolithography method, and are supported and fixed by a rectangular input side solder resist 12 serving as an insulating protective film. In addition, the bottom of a lower power source via 13 is connected to the top of the input side power terminal 9, the bottom of a lower signal via 14 is connected to the top of the input side signal terminal 10, and the bottom of a lower ground via 15 is connected to the top of the input side ground terminal 11. The lower power source via 13, the lower signal via 14 and the lower ground via 15 are formed of conductive metal wirings, such as copper or its alloy, whose length in a thickness direction (vertical direction in FIG. 2, the same will apply hereinafter) is, for example, 25 μm or so.
  • On the top of the input side solder resist 12 is laminated a lower interlayer insulating layer 16 formed of an insulating material, such as polyimide or glass epoxy, and having a film thickness of 25 μm or so, such that the lower interlayer insulating layer 16 covers circumferences of the lower power source via 13, the lower signal via 14 and the lower ground via 15. The top of the lower interlayer insulating layer 16 has the same height as the tops of the lower power source via 13, the lower signal via 14 and the lower ground via 15.
  • On the top of the lower interlayer insulating layer 16 is laminated a ground layer 17 forming one of a pair of internal electrode layers forming a part of the decoupling capacitor 8. The ground layer 17 is formed by forming a conductive metal film, such as copper or its alloy, having a thickness of 2 to 5 μm, on the lower interlayer insulating layer 16, and patterning the metal film into a predetermined pattern using a photolithography method. In addition, the top of the lower ground via 15 is connected to a position of the bottom of the ground layer 17 corresponding to the input side ground terminal 11. In addition, at a predetermined position on the top of the ground layer 17, the bottom of an upper ground via 18 is connected to the top of the ground layer 17 at a predetermined position, for example, a position corresponding to the top of the lower ground via 15. The upper ground via 18 is formed of a conductive metal wiring, such as copper or its alloy, whose length in a thickness direction is, for example, 25 μm or so.
  • In the ground layer 17 are formed a power source connecting portion 19 and a signal connecting portion 20 which are respectively connected to the tops of the lower power source via 13 and the lower signal via 14. The power source connecting portion 19 and the signal connecting portion 20 are respectively formed to have a shape of an island, which is separate from the ground layer 17, at positions opposite to the tops of the lower power source via 13 and the lower signal via 14, by patterning the ground layer 17 into a predetermined pattern using a photolithography method. In addition, the top of the lower power source via 13 is connected to the bottom of the power source connecting portion 19 and the bottom of an upper power source via 21 is connected to the top of the power source connecting portion 19. In addition, the top of the lower signal via 14 is connected to the bottom of the signal connecting portion 20 and the bottom of an upper signal via 22 is connected to the top of the signal connecting portion 20. In addition, an intermediate interlayer insulating layer 23 for securing insulating property is disposed around each of the power source connecting portion 19 and the signal connecting portion 20. In addition, the tops of the upper power source via 21 and the upper signal via 22 are formed on the same plane as the top of the upper ground via 18. In addition, the upper power source via 21 and the upper signal via 22 are formed of conductive metal wirings, such as copper or its alloy, whose length in a thickness direction is, for example, 25 μm or so.
  • On the top of the ground layer 17 is laminated a dielectric layer 24 forming a part of the decoupling capacitor 8. On the dielectric layer 24 is formed of a material such as silicon nitride or titanium oxide having a film thickness of 1 μm or so. A film thickness of the dielectric layer 24 may be 0.1 to 3.0 μm, preferably, 0.1 to 1.0 μm. If the film thickness exceeds this thickness range, capacitance may not become large, and if the film thickness is less than this thickness range, the insulating property may not be secured. In addition, the dielectric layer 24 is formed on an approximately entire surface of the ground layer 17, more specifically, an entire surface of the ground layer 17 except for an interconnecting portion between the top of the ground layer 17 and the upper ground via 18. Of course, the dielectric layer 24 is not formed on the tops of the power connecting portion 19 and the signal connecting portion 20, which are formed separate from the ground layer 17.
  • On the top of the dielectric layer 24 is laminated a power source layer 25 forming the other of the pair of internal electrode layers forming a part of the decoupling capacitor 8. The power source layer 25 is formed by forming a conductive metal film, such as copper or its alloy, having a thickness of 2 to 5 μm, on the dielectric layer 24, and patterning the metal film into a predetermined pattern using a photolithography method. In addition, the bottom of a capacitor via 26 formed of copper or its alloy for supplying power to the decoupling capacitor 8 is connected to the top of the power source layer 25, by a metal coupling, to a predetermined position on the top of the power source layer 25, more specifically, a position corresponding to a plurality of terminals for power supply of the semiconductor device 3. That is, the decoupling capacitor 8 is formed immediately below the plurality of terminals for power supply of the semiconductor device 3.
  • In this embodiment, the decoupling capacitor 8 has capacitance of 3 nF/mm2 or so by forming the dielectric layer 24 with a titanium oxide having a film thickness of 500 mm or so. The capacitance of the decoupling capacitor 8 is preferably more than 1 nF/mm2. In addition, the capacitance of the decoupling capacitor 8 may be varied depending on an area of the ground layer 17, that is, a mount area which is an area of a plane of the capacitor-embedded substrate 1.
  • Although the decoupling capacitor 8 of this embodiment has the configuration where the dielectric layer 24 is interposed between the ground layer 17 and the power source layer 25, a plurality of dielectric layers 24 may be configured according to the design concept. In this case, it is important to form intermediate electrode layers between the plurality of dielectric layers 24.
  • The length of a wiring line in a thickness direction of the capacitor via 26 is 20 μm or so. In addition, the length of the wiring line of the capacitor via 26 is less than 100 μm, preferably, 10 to 50 μm. If the length exceeds this range, it may be difficult for the capacitor 26 to function as a capacitor due to increase of an inductance component. If the length is less than this range, an electrical property of interlayer insulating resin may be unstable.
  • In other words, the length of the wiring line in the thickness direction of the capacitor via 26 becomes the length of the wiring line of the decoupling capacitor 8 and it is easy to set the length of the wiring line of the decoupling capacitor 8 to be shorter than 100 μm.
  • On the top of the dielectric layer 24 is laminated an upper interlayer insulating layer 27 formed of an insulating material, such as polyimide or glass epoxy, and having a film thickness of 25 μm or so at maximum. The upper interlayer insulating layer 27 covers circumferences of the upper power source via 21, the upper signal via 22, the upper ground via 18 and the capacitor via 26. The top of the upper interlayer insulating layer 27 has the same height as the tops of the upper power source via 21, the upper signal via 22, the upper ground via 18 and the capacitor via 26.
  • On the top of the upper interlayer insulating layer 27, that is, on the top of the capacitor-embedded substrate 1 of this embodiment, are formed a plurality of power supply terminals (VCC) 28 as the terminals 6 corresponding to the terminals 7 of the semiconductor device 3, an output side signal terminal 29, an output side ground terminal 30, an output side power source terminal 31 is not directly connected to the terminals 7 of the semiconductor device 3, and a wiring line pattern 32 connecting the plurality of power supply terminals 28 to the output side power source terminal 31. The power supply terminals 28, the output side signal terminal 29, the output side ground terminal 30, the output side power source terminal 31, and the wiring line pattern 32 are formed by forming an output side electrode layer S2 formed of a conductive metal film, such as copper or its alloy, having a thickness of 12 μm or so, on the top of the upper interlayer insulating layer 27, and patterning the output side electrode layer S2 into a predetermined pattern using a photolithography method.
  • Of course, the wiring line pattern 32 is disposed such that it does not short with the output side signal terminal 29 and the output side ground terminal 30.
  • The power supply terminals 28, the output side signal terminal 29, the output side ground terminal 30, the output side power source terminal 31, and the wiring line pattern 32 are supported and fixed by an output side solder resist 33 serving as an insulating protective film. In addition, upper parts of the output side signal terminal 29, the output side ground terminal 30 and the power supply terminals 28 have respective openings. In external exposure portions of the respective openings is formed a gold/nickel pad (not shown) consisting of a lower nickel plating layer and an upper gold plating layer, as known in the prior art. In addition, surfaces of the output side power source terminal 31 and the wiring line pattern 32 are coated with the output side solder resist 33.
  • The top of the capacitor via 26 is connected to the bottoms of the power supply terminals 28 and the top of the upper signal via 22 is connected to the bottom of the output side signal terminal 29. In addition, the top of the upper ground via 18 is connected to the bottom of the output side ground terminal 30 and the top of the upper power source via 21 is connected to the bottom of the output side power source terminal 31. In addition, the wiring line pattern 32 has one end connected to a side of the output side power source terminal 31 and the other end branched and connected to sides of the plurality of power supply terminals 28.
  • That is, each power supply terminal 28 is formed to be branches for supply of power to the semiconductor device 3 and the decoupling capacitor 8.
  • Accordingly, the decoupling capacitor 8 is disposed immediately below each power supply terminal 28, power is supplied to each power supply terminal 28 by the wiring line pattern 32 from a horizontal direction perpendicular to a thickness direction of the output side electrode layer S2, and the length of the wiring line of the capacitor via is less than 100 μm.
  • FIG. 3 illustrates an example of a structure of an interconnection between the output side power source terminal 31 using the wiring line pattern 32 and the plurality of power supply terminals 28.
  • In the capacitor-embedded substrate 1 of this embodiment, in order to secure a close adhesion between each interlayer insulating layer 16, 23 and 27 and the ground and power source layers 17 and 25, which form the pair of internal electrode layers of the decoupling capacitor 8, an adhesive agent or a chemical adsorptive film such as triazinethiol may be used. In addition, a triazinethiol-containing organic material including carbon and nitrogen and having permittivity ε of more than 60 may be used as material of the dielectric layer 24. In addition, a high-permittivity material made by dispersing metal particles having a size of an order of nanometer into a polymeric resin may be used as the material of the dielectric layer 24 (nanomaterial). Such organic materials can attain capacitance of several tens to several hundreds nF/mm2. In addition, when such organic materials are used as the material of the dielectric layer 24, it is important to use a method such as a thermo compression method by which the dielectric layer 24 is not injured when the power source layer 25 is bonded to the capacitor via 26.
  • Next, operation of this embodiment as configured above will be described.
  • In the capacitor-embedded substrate 1 of this embodiment, since the plurality of power supply terminals 28 used for power supply to the semiconductor device 3 is formed by patterning the output side electrode layer S2 and these power supply terminals 28 are connected to the power source layer 25 of the decoupling capacitor 8 by only the capacitor via 26 used for interlayer connection, the decoupling capacitor 8 for compensating for the power source voltage of the semiconductor device 3 can be connected to only the capacitor via 26 in the longitudinal direction of the wiring line. As a result, since an ideal structure where the inductance component can be removed at maximum can be attained, the decoupling capacitor 8 can sufficiently function as a capacitor even in a high frequency band of more than GHz. This can be confirmed through a simulation for a relationship between an impedance and a frequency depending on the length of the wiring line. FIG. 4 shows a result of a simulation for a relationship between an impedance and a frequency depending on the length of the wiring line. In this simulation, the capacitance of the decoupling capacitor 8 is 3.5 nF/mm2, an article where the length of the power source wiring line to the decoupling capacitor 8 in a direct-below form by only the capacitor via 26 is 100 μm is taken as the present article, an article where the wiring line length by the prior power source wiring is 1 mm is taken as prior article 1, an article where the wiring line length by the prior power source wiring is 3 mm is taken as prior article 2, and an article where the wiring line length by the prior power source wiring is 9 mm is taken as prior article 3. As shown in FIG. 4, it can be confirmed that the impedance can become lower in a wide frequency band as the wiring line length becomes shorter.
  • Accordingly, with the capacitor-embedded substrate 1 of this embodiment, the fluctuation of the power source voltage can be reliably compensated for.
  • In addition, in the capacitor-embedded substrate 1 of this embodiment, since the power supply terminals 28 are connected to the power source layer 25 of the decoupling capacitor 8 by only the capacitor via 26 used for interlayer connection, a path of power supply to the decoupling capacitor 8 can be simply minimized. As a result, since the capacitor-embedded substrate 1 can be obtained by a simple manufacturing process, productivity of the substrate can be improved and product costs can be lowered.
  • In addition, methods other than the photolithography method may be applied to the present invention. For example, the dielectric may be formed by printing methods including an offset printing method, a screen printing method, etc. In addition, the electrodes may be formed by plating using a semi-additive method or a full additive method.
  • In addition, in the capacitor-embedded substrate 1 of this embodiment, since the decoupling capacitor 8 is disposed immediately below the plurality of power supply terminals 28, power is supplied to each power supply terminal 28 by the wiring line pattern 32 from a horizontal direction perpendicular to a thickness direction of the output side electrode layer S2, and the length of the wiring line of the capacitor via 26 is less than 100 μm, a manufacturing process can be further simplified. In addition, since an ideal structure where the inductance component can be removed at maximum can be attained, the decoupling capacitor 8 can sufficiently function as a capacitor even in a high frequency band of more than GHz.
  • In addition, in the capacitor-embedded substrate 1 of this embodiment, since the decoupling capacitor 8 is disposed on the approximately entire surface of the ground layer 17, the capacitor-embedded substrate 1 itself may be used as the decoupling capacitor 8. As a result, large capacitance of the decoupling capacitor 8 and low impedance in a wide frequency band can be easily attained.
  • In addition, in the capacitor-embedded substrate 1 of this embodiment, since the capacitance of the decoupling capacitor 8 is more than 1 nF/mm2, and the capacitance of the decoupling capacitor 8 may be varied depending on an area of the ground layer 17, that is, a mount area of the capacitor-embedded substrate 1, large capacitance of the decoupling capacitor 8 can be easily attained.
  • In addition, in the capacitor-embedded substrate 1 of this embodiment, since the capacitor via 26 is formed of copper or its alloy and the capacitor via 26 and the power source layer 25 are metallically coupled to each other in a thickness direction of the power source layer 25, an interlayer connection can be attained with low resistance, at low costs, and high reliability, unlike a conventional connection between metals of different kinds.
  • In addition, in the capacitor-embedded substrate 1 of this embodiment, since the dielectric layer 24 is formed of the silicon nitride or the titanium oxide having the film thickness less than 1 μm, large capacitance of the decoupling capacitor 8 can be reliably and easily attained.
  • In addition, since triazinethiol having permittivity ε of more than 300 or nanomaterial having permittivity ε of more than 200 is used for the dielectric layer 24, the capacitance of several tens to several hundreds nF/mm2 can be attained.
  • FIGS. 5 and 6 illustrate a capacitor-embedded substrate according to a second embodiment of the present invention. FIG. 5 is a simplified schematic view illustrating a configuration of a main portion of the capacitor-embedded substrate in a mounted state, and FIG. 6 is an enlarged sectional view illustrating a main portion of the capacitor-embedded substrate. In the second embodiment, the same or equivalent components as the capacitor-embedded substrate 1 of the first embodiment are denoted by the same reference numerals.
  • As shown in FIG. 5, a capacitor-embedded substrate 1A of this embodiment is of a socket type, that is, is disposed between a mount substrate 2 such as a print wiring substrate and an interposer 41 on which a semiconductor device 3 is mounted. In addition, on the top of the mount substrate 2 is formed a plurality of terminals 4 which is electrically connected to corresponding terminals 5, which are formed on the bottom of the capacitor-embedded substrate 1A, via a bonding member such as solder. In addition, on the top of the capacitor-embedded substrate 1A is formed a plurality of terminals 6 which is electrically connected to corresponding terminals 7A, which are formed on the bottom of the interposer 41, via a bonding member such as solder. In addition, inside the capacitor-embedded substrate 1A is formed a decoupling capacitor 8 to which power source is supplied from the top of the capacitor-embedded substrate 1A, as shown in FIGS. 5 and 6. In addition, in the capacitor-embedded substrate 1A of this embodiment, a plurality of input side power source terminals (only one terminal is shown in FIG. 6) 9 is connected, via an input side wiring line pattern 35, to one input side power source terminal 36, which is not directly connected to the terminals 4 of the mount substrate 2, and the bottom of a lower power source via 13 is connected to the top of the input side power source terminal 36.
  • More specifically, the input side wiring line pattern 35 has one end connected to a side of the input side power source terminal 36 and the other end branched and connected to sides of a plurality of input side power source terminal 36. The input side wiring line pattern 35 and the input side power source terminals 36 are formed by patterning an input side electrode layer S1 into a predetermined pattern using a photolithography method, at the same time of forming the input side power source terminals 9, an input side signal terminal 10 and an input side ground terminal 11.
  • In addition, the configuration where the plurality of input side power source terminals 9 is connected, via the input side wiring line pattern 35, to one input side power source terminal 36, and the bottom of the lower power source via 13 is connected to the top of the input side power source terminal 36 may be used in the capacitor-embedded substrate 1 of the first embodiment.
  • Except the above-described configuration in connection with the second embodiment, the capacitor-embedded substrate 1A has the same configuration as the capacitor-embedded substrate 1 of the first embodiment, and therefore, detailed explanation thereof will be omitted.
  • The capacitor-embedded substrate 1A of the second embodiment as configured above has the same effect as the capacitor-embedded substrate 1 of the first embodiment.
  • In addition, the present invention is not limited to the above-described embodiments, and may be modified in various ways if necessary.
  • The capacitor-embedded substrate according to the invention has a remarkable effect that the fluctuation of the power source voltage can be reliably compensated.

Claims (7)

1. A capacitor-embedded substrate disposed between a mount substrate and a semiconductor device, comprising a decoupling capacitor formed between an input side electrode layer and an output side electrode layer via an interlayer insulating layer, the decoupling capacitor having a pair of internal electrode layers composed of a ground layer and a power source layer, and a dielectric layer formed between the pair of internal electrode layers,
wherein a plurality of power supply terminals used for power supply to the semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via used for interlayer connection.
2. The capacitor-embedded substrate according to claim 1,
wherein the decoupling capacitor is disposed immediately below the plurality of power supply terminals, power is supplied to each of the plurality of power supply terminals from a horizontal direction perpendicular to a thickness direction of the output side electrode layer, and the length of a wiring line of the capacitor via is less than 100 μm.
3. The capacitor-embedded substrate according to claim 1,
wherein the dielectric layer is disposed to form the decoupling capacitor on an approximately entire surface of the ground layer.
4. The capacitor-embedded substrate according to claim 1,
wherein capacitance of the decoupling capacitor is more than 1 nF/mm2, and the capacitance of the decoupling capacitor can be varied depending on an area of the ground layer and a film thickness of the dielectric layer.
5. The capacitor-embedded substrate according to claim 1,
wherein the capacitor via is formed of copper or its alloy, and the capacitor via and the power source layer are metallically coupled to each other in a thickness direction of the power source layer.
6. The capacitor-embedded substrate according to claim 1,
wherein the dielectric layer is formed of silicon nitride and a film thickness of the dielectric layer is less than 1 μm.
7. The capacitor-embedded substrate according to claim 1,
wherein the dielectric layer is formed of titanium oxide and a film thickness of the dielectric layer is less than 1 μm.
US11/100,827 2004-04-16 2005-04-06 Capacitor-embedded substrate Expired - Fee Related US7046501B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004121622A JP2005310814A (en) 2004-04-16 2004-04-16 Substrate with built-in capacitor
JP2004-121622 2004-04-16

Publications (2)

Publication Number Publication Date
US20050231889A1 true US20050231889A1 (en) 2005-10-20
US7046501B2 US7046501B2 (en) 2006-05-16

Family

ID=35096018

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/100,827 Expired - Fee Related US7046501B2 (en) 2004-04-16 2005-04-06 Capacitor-embedded substrate

Country Status (3)

Country Link
US (1) US7046501B2 (en)
JP (1) JP2005310814A (en)
CN (1) CN1684575A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1850648A1 (en) * 2005-11-02 2007-10-31 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor device and process for producing the same
US20090237900A1 (en) * 2008-03-24 2009-09-24 Makoto Origuchi Component built-in wiring board
US20100116529A1 (en) * 2008-11-12 2010-05-13 Ibiden Co., Ltd Printed wiring board having a stiffener
US20100117214A1 (en) * 2008-11-10 2010-05-13 Samsung Electronics Co., Ltd Image forming apparatus, chip, and chip package
US20110058348A1 (en) * 2009-09-10 2011-03-10 Ibiden Co., Ltd. Semiconductor device
US20160050768A1 (en) * 2014-08-12 2016-02-18 Infineon Technologies Ag Module with Integrated Power Electronic Circuitry and Logic Circuitry
US20160055976A1 (en) * 2014-08-25 2016-02-25 Qualcomm Incorporated Package substrates including embedded capacitors
US9640477B1 (en) 2016-03-04 2017-05-02 Fuji Xerox Co., Ltd. Semiconductor package and method of producing the semiconductor package
US10020277B2 (en) 2016-02-03 2018-07-10 Fuji Xerox Co., Ltd. Circuit substrate and method for manufacturing circuit substrate
US10211158B2 (en) 2014-10-31 2019-02-19 Infineon Technologies Ag Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module
US20210161001A1 (en) * 2018-10-31 2021-05-27 HKC Corporation Limited Circuit board and display apparatus

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5511119B2 (en) * 2006-04-14 2014-06-04 株式会社リキッド・デザイン・システムズ Interposer and semiconductor device
US20080017407A1 (en) * 2006-07-24 2008-01-24 Ibiden Co., Ltd. Interposer and electronic device using the same
TWI327361B (en) * 2006-07-28 2010-07-11 Unimicron Technology Corp Circuit board structure having passive component and stack structure thereof
CN1946267B (en) * 2006-08-26 2010-09-08 华为技术有限公司 Embedding method for printed circuit board and printed circuit board
JP5290215B2 (en) * 2010-02-15 2013-09-18 ルネサスエレクトロニクス株式会社 Semiconductor device, semiconductor package, interposer, and manufacturing method of interposer
CN101937852B (en) * 2010-08-19 2012-07-04 日月光半导体制造股份有限公司 Circuit substrate process
JP6157048B2 (en) * 2011-02-01 2017-07-05 スリーエム イノベイティブ プロパティズ カンパニー IC device socket
WO2015041127A1 (en) * 2013-09-20 2015-03-26 株式会社村田製作所 Capacitor module and power conversion device
JP2018137310A (en) * 2017-02-21 2018-08-30 Tdk株式会社 Thin film capacitor
JP2020150145A (en) * 2019-03-14 2020-09-17 キオクシア株式会社 Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4508756A (en) * 1980-10-08 1985-04-02 Murata Manufacturing Co., Ltd. Method for inhibiting oxidation of a copper film on ceramic body
US5323520A (en) * 1993-04-29 1994-06-28 Fujitsu Limited Process for fabricating a substrate with thin film capacitor
US5400210A (en) * 1992-07-06 1995-03-21 Ngk Spark Plug Co., Ltd. Substrate having a built-in capacitor and process for producing the same
US6794729B2 (en) * 2001-03-01 2004-09-21 Nec Corporation Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
US20040238942A1 (en) * 2000-08-30 2004-12-02 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
US20040257749A1 (en) * 2003-06-20 2004-12-23 Ngk Spark Plug Co., Ltd. Capacitor, capacitor equipped semiconductor device assembly, capacitor equipped circuit substrate assembly and electronic unit including semiconductor device, capacitor and circuit substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358248A (en) 2000-06-13 2001-12-26 Hitachi Ltd Circuit board incorporating capacitor, and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4508756A (en) * 1980-10-08 1985-04-02 Murata Manufacturing Co., Ltd. Method for inhibiting oxidation of a copper film on ceramic body
US5400210A (en) * 1992-07-06 1995-03-21 Ngk Spark Plug Co., Ltd. Substrate having a built-in capacitor and process for producing the same
US5323520A (en) * 1993-04-29 1994-06-28 Fujitsu Limited Process for fabricating a substrate with thin film capacitor
US20040238942A1 (en) * 2000-08-30 2004-12-02 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
US6794729B2 (en) * 2001-03-01 2004-09-21 Nec Corporation Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
US20040257749A1 (en) * 2003-06-20 2004-12-23 Ngk Spark Plug Co., Ltd. Capacitor, capacitor equipped semiconductor device assembly, capacitor equipped circuit substrate assembly and electronic unit including semiconductor device, capacitor and circuit substrate

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1850648A1 (en) * 2005-11-02 2007-10-31 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor device and process for producing the same
US8085546B2 (en) 2005-11-02 2011-12-27 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor devices and method for manufacturing the board
US8624121B2 (en) 2005-11-02 2014-01-07 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor devices and method for manufacturing the board
US20100095523A1 (en) * 2005-11-02 2010-04-22 Ibiden Co., Ltd Multilayer printed wiring board for semiconductor devices and method for manufacturing the board
EP1850648A4 (en) * 2005-11-02 2011-03-30 Ibiden Co Ltd Multilayer printed wiring board for semiconductor device and process for producing the same
US8027169B2 (en) 2005-11-02 2011-09-27 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor devices and method for manufacturing the board
US20070263370A1 (en) * 2005-11-02 2007-11-15 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor devices and method for manufacturing the board
US20110085306A1 (en) * 2005-11-02 2011-04-14 Ibiden Co., Ltd. Multilayer printed wiring board for semiconductor devices and method for manufacturing the board
US8130507B2 (en) * 2008-03-24 2012-03-06 Ngk Spark Plug Co., Ltd. Component built-in wiring board
US20090237900A1 (en) * 2008-03-24 2009-09-24 Makoto Origuchi Component built-in wiring board
US9484295B2 (en) 2008-11-10 2016-11-01 Samsung Electronics Co., Ltd. Image forming apparatus, chip, and chip package to reduce cross-talk between signals
US20100117214A1 (en) * 2008-11-10 2010-05-13 Samsung Electronics Co., Ltd Image forming apparatus, chip, and chip package
US8884423B2 (en) * 2008-11-10 2014-11-11 Samsung Electronics Co., Ltd. Image forming apparatus, chip, and chip package
US20100116529A1 (en) * 2008-11-12 2010-05-13 Ibiden Co., Ltd Printed wiring board having a stiffener
US8237056B2 (en) 2008-11-12 2012-08-07 Ibiden Co., Ltd. Printed wiring board having a stiffener
US20110058348A1 (en) * 2009-09-10 2011-03-10 Ibiden Co., Ltd. Semiconductor device
US20160050768A1 (en) * 2014-08-12 2016-02-18 Infineon Technologies Ag Module with Integrated Power Electronic Circuitry and Logic Circuitry
US9681558B2 (en) * 2014-08-12 2017-06-13 Infineon Technologies Ag Module with integrated power electronic circuitry and logic circuitry
US20160055976A1 (en) * 2014-08-25 2016-02-25 Qualcomm Incorporated Package substrates including embedded capacitors
US10211158B2 (en) 2014-10-31 2019-02-19 Infineon Technologies Ag Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module
US11322451B2 (en) 2014-10-31 2022-05-03 Infineon Technologies Ag Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module
US10020277B2 (en) 2016-02-03 2018-07-10 Fuji Xerox Co., Ltd. Circuit substrate and method for manufacturing circuit substrate
US10340243B2 (en) 2016-02-03 2019-07-02 Fuji Xerox Co., Ltd. Circuit substrate and method for manufacturing circuit substrate
US9640477B1 (en) 2016-03-04 2017-05-02 Fuji Xerox Co., Ltd. Semiconductor package and method of producing the semiconductor package
US20210161001A1 (en) * 2018-10-31 2021-05-27 HKC Corporation Limited Circuit board and display apparatus
US11638347B2 (en) * 2018-10-31 2023-04-25 HKC Corporation Limited Circuit board and display apparatus

Also Published As

Publication number Publication date
US7046501B2 (en) 2006-05-16
JP2005310814A (en) 2005-11-04
CN1684575A (en) 2005-10-19

Similar Documents

Publication Publication Date Title
US7046501B2 (en) Capacitor-embedded substrate
JP4474431B2 (en) Semiconductor package and manufacturing method thereof
JP3890947B2 (en) High frequency semiconductor device
US6853058B2 (en) Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member
KR100550480B1 (en) Multiple tier array capacitor and methods of fabrication therefor
US6376917B1 (en) Semiconductor device
US6967398B2 (en) Module power distribution network
US8179689B2 (en) Printed circuit board, method of fabricating printed circuit board, and semiconductor device
US7129571B2 (en) Semiconductor chip package having decoupling capacitor and manufacturing method thereof
US7005747B2 (en) Semiconductor device having additional functional element and method of manufacturing thereof
US6894396B2 (en) Semiconductor device with capacitor
US20080017407A1 (en) Interposer and electronic device using the same
US8242612B2 (en) Wiring board having piercing linear conductors and semiconductor device using the same
US20110316119A1 (en) Semiconductor package having de-coupling capacitor
JP3558595B2 (en) Semiconductor chip, semiconductor chip group and multi-chip module
KR20010108329A (en) Apparatus and method for an integrated circuit having high q reactive components
KR20040030604A (en) High performance, low cost microelectronic circuit package with interposer
US7023085B2 (en) Semiconductor package structure with reduced parasite capacitance and method of fabricating the same
CN111696970B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US20090079074A1 (en) Semiconductor device having decoupling capacitor formed on substrate where semiconductor chip is mounted
JP4190111B2 (en) High frequency module
US8829648B2 (en) Package substrate and semiconductor package
CN110634826A (en) Semiconductor device with a plurality of transistors
US20070069242A1 (en) Semiconductor chip and semiconductor device, and method for manufacturing semiconductor device
JP4547655B2 (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: ALPS ELECTRIC CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TSUJI, YOSHIOMI;REEL/FRAME:016455/0080

Effective date: 20050331

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20100516