US20050205501A1 - Reformed wafer boat - Google Patents

Reformed wafer boat Download PDF

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Publication number
US20050205501A1
US20050205501A1 US10/802,791 US80279104A US2005205501A1 US 20050205501 A1 US20050205501 A1 US 20050205501A1 US 80279104 A US80279104 A US 80279104A US 2005205501 A1 US2005205501 A1 US 2005205501A1
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United States
Prior art keywords
wafer boat
interval
reformed
wafer
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/802,791
Inventor
Juan Chuang
Joe Hsu
Chang Sun
Hsiuen Lu
Shun Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lite On Semiconductor Corp
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Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/802,791 priority Critical patent/US20050205501A1/en
Assigned to ANTEK SEMICONDUCTOR CORP. reassignment ANTEK SEMICONDUCTOR CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUANG, JUAN, HSU, JOE, LU, HSIUEN HSING, SUN, CHANG TE, WANG, SHUN YI
Assigned to LITE-ON SEMICONDUCTOR CORPORATION reassignment LITE-ON SEMICONDUCTOR CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: ANTEK SEMICONDUCTOR CORP.
Publication of US20050205501A1 publication Critical patent/US20050205501A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67313—Horizontal boat type carrier whereby the substrates are vertically supported, e.g. comprising rod-shaped elements

Definitions

  • the invention relates to a wafer boat for placing the semiconductor wafers, and more particularly, to a wafer boat that the distances between trenches are sequentially a long one and a short one.
  • the diffusion process using the furnace is one of the fundamental processes.
  • wafers are firstly placed on a wafer boat, and then the wafer boat is placed into the furnace for batch processing.
  • the amount of the semiconductor chips that can be manufactured in equipment at the same time seriously affects the manufacturing cost of the semiconductor chips. If the amount of wafers in each batch process can be increased, the manufacturing cost will be effectively lowered and the throughput will be also improved.
  • FIG. 1 Please refer to FIG. 1 .
  • the wafer boat 10 for placing wafers 12 needs larger intervals between trenches 14 to prevent the poor uniformity on the surface of the wafers 12 (the arrow in FIG. 1 shows the upper surface of the wafer).
  • the POCl 3 doping process has this kind of problem. But the larger interval between the wafers 12 makes the amount of wafers in the wafer boat fewer, and the throughput and manufacturing cost are unfavorable affected.
  • a reformed wafer boat has a plurality of trenches, and each trench is used for placing a wafer and each trench and its adjacent trench form an interval.
  • the plurality of intervals between the plurality of trenches are alternately composed of a first interval and a second interval, the first interval is longer than the second interval, and the wafers placed on the trenches at both ends of the second interval are in form of back to back.
  • FIG. 1 is a schematic diagram of a wafer boat according to the prior art.
  • FIG. 2 is a schematic diagram of a wafer boat according to the present invention.
  • FIG. 3 is a schematic diagram of another wafer boat according to the present invention. 10 wafer boat 12 wafer 14 trench 20 wafer boat 22 trench 24 wafer
  • the interval between the trenches and the placing direction of the wafers are reformed in the present invention. Without affecting the uniformity of the wafer, the amount of wafer placed on the wafer boat is increased.
  • FIG. 2 is a schematic diagram of a reformed wafer boat 20 according to the present invention.
  • the wafer boat 20 has a plurality of trenches 22 , and each trench 22 is used for placing a wafer 24 .
  • a first interval “a” is formed between each trench 22 and one adjacent trench 22
  • a second interval “b” is formed between each trench 22 and the other adjacent trench 22 , wherein the first interval “a” is longer than the second interval “b”.
  • the first interval “a” and the second interval “b” are alternately formed between the trenches 22 , and the wafers 24 placed on the trenches 22 at both ends of the second interval “b” are in form of back to back.
  • the space in front of the upper surface of each wafer is at least one first interval “a”. Even though the POCl 3 doping process is proceeded, the uniformity of the wafer can be also kept.
  • the wafer boat with little difference from the present invention is also claimed.
  • the wafer boat partially utilizes the conventional design of equal intervals, but the greater part still utilizes the claimed invention sequentially using intervals a long one and a short one.
  • the wafers placed at both ends of the smaller interval are in form of back to back. This kind of design is developed from the present invention and is also protected by the claims.
  • the present invention of the reformed wafer boat can increase the amount of wafer placed on the wafer boat without affecting the uniformity of wafers, so that the manufacturing cost can be effectively lowered and the throughput can be also improved.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The present invention discloses a reformed wafer boat. The reformed wafer boat has a plurality of trenches. A first interval is formed between each trench and one adjacent trench, and a second interval is formed between each trench and the other adjacent trench. The wafers placed on the trenches at both ends of the second interval are in form of back to back, and the first interval is formed between surfaces of each wafers. This kind of design does not affect uniformity during process, and the throughput can also be effectively improved.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a wafer boat for placing the semiconductor wafers, and more particularly, to a wafer boat that the distances between trenches are sequentially a long one and a short one.
  • 2. Description of the Prior Art
  • With the development of science and technology, various electric appliances have influenced our life profoundly. There are semiconductor chips in most of the electric appliances, so the importance of semiconductor chip industry cannot be ignored.
  • In the manufacturing process of the semiconductor chips, the diffusion process using the furnace is one of the fundamental processes. In the diffusion process, wafers are firstly placed on a wafer boat, and then the wafer boat is placed into the furnace for batch processing. The amount of the semiconductor chips that can be manufactured in equipment at the same time seriously affects the manufacturing cost of the semiconductor chips. If the amount of wafers in each batch process can be increased, the manufacturing cost will be effectively lowered and the throughput will be also improved.
  • Please refer to FIG. 1. When proceeding the doping process in the furnace, some process gases have greater coefficient of viscosity and lower flowing rate, so the wafer boat 10 for placing wafers 12 needs larger intervals between trenches 14 to prevent the poor uniformity on the surface of the wafers 12 (the arrow in FIG. 1 shows the upper surface of the wafer). For example, the POCl3 doping process has this kind of problem. But the larger interval between the wafers 12 makes the amount of wafers in the wafer boat fewer, and the throughput and manufacturing cost are unfavorable affected.
    • SUMMARY OF INVENTION
  • It is therefore a primary objective of the claimed invention to provide a reformed wafer boat that can increase the amount of wafer carried in the wafer boat while proceeding the diffusion process using gases with great coefficient of viscosity.
  • It is therefore another objective of the claimed invention to provide a reformed wafer boat that can improve the manufacturing throughput.
  • According to the claimed invention, a reformed wafer boat is disclosed. The reformed wafer boat has a plurality of trenches, and each trench is used for placing a wafer and each trench and its adjacent trench form an interval. The plurality of intervals between the plurality of trenches are alternately composed of a first interval and a second interval, the first interval is longer than the second interval, and the wafers placed on the trenches at both ends of the second interval are in form of back to back.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a schematic diagram of a wafer boat according to the prior art.
  • FIG. 2 is a schematic diagram of a wafer boat according to the present invention.
  • FIG. 3 is a schematic diagram of another wafer boat according to the present invention.
    10 wafer boat 12 wafer
    14 trench
    20 wafer boat 22 trench
    24 wafer
    • DETAILED DESCRIPTION
  • For increasing the amount of wafers placed on the wafer boat during the POCl3 doping process, the interval between the trenches and the placing direction of the wafers are reformed in the present invention. Without affecting the uniformity of the wafer, the amount of wafer placed on the wafer boat is increased.
  • Please refer to FIG. 2, which is a schematic diagram of a reformed wafer boat 20 according to the present invention. The wafer boat 20 has a plurality of trenches 22, and each trench 22 is used for placing a wafer 24. As shown in figure, a first interval “a” is formed between each trench 22 and one adjacent trench 22, and a second interval “b” is formed between each trench 22 and the other adjacent trench 22, wherein the first interval “a” is longer than the second interval “b”. The first interval “a” and the second interval “b” are alternately formed between the trenches 22, and the wafers 24 placed on the trenches 22 at both ends of the second interval “b” are in form of back to back. The space in front of the upper surface of each wafer is at least one first interval “a”. Even though the POCl3 doping process is proceeded, the uniformity of the wafer can be also kept.
  • Besides the first preferred embodiment, the wafer boat with little difference from the present invention is also claimed. As shown in FIG. 3, the wafer boat partially utilizes the conventional design of equal intervals, but the greater part still utilizes the claimed invention sequentially using intervals a long one and a short one. The wafers placed at both ends of the smaller interval are in form of back to back. This kind of design is developed from the present invention and is also protected by the claims.
  • In contrast to the prior art, the present invention of the reformed wafer boat can increase the amount of wafer placed on the wafer boat without affecting the uniformity of wafers, so that the manufacturing cost can be effectively lowered and the throughput can be also improved.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (3)

1. A reformed wafer boat with a plurality of trenches, each trench is used for placing a wafer and each trench and its adjacent trench form an interval, the plurality of intervals between the plurality of trenches are alternately composed of a first interval and a second interval, the first interval is longer than the second interval, and the wafers placed on the trenches at both ends of the second interval are in form of back to back.
2. The reformed wafer boat of claim 1, wherein the reformed wafer boat is used in a furnace process.
3. The reformed wafer boat of claim 1, wherein the reformed wafer boat is used in a POCl3 doping process.
US10/802,791 2004-03-18 2004-03-18 Reformed wafer boat Abandoned US20050205501A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/802,791 US20050205501A1 (en) 2004-03-18 2004-03-18 Reformed wafer boat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/802,791 US20050205501A1 (en) 2004-03-18 2004-03-18 Reformed wafer boat

Publications (1)

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US20050205501A1 true US20050205501A1 (en) 2005-09-22

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060010368A1 (en) * 2004-06-24 2006-01-12 Avaya Technology Corp. Method for storing and retrieving digital ink call logs
NL2002362C (en) * 2007-12-21 2010-03-18 Ardenne Anlagentech Gmbh SUBSTRATE HOLDER FOR GAS DIFFUSION OVENS.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6427850B2 (en) * 1998-02-04 2002-08-06 Micron Technology, Inc. Electronic device workpiece carriers
US6506256B2 (en) * 1998-01-30 2003-01-14 Nec Corporation Method and apparatus for diffusion of an impurity into a semiconductor wafer with high in-plane diffusion uniformity

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6506256B2 (en) * 1998-01-30 2003-01-14 Nec Corporation Method and apparatus for diffusion of an impurity into a semiconductor wafer with high in-plane diffusion uniformity
US6427850B2 (en) * 1998-02-04 2002-08-06 Micron Technology, Inc. Electronic device workpiece carriers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060010368A1 (en) * 2004-06-24 2006-01-12 Avaya Technology Corp. Method for storing and retrieving digital ink call logs
NL2002362C (en) * 2007-12-21 2010-03-18 Ardenne Anlagentech Gmbh SUBSTRATE HOLDER FOR GAS DIFFUSION OVENS.

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Legal Events

Date Code Title Description
AS Assignment

Owner name: ANTEK SEMICONDUCTOR CORP., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUANG, JUAN;HSU, JOE;SUN, CHANG TE;AND OTHERS;REEL/FRAME:015113/0264

Effective date: 20040308

AS Assignment

Owner name: LITE-ON SEMICONDUCTOR CORPORATION, TAIWAN

Free format text: MERGER;ASSIGNOR:ANTEK SEMICONDUCTOR CORP.;REEL/FRAME:016816/0359

Effective date: 20050708

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION