US20050164424A1 - Silison film for thin film transistors - Google Patents

Silison film for thin film transistors Download PDF

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US20050164424A1
US20050164424A1 US10/704,928 US70492803A US2005164424A1 US 20050164424 A1 US20050164424 A1 US 20050164424A1 US 70492803 A US70492803 A US 70492803A US 2005164424 A1 US2005164424 A1 US 2005164424A1
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amorphous silicon
hydrogen
film
range
silicon film
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Apostolos Voutsas
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Sharp Laboratories of America Inc
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Sharp Laboratories of America Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Definitions

  • This invention generally relates to the fabrication of integrated circuits and, more particularly, to a system and method for forming polysilicon (p-Si) films from the sputter deposition of amorphous Si (a-Si) using an Argon (Ar)-Hydrogen (H 2 ) gas mixture.
  • Amorphous Si thin films are used in the fabrication of polycrystalline silicon thin film transistors (TFTs), which in turn are a key element in active matrix (AM) type liquid crystal displays (LCDs).
  • TFTs polycrystalline silicon thin film transistors
  • AM active matrix
  • Sputtering is a well-known conventional process, suited to the formation of the various Si-based, TFT layers because:
  • Silicon films with very low H 2 content can be deposited by this method. Hence, there is no need for dehydrogenation to release excessive hydrogen. Alternatively, hydrogen can be incorporated into the film if, and when, necessary; and
  • the deposited amorphous silicon film be converted, typically by annealing, into a microcrystalline or polycrystalline Si film.
  • annealing There are many processes known in the art to form polycrystalline silicon (polysilicon) from amorphous silicon.
  • FIGS. 1 a through 1 e are partial cross-sectional diagrams illustrating the fabrication of a conventional top-gate TFT structure (prior art).
  • Poly-Si (polycrystalline-Si) TFTs are made by a plurality of processes. In the majority of polycrystalline silicon TFT LCD applications, the so-called top-gate, polycrystalline silicon TFT structure is used.
  • PE-CVD Plasma-Enhanced Chemical Vapor Deposition
  • LPCVD Low-Pressure CVD
  • PVD physical vapor deposition
  • sputtering to form the silicon film. Such advantages are a reduction in process steps, since there is no need for dehydrogenation, a reduction in equipment costs, and improved process safety, since no toxic/pyrophoric gases are necessary.
  • a barrier layer 10 is deposited over a substrate 12 .
  • Amorphous Si 14 is deposited over barrier layer 10 .
  • the silicon layer 14 is annealed, using an Excimer Laser for example, to form polycrystalline silicon layer 14 . Then, the polycrystalline silicon layer 14 is patterned and dry etched.
  • a gate isolation layer 16 is formed over the polycrystalline silicon layer 14 .
  • a gate 18 is formed over gate isolation layer 16 , and the source region 20 and drain region 22 are implanted with P material.
  • an interlayer dielectric 24 is isotropically deposited.
  • the interlayer dielectric 24 is selectively etched to form vias to the source/drain regions 20 / 22 .
  • a source contact 26 and a drain contact 28 are deposited and patterned.
  • the present invention is concerned with the sputter deposition of the amorphous silicon used to form polycrystalline silicon layer 14 ( FIG. 1 a ).
  • FIG. 2 is a partial cross-sectional diagram of a typical DC magnetron sputtering chamber (prior art).
  • the target is a block of the material to be deposited, mounted on an appropriate metal backing plate, and placed opposite to the substrate where the film is to be deposited.
  • Plasma strikes in the gap between the target and the substrate.
  • the magnet that is scanning above the target backing plate is used to intensify the plasma and confine it in the region defined by the magnetic field. By scanning the magnet, the plasma is swept across the surface of the target, resulting in deposition of the film on the substrate opposite to the target.
  • the plasma is generated by applying high voltage to an inert gas (typically Ar, but alternately He, Ne, Kr or mixtures) that flows in the region between the target and the substrate.
  • an inert gas typically Ar, but alternately He, Ne, Kr or mixtures
  • other gases may be mixed to the sputtering gas, such as H 2 , O 2 , N 2 , etc., to alter the composition and/or the properties of the sputtered film.
  • a method for forming a polycrystalline silicon (p-Si) film in an integrated circuit (IC) fabrication process comprises: sputtering amorphous silicon (a-Si) material on a substrate; supplying an Ar gas mixture including a hydrogen content of no more than 4% volume (in the gas feed); forming an amorphous silicon film incorporating hydrogen; annealing the amorphous silicon film using a rapid thermal annealing or Excimer laser process; and, forming a polycrystalline silicon film having a crystalline content in the range from 95 percent (%) to 100%, as measured by Raman Spectroscopy or equivalent measurement means, and a hydrogen content in the range from 1% atomic weight (at %) to 3 at %.
  • the polycrystalline silicon film comprises a pre-anneal amorphous silicon (a-Si) film having a content of no more than 4% hydrogen, by atomic weight, and a post-anneal polycrystalline silicon film having a crystalline content in the range from 95% to 100%, and a hydrogen content in the range from 1 at % to 3 at %.
  • a-Si pre-anneal amorphous silicon
  • FIGS. 1 a through 1 e are partial cross-sectional diagrams illustrating the fabrication of a conventional top-gate TFT structure (prior art).
  • FIG. 2 is a partial cross-sectional diagram of a typical DC magnetron sputtering chamber (prior art).
  • FIG. 3 is a partial cross-sectional view of a pre-anneal film used in the fabrication of a thin film transistor (TFT).
  • TFT thin film transistor
  • FIG. 4 is a partial cross-sectional view of the TFT transistor of FIG. 3 following an annealing process.
  • FIGS. 5 and 6 are graphs comparing the sheet resistance of PVD-Si films as a function of the gas mixture used for their formation.
  • FIG. 7 is a graph illustrating the relationship between the amount of hydrogen in the sputter deposition gas and the resulting hydrogen in the deposited film.
  • FIG. 8 is a flowchart illustrating a method for forming a polycrystalline silicon (p-Si) film in an IC fabrication process.
  • FIG. 9 is a flowchart illustrating another method for forming a polycrystalline silicon film in an IC fabrication process.
  • FIG. 10 is a flowchart illustrating yet another method for forming a polycrystalline silicon film in an IC fabrication process.
  • FIG. 3 is a partial cross-sectional view of a pre-anneal film used in the fabrication of a thin film transistor (TFT) 300 .
  • TFT thin film transistor
  • a barrier layer 302 is deposited over a substrate 304 .
  • Amorphous Si 306 is deposited over barrier layer 302 .
  • the silicon layer 306 is formed over others materials (not shown), as FIG. 3 is only one example process.
  • the amorphous silicon film 306 has been formed so that it has a small hydrogen content. Specifically, the amorphous silicon film 306 has no more than 4% hydrogen content in the amorphous silicon, by atomic weight.
  • the hydrogen content is in the range from 0.1 percent by atomic weight (at %) to 4 at %. In other aspects of the invention the hydrogen content is in the range from 1 at % to 4 at %, or in the range from 3 at % to 4 at %. The percentage is varied to achieve differences in the resultant film characteristics.
  • FIG. 4 is a partial cross-sectional view of the TFT 300 transistor of FIG. 3 following an annealing process. Following annealing, the amorphous silicon film is transformed into a post-anneal polycrystalline silicon film 400 having a crystalline content in the range from 95% to 100%, and a hydrogen content in the range from 1 at % to 3 at %.
  • the present invention is concerned with a Si sputtering using mainly Ar gas, with the addition of a small percentage of H 2 .
  • the present invention discloses an amorphous silicon film including 0.1 at % to 4 at % H 2 .
  • Amorphous Si film, with H 2 content in the range of 0.1-4 at %, is initially deposited and the crystallized via an annealing step to yield polycrystalline silicon.
  • the annealing step can be conducted by a rapid thermal annealing method, by Excimer laser annealing, or by equivalent methods known in the art.
  • the low hydrogen content in the film enables a better microstructure that responds favorably to the annealing process, and yields a lower defect-density crystalline network.
  • PVD physical vapor deposition
  • FIGS. 5 and 6 are graphs comparing the sheet resistance of PVD-Si films as a function of the gas mixture used for their formation.
  • the sheet resistance was obtained after implantation of either phosphorus ( FIG. 5 ) or boron ( FIG. 6 ). Both furnace and rapid thermal anneal (RTA) activation were used for comparison.
  • the PVD-Si films were formed by sputtering with pure Ar (Ar std), a mixture of Ar—He gas, a mixture of Ar—H 2 gas, and pure He (He std). These results are compared to a plasma-enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma-enhanced chemical vapor deposition
  • FIGS. 5 and 6 demonstrate that the PVD-Si films deposited with Ar—H 2 gas have a sheet resistance range comparable to that of the PECVD-Si films (reference samples). This finding suggests that for the crystallization of amorphous silicon, or for source-drain activation, Ar—H 2 sputtering may be a more desirable process that pure Ar sputtering.
  • a gas mixture of Ar with 4% hydrogen by volume, or 4% hydrogen as measured by volume in the gas feed supplying the gas to the deposition chamber is used as the sputtering gas in the present invention deposition of amorphous silicon film.
  • the advantage of 4% H 2 in Ar gas is that it can be treated as inert, not requiring special handling and storage. Since the gas is easy to control, the correct amount of hydrogen can be incorporated into the film.
  • the graphs show the results of a small amount of hydrogen mixed with Ar, the present invention concept will be equally applicable to the mixing of a small amount of hydrogen with other gases commonly used for sputter deposition, such as He, Ne, Kr, and mixtures of these gases. However, these other gas mixtures may require a different percentage of hydrogen in the mixture to achieve the same results as described above.
  • FIG. 7 is a graph illustrating the relationship between the amount of hydrogen in the sputter deposition gas and the resulting hydrogen in the deposited film.
  • the control of the H 2 incorporation is accomplished by adjusting the process temperature and/or the process pressure (gas flow).
  • the incorporation of H 2 decreases at higher process temperatures, as H 2 tends to readily desorb at process temperatures higher than about 300 degrees C.
  • an amorphous silicon film with a hydrogen content in the range of 0.1-4 at % (percentage by atomic weight) can be realized.
  • FIG. 8 is a flowchart illustrating a method for forming a polycrystalline silicon (p-Si) film in an IC fabrication process. Although the method is depicted as a sequence of numbered steps for clarity, no order should be inferred from the numbering unless explicitly stated.
  • the method begins at Step 800 .
  • Step 802 sputters amorphous silicon (a-Si) material on a substrate. Sputtering amorphous silicon (a-Si) material on a substrate in Step 802 includes setting the process temperature to be in the range from 200 degrees C. to 400 degrees C.
  • Step 804 supplies a gas mixture including a hydrogen content of no more than 4% volume in the gas feed.
  • Step 806 forms an amorphous silicon film incorporating hydrogen.
  • Step 808 anneals the amorphous silicon film.
  • Step 810 forms a polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 at % to 3 at %.
  • FIG. 9 is a flowchart illustrating another method for forming a polycrystalline silicon film in an IC fabrication process.
  • the method begins at Step 900 .
  • Step 902 sputters amorphous silicon (a-Si) material on a substrate.
  • Sputtering amorphous silicon (a-Si) material on a substrate in Step 902 includes setting the process temperature in the range from 200 degrees C. to 400 degrees C.
  • Step 904 supplies a gas mixture having a low hydrogen volume at the gas feed.
  • Step 906 forms an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight.
  • Step 908 anneals the amorphous silicon film.
  • Step 910 forms a polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 at % to 3 at %.
  • FIG. 10 is a flowchart illustrating yet another method for forming a polycrystalline silicon film in an IC fabrication process.
  • the method begins at Step 1000 .
  • Step 1000 sputters amorphous silicon material on a substrate.
  • Sputtering amorphous silicon material on a substrate includes setting the process temperature to be in the range from 200 degrees C. to 400 degrees C.
  • Step 1004 supplies a gas mixture including no more than 4% hydrogen volume in the gas feed.
  • supplying a gas mixture including no more than 4% hydrogen volume in the gas feed in Step 1004 includes supplying a gas mixture substantially including Ar, mixed with no more than 4% hydrogen.
  • the gas mixture includes hydrogen in the range from 0.1% to 4%.
  • Other inert gases, besides Ar, would yield equivalent results.
  • Step 1006 forms an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight.
  • forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight includes forming an amorphous silicon film having hydrogen content in the range from 0.1% to 4%, by atomic weight. Alternate ranges include hydrogen content in the range from 1% to 4%, or hydrogen content in the range from 3% to 4%, by atomic weight.
  • Step 1008 anneals the amorphous silicon film.
  • Annealing the amorphous silicon film includes annealing with a process selected from the group including rapid thermal annealing (RTA) and Excimer laser annealing (ELA).
  • RTA rapid thermal annealing
  • ELA Excimer laser annealing
  • Step 1008 rapid thermal anneals (RTA) at a temperature greater than approximately 600 degrees C.
  • the rapid thermal annealing temperature is in the range from 600 degrees C. to 900 degrees C.
  • Step 1010 forms a polycrystalline silicon film as described above.
  • Step 1006 includes forming an amorphous silicon film incorporating hydrogen content in the range from 3% to 4%, by atomic weight. Then, Step 1008 rapid thermal anneals at a temperature in the range from 600 degrees C. to 900 degrees C.
  • a polycrystalline silicon film with a small amount of hydrogen, and a method for forming such a polycrystalline silicon film have been provided.
  • the polycrystalline silicon film of the present invention is immediately applicable to amorphous silicon and polycrystalline silicon TFT devices in an LCD panel.
  • the process will have uses in other, more general, and unspecified IC fabrication process. Variations and other embodiments of the invention will occur to those skilled in the art.

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Abstract

A method has been provided for forming a polycrystalline silicon (p-Si) film with a small amount of hydrogen. Such a film has been found to have excellent sheet resistance, and it is useful in the fabrication of liquid crystal display (LCD) panels made from thin film transistors (TFTs). The low hydrogen content polycrystalline silicon films are made from introducing a small amount of hydrogen gas, with Ar, during the sputter deposition of an amorphous silicon film. The hydrogen content in the film is regulated by controlling the deposition temperatures and the volume of hydrogen in the gas feed during the sputter deposition. The polycrystalline silicon film results from annealing the low hydrogen content amorphous silicon film thus formed.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of application Ser. No. 09/862,092, filed May 21, 2001, entitled “System and Method for Sputtering Silicon Films Using Hydrogen Gas Mixtures,” invented by Apostolos Voutsas, now issued as U.S. Pat. No. 6,649,032.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention generally relates to the fabrication of integrated circuits and, more particularly, to a system and method for forming polysilicon (p-Si) films from the sputter deposition of amorphous Si (a-Si) using an Argon (Ar)-Hydrogen (H2) gas mixture.
  • 2. Description of the Related Art
  • Amorphous Si thin films are used in the fabrication of polycrystalline silicon thin film transistors (TFTs), which in turn are a key element in active matrix (AM) type liquid crystal displays (LCDs).
  • Sputtering is a well-known conventional process, suited to the formation of the various Si-based, TFT layers because:
  • 1. It is a safe and environmentally benign technique;
  • 2. It can be used even at room temperature. Hence, it is compatible with any kind of substrate;
  • 3. Silicon films with very low H2 content can be deposited by this method. Hence, there is no need for dehydrogenation to release excessive hydrogen. Alternatively, hydrogen can be incorporated into the film if, and when, necessary; and
  • 4. It is a simpler and a more easily scaled method than comparable methods that rely upon chemistry.
  • For improved electrical performance it is desirable that the deposited amorphous silicon film be converted, typically by annealing, into a microcrystalline or polycrystalline Si film. There are many processes known in the art to form polycrystalline silicon (polysilicon) from amorphous silicon.
  • It is known to use a large amount of hydrogen in the Ar gas in the sputtering deposition process for applications such as deposition of hydrogenated a-Si:H films used in amorphous silicon solar cells or amorphous silicon LCDs. In these films, H2 termination of Si dangling bonds is necessary to achieve desired film characteristics. However, the use of hydrogen in the sputtering deposition process is not conventionally known to improve the electrical characteristics of the polycrystalline silicon film formed by this method.
  • FIGS. 1 a through 1 e are partial cross-sectional diagrams illustrating the fabrication of a conventional top-gate TFT structure (prior art). Poly-Si (polycrystalline-Si) TFTs are made by a plurality of processes. In the majority of polycrystalline silicon TFT LCD applications, the so-called top-gate, polycrystalline silicon TFT structure is used. Typically, Plasma-Enhanced Chemical Vapor Deposition (PE-CVD) or Low-Pressure CVD (LPCVD) is used to deposit the amorphous silicon precursor. However, there are several advantages in using physical vapor deposition (PVD) or sputtering to form the silicon film. Such advantages are a reduction in process steps, since there is no need for dehydrogenation, a reduction in equipment costs, and improved process safety, since no toxic/pyrophoric gases are necessary.
  • In FIG. 1 a a barrier layer 10 is deposited over a substrate 12. Amorphous Si 14 is deposited over barrier layer 10.
  • In FIG. 1 b the silicon layer 14 is annealed, using an Excimer Laser for example, to form polycrystalline silicon layer 14. Then, the polycrystalline silicon layer 14 is patterned and dry etched.
  • In FIG. 1 c a gate isolation layer 16 is formed over the polycrystalline silicon layer 14. A gate 18 is formed over gate isolation layer 16, and the source region 20 and drain region 22 are implanted with P material.
  • In FIG. 1 d an interlayer dielectric 24 is isotropically deposited.
  • In FIG. 1 e the interlayer dielectric 24 is selectively etched to form vias to the source/drain regions 20/22. A source contact 26 and a drain contact 28 are deposited and patterned. The present invention is concerned with the sputter deposition of the amorphous silicon used to form polycrystalline silicon layer 14 (FIG. 1 a).
  • FIG. 2 is a partial cross-sectional diagram of a typical DC magnetron sputtering chamber (prior art). One of the key aspects of the Si-sputtering process is the ‘target’ component. The target is a block of the material to be deposited, mounted on an appropriate metal backing plate, and placed opposite to the substrate where the film is to be deposited. Plasma strikes in the gap between the target and the substrate. The magnet that is scanning above the target backing plate is used to intensify the plasma and confine it in the region defined by the magnetic field. By scanning the magnet, the plasma is swept across the surface of the target, resulting in deposition of the film on the substrate opposite to the target. The plasma is generated by applying high voltage to an inert gas (typically Ar, but alternately He, Ne, Kr or mixtures) that flows in the region between the target and the substrate. For certain applications, other gases may be mixed to the sputtering gas, such as H2, O2, N2, etc., to alter the composition and/or the properties of the sputtered film.
  • It would be advantageous if a process existed for improving the electrical characteristics associated with an amorphous silicon film deposited by sputtering.
  • It would be advantageous if a process existed for improving the sheet resistance of polycrystalline silicon film, annealed from a sputter deposited amorphous silicon film.
  • It would be advantageous if the above-mentioned polycrystalline silicon film could be fabricated using easily controlled process steps and inert materials.
    • SUMMARY OF THE INVENTION
  • Accordingly, a method is provided for forming a polycrystalline silicon (p-Si) film in an integrated circuit (IC) fabrication process. The method comprises: sputtering amorphous silicon (a-Si) material on a substrate; supplying an Ar gas mixture including a hydrogen content of no more than 4% volume (in the gas feed); forming an amorphous silicon film incorporating hydrogen; annealing the amorphous silicon film using a rapid thermal annealing or Excimer laser process; and, forming a polycrystalline silicon film having a crystalline content in the range from 95 percent (%) to 100%, as measured by Raman Spectroscopy or equivalent measurement means, and a hydrogen content in the range from 1% atomic weight (at %) to 3 at %.
  • Also provided is a polysilicon (p-Si) film, such as might be used in the fabrication of a thin film transistor (TFT). The polycrystalline silicon film comprises a pre-anneal amorphous silicon (a-Si) film having a content of no more than 4% hydrogen, by atomic weight, and a post-anneal polycrystalline silicon film having a crystalline content in the range from 95% to 100%, and a hydrogen content in the range from 1 at % to 3 at %.
  • Additional details of the polycrystalline silicon film, polycrystalline silicon film fabrication process, and a pre-anneal film are provided below.
    • BRIEF DESCRIPTION OF THE DRAWING
  • FIGS. 1 a through 1 e are partial cross-sectional diagrams illustrating the fabrication of a conventional top-gate TFT structure (prior art).
  • FIG. 2 is a partial cross-sectional diagram of a typical DC magnetron sputtering chamber (prior art).
  • FIG. 3 is a partial cross-sectional view of a pre-anneal film used in the fabrication of a thin film transistor (TFT).
  • FIG. 4 is a partial cross-sectional view of the TFT transistor of FIG. 3 following an annealing process.
  • FIGS. 5 and 6 are graphs comparing the sheet resistance of PVD-Si films as a function of the gas mixture used for their formation.
  • FIG. 7 is a graph illustrating the relationship between the amount of hydrogen in the sputter deposition gas and the resulting hydrogen in the deposited film.
  • FIG. 8 is a flowchart illustrating a method for forming a polycrystalline silicon (p-Si) film in an IC fabrication process.
  • FIG. 9 is a flowchart illustrating another method for forming a polycrystalline silicon film in an IC fabrication process.
  • FIG. 10 is a flowchart illustrating yet another method for forming a polycrystalline silicon film in an IC fabrication process.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 3 is a partial cross-sectional view of a pre-anneal film used in the fabrication of a thin film transistor (TFT) 300. Such a transistor might be, in turn, used in the fabrication of an LCD panel. As in FIG. 1 a, a barrier layer 302 is deposited over a substrate 304. Amorphous Si 306 is deposited over barrier layer 302. Alternately, the silicon layer 306 is formed over others materials (not shown), as FIG. 3 is only one example process. The amorphous silicon film 306 has been formed so that it has a small hydrogen content. Specifically, the amorphous silicon film 306 has no more than 4% hydrogen content in the amorphous silicon, by atomic weight. Even more specifically, the hydrogen content is in the range from 0.1 percent by atomic weight (at %) to 4 at %. In other aspects of the invention the hydrogen content is in the range from 1 at % to 4 at %, or in the range from 3 at % to 4 at %. The percentage is varied to achieve differences in the resultant film characteristics.
  • FIG. 4 is a partial cross-sectional view of the TFT 300 transistor of FIG. 3 following an annealing process. Following annealing, the amorphous silicon film is transformed into a post-anneal polycrystalline silicon film 400 having a crystalline content in the range from 95% to 100%, and a hydrogen content in the range from 1 at % to 3 at %.
  • The present invention is concerned with a Si sputtering using mainly Ar gas, with the addition of a small percentage of H2. The present invention discloses an amorphous silicon film including 0.1 at % to 4 at % H2. Amorphous Si film, with H2 content in the range of 0.1-4 at %, is initially deposited and the crystallized via an annealing step to yield polycrystalline silicon. The annealing step can be conducted by a rapid thermal annealing method, by Excimer laser annealing, or by equivalent methods known in the art. The low hydrogen content in the film enables a better microstructure that responds favorably to the annealing process, and yields a lower defect-density crystalline network. In the complete absence of hydrogen, physical vapor deposition (PVD) Si films are more difficult to crystallize by thermal-processes, and tend to generate more film defects, even after laser crystallization. This implies that the expected electrical performance of PVD-Si films formed by only Ar may be inferior to that of PVD-Si films formed by Ar—H2 mixture.
  • FIGS. 5 and 6 are graphs comparing the sheet resistance of PVD-Si films as a function of the gas mixture used for their formation. The sheet resistance was obtained after implantation of either phosphorus (FIG. 5) or boron (FIG. 6). Both furnace and rapid thermal anneal (RTA) activation were used for comparison. The PVD-Si films were formed by sputtering with pure Ar (Ar std), a mixture of Ar—He gas, a mixture of Ar—H2 gas, and pure He (He std). These results are compared to a plasma-enhanced chemical vapor deposition (PECVD) process.
  • FIGS. 5 and 6 demonstrate that the PVD-Si films deposited with Ar—H2 gas have a sheet resistance range comparable to that of the PECVD-Si films (reference samples). This finding suggests that for the crystallization of amorphous silicon, or for source-drain activation, Ar—H2 sputtering may be a more desirable process that pure Ar sputtering.
  • Thus, a gas mixture of Ar with 4% hydrogen by volume, or 4% hydrogen as measured by volume in the gas feed supplying the gas to the deposition chamber, is used as the sputtering gas in the present invention deposition of amorphous silicon film. The advantage of 4% H2 in Ar gas is that it can be treated as inert, not requiring special handling and storage. Since the gas is easy to control, the correct amount of hydrogen can be incorporated into the film. Although the graphs show the results of a small amount of hydrogen mixed with Ar, the present invention concept will be equally applicable to the mixing of a small amount of hydrogen with other gases commonly used for sputter deposition, such as He, Ne, Kr, and mixtures of these gases. However, these other gas mixtures may require a different percentage of hydrogen in the mixture to achieve the same results as described above.
  • FIG. 7 is a graph illustrating the relationship between the amount of hydrogen in the sputter deposition gas and the resulting hydrogen in the deposited film. The control of the H2 incorporation is accomplished by adjusting the process temperature and/or the process pressure (gas flow). The incorporation of H2 decreases at higher process temperatures, as H2 tends to readily desorb at process temperatures higher than about 300 degrees C. Thus, by controlling the hydrogen in the gas feed and the range of process temperatures in the range of 200 degrees C. to 400 degrees C., an amorphous silicon film with a hydrogen content in the range of 0.1-4 at % (percentage by atomic weight) can be realized.
  • FIG. 8 is a flowchart illustrating a method for forming a polycrystalline silicon (p-Si) film in an IC fabrication process. Although the method is depicted as a sequence of numbered steps for clarity, no order should be inferred from the numbering unless explicitly stated. The method begins at Step 800. Step 802 sputters amorphous silicon (a-Si) material on a substrate. Sputtering amorphous silicon (a-Si) material on a substrate in Step 802 includes setting the process temperature to be in the range from 200 degrees C. to 400 degrees C. Step 804 supplies a gas mixture including a hydrogen content of no more than 4% volume in the gas feed. Step 806 forms an amorphous silicon film incorporating hydrogen. Step 808 anneals the amorphous silicon film. Step 810 forms a polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 at % to 3 at %.
  • FIG. 9 is a flowchart illustrating another method for forming a polycrystalline silicon film in an IC fabrication process. The method begins at Step 900. Step 902 sputters amorphous silicon (a-Si) material on a substrate. Sputtering amorphous silicon (a-Si) material on a substrate in Step 902 includes setting the process temperature in the range from 200 degrees C. to 400 degrees C. Step 904 supplies a gas mixture having a low hydrogen volume at the gas feed. Step 906 forms an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight. Step 908 anneals the amorphous silicon film. Step 910 forms a polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 at % to 3 at %.
  • FIG. 10 is a flowchart illustrating yet another method for forming a polycrystalline silicon film in an IC fabrication process. The method begins at Step 1000. Step 1000 sputters amorphous silicon material on a substrate. Sputtering amorphous silicon material on a substrate includes setting the process temperature to be in the range from 200 degrees C. to 400 degrees C. Step 1004 supplies a gas mixture including no more than 4% hydrogen volume in the gas feed. In some aspects of the invention supplying a gas mixture including no more than 4% hydrogen volume in the gas feed in Step 1004 includes supplying a gas mixture substantially including Ar, mixed with no more than 4% hydrogen. Alternately, the gas mixture includes hydrogen in the range from 0.1% to 4%. Other inert gases, besides Ar, would yield equivalent results.
  • Step 1006 forms an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight. In some aspects forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight includes forming an amorphous silicon film having hydrogen content in the range from 0.1% to 4%, by atomic weight. Alternate ranges include hydrogen content in the range from 1% to 4%, or hydrogen content in the range from 3% to 4%, by atomic weight.
  • Step 1008 anneals the amorphous silicon film. Annealing the amorphous silicon film includes annealing with a process selected from the group including rapid thermal annealing (RTA) and Excimer laser annealing (ELA). In some aspects Step 1008 rapid thermal anneals (RTA) at a temperature greater than approximately 600 degrees C. Alternately, the rapid thermal annealing temperature is in the range from 600 degrees C. to 900 degrees C. Step 1010 forms a polycrystalline silicon film as described above.
  • In some aspects of the invention Step 1006 includes forming an amorphous silicon film incorporating hydrogen content in the range from 3% to 4%, by atomic weight. Then, Step 1008 rapid thermal anneals at a temperature in the range from 600 degrees C. to 900 degrees C.
  • A polycrystalline silicon film with a small amount of hydrogen, and a method for forming such a polycrystalline silicon film have been provided. The polycrystalline silicon film of the present invention is immediately applicable to amorphous silicon and polycrystalline silicon TFT devices in an LCD panel. However, the process will have uses in other, more general, and unspecified IC fabrication process. Variations and other embodiments of the invention will occur to those skilled in the art.

Claims (27)

1. In an integrated circuit (IC) fabrication process, a method for forming a polycrystalline silicon (p-Si) film, the method comprising:
sputtering amorphous silicon (a-Si) material on a substrate;
supplying a gas mixture including a hydrogen content of no more than 4% volume in the gas feed; and
forming an amorphous silicon film incorporating hydrogen.
2. The method of claim 1 further comprising:
annealing the amorphous silicon film; and
forming a polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 percent by atomic weight (at %) to 3 at %.
3. The method of claim 1 wherein sputtering amorphous silicon material on a substrate includes setting the process temperature to be in the range from 200 degrees C. to 400 degrees C.
4. In an integrated circuit (IC) fabrication process, a method for forming a polycrystalline silicon (p-Si) film, the method comprising:
sputtering amorphous silicon (a-Si) material on a substrate;
supplying a gas mixture having a low hydrogen volume at the gas feed; and
forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight.
5. The method of claim 4 further comprising:
annealing the amorphous silicon film; and
forming a polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 percent by atomic weight (at %) to 3 at %.
6. The method of claim 4 wherein sputtering amorphous silicon material on a substrate includes setting the process temperature in the range from 200 degrees C. to 400 degrees C.
7. In an integrated circuit (IC) fabrication process, a method for forming a polycrystalline silicon (p-Si) film, the method comprising:
sputtering amorphous silicon (a-Si) material on a substrate;
supplying a gas mixture including no more than 4%. hydrogen volume in the gas feed; forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight.
8. The method of claim 7 wherein supplying a gas mixture including no more than 4% hydrogen volume in the gas feed includes supplying a gas mixture substantially including Ar, mixed with no more than 4% hydrogen.
9. The method of claim 7 wherein supplying a gas mixture including no more than 4% hydrogen volume in the gas feed includes supplying a gas mixture including hydrogen in the range from 0.1% to 4%.
10. The method of claim 7 wherein forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight includes forming an amorphous silicon film having hydrogen content in the range from 0.1% to 4%, by atomic weight.
11. The method of claim 10 wherein forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight includes forming an amorphous silicon film having hydrogen content in the range from 1% to 4%, by atomic weight.
12. The method of claim 11 wherein forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight includes forming an amorphous silicon film having hydrogen content in the range from 3% to 4%, by atomic weight.
13. The method of claim 7 further comprising:
annealing the amorphous silicon film; and
forming a polycrystalline silicon film.
14. The method of claim 13 wherein annealing the amorphous silicon film includes annealing with a process selected from the group including rapid thermal annealing (RTA) and Excimer laser annealing (ELA).
15. The method of claim 13 wherein annealing the amorphous silicon film includes rapid thermal annealing at a temperature greater than approximately 600 degrees C.
16. The method of claim 13 wherein annealing the amorphous silicon film includes rapid thermal annealing at a temperature in the range from 600 degrees C. to 900 degrees C.
17. The method of claim 13 wherein forming an amorphous silicon film incorporating no more than 4% hydrogen, by atomic weight includes forming an amorphous silicon film incorporating hydrogen content in the range from 3% to 4%, by atomic weight; and
wherein annealing the amorphous silicon film includes rapid thermal annealing at a temperature in the range from 600 degrees C. to 900 degrees C.
18. The method of claim 7 wherein sputtering amorphous silicon amorphous silicon material on a substrate includes setting the process temperature to be in the range from 200 degrees C. to 400 degrees C.
19. In the fabrication of a thin film transistor (TFT), a polysilicon (p-Si) film comprising:
a pre-anneal amorphous silicon (a-Si) film having a content of no more than 4% hydrogen, by atomic weight; and
a post-anneal polycrystalline silicon film having a crystalline content in the range from 95% to 100%, and a hydrogen content in the range from 1 percent by atomic weight (at %) to 3 at %.
20. The silicon film of claim 19 wherein the pre-anneal amorphous silicon film has a hydrogen content in the range from 0.1 at % to 4 at %.
21. The silicon film of claim 20 wherein the pre-anneal amorphous silicon film-has a hydrogen content in the range from 1 at % to 4 at %.
22. The silicon film of claim 21 wherein the pre-anneal amorphous silicon film has a hydrogen content in the range from 3 at % to 4 at %.
23. In the fabrication of a thin film transistor (TFT), a pre-anneal film comprising:
amorphous silicon (a-Si); and
no more than 4% hydrogen content in the amorphous silicon, by atomic weight.
24. The pre-anneal film of claim 23 wherein the hydrogen content is in the range from 0.1 percent by atomic weight (at %) to 4 at %.
25. The pre-anneal film of claim 24 wherein the hydrogen content is in the range from 1 at % to 4 at %.
26. The pre-anneal film of claim 25 wherein the hydrogen content is in the range from 3 at % to 4 at %.
27. In the fabrication of a liquid crystal display (LCD) including a thin film transistor (TFT), a polysilicon (p-Si) film comprising:
a pre-anneal amorphous silicon (a-Si) film having a content of no more than 4 percent by atomic weight (at %) hydrogen; and
a post-anneal polycrystalline silicon film having a crystalline content in the range from 95% to 100% and a hydrogen content in the range from 1 percent by atomic weight (at %) to 3 at %.
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