US20050151476A1 - Plasma display panel - Google Patents
Plasma display panel Download PDFInfo
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- US20050151476A1 US20050151476A1 US10/512,580 US51258004A US2005151476A1 US 20050151476 A1 US20050151476 A1 US 20050151476A1 US 51258004 A US51258004 A US 51258004A US 2005151476 A1 US2005151476 A1 US 2005151476A1
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- electrode
- wiring lead
- dielectric layer
- wiring
- plasma display
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
- H01J11/12—AC-PDPs with at least one main electrode being out of contact with the plasma with main electrodes provided on both sides of the discharge space
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/13—Solid thermionic cathodes
- H01J1/20—Cathodes heated indirectly by an electric current; Cathodes heated by electron or ion bombardment
- H01J1/22—Heaters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/20—Constructional details
- H01J11/22—Electrodes, e.g. special shape, material or configuration
- H01J11/28—Auxiliary electrodes, e.g. priming electrodes or trigger electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/20—Constructional details
- H01J11/34—Vessels, containers or parts thereof, e.g. substrates
- H01J11/38—Dielectric or insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/20—Constructional details
- H01J11/46—Connecting or feeding means, e.g. leading-in conductors
Definitions
- the present invention relates to plasma display panels, and more particularly to plasma display panels achieving highly reliable connections in multilayer electrode wiring.
- Plasma display devices employing plasma display panels are drawing increasing attention as display devices for high-definition television images on large screens.
- a PDP is basically composed of front and rear boards.
- the front board includes a glass substrate, display electrodes including transparent electrodes and bus electrodes aligned in stripes on one main face of the glass substrate, a dielectric layer covering the display electrodes that functions as a capacitor, and a dielectric protective film formed on the dielectric layer.
- the rear board includes a glass substrate, address electrodes aligned in stripes on one main face, a dielectric layer covering the address electrodes, barrier ribs formed on the dielectric layer, and a phosphor layer which emits red, green, and blue lights formed between barrier ribs.
- the electrodes on the front and rear boards face each other, and their peripheries are hermetically sealed.
- Discharge gas such as neon (Ne)-xenon (Xe) is injected into the discharge space created by the barrier ribs at pressures of 400 ⁇ 600 torr.
- the discharge gas is discharged by selectively applying video signal voltages to the display electrodes.
- Ultraviolet rays emitted by the discharge gas excite the different color phosphor layers. Red, green, and blue light is thus emitted to display color images.
- a wiring lead-out of display electrodes on the front board and address electrodes on the rear board are provided on respective boards in the same plane, and a flexible printed circuit board (FPC) is press-bonded on the lead-out via an anisotropic conductive member to connect to external wiring.
- FPC flexible printed circuit board
- One example of a PDP in which these electrodes have a multilayer structure on each board by interposing an insulating layer with a predetermined thickness is disclosed in Japanese Laid-open Patent No. 2 001-210243.
- the electrode wiring layer on the front board has scanning electrodes and susutain electrodes as the first electrode layer, and trigger electrodes separated by the dielectric layer as the second electrode layer.
- the wiring lead-out is provided on the four sides which are the periphery of the PDP, and the electrodes are disposed in such a way that the potential applied to the wiring lead-out on each side is uniform. Accordingly, the wiring lead-out on each side is provided in the same plane to avoid coupling failure between the wiring lead-out and the FPC while press-bonding the FPC onto each side.
- the electrode wiring in the second layer is disposed in such a way as to cross the step of insulating layer at the wiring lead-out. This makes the thickness of electrode wiring on the second layer thinner at this step, resulting in increasing the wiring resistance or causing disconnection.
- the present invention aims to offer a highly reliable PDP by stabilizing the characteristics of the electrode wiring at the wiring lead-out even if the electrodes formed on the boards have a multilayer structure and their applied potential differs.
- a PDP of the present invention includes a front board having the first electrode that at least acts as a display electrode, and a rear board having the second electrode which at least acts as a data electrode and create a discharge space with the front board.
- the periphery of the front board and rear board is sealed to configure the PDP.
- the third electrode is disposed on the first electrode or second electrode with the dielectric layer in between.
- a lead-out of the first or second electrode to external wiring and a lead-out of the third electrode to external wiring are provided with a step equivalent to the thickness of the dielectric layer.
- FIG. 1 is a sectional view of a PDP in accordance with the first exemplary embodiment of the present invention.
- FIG. 2 is a perspective view of a rear board of the PDP in accordance with the first exemplary embodiment of the present invention.
- FIG. 3 is a plan view of the rear board of the PDP in accordance with the first exemplary embodiment of the present invention.
- FIG. 4 is a sectional view taken along A-A in FIG. 3 .
- FIG. 5 is a plan view of a sealed PDP in accordance with the first exemplary embodiment of the present invention.
- FIG. 6 is a sectional view of a structure in which an FPC is connected to a wiring lead-out of the PDP in accordance with the first exemplary embodiment of the present invention.
- FIG. 7A is a plan view illustrating a structure of the wiring lead-out of the PDP in accordance with the first exemplary embodiment of the present invention.
- FIG. 7B is a sectional view taken along C-C in FIG. 7A .
- FIG. 8A is a plan view illustrating a structure of a wiring lead-out of a PDP in accordance with the second exemplary embodiment of the present invention.
- FIG. 8B is a sectional view taken along D-D in FIG. 8A .
- FIG. 9A is a plan view of a structure illustrating a wiring lead-out of a PDP in accordance with the third exemplary embodiment.
- FIG. 9B is a sectional view taken along E-E in FIG. 9A .
- FIG. 10A is a plan view illustrating a structure of a wiring lead-out of a PDP in the fourth exemplary embodiment of the present invention.
- FIG. 10B is a sectional view taken along F-F in FIG. 10A .
- FIG. 11 is a sectional view of a PDP in the fifth exemplary embodiment of the present invention.
- FIG. 12A is a plan view of a structure of a wiring lead-out member of the PDP in accordance with the fifth exemplary embodiment of the present invention.
- FIG. 13A is a plan view of a structure of the wiring lead-out when electrodes are disposed on a different level.
- FIG. 13B is a sectional view taken along B-B in FIG. 13A .
- FIG. 1 shows a sectional view of a PDP in the first exemplary embodiment of the present invention.
- FIG. 2 is a perspective view of a rear board of the PDP in the first exemplary embodiment of the present invention.
- front board 1 and rear board 2 face each other with discharge space 3 in between. Gases such as neon (Ne) and xenon (Xe) are injected into this discharge space 3 and emit ultraviolet rays when subjected to electric discharge.
- the first electrode which acts as a display electrode, includes stripes of a pair of scanning electrodes 6 and susutain electrodes 7 aligned in parallel and covered with dielectric layer 4 and protective film 5 , and is disposed on front substrate 100 . These scanning electrodes 6 and susutain electrodes 7 are configured, respectively, with transparent electrodes 6 a and 7 a, and metal bus lines 6 b and 7 b, made such as of silver (Ag) for better conductivity.
- Metal bus lines 6 b and 7 b are overlaid on transparent electrodes 6 a and 7 a.
- scanning electrodes 6 and susutain electrodes 7 are alternately aligned in two rows each such as scanning electrode 6 -scanning electrode 6 -susutain electrode 7 -susutain electrode 7 , and so on.
- Optical absorption film 8 made of black material is provided between rows of scanning electrodes 6 and between rows of susutain electrodes 7 .
- stripes of data electrodes are disposed in parallel to each other on rear substrate 200 of rear board 2 as the second electrode in a direction perpendicular to scanning electrodes 6 and susutain electrodes 7 .
- barrier ribs 10 for dividing discharge cells formed with scanning electrodes 6 , susutain electrodes 7 , and data electrodes 9 are formed on rear board 2 .
- Phosphor layer 12 corresponding to each discharge cell is formed on cell space 11 divided by barrier ribs 10 .
- Barrier ribs 10 create cell space 11 with vertical wall 10 a stretching so as to intersect at right angles with scanning electrodes 6 and susutain electrodes 7 on front board 1 , i.e., parallel to data electrode 9 ; and horizontal wall 10 b crossing this vertical wall 10 a. Horizontal wall 10 b also creates gap 13 between cell spaces 11 .
- Optical absorption film 8 formed on front board 1 is disposed at positions corresponding to space in gap 13 formed between horizontal walls 10 b of barrier rib 10 .
- priming electrode 14 In gap 13 of rear board 2 , priming electrode 14 , the third electrode, for triggering a discharge in the space of this gap 13 between front board 1 and rear board 2 is formed intersecting at right angles with data electrode 9 . A priming cell is thus formed in gap 13 .
- This priming electrode 14 is formed on dielectric layer 15 covering data electrode 9 , and dielectric layer 16 is further formed to cover priming electrode 14 . Accordingly, priming electrode 14 is formed in a position closer to the space of gap 13 than data electrode 9 .
- priming electrode 14 is formed only at the position of gap 13 opposing adjacent scanning electrodes 6 to which a scanning pulse is applied.
- a part of metal bus line 6 b of scanning electrode 6 extends to the position corresponding to gap 13 , and is formed on optical absorption film 8 .
- priming discharge occurs between metal bus line 6 b protruding toward area of gap 13 and priming electrode 14 formed on rear board 2 .
- front board 1 and rear board 2 face each other such that data electrode 9 and scanning electrode 6 , and susutain electrode 7 intersect at right angles; and their peripheries are hermetically sealed.
- discharge spaces 17 R, 17 G and 17 B for red, green and blue are created, and phosphor layer 12 of each color is formed on the wall of each discharge space.
- Discharge gases such as neon (Ne)-Xenon (Xe) are injected under a pressure of 400 ⁇ 600 torr. Discharge gas is discharged by selectively applying the video signal voltage to the scanning electrodes 6 and susutain electrodes 7 .
- the ultraviolet rays emitted excite phosphor layer 12 of each color, and a color image is displayed when the phosphor emits red, green and blue colors.
- priming discharge takes place in gap 13 so as to reduce discharge delay in writing. This realizes a PDP achieving a stable address characteristic, such as in a high-definition panel.
- FIG. 3 shows a plan view of rear board 2 of the PDP in the first exemplary embodiment of the present invention
- FIG. 4 shows a sectional view taken along A-A in FIG. 3
- Priming electrode 14 the third electrode, indicated by the broken line in FIG. 3 , is formed only at gap 13 , corresponding to adjacent scanning electrodes 6 to which a scanning pulse is applied, and the same potential is applied within the face of the PDP. This potential is different from that given to scanning electrodes 6 and susutain electrodes 7 configuring the first electrode and data electrodes 9 configuring the second electrode.
- wiring lead-out 18 of priming electrode 14 is provided at the four comers of rear board 2 , and dielectric layer 16 covers priming electrode 14 except for these wiring lead-outs 18 .
- Dielectric layer 15 covers data electrodes 9 except for their wiring lead-outs 19 . Accordingly, as shown in FIG. 4 , wiring lead-outs 18 and wiring lead-outs 19 have step 20 , equivalent to the film thickness of dielectric layer 15 .
- FIG. 5 shows a plan view of a PDP in which front board 1 and rear board 2 are sealed, seen from the side of front board 1 .
- Wiring lead-outs 19 of data electrodes 9 are provided at upper edge 22 and lower edge 21 of rear board 2 in several blocks.
- FIG. 6 shows a sectional view of a part where FP C 23 for connecting to external wiring is attached to wiring lead-out 19 of data electrode 9 when lead-out electrodes are in the same plane.
- FPC 23 has multiple wiring patterns 25 , made such as of copper foil, formed on resin base film 24 that acts as a flexible insulator such as polyimide. A connecting portion at the end of wiring pattern 25 is exposed and the other portion of wiring pattern 25 is covered with resin cover film 26 such as polyimide.
- Wiring pattern 25 is connected to data electrode 9 of wiring lead-out 19 via anisotropic conductive material 27 , and its periphery is covered with adhesive 28 .
- Anisotropic conductive material 27 is made by dispersing conductive particles such as nickel (Ni) in an insulating material.
- anisotropic conductive material 27 shows no conductivity as it is, connection is established when conductive particles bond in the space between data electrode 9 and wiring patterns 25 as a result of sandwiching conductive particles between rear board 2 and FPC 23 , and intensely compressing the insulating material by means of thermal pressing.
- FIG. 13A is a plan view illustrating a wiring lead-out structure for leading out the electrode when a step exists between the electrodes in the PDP.
- FIG. 13B is a sectional view taken along B-B in FIG. 13A .
- data electrode 9 and priming electrode 14 are provided in the same plane at the wiring lead-outs so as to simplify process including press-bonding of the FPC. More specifically, dielectric layer 15 is provided on rear substrate 200 and priming electrode 14 is disposed on dielectric layer 15 , but wiring of priming electrode 14 and wiring of data electrode 9 are led out in the same plane of rear substrate 200 at the edge of rear substrate 200 .
- priming electrode 14 has step 40 equivalent to the thickness of dielectric layer 15 . If the electrode wiring is stepped, the wiring thickness differs at the step, increasing wiring resistance at the thinned portion. This results in an inability to drive signals at high speed due to significant delay in carrying the signals. Accordingly, this step becomes a major obstacle to increasing pixel density to achieve higher-definition PDPs. In addition, such step likely to cause disconnection of electrodes, significantly reducing reliability.
- FIGS. 7A and 7B show the detailed structure of the wiring lead-out of the PDP shown in FIGS. 3 and 4 in the first exemplary embodiment.
- FIG. 7A is a plan view
- FIG. 7B is a sectional view taken along C-C in FIG. 7A .
- wiring lead-out 18 of priming electrode 14 is formed on dielectric layer 15 .
- the level of wiring lead-out 19 of data electrode 9 and wiring lead-out 18 of priming electrode 14 is different for step 20 equivalent to the thickness of dielectric layer 15 , as shown in FIG. 4 .
- data electrode 9 is connected to the FPC and priming electrode 14 is connected to the FPC at a different level, equivalent to step 20 .
- Priming electrode 14 the third electrode in the present invention, is an electrode that gives the same potential in the PDP face. This potential is different from that of other electrodes. This means that the function of priming electrode 14 is achievable with at least one wiring lead-out 18 , although wiring lead-out 18 is provided at the four comers in FIG. 3 .
- the FPC connection to wiring lead-out 19 of data electrode 9 can thus be established in a separate process. Accordingly, priming electrode 14 can be formed in the same plane, eliminating stepped electrode wiring and allowing signals to be driven at high speed.
- failures such as disconnection due to variable wiring thickness of electrodes and degradation by heat generated due to high wiring resistance can be reduced, making feasible a PDP with highly reliable wiring.
- the wiring lead-out direction of priming electrode 14 and the wiring lead-out direction of data electrode 9 are the same, but are not necessarily leading in the same direction, depending on the pattern of dielectric layer 15 .
- FIGS. 8A and 8B show details of a structure of a wiring lead-out of a PDP in the second exemplary embodiment of the present invention.
- FIG. 8A is a plan view
- FIG. 8B is a sectional view taken along D-D in FIG. 8A .
- slope 31 is provided in the wiring lead-out area of priming electrode 14 .
- the film thickness of dielectric layer 15 gradually reduces in a slope toward the edge of rear substrate 200 , and wiring lead-out 29 is formed on rear substrate 200 . Accordingly, priming electrode 14 and data electrode 9 are in the same plane at wiring lead-out 29 connected to the FPC.
- the thickness of dielectric layer 15 is gradually reduced in the wiring lead-out area of priming electrode 14 such that there is no effect of reduced thickness or line width of priming electrode 14 that is formed on dielectric layer 15 .
- connection to the FPC is established in the same plane as wiring lead-out 19 of data electrode 9 . This allows connection of priming electrode 14 to the FPC and connection of data electrode 9 to the FPC in the same process, simplifying the manufacturing process.
- provision of priming electrode 14 and data electrode 9 in the same plane allows sharing of the wiring FPC between priming electrode 14 and data electrode 9 .
- the thickness of dielectric layer 15 can be reduced step by step or linearly as long as the thickness is changed in a way such that to eliminate any non-uniformity in electrode thickness and line width when forming priming electrode 14 on dielectric layer 15 .
- FIGS. 9A and 9B show the details of a structure of wiring lead-out of a PDP in the third exemplary embodiment.
- FIG. 9A is a plan view
- FIG. 9B is a sectional view taken along E-E in FIG. 9A .
- priming electrode wiring 33 formed on rear substrate 200 in advance and priming electrode 14 formed on dielectric layer 15 are connected by via hole 32 created on dielectric layer 15 .
- This via hole is filled with conductive material. Accordingly, wiring lead-out 30 to be connected to the FPC is formed in the same plane as data electrode 9 .
- Via hole 32 is created such as by laser beam after forming dielectric layer 15 , and the conductive material is injected into via hole 32 .
- This method secures the wiring reliability of priming electrode 14 .
- connection to the FPC is established in the same plane as wiring lead-out 19 of data electrode 9 . This allows wiring to be carried out in the same process as connection of the FPC to data electrode 9 , simplifying the manufacturing process.
- FIGS. 10A and 10B show details of the structure of a wiring lead-out in the fourth exemplary embodiment of the present invention.
- FIG. 10A is a plan view illustrating the structure of a rear board
- FIG. 10B is a sectional view taken along F-F in FIG. 10A .
- priming electrode 14 includes vertical priming electrode 34 and horizontal priming electrode 35 .
- Vertical priming electrode 34 also acts as wiring lead-out of priming electrode 14 .
- Vertical priming electrode 34 is formed on rear substrate 200 , same as data electrode 9
- horizontal priming electrode 35 is formed on dielectric layer 15 .
- a dielectric layer can be further formed on horizontal priming electrode 35 .
- Via hole 36 is created on dielectric layer 15 at crossing of vertical priming electrode 34 and horizontal priming electrode 35 . Conductive material is injected into via hole 36 to secure mutual conductivity.
- the above structure enables formation of vertical priming electrode 34 at the same time as forming data electrode 9 on rear substrate 200 .
- wiring lead-out 18 of priming electrode 14 can be connected to the FPC in the same plane as wiring lead-out 19 of data electrode 9 . Accordingly, this connection can be established in the same process as connection of data electrode 9 to the FPC, thus simplifying the process.
- FIG. 11 is a sectional view of a PDP in the fifth exemplary embodiment of the present invention.
- the structures of data electrode 9 , i.e., the second electrode, and priming electrode 14 , i.e., the third electrode, formed on rear substrate 200 differ from those in the first exemplary embodiment.
- priming electrode 14 is first formed on rear substrate 200 .
- Dielectric layer 15 is then provided covering priming electrode 14 .
- Data electrode 9 is then disposed on dielectric layer 15 .
- dielectric layer 16 that also acts as a base for forming barrier ribs is provided covering data electrode 9 .
- Barrier rib 10 is formed on this dielectric layer 16 .
- the fifth exemplary embodiment has a different structure for rear substrate 200 , but the same structure as the first exemplary embodiment for front substrate 100 .
- the fifth exemplary embodiment has data electrode 9 formed closer to discharge space 3 than priming electrode 14 .
- This allows a thinner dielectric layer 16 to be formed on data electrode 9 , enabling lower voltage during write discharge. Write discharge can thus be stabilized.
- Dielectric layer 15 formed on priming electrode 14 , is a dielectric layer between priming electrode 14 and data electrode 9 , and any material at any thickness can be applied to secure insulation between priming electrode 14 and data electrode 9 .
- the structure described in the first to fourth exemplary embodiments is applicable to the structure of wiring lead-out 18 of priming electrode 14 and wiring lead-out 19 of data electrode 9 in the fifth exemplary embodiment.
- the positions of priming electrode 14 and data electrode 9 in the fifth embodiment are upside down with respect to dielectric layer 15 .
- FIGS. 12A and 12B the structure of the wiring lead-out identical to that described in the first exemplary embodiment is shown in FIGS. 12A and 12B .
- wiring lead-out 18 of priming electrode 14 is provided on dielectric layer 15 .
- wiring lead-out 50 of data electrode 9 is provided on dielectric layer 15
- wiring lead-out 51 of priming electrode 14 is provided on rear substrate 200 . Accordingly, a PDP with highly reliable wiring can be realized by securing stable wiring even though the positions of data electrode 9 and priming electrode 14 are reversed.
- dielectric layer 15 or dielectric layer 16 has a patterned shape at the wiring lead-out. This pattern can be formed using known methods including screen-printing and photo etching.
- the above exemplary embodiments refer to the case of the two-layer electrode on the rear board. It is apparent, however, the structure of the present invention is not limited to the rear board. Naturally, the wiring lead-out structure of the present invention is also applicable to a multilayer structure of two or more layers for the front board or for both front and rear boards.
- the present invention employs a structure without a step in the electrode wiring at the wiring lead-out of the PDP. This eliminates variations in the wiring thickness of the electrode, and problems deriving from the resultant high wiring resistance. Accordingly, a highly reliable PDP suitable for a large-screen display device is achieved.
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Abstract
Description
- The present invention relates to plasma display panels, and more particularly to plasma display panels achieving highly reliable connections in multilayer electrode wiring.
- Plasma display devices employing plasma display panels (PDPs) are drawing increasing attention as display devices for high-definition television images on large screens.
- A PDP is basically composed of front and rear boards. The front board includes a glass substrate, display electrodes including transparent electrodes and bus electrodes aligned in stripes on one main face of the glass substrate, a dielectric layer covering the display electrodes that functions as a capacitor, and a dielectric protective film formed on the dielectric layer. The rear board includes a glass substrate, address electrodes aligned in stripes on one main face, a dielectric layer covering the address electrodes, barrier ribs formed on the dielectric layer, and a phosphor layer which emits red, green, and blue lights formed between barrier ribs.
- The electrodes on the front and rear boards face each other, and their peripheries are hermetically sealed. Discharge gas such as neon (Ne)-xenon (Xe) is injected into the discharge space created by the barrier ribs at pressures of 400˜600 torr. The discharge gas is discharged by selectively applying video signal voltages to the display electrodes. Ultraviolet rays emitted by the discharge gas excite the different color phosphor layers. Red, green, and blue light is thus emitted to display color images.
- A wiring lead-out of display electrodes on the front board and address electrodes on the rear board are provided on respective boards in the same plane, and a flexible printed circuit board (FPC) is press-bonded on the lead-out via an anisotropic conductive member to connect to external wiring. One example of a PDP in which these electrodes have a multilayer structure on each board by interposing an insulating layer with a predetermined thickness is disclosed in Japanese Laid-open Patent No. 2 001-210243. In this example, the electrode wiring layer on the front board has scanning electrodes and susutain electrodes as the first electrode layer, and trigger electrodes separated by the dielectric layer as the second electrode layer.
- In this method of press-bonding the FPC onto the wiring lead-out via the anisotropic conductive member for coupling the wiring lead-out to the external wiring, the wiring lead-out is provided on the four sides which are the periphery of the PDP, and the electrodes are disposed in such a way that the potential applied to the wiring lead-out on each side is uniform. Accordingly, the wiring lead-out on each side is provided in the same plane to avoid coupling failure between the wiring lead-out and the FPC while press-bonding the FPC onto each side. If electrodes are given a multilayer structure by interposing the insulating layer, in addition to providing wiring lead-outs in such a way that the potential applied to each side is uniform, the electrode wiring in the second layer is disposed in such a way as to cross the step of insulating layer at the wiring lead-out. This makes the thickness of electrode wiring on the second layer thinner at this step, resulting in increasing the wiring resistance or causing disconnection.
- The present invention aims to offer a highly reliable PDP by stabilizing the characteristics of the electrode wiring at the wiring lead-out even if the electrodes formed on the boards have a multilayer structure and their applied potential differs.
- A PDP of the present invention includes a front board having the first electrode that at least acts as a display electrode, and a rear board having the second electrode which at least acts as a data electrode and create a discharge space with the front board. The periphery of the front board and rear board is sealed to configure the PDP. The third electrode is disposed on the first electrode or second electrode with the dielectric layer in between. A lead-out of the first or second electrode to external wiring and a lead-out of the third electrode to external wiring are provided with a step equivalent to the thickness of the dielectric layer.
- The above configuration allows the formation of each electrode in the same plane up to the wiring lead-out. This results in stable electrode wiring characteristics at the wiring lead-out, making feasible a highly reliable PDP.
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FIG. 1 is a sectional view of a PDP in accordance with the first exemplary embodiment of the present invention. -
FIG. 2 is a perspective view of a rear board of the PDP in accordance with the first exemplary embodiment of the present invention. -
FIG. 3 is a plan view of the rear board of the PDP in accordance with the first exemplary embodiment of the present invention. -
FIG. 4 is a sectional view taken along A-A inFIG. 3 . -
FIG. 5 is a plan view of a sealed PDP in accordance with the first exemplary embodiment of the present invention. -
FIG. 6 is a sectional view of a structure in which an FPC is connected to a wiring lead-out of the PDP in accordance with the first exemplary embodiment of the present invention. -
FIG. 7A is a plan view illustrating a structure of the wiring lead-out of the PDP in accordance with the first exemplary embodiment of the present invention. -
FIG. 7B is a sectional view taken along C-C inFIG. 7A . -
FIG. 8A is a plan view illustrating a structure of a wiring lead-out of a PDP in accordance with the second exemplary embodiment of the present invention. -
FIG. 8B is a sectional view taken along D-D inFIG. 8A . -
FIG. 9A is a plan view of a structure illustrating a wiring lead-out of a PDP in accordance with the third exemplary embodiment. -
FIG. 9B is a sectional view taken along E-E inFIG. 9A . -
FIG. 10A is a plan view illustrating a structure of a wiring lead-out of a PDP in the fourth exemplary embodiment of the present invention. -
FIG. 10B is a sectional view taken along F-F inFIG. 10A . -
FIG. 11 is a sectional view of a PDP in the fifth exemplary embodiment of the present invention. -
FIG. 12A is a plan view of a structure of a wiring lead-out member of the PDP in accordance with the fifth exemplary embodiment of the present invention. -
FIG. 13A is a plan view of a structure of the wiring lead-out when electrodes are disposed on a different level. -
FIG. 13B is a sectional view taken along B-B inFIG. 13A . - Preferred embodiments of the present invention are described below with reference to drawings.
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FIG. 1 shows a sectional view of a PDP in the first exemplary embodiment of the present invention.FIG. 2 is a perspective view of a rear board of the PDP in the first exemplary embodiment of the present invention. - As shown in
FIG. 1 ,front board 1 andrear board 2 face each other withdischarge space 3 in between. Gases such as neon (Ne) and xenon (Xe) are injected into thisdischarge space 3 and emit ultraviolet rays when subjected to electric discharge. The first electrode, which acts as a display electrode, includes stripes of a pair ofscanning electrodes 6 andsusutain electrodes 7 aligned in parallel and covered withdielectric layer 4 andprotective film 5, and is disposed onfront substrate 100. Thesescanning electrodes 6 andsusutain electrodes 7 are configured, respectively, withtransparent electrodes metal bus lines Metal bus lines transparent electrodes scanning electrodes 6 andsusutain electrodes 7 are alternately aligned in two rows each such as scanning electrode 6-scanning electrode 6-susutain electrode 7-susutain electrode 7, and so on.Optical absorption film 8 made of black material is provided between rows ofscanning electrodes 6 and between rows ofsusutain electrodes 7. - As shown in
FIGS. 1 and 2 , stripes of data electrodes are disposed in parallel to each other onrear substrate 200 ofrear board 2 as the second electrode in a direction perpendicular toscanning electrodes 6 andsusutain electrodes 7. Moreover,barrier ribs 10 for dividing discharge cells formed withscanning electrodes 6,susutain electrodes 7, anddata electrodes 9 are formed onrear board 2.Phosphor layer 12 corresponding to each discharge cell is formed oncell space 11 divided bybarrier ribs 10.Barrier ribs 10 createcell space 11 withvertical wall 10 a stretching so as to intersect at right angles withscanning electrodes 6 andsusutain electrodes 7 onfront board 1, i.e., parallel todata electrode 9; andhorizontal wall 10 b crossing thisvertical wall 10 a.Horizontal wall 10 b also createsgap 13 betweencell spaces 11.Optical absorption film 8 formed onfront board 1 is disposed at positions corresponding to space ingap 13 formed betweenhorizontal walls 10 b ofbarrier rib 10. - In
gap 13 ofrear board 2, primingelectrode 14, the third electrode, for triggering a discharge in the space of thisgap 13 betweenfront board 1 andrear board 2 is formed intersecting at right angles withdata electrode 9. A priming cell is thus formed ingap 13. This primingelectrode 14 is formed ondielectric layer 15covering data electrode 9, anddielectric layer 16 is further formed to coverpriming electrode 14. Accordingly, primingelectrode 14 is formed in a position closer to the space ofgap 13 thandata electrode 9. In addition, primingelectrode 14 is formed only at the position ofgap 13 opposingadjacent scanning electrodes 6 to which a scanning pulse is applied. A part ofmetal bus line 6 b ofscanning electrode 6 extends to the position corresponding to gap 13, and is formed onoptical absorption film 8. In other words, priming discharge occurs betweenmetal bus line 6 b protruding toward area ofgap 13 andpriming electrode 14 formed onrear board 2. - In the PDP,
front board 1 andrear board 2 face each other such thatdata electrode 9 andscanning electrode 6, andsusutain electrode 7 intersect at right angles; and their peripheries are hermetically sealed. Incell space 11 formed bybarrier rib 10,discharge spaces phosphor layer 12 of each color is formed on the wall of each discharge space. Discharge gases such as neon (Ne)-Xenon (Xe) are injected under a pressure of 400˜600 torr. Discharge gas is discharged by selectively applying the video signal voltage to thescanning electrodes 6 andsusutain electrodes 7. As a result, the ultraviolet rays emitted excitephosphor layer 12 of each color, and a color image is displayed when the phosphor emits red, green and blue colors. Moreover, in the PDP in this exemplary embodiment, priming discharge takes place ingap 13 so as to reduce discharge delay in writing. This realizes a PDP achieving a stable address characteristic, such as in a high-definition panel. -
FIG. 3 shows a plan view ofrear board 2 of the PDP in the first exemplary embodiment of the present invention, andFIG. 4 shows a sectional view taken along A-A inFIG. 3 . Primingelectrode 14, the third electrode, indicated by the broken line inFIG. 3 , is formed only atgap 13, corresponding toadjacent scanning electrodes 6 to which a scanning pulse is applied, and the same potential is applied within the face of the PDP. This potential is different from that given toscanning electrodes 6 andsusutain electrodes 7 configuring the first electrode anddata electrodes 9 configuring the second electrode. Moreover, wiring lead-out 18 of primingelectrode 14 is provided at the four comers ofrear board 2, anddielectric layer 16covers priming electrode 14 except for these wiring lead-outs 18.Dielectric layer 15 coversdata electrodes 9 except for their wiring lead-outs 19. Accordingly, as shown inFIG. 4 , wiring lead-outs 18 and wiring lead-outs 19 havestep 20, equivalent to the film thickness ofdielectric layer 15. - On the other hand,
scanning electrodes 6,susutain electrodes 7, anddata electrodes 9 of the PDP are connected to an electric circuit for driving and controlling electrodes using an FPC.FIG. 5 shows a plan view of a PDP in whichfront board 1 andrear board 2 are sealed, seen from the side offront board 1. Wiring lead-outs 19 ofdata electrodes 9 are provided atupper edge 22 andlower edge 21 ofrear board 2 in several blocks. -
FIG. 6 shows a sectional view of a part whereFP C 23 for connecting to external wiring is attached to wiring lead-out 19 ofdata electrode 9 when lead-out electrodes are in the same plane.FPC 23 hasmultiple wiring patterns 25, made such as of copper foil, formed onresin base film 24 that acts as a flexible insulator such as polyimide. A connecting portion at the end ofwiring pattern 25 is exposed and the other portion ofwiring pattern 25 is covered withresin cover film 26 such as polyimide.Wiring pattern 25 is connected todata electrode 9 of wiring lead-out 19 via anisotropicconductive material 27, and its periphery is covered with adhesive 28. Anisotropicconductive material 27 is made by dispersing conductive particles such as nickel (Ni) in an insulating material. Although anisotropicconductive material 27 shows no conductivity as it is, connection is established when conductive particles bond in the space betweendata electrode 9 andwiring patterns 25 as a result of sandwiching conductive particles betweenrear board 2 andFPC 23, and intensely compressing the insulating material by means of thermal pressing. -
FIG. 13A is a plan view illustrating a wiring lead-out structure for leading out the electrode when a step exists between the electrodes in the PDP.FIG. 13B is a sectional view taken along B-B inFIG. 13A . One of the four comers shown in the plan view ofrear board 2 inFIG. 3 is magnified. As shown inFIGS. 13A and 13B ,data electrode 9 andpriming electrode 14 are provided in the same plane at the wiring lead-outs so as to simplify process including press-bonding of the FPC. More specifically,dielectric layer 15 is provided onrear substrate 200 and primingelectrode 14 is disposed ondielectric layer 15, but wiring of primingelectrode 14 and wiring ofdata electrode 9 are led out in the same plane ofrear substrate 200 at the edge ofrear substrate 200. - In this case, priming
electrode 14 hasstep 40 equivalent to the thickness ofdielectric layer 15. If the electrode wiring is stepped, the wiring thickness differs at the step, increasing wiring resistance at the thinned portion. This results in an inability to drive signals at high speed due to significant delay in carrying the signals. Accordingly, this step becomes a major obstacle to increasing pixel density to achieve higher-definition PDPs. In addition, such step likely to cause disconnection of electrodes, significantly reducing reliability. -
FIGS. 7A and 7B show the detailed structure of the wiring lead-out of the PDP shown inFIGS. 3 and 4 in the first exemplary embodiment.FIG. 7A is a plan view, andFIG. 7B is a sectional view taken along C-C inFIG. 7A . In the first exemplary embodiment, wiring lead-out 18 of primingelectrode 14 is formed ondielectric layer 15. In other words, the level of wiring lead-out 19 ofdata electrode 9 and wiring lead-out 18 of primingelectrode 14 is different forstep 20 equivalent to the thickness ofdielectric layer 15, as shown inFIG. 4 . Accordingly,data electrode 9 is connected to the FPC and primingelectrode 14 is connected to the FPC at a different level, equivalent to step 20. - Priming
electrode 14, the third electrode in the present invention, is an electrode that gives the same potential in the PDP face. This potential is different from that of other electrodes. This means that the function of primingelectrode 14 is achievable with at least one wiring lead-out 18, although wiring lead-out 18 is provided at the four comers inFIG. 3 . The FPC connection to wiring lead-out 19 ofdata electrode 9 can thus be established in a separate process. Accordingly, primingelectrode 14 can be formed in the same plane, eliminating stepped electrode wiring and allowing signals to be driven at high speed. In addition, failures such as disconnection due to variable wiring thickness of electrodes and degradation by heat generated due to high wiring resistance can be reduced, making feasible a PDP with highly reliable wiring. - In the first exemplary embodiment, the wiring lead-out direction of priming
electrode 14 and the wiring lead-out direction ofdata electrode 9 are the same, but are not necessarily leading in the same direction, depending on the pattern ofdielectric layer 15. -
FIGS. 8A and 8B show details of a structure of a wiring lead-out of a PDP in the second exemplary embodiment of the present invention.FIG. 8A is a plan view, andFIG. 8B is a sectional view taken along D-D inFIG. 8A . - In the second exemplary embodiment,
slope 31 is provided in the wiring lead-out area of primingelectrode 14. In thisslope 31, the film thickness ofdielectric layer 15 gradually reduces in a slope toward the edge ofrear substrate 200, and wiring lead-out 29 is formed onrear substrate 200. Accordingly, primingelectrode 14 anddata electrode 9 are in the same plane at wiring lead-out 29 connected to the FPC. - As described above, the thickness of
dielectric layer 15 is gradually reduced in the wiring lead-out area of primingelectrode 14 such that there is no effect of reduced thickness or line width of primingelectrode 14 that is formed ondielectric layer 15. This secures the reliability of wiring of primingelectrode 14. Moreover, connection to the FPC is established in the same plane as wiring lead-out 19 ofdata electrode 9. This allows connection of primingelectrode 14 to the FPC and connection ofdata electrode 9 to the FPC in the same process, simplifying the manufacturing process. Furthermore, provision of primingelectrode 14 anddata electrode 9 in the same plane allows sharing of the wiring FPC between primingelectrode 14 anddata electrode 9. - The thickness of
dielectric layer 15 can be reduced step by step or linearly as long as the thickness is changed in a way such that to eliminate any non-uniformity in electrode thickness and line width when formingpriming electrode 14 ondielectric layer 15. -
FIGS. 9A and 9B show the details of a structure of wiring lead-out of a PDP in the third exemplary embodiment.FIG. 9A is a plan view, andFIG. 9B is a sectional view taken along E-E inFIG. 9A . - In the third exemplary embodiment, priming
electrode wiring 33 formed onrear substrate 200 in advance and primingelectrode 14 formed ondielectric layer 15 are connected by viahole 32 created ondielectric layer 15. This via hole is filled with conductive material. Accordingly, wiring lead-out 30 to be connected to the FPC is formed in the same plane asdata electrode 9. - Via
hole 32 is created such as by laser beam after formingdielectric layer 15, and the conductive material is injected into viahole 32. This method secures the wiring reliability of primingelectrode 14. In addition, connection to the FPC is established in the same plane as wiring lead-out 19 ofdata electrode 9. This allows wiring to be carried out in the same process as connection of the FPC todata electrode 9, simplifying the manufacturing process. -
FIGS. 10A and 10B show details of the structure of a wiring lead-out in the fourth exemplary embodiment of the present invention.FIG. 10A is a plan view illustrating the structure of a rear board, andFIG. 10B is a sectional view taken along F-F inFIG. 10A . - As shown in
FIGS. 10A and 10B , primingelectrode 14 includesvertical priming electrode 34 andhorizontal priming electrode 35.Vertical priming electrode 34 also acts as wiring lead-out of primingelectrode 14.Vertical priming electrode 34 is formed onrear substrate 200, same asdata electrode 9, andhorizontal priming electrode 35 is formed ondielectric layer 15. A dielectric layer can be further formed onhorizontal priming electrode 35. Viahole 36 is created ondielectric layer 15 at crossing ofvertical priming electrode 34 andhorizontal priming electrode 35. Conductive material is injected into viahole 36 to secure mutual conductivity. - The above structure enables formation of
vertical priming electrode 34 at the same time as formingdata electrode 9 onrear substrate 200. In addition, wiring lead-out 18 of primingelectrode 14 can be connected to the FPC in the same plane as wiring lead-out 19 ofdata electrode 9. Accordingly, this connection can be established in the same process as connection ofdata electrode 9 to the FPC, thus simplifying the process. -
FIG. 11 is a sectional view of a PDP in the fifth exemplary embodiment of the present invention. As shown inFIG. 11 , the structures ofdata electrode 9, i.e., the second electrode, and primingelectrode 14, i.e., the third electrode, formed onrear substrate 200 differ from those in the first exemplary embodiment. - More specifically, in the fifth exemplary embodiment, priming
electrode 14 is first formed onrear substrate 200.Dielectric layer 15 is then provided coveringpriming electrode 14.Data electrode 9 is then disposed ondielectric layer 15. Moreover,dielectric layer 16 that also acts as a base for forming barrier ribs is provided coveringdata electrode 9.Barrier rib 10 is formed on thisdielectric layer 16. As described above, the fifth exemplary embodiment has a different structure forrear substrate 200, but the same structure as the first exemplary embodiment forfront substrate 100. - Accordingly, the fifth exemplary embodiment has
data electrode 9 formed closer to dischargespace 3 than primingelectrode 14. This allows a thinnerdielectric layer 16 to be formed ondata electrode 9, enabling lower voltage during write discharge. Write discharge can thus be stabilized.Dielectric layer 15, formed on primingelectrode 14, is a dielectric layer between primingelectrode 14 anddata electrode 9, and any material at any thickness can be applied to secure insulation between primingelectrode 14 anddata electrode 9. - The structure described in the first to fourth exemplary embodiments is applicable to the structure of wiring lead-out 18 of priming
electrode 14 and wiring lead-out 19 ofdata electrode 9 in the fifth exemplary embodiment. However, the positions of primingelectrode 14 anddata electrode 9 in the fifth embodiment are upside down with respect todielectric layer 15. - As an example, the structure of the wiring lead-out identical to that described in the first exemplary embodiment is shown in
FIGS. 12A and 12B . In the structure of the first exemplary embodiment shown inFIGS. 7A and 7B , wiring lead-out 18 of primingelectrode 14 is provided ondielectric layer 15. However, in the fifth exemplary embodiment, wiring lead-out 50 ofdata electrode 9 is provided ondielectric layer 15, and wiring lead-out 51 of primingelectrode 14 is provided onrear substrate 200. Accordingly, a PDP with highly reliable wiring can be realized by securing stable wiring even though the positions ofdata electrode 9 andpriming electrode 14 are reversed. - In the above exemplary embodiments,
dielectric layer 15 ordielectric layer 16 has a patterned shape at the wiring lead-out. This pattern can be formed using known methods including screen-printing and photo etching. - Furthermore, the above exemplary embodiments refer to the case of the two-layer electrode on the rear board. It is apparent, however, the structure of the present invention is not limited to the rear board. Naturally, the wiring lead-out structure of the present invention is also applicable to a multilayer structure of two or more layers for the front board or for both front and rear boards.
- The present invention employs a structure without a step in the electrode wiring at the wiring lead-out of the PDP. This eliminates variations in the wiring thickness of the electrode, and problems deriving from the resultant high wiring resistance. Accordingly, a highly reliable PDP suitable for a large-screen display device is achieved.
Claims (9)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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JP2003042868 | 2003-02-20 | ||
JP2003-042868 | 2003-02-20 | ||
JP2003383551A JP4179138B2 (en) | 2003-02-20 | 2003-11-13 | Plasma display panel |
JP2003-383551 | 2003-11-13 | ||
PCT/JP2004/001811 WO2004075238A1 (en) | 2003-02-20 | 2004-02-18 | Plasma display panel |
Publications (2)
Publication Number | Publication Date |
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US20050151476A1 true US20050151476A1 (en) | 2005-07-14 |
US7084569B2 US7084569B2 (en) | 2006-08-01 |
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US10/512,580 Expired - Fee Related US7084569B2 (en) | 2003-02-20 | 2004-02-18 | Plasma display panel |
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US (1) | US7084569B2 (en) |
EP (1) | EP1505623B1 (en) |
JP (1) | JP4179138B2 (en) |
KR (1) | KR100647869B1 (en) |
CN (1) | CN1331182C (en) |
WO (1) | WO2004075238A1 (en) |
Cited By (4)
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US20050104807A1 (en) * | 2003-03-27 | 2005-05-19 | Hiroyuki Tachibana | Plasma display panel |
US20060103308A1 (en) * | 2004-11-12 | 2006-05-18 | Samsung Sdi Co., Ltd. | Plasma display panel |
US20070120484A1 (en) * | 2005-11-25 | 2007-05-31 | Lg Electronics Inc. | Plasma display panel |
US20070200500A1 (en) * | 2006-02-27 | 2007-08-30 | Samsung Techwin Co., Ltd. | Plasma display panel, method of manufacturing electrode burying dielectric wall of display panel and method of manufacturing electrode burying dielectric wall of the plasma display panel |
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JP4285039B2 (en) * | 2003-03-27 | 2009-06-24 | パナソニック株式会社 | Plasma display panel |
JP4285040B2 (en) * | 2003-03-27 | 2009-06-24 | パナソニック株式会社 | Plasma display panel |
JP4325244B2 (en) * | 2003-03-27 | 2009-09-02 | パナソニック株式会社 | Plasma display panel |
EP1715506B1 (en) * | 2005-04-20 | 2013-04-03 | Snu R & Db Foundation | High efficiency mercury-free flat light source structure, flat light source apparatus and driving method thereof |
JP4662350B2 (en) * | 2005-07-21 | 2011-03-30 | エプソンイメージングデバイス株式会社 | Liquid crystal display device and manufacturing method thereof |
KR100637237B1 (en) * | 2005-08-26 | 2006-10-20 | 삼성에스디아이 주식회사 | Plasma display panel |
KR100751375B1 (en) | 2006-03-15 | 2007-08-22 | 삼성에스디아이 주식회사 | Plasma display panel and flat display device therewith |
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Also Published As
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WO2004075238A1 (en) | 2004-09-02 |
EP1505623A4 (en) | 2008-10-01 |
KR20050019127A (en) | 2005-02-28 |
EP1505623A1 (en) | 2005-02-09 |
CN1331182C (en) | 2007-08-08 |
JP2004273425A (en) | 2004-09-30 |
EP1505623B1 (en) | 2011-08-10 |
US7084569B2 (en) | 2006-08-01 |
JP4179138B2 (en) | 2008-11-12 |
CN1698168A (en) | 2005-11-16 |
KR100647869B1 (en) | 2006-11-23 |
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