US20050144516A1 - Adaptive deterministic grouping of blocks into multi-block units - Google Patents
Adaptive deterministic grouping of blocks into multi-block units Download PDFInfo
- Publication number
- US20050144516A1 US20050144516A1 US10/750,157 US75015703A US2005144516A1 US 20050144516 A1 US20050144516 A1 US 20050144516A1 US 75015703 A US75015703 A US 75015703A US 2005144516 A1 US2005144516 A1 US 2005144516A1
- Authority
- US
- United States
- Prior art keywords
- metablock
- erase
- block
- blocks
- linkings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
Definitions
- This invention relates generally to semiconductor non-volatile data storage systems, and more specifically, to a system and method for forming physical blocks into larger logical structures that accommodate defects in non-volatile data storage systems.
- Nonvolatile memory devices such as flash memories are commonly used as mass data storage subsystems. Such nonvolatile memory devices are typically packaged in an enclosed card that is removably connected with a host system, and can also be packaged as the non-removable embedded storage within a host system.
- the subsystem includes one or more flash devices and often a subsystem controller.
- PCMCIA Personal Computer Memory Card International Association
- CF CompactFlash
- MMC MultiMediaCard
- SD Secure Digital
- MemoryStick MemoryStick-Pro
- PCMCIA Personal Computer Memory Card International Association
- CF CompactFlash
- MMC MultiMediaCard
- SD Secure Digital
- MemoryStick-Pro One supplier of these cards is SanDisk Corporation, assignee of this application.
- Host systems with which such cards are used include digital cameras, cellular phones, personal computers, notebook computers, hand held computing devices, audio reproducing devices, and the like.
- the nonvolatile memory devices themselves are composed of one or more arrays of nonvolatile storage elements. Each storage element is capable of storing one or more bits of data.
- One important characteristic of the nonvolatile memory array is that it retains the data programmed therein, even when power is no longer applied to the memory array. In contrast, a volatile memory device requires that the power to the array be refreshed periodically in order to preserve the data contained in the volatile memory array.
- Another characteristic of nonvolatile memory is that once a cell contained within a nonvolatile memory array is programmed, that cell must be erased before it can be reprogrammed with a new data value.
- the physical means for storing the charge in the memory cell can be implemented by using a floating gate transistor, such as an electrically erasable programmable read only memory (EEPROM).
- EEPROM electrically erasable programmable read only memory
- One known problem with floating gate devices such as EEPROMs is that the floating gate eventually wears out and breaks down after a very large number of write, program and erase cycles. When this happens, the cell is no longer usable and must be taken out of the list of available memory cells in the array. This sort of defect is called a “grown” defect. In one commercially available implementation, these defects are dealt with by mapping out the defective cells and substituting the physical addresses of good memory cells for the newly detected defective memory cells. Examples of implementations where defective cells or sectors are mapped out and replaced are described in U.S. Pat. No. 5,659,550 issued on Aug.
- Arrays of nonvolatile memory cells typically are partitioned into groups to provide for efficient implementation of read, program and erase functions. For example, in many nonvolatile memory architectures, the memory cells are arranged into a larger group called a unit of erase. This unit of erase is the smallest number of memory cells that are erasable at one time.
- the size of the unit of erase depends on the memory architecture that is being implemented. In earlier nonvolatile memories, the unit of erase was a block that was the same size as a standard 512-byte disk drive sector. In one commercial form, each block contained enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it was stored. In order to ensure that the blocks of cells were individually erasable, the blocks had to be sufficiently isolated from one another.
- the unit of erase is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data (unit of programming and/or reading).
- the unit of erase is a metablock.
- a metablock is a virtual unit of erase that is composed of multiple physical units of erase. These multiple physical units of erase can be used in parallel program and erase operations, but are addressed as a single logical block.
- metablocks or “super” blocks
- U.S. Pat. No. 6,034,897 which is expressly incorporated herein in its entirety by this reference.
- the same physical block in each of the devices is grouped into a metablock.
- this allows for the formation of metablocks and all of the blocks in a given metablock to be addressed by the same address, namely the address of the block in the first of the devices, it has a number of limitations.
- the linking of blocks into metablocks is pre-determined in this fixed configuration, when a block goes bad, the metablock to which it belongs becomes bad despite the other blocks within it still being functional.
- it is desirable goal to provide a system and method for an adaptable metablock arrangement without the operational overhead of establishing a new linking every time one is needed.
- a system for maintaining a defect map includes a defect map structure for tracking the existence of factory and grown defects in a nonvolatile memory system that is organized into metablocks.
- a method for maintaining a defect map makes use of the defect map structure and the characteristics of a metablock.
- the size of the defect map structure is equal to the parallelism of the nonvolatile memory system.
- the remaining units of erase that cannot be assigned to a metablock will be kept in a list of spare units of erase for later use.
- a record of the linking of blocks into metablocks is maintained in the non-volatile memory.
- the controller can then read out the linking into its volatile memory as needed.
- the record is updated in response to re-linkings resulting from defects.
- a complete linking record may be maintained in the non-volatile memory, for example in a specified location, or only a partial linking record may be maintained.
- an initial linking of blocks into metablocks is deterministically formed by an algorithm using, for example, a firmware based implementation. In this case, the linking record stored in the non-volatile memory need only contain the deviations from the standard algorithm.
- FIG. 1 is a block diagram of an existing nonvolatile memory system in which the nonvolatile memory array and the memory controller are packaged in an enclosed card that is removably connected with a host system.
- FIG. 2 is a block diagram of an existing nonvolatile memory system in which the nonvolatile memory array is packaged in an enclosed card that is removably connected with a host system.
- FIG. 3 is a block diagram of an existing nonvolatile memory system in which the nonvolatile memory array is packaged as non-removable embedded storage within a host system.
- FIGS. 4 b - d illustrate various linkings of physical blocks into metablocks.
- FIG. 11 illustrates an example of the mapping of the virtual structure elements of a metablock in response to the detection of a grown defect on a unit of erase.
- FIG. 12 illustrates an example of a system for maintaining a defect map, wherein a spare unit of erase is not available in the same plane as a unit of erase having a grown defect.
- FIG. 13 illustrates an example of a method for maintaining a defect map.
- FIG. 14 illustrates an example of a method for maintaining a defect map using the data structure of FIGS. 11-13 .
- FIGS. 15-18 illustrate an algorithmically based linking of physical blocks.
- FIGS. 19, 20 and 22 illustrate the re-linking of physical blocks.
- the memory system of the present invention maintains in its main non-volatile memory a record of the linking of blocks into multi-block metablock structures.
- This record contains a defect map of factory and grown defects in a map table that can be read into non-volatile memory on demand. This map is updated as grown defects are encountered and blocks are assigned to new locations.
- Metablocks are preferable formed by one block in each of several subarrays, or planes, and in this case, the grouping is done preferably with same-numbered blocks in each plane, with the exception of blocks that are marked bad and placed in the map. In one embodiment, the blocks are directly mapped to alternate blocks. Metablocks that would contain the defective block are then reformed with the alternate block in the corresponding plane.
- a “standard” linking can be based on an algorithm implanted, for example, in the system's firmware, with only the deviations due to defects from this algorithm needing to be stored. Those standard metablocks with no defects present will be termed usable standard metablocks. The remaining Metablocks are termed unusable standard metablocks, and the component physical blocks will be termed spare blocks.
- FIG. 1-3 are block diagrams of typical existing nonvolatile memory systems which include a host 102 , 202 , 302 , a controller 104 , 204 , 304 and a nonvolatile memory array or plurality of arrays 103 , 203 , 303 .
- the nonvolatile memory array 103 and the memory controller 104 are shown as being packaged in an enclosed card that is removably connected with a host system 102 .
- controller 204 is shown as being part of the host system 202 and the nonvolatile memory array 203 is shown as being packaged in an enclosed card that is removably connected with a host system.
- the nonvolatile memory array 303 is shown as being packaged as non-removable embedded storage within a host system 302 .
- the nonvolatile memory array includes memory cells that include one or more conductive floating gates as storage elements.
- the memory arrays could include other long-term electron charge storage elements instead, for example a charge trapping dielectric.
- a variety of nonvolatile storage elements can be used, including nonvolatile multi-state storage elements, storage elements that are Flash/EEPROM/floating gate, nonvolatile storage elements such as NROM, MNOS, MRAM/FRAM, NAND, NOR, and non-volatile storage elements that are organized into units of erasure.
- Non-volatile storage elements that store digital information, analog information or combinations of both can be used.
- the memory cell array can be operated with two levels of charge defined for each storage element to therefore store one bit of data with each element.
- more than two storage states can be defined for each storage element, in which case more than one bit of data is stored in each storage element.
- FIG. 4 a illustrates an example of how a memory chip can be formatted into groups of units of erase (or blocks), where the blocks are arranged according to physical planes and logical zones.
- Some reasons for dividing the chip this way include equalizing the number of good units of erase within each group, and setting aside special purpose sections of the memory chip.
- a special “reserved” section can be set aside to store information such as system and device parameters, and information about zone alignment.
- a section can also be set aside to store spare units of erase, also known as spares, or spare blocks.
- Information that is relevant to the spares for example, their physical addresses, can be kept in a spares list for retrieval when needed. For example, when a defect is detected in one of the units of erase contained in one of the N zones, a spare can be found by remapping the defective unit of erase to one of the spare units of erase that are available.
- Data from the host is typically just provided to the memory system identified as logical sectors.
- the host will send data described in terms of a starting logical sector and the total number of sectors.
- these logical sectors may be structured into larger units, but this information is typically not passed on to the memory's controller.
- the controller organizes the host structures into logical constructs that mimic the physical structure for more efficient storage of them in the physical memory.
- the memory system controller groups logical sectors (as defined by the host) into logical blocks that correspond in size to the physical structure of a block, which is the physical unit of erase for a flash type memory.
- the controller can then maintain the relation of the physical structures to the logical constructs, for instance in the form of a Sector Address Table (SAT), and update this correspondence as the logical to physical relation changes.
- SAT Sector Address Table
- a metablock can be formed from planes with a single memory chip or one or more planes distributed across several memory chips.
- FIGS. 5-10 show an arrangement of six blocks in four planes, for a total of 24 units of erase, as an example of the memory array of FIGS. 1-3 .
- the units of erase will be referred to as blocks since a block is a kind of unit of erase.
- the size of this 6 ⁇ 4 block structure is chosen for convenience of explanation, as will become apparent below.
- a typical memory array would contain many more blocks (have many more rows) than are shown here, and could have more planes than shown if the parallelism of the nonvolatile memory system is greater than four.
- Each plane typically has its own data registers and programming circuits. This allows for simultaneous programming into the blocks of memory cells of each of the planes.
- Each plane is operable semi-independently of the other planes. For convenience of illustration, the planes depicted in FIGS. 5-10 are shown to have 6 physical blocks 0 - 5 . The actual number of blocks in any given configuration can be lower but is typically much higher.
- the planes can be logically divided into zones as shown in FIG. 4 a.
- the zones extend across the plurality of planes. Dividing the planes into zones is done to divide a plane into smaller more manageable segments.
- the blocks in each plane within a zone can occupy the same contiguous set of physical block addresses.
- the number of zones is not specifically limited, although practical design decisions can affect the number of zones implemented in a particular memory system.
- the various aspects of the present invention may be implemented in a memory with or without the zone structure, and, for memories that do have a zone structure, within the planes as a whole or with the individual zones.
- the unit of operation used by the memory system as applied to the scenarios in FIGS. 5-10 is preferably a metablock.
- a metablock represents a virtual linking of a plurality of physical blocks across planes.
- Optional uses of a metablock include pipelined erasure of all the blocks within the metablock, and pipelined programming and reading of one or more pages from each block of the metablock.
- a metablock extends across multiple planes and typically includes one block from each of these planes, as shown by the arrows in each of the sets of connected arrows shown in FIGS. 5-10 .
- FIG. 5 shows the simplest form of metablock, where each physical block of every metablock has the same block offset and extends across all four planes 0 - 3 .
- FIG. 10 illustrates two more complicated metablocks. The creation of these metablocks will be discussed in the description of FIGS. 5-10 , where the component blocks contained in a metablock are updated as defects are encountered.
- FIG. 4 b The more general situation for the linking of blocks into metablocks is shown in FIG. 4 b.
- the memory portion of the system ( 103 , 203 , 303 of FIGS. 1-3 respectively) is taken to consist of chips 0 -Z, with each chip having a number of planes, such as planes 00 to 0 W for chip 0 .
- Each linked physical unit in a plane, indicated by an x can consist of a single physical block, as shown in FIG. 4 c, or multiple physical blocks, as shown in FIG. 4 d.
- the sort of two-dimensional meta-blocks shown in FIG. 4 d that link blocks not only across planes and chips, but also in depth, can be convenient especially when physical blocks are small.
- each metablock MB is numbered according to the first row of the first block in the linking; for example, the metablock starting with block 0 is labeled MB 0 , and so on.
- FIG. 4 b shows each plane having a block (and only one block) in a given linking and the linking running across several planes, neither of this situations need always be the case.
- a linking of, say, four blocks as in FIGS. 5-10 could consist of four planes on a single chip or one plane from four planes.
- the linking MB 0 has all of its blocks from the same row
- MB 1 has most of its blocks from the same row
- MB 2 has each block from the row below the preceding block.
- FIGS. 5-10 will take the case MB 0 , with all blocks from the same row, for ease of discussion, with the more general case discussed below.
- These various linking methods may either be fixed or, according to an aspect of the present invention discussed more below, determined based upon an algorithm. (Alternately, the initial determination may be based on a random allocation.)
- the various aspects of the present invention can be applied generally when physical structures are formed in larger logical conglomerates and be applied to how these conglomerates are managed.
- the first metablock as shown in FIG. 10 includes block 0 in each of the four planes 0 - 3 .
- the second metablock includes block 1 in plane 0 , block 4 in plane 1 , block 5 in plane 3 , and block 4 in plane 3 .
- the third metablock includes block 2 in each of the four planes 0 - 3 .
- the fourth metablock includes block 3 in plane 0 , block 3 in plane 1 , block 3 in plane 2 and block 1 in plane 3 .
- a metablock could include only a subset of the number of planes contained within a single zone. This example is not shown but can be useful if variable degrees of parallelism are desired.
- a system having variable degrees of parallelism could allow for blocks to move between areas having different parallelism. For example, a metablock that contained two blocks instead of four could move from an area where the parallelism is two (two planes) to an area where the parallelism is four (as in our four-plane example). If two metablocks each containing two members exist in such a system, they could be combined into one four-member metablock.
- One caveat to using such a mixed-parallelism system is that the defect map would have to be reconciled to account for the varying parallelism.
- metablocks In general, using metablocks increases the parallelism of the memory system by allowing for more blocks to be processed at one time in parallel. This increased parallelism significantly increases the performance of the memory system.
- the memory system maintains the identity of the individual blocks within the various metablocks. For example, the identity of the individual blocks within the various metablocks can be maintained as a linked list in any convenient location within the system.
- overhead data stored along with user data of each page will include an address, logical and/or physical, sufficient to identify the plane, zone and block in which the pages reside, as well as an offset of the page within that block.
- An address map is then created within a memory of the controller by the controller reading these address fields of the page overhead data. This is usually done for part of the memory at a time, preceding a programming, reading or erasing operation directed to that part of the memory.
- FIGS. 5-10 show how the system responds to the detection of defects in the physical blocks of the memory array. These defects can be factory or grown defects. This series of figures are intended to show what occurs each time a new defect is encountered. For purposes of illustration, the physical blocks that are numbered 1-5 contain defects.
- FIG. 5 shows a portion of a memory array in which no defects exist.
- a plurality of metablocks is depicted by six horizontal arrows extending across all of the four planes.
- Each metablock comprises a defined number of physical blocks.
- the defined number of physical blocks is four for all of the metablocks, which corresponds to the number of planes.
- FIG. 5 shows a portion of a memory array in which no factory or grown defects have been found.
- the black arrows extending horizontally across the diagram depict six linear standard metablocks.
- a linear standard metablock is a metablock that comprises physical blocks with matching offsets, as shown in FIG. 5 .
- the initial linkings may either be established according to an algorithm, as described further below, or formed from a erase pool of available good blocks.
- a feature of the metablock is that the first virtual block address (associated with the first physical block address) is the only information required to determine the locations of the remaining physical blocks associated with that particular metablock, the rest of the linked metablocks being determined by a linking algorithm. This reduces the size of the data required for storing the metablocks. If a defect is encountered in the first physical block, then the entire metablock becomes invalid and gets mapped out of the address space because there is no longer any mechanism for pointing to the remaining members of the metablock located across each of the available planes or planes. An example of this will be shown in the discussion of FIG. 9 below.
- FIG. 6 shows the state of the array after a first new defect is encountered.
- the new defect is located in MB 1 at the physical block labeled “A”, located at block 1 on plane 2 .
- A physical block within a metablock
- the metablock can no longer be used as is.
- One simple solution would be to map that metablock out of the address space and never use it again. This is the only solution available if the system only has one single bad physical block and no spare blocks are available. However, if multiple bad physical blocks appear, this solution quickly becomes wasteful because the remaining physical blocks associated with the failed metablock can be used to create other good metablocks.
- the remaining three good physical blocks (shown by hatch marks) become spares.
- FIG. 7 shows the state of the array after a second new defect is encountered.
- the new defect is at the physical block labeled “B”, located in MB 3 at block 3 on plane 3 .
- the plane where the defect occurred plane 3
- physical block 1 is available (and shown by hatch marks in FIG. 6 ) in plane 3 .
- the metablock Since block 1 is available in plane 3 , the metablock will be updated to point to block 1 in order to replace the defective part of the metablock; that is, the defective block in MB 3 at plane 3 (“B”) is replaced in the linking by the good block at plane 3 in MB 1 that was made redundant due to the failure of the block “A” at plane 2 of MB 1 .
- a spare physical block is linked into the metablock to take the place of the failed physical block.
- FIG. 8 shows the state of the array after a third new defect is encountered.
- the new defect is located at the physical block labeled “C”, located at block 4 on plane 0 .
- This metablock cannot be re-linked because the defective block is located on plane 0 .
- the block located on plane 0 is the block that contains the reference information to the rest of the members of the metablock, and without the block on plane 0 , there is no way to reference the metablock under the adopted convention. Therefore, even though a spare block is available at block 1 on plane 0 , it cannot be used to complete this metablock.
- block 1 on plane 0 is re-mapped into the virtual address space and used as the first block in a new metablock to take advantage of the now redundant blocks in planes 1 , 2 , and 3 of the former metablock MB 4 .
- defective block “A” can be replaced by block 4 of plane 2 .
- block 1 of plane 3 has been remapped in FIG. 7 , it will also need to be replaced. Consequently, a re-linked MB 1 can be formed using the spares at block 4 from planes 2 and 3 .
- a block is available in both block 1 and block 4 .
- the block formerly in MB 4 is used in the example. Consequently, the re-linked MB 1 comprises block 1 on plane 0 , block 4 on plane 1 , block 4 on plane 2 and block 4 on plane 3 . At this point, only one spare block remains at block 1 on plane 1 .
- FIG. 9 shows the state of the array after a fourth new defect is encountered.
- the new defect is located at the physical block labeled “D”, located at block 5 on plane 0 . Since there are no spare blocks located in plane 0 at this point, this metablock cannot be re-linked. As a result, the remaining physical blocks are added to the spare physical block pool. This includes block 5 on plane 1 , block 5 on plane 2 and block 5 on plane 3 . At this point, four spare blocks are available in the memory array shown.
- FIG. 10 shows the state of the array after a fifth new defect is encountered.
- the new defect is located at the physical block labeled “E”, located at block 4 on plane 2 . Since a spare block is available on the same plane (block 5 on plane 2 ), the metablock MB 1 is re-linked using that spare block.
- FIG. 11 illustrates how the component members of a metablock can be mapped using a logical-to-physical mapping table 1101 .
- a metablock in memory 1103 (or memory zone in an embodiment using that structure) associated with LBN[ 0 ] is shown by the blocks marked by hash marks.
- the (in this example) four planes of the memory may again be distributed across more than one chip.
- the PBN entries contained within LBN[ 0 ] refer to the physical addresses of each of the blocks marked by hash marks and which are parts of the metablock.
- the first member of the metablock, contained in plane 0 is used to access the other metablock members. As described with respect of FIGS. 5-10 , if the metablock member in plane 0 is found to be defective, then the entire metablock must be marked as defective because they are linked to the rest of the metablock via the member on plane 0 .
- the mapping table 1101 is one example of a record of the linking of blocks to form metablocks.
- One technique that allows for adaptability of the metablock composition is, whenever a metablock is needed for a write process, to dynamically form a metablock from a pool of available good blocks. Although this technique allows for adaptability for the metablock structure, it then requires that the linking be re-established whenever a block is needed; further, it requires that each plane be accessed in order to determine this pool.
- this record is stored at a location in the non-volatile memory. This record can then be read from the flash memory into volatile memory (or an alternate non-volatile memory) on the controller on demand for use in address translation.
- the record of the linking information can be maintained in a special non-volatile memory location, such as somewhere outside the normal physical blocks where user data is stored. For instance, this record can be maintained in one of the reserved areas in plane 0 of FIG. 4 a, or in any of the system zones in an arrangement such as is described in U.S. patent application publication US2003/0065899, which is hereby incorporated by reference.
- the linking information can be kept in the header area of the user data sectors/control data sectors for written, or partially written, blocks. For blocks in the erased state, the linking information can be stored in a special control data area in non-volatile memory.
- FIG. 12 shows a bad block at on plane 1 .
- the bad block is marked with an “X.”
- the second member of the metablock LBN[ 0 ] pointed to that block, as shown by dotted line arrow 1201 .
- the collection of spare blocks 1203 has a spare available on the same plane that is shown by the hatch marks. (Alternately, if a spare was available in plane 1 from another linking that had developed an error, as in the process of FIGS. 5-10 , it could be used instead of a block from the collection of spares 1203 .)
- the physical block number (PBN) of the spare PBN′ will replace the PBN of the block that failed. As a result, this spare becomes part of the metablock, as shown by arrow 1202 .
- FIG. 13 illustrates an example of a map structure similar to the map structure in FIG. 11 .
- the map structure in FIG. 13 shows a bad block, possibly a grown defect, as shown on the block marked by an “X” on plane 2 .
- a spare is not available on the same plane as the bad block, as shown by the fact that the collection of spare blocks in erase pool 1302 on plane 2 has no spares. Therefore, instead of redirecting the bad block on plane 2 to point to a spare, the physical blocks associated with the rest of the metablock (the blocks on planes 0 , 1 and 3 ) are added to the spares pool, as shown by the three downward pointing arrows.
- the controller maintains a record of the linking table in the non-volatile memory.
- This record may be a complete listing of the blocks forming each metablock corresponding to a given physical address, such as logical-to-physical mapping table 1101 of FIGS. 11-13 .
- a standard linking of physical blocks into metablocks may be based upon a deterministic algorithm, and the record maintained in the non-volatile memory need only contain any deviations from the linking rule. As a linking is updated due to defects and consequently deviates from a standard linking, the record is correspondingly updated.
- metablock number is defined from the address of the physical block in the first plane incorporated in the metablock.
- a “standard” metablock comprises physical blocks whose physical block addresses are a deterministic function of the metablock number.
- this could be the arrangement of metablock MB 0 in FIG. 4 b, which is also used for the example of FIGS. 5-10 , where all of the blocks of a standard metablock are in the same row.
- the physical block address is given by the metablock number plus an offset equal to the sequential number of the plane to which the physical block belongs; that is metablock i is composed of the blocks i+(plane number).
- MB i (i, i+ 1 , i+ 2 , i+ 3 ). This structure is shown in FIG. 15 and will be used to discuss the algorithmically based linking table.
- MB i (i, f 1 (i, plane number), f 2 (i, plane number) , f 3 (i, plane number)) for the case of a four block metablock, with the extension for other numbers following in the obvious manner.
- i is the row number
- f 1 , f 2 , and f 3 are some functions of the row and plane number.
- the metablock number is the same as the row number of plane 0
- the first entry in MB i is i.
- the discussion of the re-linking process for the algorithmic based linking will largely go through an abbreviated version of process of FIGS. 5-10 , but based on the standard linking of FIG. 15 .
- the controller can use a firmware-based implementation for determining the standard linking.
- the physical blocks are linked into metablocks according to rules that maximize the possible number of standard metablocks.
- a metablock is being linked, a standard block is created if the required physical blocks are available. If any physical block required for formation of a standard metablock is bad, the metablock number is classified as unused. If any physical block required for formation of a standard metablock is bad, the metablock number is classified as unused. In this case, other usable physical blocks which are consequently left unlinked are classified as spare, as shown for metablock n+ 1 in FIG. 15 .
- Another aspect of the present invention is the optimization of the standard linking pattern based on the pattern of defects on the card or to otherwise maximize the number of usable standard metablocks.
- the pattern of bad blocks can be scanned and the decision about the ‘standard’ linking pattern can be made so that they match each other as much as possible.
- the matching of the algorithm for the standard linking to the bad block pattern will reduce the needed re-linked metablock and meta- to physical address translation overhead, thereby optimizing (at least initially) the linking. An example of this is shown in FIGS. 16 and 17 .
- FIGS. 16 and 17 consider an example where four bad physical blocks, one from each of planes 0 - 3 , run diagonally. In the case of a diagonal pattern of bad blocks, the best pattern for standard blocks will also be diagonal, as shown in FIG. 16 . As a result, in this example, there will be no re-linked blocks at all and, consequently, none of the metablocks require translation through a linking table and the number of usable metablocks is increased.
- FIG. 17 is shows the equivalent situation when the standard linking is straight across, rather than matching the bad block pattern. In the example where the standard method is straight across, three metablocks (n+ 2 , n+ 3 , and n+ 4 ) need to be re-linked.
- the standard block pattern can be unique for every card, for every re-formatting, or both. This can provide an extra level of data security, where every card has a unique method of data scrambling across different blocks. Consequently, standard metablocks need not necessarily have the same configuration, although they will have been formed using the same rule. In another embodiment, the host may want to provide the rule and code for the metablock linking rule, so that the algorithm is not system specific.
- Metablocks which cannot exist as standard blocks may be structured as re-linked metablocks.
- Re-linked metablocks may be formed during the initial formatting process of the memory system, or in response to failure of a physical block within an existing metablock.
- Metablock n+ 4 in FIG. 19 cannot be linked as a standard metablock, because the required physical block in plane 2 is bad.
- a re-linked metablock is created by substituting a spare physical block in plane 2 .
- a spare physical block being re-linked in place of a bad physical block is preferably located in the same plane as the bad block to maintain programming parallelism within the metablock.
- re-link blocks only within the same die or chip, as a re-linking running across to another die or chip may trigger additional die/chip reads or programs.
- the data can be programmed to (or read from) all 4 planes, which requires 2 chip read/program in parallel. (This may not be 100% parallel but pipelined, so that the page read, block program and erase can be done in parallel, but the data bus being shared so that data transfers are not parallel).
- a metablock is re-linked so that a physical block is taken from another, third chip, than it may be not possible to access it concurrently with the other two and the operation time can double.
- metablock number is defined by that of the spare block, as shown for metablock n+ 1 in FIG. 20 .
- Re-linked metablocks may be further re-linked in the event of subsequent physical block failure. Metablocks close to the top of the address space, which cannot be linked as standard metablocks, can take the form of re-linked metablocks.
- FIG. 21 shows an example of re-linking in the two-dimensional case.
- the ‘2-D metablock’ is example of a 2*4 metablock.
- the maximum benefit in performance can be achieved when all 8 blocks can be accessed in parallel.
- the main linking and re-linking principles of 1-D linking methods also apply, but with some extensions. As can be seen in the figure, a bad physical block in any of the physical blocks within a plane lead to a metablock being unused, as is shown for Metablock n.
- the management data structures for metablock linking can be contained within two types of sectors in one or more dedicated block linkage management blocks in flash memory. This arrangement has the advantage, with respect to saving the complete linking, of requiring the storage of less information. Metablock numbers of every re-linked metablock in the memory system are contained in a link table in a set of link table sectors. No entries for standard metablocks need be stored in the link table, because their physical block addresses are generated deterministically from the metablock number.
- An RF (re-linked) flag can be used as an attribute of a meta-block, indicating whether the block is standard, and all the blocks are linked in a standard fashion, or whether it is re-linked and requires additional block address translation through the link table (LT).
- the RF flag can be determined by analyzing the LT and then stored in SRAM, or else stored in a control data structure in the main non-volatile memory as an attribute for the meta-block.
- a list of re-linked sectors can be keep in a list that can be searched through to determine which meta-blocks are re-linked.
- Entries in the link table can be ordered by metablock number, and each entry has fields for metablock number and block address of each linked physical block.
- the deviations from the basic algorithm establishing the standard linking can themselves be based on a set of rules; for example, the non-standard linking could be limited to a single plane or limiting how far from its original row a block can be re-linked. Only when the re-linking is an exception to all of the algorithms need it be explicitly kept in the non-volatile memory.
- the Link Table sector holds information about blocks that have been re-linked within the card. Depending upon the size of the card and the number of bad blocks within each die, it is possible that there will be more than one Link Table sector present, which can be stored in the Boot Block block. As described above, meta-blocks have a standard method for linking and if one of the blocks is bad, then the meta-block may be able to be re-linked with a spare physical block in the same plane.
- the Link Tables sectors store the information about which blocks are used in the re-linking.
- FIG. 22 is another example of the re-linking of meta-blocks.
- metablock 0 has the standard linking, here taken as straight across the eight planes.
- the figure shows several block linking situations:
- the compression algorithm used for block re-linking shown in FIG. 22 can be defined as in Table 1.
- TABLE 1 Repeated values to match Total Meta- number of items bytes block in Meta-block Number of re-linked Physical in Diagram number items in entry Plane address entry 2 bytes 1 byte 1 byte 2 bytes 1 0x0001 0x02 0x00 0x0002 0x01 0x0005 9 4 0x0004 0x02 0x00 0x0003 0x05 0x0001 9 5 0x0005 0x03 0x01 0x0004 0x03 0x0004 0x04 0x0007 12 7 0x0007 0x01 0x00 0x0006 6 9 0x0009 0x06 0x01 0x0008 0x02 0x0007 0x03 0x0007 0x04 0x0008 0x05 0x0008 0x06 0x
- the full set of entries in the link table may be spread across multiple link table sectors.
- a link table sector is created or modified by writing it to the next available sector position in the block linkage management block. Multiple copies of a link table sector may therefore exist, with only the latest version being valid.
- An index to the positions of valid link table sectors in the block linkage management block can be contained in a field in the spare physical block list sector in the block linkage management block, which is described below.
- the metablock number relating to the first entry in each valid link table sector can be held in a list in controller RAM, to allow easy identification of the relevant link table sector for any metablock number. If an additional entry must be added to a link table sector which already contains the maximum number of entries, the sector is split into two new sectors, each with half the entries, and the new entry is inserted in the appropriate new sector.
- the block addresses of all spare physical blocks are held as entries in an unordered list in the spare physical block list sector. In some embodiments, it may be convenient to limit the maximum number of spare blocks per plane per chip. In an exemplary embodiment, this is limited to 16, as in most cases this should be large enough. If there are more than 16 spare blocks in a plane, they will be “lost”.
- Blocks that become spare because either a standard metablock cannot be created during initial configuration of the flash memory into metablocks or because a physical block linked into a standard or re-linked metablock has failed, are added as new entries to the end of the spare physical block list.
- a spare block is required for creation of a re-linked metablock, the first block in the relevant plane closest to the beginning of the spare physical block list can be used.
- the spare physical block list sector also contains a field with an index to valid link table sector locations.
- spare physical block list and link table sector index fields can both be modified in the spare physical block list sector.
- a valid spare physical block list sector is therefore the last written sector in the block linkage management block.
- the spare physical block list can be stored by chip, die, and plane.
- the actual number of sectors required depends on the size of memory device, number of devices, and the interleaving method used. As noted above, it may be convenient to store only a certain number of physical blocks per plane. The number held will depend upon the expected failure rate of blocks and the number of blocks per plane. This means that each spare physical block list sector will hold the spare physical blocks for several planes.
- the firmware will calculate the correct sector to load and then index into the sector to load the correct values.
- a new spare physical block list sector will be written. This may mean two spare physical block list sectors covering the same physical area.
- the Boot Sector holds the spare physical block list Indices containing the index of the valid sector. If no spare physical blocks exist in an area covered by a spare physical block list, then the sector will not exist in the Boot Block.
- the spare physical block list corresponding to FIG. 22 is shown in Table 2.
- the spare physical block list can be stored as a table in non-volatile memory which can be cached into volatile RAM upon demand.
- a hardware engine on the controller or, preferably, on a memory chip itself can do the re-linking.
- the re-linking information can be stored on the chip itself at a special memory location.
- the controller can then treat all the blocks as standard, and the engine will translate the block addresses to the true internal addresses.
- the memory will appear to the host (or controller) as a memory with only standard blocks, or as a memory with large physical blocks, without having to know about either the smaller block structures or the details of any re-linking.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Error Detection And Correction (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
- This application is related to U.S. patent application entitled “NON-VOLATILE MEMORY AND METHOD WITH BLOCK MANAGEMENT SYSTEM”, by Peter Smith, Alan Bennett, Alan Bryce, Sergei Gorobets, and Alan Sinclair with which it is filed concurrently and which is hereby incorporated by reference:
- This invention relates generally to semiconductor non-volatile data storage systems, and more specifically, to a system and method for forming physical blocks into larger logical structures that accommodate defects in non-volatile data storage systems.
- Nonvolatile memory devices such as flash memories are commonly used as mass data storage subsystems. Such nonvolatile memory devices are typically packaged in an enclosed card that is removably connected with a host system, and can also be packaged as the non-removable embedded storage within a host system. In a typical implementation, the subsystem includes one or more flash devices and often a subsystem controller.
- Current commercial memory card formats include that of the Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF), MultiMediaCard (MMC), Secure Digital (SD), MemoryStick, and MemoryStick-Pro. One supplier of these cards is SanDisk Corporation, assignee of this application. Host systems with which such cards are used include digital cameras, cellular phones, personal computers, notebook computers, hand held computing devices, audio reproducing devices, and the like.
- The nonvolatile memory devices themselves are composed of one or more arrays of nonvolatile storage elements. Each storage element is capable of storing one or more bits of data. One important characteristic of the nonvolatile memory array is that it retains the data programmed therein, even when power is no longer applied to the memory array. In contrast, a volatile memory device requires that the power to the array be refreshed periodically in order to preserve the data contained in the volatile memory array. Another characteristic of nonvolatile memory is that once a cell contained within a nonvolatile memory array is programmed, that cell must be erased before it can be reprogrammed with a new data value.
- The physical means for storing the charge in the memory cell can be implemented by using a floating gate transistor, such as an electrically erasable programmable read only memory (EEPROM). One known problem with floating gate devices such as EEPROMs is that the floating gate eventually wears out and breaks down after a very large number of write, program and erase cycles. When this happens, the cell is no longer usable and must be taken out of the list of available memory cells in the array. This sort of defect is called a “grown” defect. In one commercially available implementation, these defects are dealt with by mapping out the defective cells and substituting the physical addresses of good memory cells for the newly detected defective memory cells. Examples of implementations where defective cells or sectors are mapped out and replaced are described in U.S. Pat. No. 5,659,550 issued on Aug. 19, 1997 by Mehrotra et al.; U.S. Pat. No. 5,671,229 issued on Sep. 23, 1997 by Harari et al.; and in U.S. Pat. No. 5,862,080 issued on Jan. 19, 1999 by Harari et al., which applications are expressly incorporated herein in their entirety by this reference.
- Arrays of nonvolatile memory cells typically are partitioned into groups to provide for efficient implementation of read, program and erase functions. For example, in many nonvolatile memory architectures, the memory cells are arranged into a larger group called a unit of erase. This unit of erase is the smallest number of memory cells that are erasable at one time.
- The size of the unit of erase depends on the memory architecture that is being implemented. In earlier nonvolatile memories, the unit of erase was a block that was the same size as a standard 512-byte disk drive sector. In one commercial form, each block contained enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it was stored. In order to ensure that the blocks of cells were individually erasable, the blocks had to be sufficiently isolated from one another.
- Because this isolation took up valuable space on the integrated circuit chip, another memory architecture was developed in which the unit of erase was made significantly larger so there would be less space required for such isolation. An example of this large block system architecture is described in U.S. Pat. No. 6,580,638 issued on Jun. 17, 2003 by Conley et al., which is a continuation of U.S. Pat. No. 6,426,893 issued on Jul. 30, 2002. Both of these patents are expressly incorporated herein in their entirety by this reference. In a large block system, the unit of erase is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data (unit of programming and/or reading). In one commercial implementation, the unit of erase is a metablock. A metablock is a virtual unit of erase that is composed of multiple physical units of erase. These multiple physical units of erase can be used in parallel program and erase operations, but are addressed as a single logical block.
- One method of forming metablocks, or “super” blocks is described in U.S. Pat. No. 6,034,897, which is expressly incorporated herein in its entirety by this reference. As described therein, for a memory having a number of devices, the same physical block in each of the devices is grouped into a metablock. Although this allows for the formation of metablocks and all of the blocks in a given metablock to be addressed by the same address, namely the address of the block in the first of the devices, it has a number of limitations. For example, as the linking of blocks into metablocks is pre-determined in this fixed configuration, when a block goes bad, the metablock to which it belongs becomes bad despite the other blocks within it still being functional. Thus, it is desirable goal to provide a system and method for an adaptable metablock arrangement without the operational overhead of establishing a new linking every time one is needed.
- The various aspects of the present invention overcome these and other limitations found in the prior art for the linking of physical memory structures into composite logical structures. In the primary embodiment of the present invention, techniques are presented for the formation of metablock structure in flash memories. According to a first aspect of the present invention, the linking of block into metablocks is updated to accommodate defective portions of the memory. A system for maintaining a defect map includes a defect map structure for tracking the existence of factory and grown defects in a nonvolatile memory system that is organized into metablocks. A method for maintaining a defect map makes use of the defect map structure and the characteristics of a metablock. In one embodiment, the size of the defect map structure is equal to the parallelism of the nonvolatile memory system. In another embodiment, the remaining units of erase that cannot be assigned to a metablock will be kept in a list of spare units of erase for later use.
- According to another aspect of the present invention, a record of the linking of blocks into metablocks is maintained in the non-volatile memory. The controller can then read out the linking into its volatile memory as needed. The record is updated in response to re-linkings resulting from defects. A complete linking record may be maintained in the non-volatile memory, for example in a specified location, or only a partial linking record may be maintained. In another aspect of the present invention, an initial linking of blocks into metablocks is deterministically formed by an algorithm using, for example, a firmware based implementation. In this case, the linking record stored in the non-volatile memory need only contain the deviations from the standard algorithm.
- Additional aspects, features and advantages of the present invention are included in the following description of exemplary embodiments, which description should be read in conjunction with the accompanying drawings.
-
FIG. 1 is a block diagram of an existing nonvolatile memory system in which the nonvolatile memory array and the memory controller are packaged in an enclosed card that is removably connected with a host system. -
FIG. 2 is a block diagram of an existing nonvolatile memory system in which the nonvolatile memory array is packaged in an enclosed card that is removably connected with a host system. -
FIG. 3 is a block diagram of an existing nonvolatile memory system in which the nonvolatile memory array is packaged as non-removable embedded storage within a host system. -
FIG. 4 a illustrates an example chip format showing planes, zones and spares. -
FIGS. 4 b-d illustrate various linkings of physical blocks into metablocks. -
FIGS. 5-10 illustrate how the system can respond to a series of grown defects occurring on a portion of a memory array. -
FIG. 11 illustrates an example of the mapping of the virtual structure elements of a metablock in response to the detection of a grown defect on a unit of erase. -
FIG. 12 illustrates an example of a system for maintaining a defect map, wherein a spare unit of erase is not available in the same plane as a unit of erase having a grown defect. -
FIG. 13 illustrates an example of a method for maintaining a defect map. -
FIG. 14 illustrates an example of a method for maintaining a defect map using the data structure ofFIGS. 11-13 . -
FIGS. 15-18 illustrate an algorithmically based linking of physical blocks. -
FIGS. 19, 20 and 22 illustrate the re-linking of physical blocks. -
FIG. 21 shows an example of re-linking in the two-dimensional case. - Generally, the memory system of the present invention maintains in its main non-volatile memory a record of the linking of blocks into multi-block metablock structures. This record contains a defect map of factory and grown defects in a map table that can be read into non-volatile memory on demand. This map is updated as grown defects are encountered and blocks are assigned to new locations. Metablocks are preferable formed by one block in each of several subarrays, or planes, and in this case, the grouping is done preferably with same-numbered blocks in each plane, with the exception of blocks that are marked bad and placed in the map. In one embodiment, the blocks are directly mapped to alternate blocks. Metablocks that would contain the defective block are then reformed with the alternate block in the corresponding plane. Rather than maintain a complete record of the linking of blocks into metablocks within the non-volatile memory, a “standard” linking can be based on an algorithm implanted, for example, in the system's firmware, with only the deviations due to defects from this algorithm needing to be stored. Those standard metablocks with no defects present will be termed usable standard metablocks. The remaining Metablocks are termed unusable standard metablocks, and the component physical blocks will be termed spare blocks.
-
FIG. 1-3 are block diagrams of typical existing nonvolatile memory systems which include ahost controller arrays FIG. 1 , thenonvolatile memory array 103 and thememory controller 104 are shown as being packaged in an enclosed card that is removably connected with ahost system 102. InFIG. 2 ,controller 204 is shown as being part of thehost system 202 and thenonvolatile memory array 203 is shown as being packaged in an enclosed card that is removably connected with a host system. InFIG. 3 , thenonvolatile memory array 303 is shown as being packaged as non-removable embedded storage within ahost system 302. - Typically, the nonvolatile memory array includes memory cells that include one or more conductive floating gates as storage elements. The memory arrays could include other long-term electron charge storage elements instead, for example a charge trapping dielectric. A variety of nonvolatile storage elements can be used, including nonvolatile multi-state storage elements, storage elements that are Flash/EEPROM/floating gate, nonvolatile storage elements such as NROM, MNOS, MRAM/FRAM, NAND, NOR, and non-volatile storage elements that are organized into units of erasure. Non-volatile storage elements that store digital information, analog information or combinations of both can be used.
- The memory cell array can be operated with two levels of charge defined for each storage element to therefore store one bit of data with each element. Alternatively, more than two storage states can be defined for each storage element, in which case more than one bit of data is stored in each storage element.
-
FIG. 4 a illustrates an example of how a memory chip can be formatted into groups of units of erase (or blocks), where the blocks are arranged according to physical planes and logical zones. Some reasons for dividing the chip this way include equalizing the number of good units of erase within each group, and setting aside special purpose sections of the memory chip. For example, a special “reserved” section can be set aside to store information such as system and device parameters, and information about zone alignment. A section can also be set aside to store spare units of erase, also known as spares, or spare blocks. Information that is relevant to the spares, for example, their physical addresses, can be kept in a spares list for retrieval when needed. For example, when a defect is detected in one of the units of erase contained in one of the N zones, a spare can be found by remapping the defective unit of erase to one of the spare units of erase that are available. - Data from the host is typically just provided to the memory system identified as logical sectors. For example, the host will send data described in terms of a starting logical sector and the total number of sectors. Within the host, these logical sectors may be structured into larger units, but this information is typically not passed on to the memory's controller. (Knowledge of these host structures can be used, though, to have physical structures in the memory or controller constructs that reflect these host structures as they will reflect how the host transfers data: for example, memories are typically structured to store user data based on a physical sector that is the same size as a logical sector.) The controller organizes the host structures into logical constructs that mimic the physical structure for more efficient storage of them in the physical memory. For example, in a common arrangement the memory system controller groups logical sectors (as defined by the host) into logical blocks that correspond in size to the physical structure of a block, which is the physical unit of erase for a flash type memory. The controller can then maintain the relation of the physical structures to the logical constructs, for instance in the form of a Sector Address Table (SAT), and update this correspondence as the logical to physical relation changes.
- For greater efficiency, memory systems often increase parallelism by introducing larger structures. For instance, in a memory system having a number of semi-autonomous arrays that can be written, read, or both, concurrently, blocks from different arrays are grouped into “metablock” structures and the controller will form logical blocks of data into corresponding logical metablocks, allowing for the multiple blocks to be operated upon at the same time. A metablock can be formed from planes with a single memory chip or one or more planes distributed across several memory chips. In this way, by allowing a group of (logically) sequential sectors spans over multiple physical blocks that can be read/programmed/erased in parallel, then this group can be read/programmed/erased concurrently with a minimal number of non-concurrent read, program, or erase operations. This arrangement is beneficial for sequential read and writes of logically contiguous sectors of relatively large amounts of data.
- The structure of
FIGS. 5-10 will be discussed first and then the operations shown by each figure will be explained individually.FIGS. 5-10 show an arrangement of six blocks in four planes, for a total of 24 units of erase, as an example of the memory array ofFIGS. 1-3 . For convenience, the units of erase will be referred to as blocks since a block is a kind of unit of erase. The size of this 6×4 block structure is chosen for convenience of explanation, as will become apparent below. A typical memory array would contain many more blocks (have many more rows) than are shown here, and could have more planes than shown if the parallelism of the nonvolatile memory system is greater than four. - Each plane typically has its own data registers and programming circuits. This allows for simultaneous programming into the blocks of memory cells of each of the planes. Each plane is operable semi-independently of the other planes. For convenience of illustration, the planes depicted in
FIGS. 5-10 are shown to have 6 physical blocks 0-5. The actual number of blocks in any given configuration can be lower but is typically much higher. - In systems where there are a large number of blocks, the planes can be logically divided into zones as shown in
FIG. 4 a. The zones extend across the plurality of planes. Dividing the planes into zones is done to divide a plane into smaller more manageable segments. The blocks in each plane within a zone can occupy the same contiguous set of physical block addresses. The number of zones is not specifically limited, although practical design decisions can affect the number of zones implemented in a particular memory system. The various aspects of the present invention may be implemented in a memory with or without the zone structure, and, for memories that do have a zone structure, within the planes as a whole or with the individual zones. - The unit of operation used by the memory system as applied to the scenarios in
FIGS. 5-10 is preferably a metablock. A metablock represents a virtual linking of a plurality of physical blocks across planes. Optional uses of a metablock include pipelined erasure of all the blocks within the metablock, and pipelined programming and reading of one or more pages from each block of the metablock. - A metablock extends across multiple planes and typically includes one block from each of these planes, as shown by the arrows in each of the sets of connected arrows shown in
FIGS. 5-10 .FIG. 5 shows the simplest form of metablock, where each physical block of every metablock has the same block offset and extends across all four planes 0-3.FIG. 10 illustrates two more complicated metablocks. The creation of these metablocks will be discussed in the description ofFIGS. 5-10 , where the component blocks contained in a metablock are updated as defects are encountered. - The more general situation for the linking of blocks into metablocks is shown in
FIG. 4 b. The memory portion of the system (103, 203, 303 ofFIGS. 1-3 respectively) is taken to consist of chips 0-Z, with each chip having a number of planes, such asplanes 00 to 0W forchip 0. Each linked physical unit in a plane, indicated by an x, can consist of a single physical block, as shown inFIG. 4 c, or multiple physical blocks, as shown inFIG. 4 d. The sort of two-dimensional meta-blocks shown inFIG. 4 d that link blocks not only across planes and chips, but also in depth, can be convenient especially when physical blocks are small. However, convenience may not be the only or even the main reason for the arrangement ofFIG. 4 d. In the usual, or one-dimensional, linking a primary motivation is to provide a mechanism for handling data that can be written to multiple blocks in different chips/planes concurrently. Similarly, if the memory design allows parallel access (read and program) of more than one location in a plane in parallel, then it may make sense also to link multiple blocks within the same plane. - Several metablock linkings are shown, where each metablock MB is numbered according to the first row of the first block in the linking; for example, the metablock starting with
block 0 is labeled MB0, and so on. AlthoughFIG. 4 b shows each plane having a block (and only one block) in a given linking and the linking running across several planes, neither of this situations need always be the case. For example, a linking of, say, four blocks as inFIGS. 5-10 could consist of four planes on a single chip or one plane from four planes. - As shown in
FIG. 4 b, the linking MB0 has all of its blocks from the same row, MB1 has most of its blocks from the same row, and MB2 has each block from the row below the preceding block. The discussion ofFIGS. 5-10 will take the case MB0, with all blocks from the same row, for ease of discussion, with the more general case discussed below. These various linking methods may either be fixed or, according to an aspect of the present invention discussed more below, determined based upon an algorithm. (Alternately, the initial determination may be based on a random allocation.) In a more general context, it will be appreciated that the various aspects of the present invention can be applied generally when physical structures are formed in larger logical conglomerates and be applied to how these conglomerates are managed. - The first metablock as shown in
FIG. 10 includesblock 0 in each of the four planes 0-3. The second metablock includesblock 1 inplane 0, block 4 inplane 1, block 5 inplane 3, andblock 4 inplane 3. The third metablock includesblock 2 in each of the four planes 0-3. The fourth metablock includesblock 3 inplane 0, block 3 inplane 1, block 3 inplane 2 andblock 1 inplane 3. - Alternatively, a metablock could include only a subset of the number of planes contained within a single zone. This example is not shown but can be useful if variable degrees of parallelism are desired. A system having variable degrees of parallelism could allow for blocks to move between areas having different parallelism. For example, a metablock that contained two blocks instead of four could move from an area where the parallelism is two (two planes) to an area where the parallelism is four (as in our four-plane example). If two metablocks each containing two members exist in such a system, they could be combined into one four-member metablock. One caveat to using such a mixed-parallelism system is that the defect map would have to be reconciled to account for the varying parallelism.
- In general, using metablocks increases the parallelism of the memory system by allowing for more blocks to be processed at one time in parallel. This increased parallelism significantly increases the performance of the memory system. The memory system maintains the identity of the individual blocks within the various metablocks. For example, the identity of the individual blocks within the various metablocks can be maintained as a linked list in any convenient location within the system.
- Usually, overhead data stored along with user data of each page will include an address, logical and/or physical, sufficient to identify the plane, zone and block in which the pages reside, as well as an offset of the page within that block. An address map is then created within a memory of the controller by the controller reading these address fields of the page overhead data. This is usually done for part of the memory at a time, preceding a programming, reading or erasing operation directed to that part of the memory.
-
FIGS. 5-10 show how the system responds to the detection of defects in the physical blocks of the memory array. These defects can be factory or grown defects. This series of figures are intended to show what occurs each time a new defect is encountered. For purposes of illustration, the physical blocks that are numbered 1-5 contain defects. - The first figure,
FIG. 5 shows a portion of a memory array in which no defects exist. A plurality of metablocks is depicted by six horizontal arrows extending across all of the four planes. Each metablock comprises a defined number of physical blocks. InFIGS. 5-10 the defined number of physical blocks is four for all of the metablocks, which corresponds to the number of planes. -
FIG. 5 shows a portion of a memory array in which no factory or grown defects have been found. The black arrows extending horizontally across the diagram depict six linear standard metablocks. A linear standard metablock is a metablock that comprises physical blocks with matching offsets, as shown inFIG. 5 . The initial linkings may either be established according to an algorithm, as described further below, or formed from a erase pool of available good blocks. - In one embodiment of the invention, a feature of the metablock is that the first virtual block address (associated with the first physical block address) is the only information required to determine the locations of the remaining physical blocks associated with that particular metablock, the rest of the linked metablocks being determined by a linking algorithm. This reduces the size of the data required for storing the metablocks. If a defect is encountered in the first physical block, then the entire metablock becomes invalid and gets mapped out of the address space because there is no longer any mechanism for pointing to the remaining members of the metablock located across each of the available planes or planes. An example of this will be shown in the discussion of
FIG. 9 below. -
FIG. 6 shows the state of the array after a first new defect is encountered. The new defect is located in MB1 at the physical block labeled “A”, located atblock 1 onplane 2. When a physical block within a metablock fails, the metablock can no longer be used as is. One simple solution would be to map that metablock out of the address space and never use it again. This is the only solution available if the system only has one single bad physical block and no spare blocks are available. However, if multiple bad physical blocks appear, this solution quickly becomes wasteful because the remaining physical blocks associated with the failed metablock can be used to create other good metablocks. As a result of the defect found inFIG. 6 (labeled “A”), the remaining three good physical blocks (shown by hatch marks) become spares. -
FIG. 7 shows the state of the array after a second new defect is encountered. The new defect is at the physical block labeled “B”, located in MB3 atblock 3 onplane 3. In a method for maintaining a defect map such as the one shown inFIG. 11 , the plane where the defect occurred (plane 3) will be searched for any available spare blocks. Here,physical block 1 is available (and shown by hatch marks inFIG. 6 ) inplane 3. Sinceblock 1 is available inplane 3, the metablock will be updated to point to block 1 in order to replace the defective part of the metablock; that is, the defective block in MB3 at plane 3 (“B”) is replaced in the linking by the good block atplane 3 in MB1 that was made redundant due to the failure of the block “A” atplane 2 of MB1. When a physical block failure is encountered, a spare physical block is linked into the metablock to take the place of the failed physical block. - (Under the naming convention being used, there is no metablock MB1 at the point of
FIGS. 6 and 7 since the whole metablock is named based upon the block number inplane 0. The name MB1 is retired unless theblock 1 atplane 0 is returned in a new linking, as occurs inFIG. 8 .) -
FIG. 8 shows the state of the array after a third new defect is encountered. The new defect is located at the physical block labeled “C”, located atblock 4 onplane 0. This metablock cannot be re-linked because the defective block is located onplane 0. The block located onplane 0 is the block that contains the reference information to the rest of the members of the metablock, and without the block onplane 0, there is no way to reference the metablock under the adopted convention. Therefore, even though a spare block is available atblock 1 onplane 0, it cannot be used to complete this metablock. Instead, block 1 onplane 0 is re-mapped into the virtual address space and used as the first block in a new metablock to take advantage of the now redundant blocks inplanes block 4 ofplane 2. Asblock 1 ofplane 3 has been remapped inFIG. 7 , it will also need to be replaced. Consequently, a re-linked MB1 can be formed using the spares atblock 4 fromplanes plane 1, a block is available in bothblock 1 andblock 4. Although either can be chosen to complete the re-linked MB1, the block formerly in MB4 is used in the example. Consequently, the re-linked MB1 comprisesblock 1 onplane 0, block 4 onplane 1, block 4 onplane 2 and block 4 onplane 3. At this point, only one spare block remains atblock 1 onplane 1. -
FIG. 9 shows the state of the array after a fourth new defect is encountered. The new defect is located at the physical block labeled “D”, located atblock 5 onplane 0. Since there are no spare blocks located inplane 0 at this point, this metablock cannot be re-linked. As a result, the remaining physical blocks are added to the spare physical block pool. This includesblock 5 onplane 1, block 5 onplane 2 and block 5 onplane 3. At this point, four spare blocks are available in the memory array shown. -
FIG. 10 shows the state of the array after a fifth new defect is encountered. The new defect is located at the physical block labeled “E”, located atblock 4 onplane 2. Since a spare block is available on the same plane (block 5 on plane 2), the metablock MB1 is re-linked using that spare block. - Note that in
FIG. 10 , although four of the six original metablocks, corresponding torows -
FIG. 11 illustrates how the component members of a metablock can be mapped using a logical-to-physical mapping table 1101. A metablock in memory 1103 (or memory zone in an embodiment using that structure) associated with LBN[0 ] is shown by the blocks marked by hash marks. The (in this example) four planes of the memory may again be distributed across more than one chip. The PBN entries contained within LBN[0 ] refer to the physical addresses of each of the blocks marked by hash marks and which are parts of the metablock. The first member of the metablock, contained inplane 0, is used to access the other metablock members. As described with respect ofFIGS. 5-10 , if the metablock member inplane 0 is found to be defective, then the entire metablock must be marked as defective because they are linked to the rest of the metablock via the member onplane 0. - The mapping table 1101 is one example of a record of the linking of blocks to form metablocks. One technique that allows for adaptability of the metablock composition is, whenever a metablock is needed for a write process, to dynamically form a metablock from a pool of available good blocks. Although this technique allows for adaptability for the metablock structure, it then requires that the linking be re-established whenever a block is needed; further, it requires that each plane be accessed in order to determine this pool. According to one of the primary aspects of the present invention, this record is stored at a location in the non-volatile memory. This record can then be read from the flash memory into volatile memory (or an alternate non-volatile memory) on the controller on demand for use in address translation.
- In one set of embodiments, the record of the linking information can be maintained in a special non-volatile memory location, such as somewhere outside the normal physical blocks where user data is stored. For instance, this record can be maintained in one of the reserved areas in
plane 0 ofFIG. 4 a, or in any of the system zones in an arrangement such as is described in U.S. patent application publication US2003/0065899, which is hereby incorporated by reference. In another set of embodiments, the linking information can be kept in the header area of the user data sectors/control data sectors for written, or partially written, blocks. For blocks in the erased state, the linking information can be stored in a special control data area in non-volatile memory. - By use of such a table, the linking of blocks into metablocks can be updated to accommodate defects and, by keeping a record in the non-volatile memory, it is readily accessible when needed, thereby overcoming the limitation of the prior art discussed in the Background.
- The defect map aspect of the present invention is illustrated in
FIG. 12 , which shows a bad block at onplane 1. The bad block is marked with an “X.” Before the block was found to be defective, the second member of the metablock LBN[0 ] pointed to that block, as shown by dottedline arrow 1201. The collection ofspare blocks 1203 has a spare available on the same plane that is shown by the hatch marks. (Alternately, if a spare was available inplane 1 from another linking that had developed an error, as in the process ofFIGS. 5-10 , it could be used instead of a block from the collection ofspares 1203.) The physical block number (PBN) of the spare PBN′ will replace the PBN of the block that failed. As a result, this spare becomes part of the metablock, as shown byarrow 1202. -
FIG. 13 illustrates an example of a map structure similar to the map structure inFIG. 11 . The map structure inFIG. 13 shows a bad block, possibly a grown defect, as shown on the block marked by an “X” onplane 2. A spare is not available on the same plane as the bad block, as shown by the fact that the collection of spare blocks in erase pool 1302 onplane 2 has no spares. Therefore, instead of redirecting the bad block onplane 2 to point to a spare, the physical blocks associated with the rest of the metablock (the blocks onplanes -
FIG. 14 illustrates an example of a method for maintaining a defect map using the data structure ofFIGS. 11-13 . If a defect is detected or encountered, the location of that defect is determined by looking up the physical location or physical block number (PBN). If a spare block is available in the same plane as the physical location of the defective block, then the metablock associated with the defect is pointed to the spare in order to replace the defective block, after which the defect map is updated. This scenario is shown inFIG. 12 . Otherwise, if there are no remaining spare blocks in the same plane as the defective block, then the remaining good blocks from the metablock are directed to the spares pool. This scenario is shown inFIG. 13 . - As noted above, one of the principle aspects of the present invention is that the controller maintains a record of the linking table in the non-volatile memory. This record may be a complete listing of the blocks forming each metablock corresponding to a given physical address, such as logical-to-physical mapping table 1101 of
FIGS. 11-13 . Alternately, a standard linking of physical blocks into metablocks may be based upon a deterministic algorithm, and the record maintained in the non-volatile memory need only contain any deviations from the linking rule. As a linking is updated due to defects and consequently deviates from a standard linking, the record is correspondingly updated. - The described mechanisms employed for linking physical blocks into metablocks are designed to maximize the number of metablocks for any distribution of bad physical blocks, and to allow new metablocks to be created when physical blocks fail during the life of the system. As above, metablock number is defined from the address of the physical block in the first plane incorporated in the metablock.
- A “standard” metablock comprises physical blocks whose physical block addresses are a deterministic function of the metablock number. For example, this could be the arrangement of metablock MB0 in
FIG. 4 b, which is also used for the example ofFIGS. 5-10 , where all of the blocks of a standard metablock are in the same row. This arrangement can be represented as MBi=(i,i,i,i), where the nth entry in the parentheses represent the row to which the block in the nth plane belongs. - In another example, as in the arrangement of metablock MB2 in
FIG. 4 b, the physical block address is given by the metablock number plus an offset equal to the sequential number of the plane to which the physical block belongs; that is metablock i is composed of the blocks i+(plane number). For a metablock of four blocks, this can be represented, MBi=(i, i+1, i+2, i+3). This structure is shown inFIG. 15 and will be used to discuss the algorithmically based linking table. More generally, the algorithm based, deterministic linking can be described as
MBi=(i, f1(i, plane number), f2(i, plane number) , f3(i, plane number))
for the case of a four block metablock, with the extension for other numbers following in the obvious manner. In the expression, i is the row number and f1, f2, and f3 are some functions of the row and plane number. As the convention that the metablock number is the same as the row number ofplane 0, the first entry in MBi is i. For the examples ofFIGS. 5-10 , f1=f2=f3=i, while forFIG. 15 , f1=f2=f3=i+(plane number). The discussion of the re-linking process for the algorithmic based linking will largely go through an abbreviated version of process ofFIGS. 5-10 , but based on the standard linking ofFIG. 15 . The controller can use a firmware-based implementation for determining the standard linking. - The physical blocks are linked into metablocks according to rules that maximize the possible number of standard metablocks. When a metablock is being linked, a standard block is created if the required physical blocks are available. If any physical block required for formation of a standard metablock is bad, the metablock number is classified as unused. If any physical block required for formation of a standard metablock is bad, the metablock number is classified as unused. In this case, other usable physical blocks which are consequently left unlinked are classified as spare, as shown for metablock n+1 in
FIG. 15 . - Another aspect of the present invention is the optimization of the standard linking pattern based on the pattern of defects on the card or to otherwise maximize the number of usable standard metablocks. When a card is being formatted (or re-formatted), the pattern of bad blocks can be scanned and the decision about the ‘standard’ linking pattern can be made so that they match each other as much as possible. In many cases, the matching of the algorithm for the standard linking to the bad block pattern will reduce the needed re-linked metablock and meta- to physical address translation overhead, thereby optimizing (at least initially) the linking. An example of this is shown in
FIGS. 16 and 17 . -
FIGS. 16 and 17 consider an example where four bad physical blocks, one from each of planes 0-3, run diagonally. In the case of a diagonal pattern of bad blocks, the best pattern for standard blocks will also be diagonal, as shown inFIG. 16 . As a result, in this example, there will be no re-linked blocks at all and, consequently, none of the metablocks require translation through a linking table and the number of usable metablocks is increased.FIG. 17 is shows the equivalent situation when the standard linking is straight across, rather than matching the bad block pattern. In the example where the standard method is straight across, three metablocks (n+2, n+3, and n+4) need to be re-linked. - The standard block pattern can be unique for every card, for every re-formatting, or both. This can provide an extra level of data security, where every card has a unique method of data scrambling across different blocks. Consequently, standard metablocks need not necessarily have the same configuration, although they will have been formed using the same rule. In another embodiment, the host may want to provide the rule and code for the metablock linking rule, so that the algorithm is not system specific.
- When metablocks are being linked during an initial formatting process, some physical blocks near the beginning of block address space, or near chip or die boundaries, cannot be linked into standard metablocks, as shown in
FIG. 20 . These physical blocks are classified as spare. Spare physical blocks are recorded in a spare physical block list, and may subsequently be used in the formation of re-linked metablocks, as described inFIG. 19 . - Metablocks which cannot exist as standard blocks may be structured as re-linked metablocks. Re-linked metablocks may be formed during the initial formatting process of the memory system, or in response to failure of a physical block within an existing metablock. Metablock n+4 in
FIG. 19 cannot be linked as a standard metablock, because the required physical block inplane 2 is bad. In this case, a re-linked metablock is created by substituting a spare physical block inplane 2. A spare physical block being re-linked in place of a bad physical block is preferably located in the same plane as the bad block to maintain programming parallelism within the metablock. - In a preferred embodiment, it is preferable to re-link blocks only within the same die or chip, as a re-linking running across to another die or chip may trigger additional die/chip reads or programs. For example, in an exemplary case of a 4-plane meta-block, where the meta-block spans over 2 chips with 2 planes each, the data can be programmed to (or read from) all 4 planes, which requires 2 chip read/program in parallel. (This may not be 100% parallel but pipelined, so that the page read, block program and erase can be done in parallel, but the data bus being shared so that data transfers are not parallel). In this case, if a metablock is re-linked so that a physical block is taken from another, third chip, than it may be not possible to access it concurrently with the other two and the operation time can double.
- If a bad physical block in
plane 0 is substituted by a spare block fromplane 0, the metablock number is defined by that of the spare block, as shown for metablock n+1 inFIG. 20 . Re-linked metablocks may be further re-linked in the event of subsequent physical block failure. Metablocks close to the top of the address space, which cannot be linked as standard metablocks, can take the form of re-linked metablocks. - As noted above with respect to
FIG. 4 d, there are also configurations using two dimensional meta-blocks that link block not only across planes and chips, but also in depth within a given plane.FIG. 21 shows an example of re-linking in the two-dimensional case. InFIG. 21 , the ‘2-D metablock’ is example of a 2*4 metablock. The maximum benefit in performance can be achieved when all 8 blocks can be accessed in parallel. The main linking and re-linking principles of 1-D linking methods also apply, but with some extensions. As can be seen in the figure, a bad physical block in any of the physical blocks within a plane lead to a metablock being unused, as is shown for Metablock n. When a 2-D metablock is re-linked, as for the upper block of Metablock n+2 inplane 2, only the bad physical block in a given plane needs to be replaced; for example, for the upper block of Metablock n+2 inplane 2 is re-linked while the lower block of Metablock n+2 inplane 2 is not. - In the embodiment where only the deviations from the standard linking are maintained in a record in the non-volatile memory, the management data structures for metablock linking can be contained within two types of sectors in one or more dedicated block linkage management blocks in flash memory. This arrangement has the advantage, with respect to saving the complete linking, of requiring the storage of less information. Metablock numbers of every re-linked metablock in the memory system are contained in a link table in a set of link table sectors. No entries for standard metablocks need be stored in the link table, because their physical block addresses are generated deterministically from the metablock number. An RF (re-linked) flag can be used as an attribute of a meta-block, indicating whether the block is standard, and all the blocks are linked in a standard fashion, or whether it is re-linked and requires additional block address translation through the link table (LT). The RF flag can be determined by analyzing the LT and then stored in SRAM, or else stored in a control data structure in the main non-volatile memory as an attribute for the meta-block. Alternately, a list of re-linked sectors can be keep in a list that can be searched through to determine which meta-blocks are re-linked. Entries in the link table can be ordered by metablock number, and each entry has fields for metablock number and block address of each linked physical block.
- In an extension of the link table structure, the deviations from the basic algorithm establishing the standard linking can themselves be based on a set of rules; for example, the non-standard linking could be limited to a single plane or limiting how far from its original row a block can be re-linked. Only when the re-linking is an exception to all of the algorithms need it be explicitly kept in the non-volatile memory.
- A particular example of a link table and how the information it contains can be compressed is described with respect to
FIG. 22 and Table 1. The Link Table sector holds information about blocks that have been re-linked within the card. Depending upon the size of the card and the number of bad blocks within each die, it is possible that there will be more than one Link Table sector present, which can be stored in the Boot Block block. As described above, meta-blocks have a standard method for linking and if one of the blocks is bad, then the meta-block may be able to be re-linked with a spare physical block in the same plane. The Link Tables sectors store the information about which blocks are used in the re-linking.FIG. 22 is another example of the re-linking of meta-blocks. - Of the metablocks shown in
FIG. 22 , only metablock 0 has the standard linking, here taken as straight across the eight planes. The figure shows several block linking situations: -
-
A. Metablock 0 is a standard metablock with no re-linking and would therefore not appear in a Link Table sector -
B. Metablock 1 has 2 bad blocks inplanes 0* and 1 -
C. Metablock 4 has 2 bad blocks inplanes -
D. Metablock 5 has 3 bad blocks inplanes -
E. Metablock 7 has 1 bad block inplane 0* -
F. Metablock 9 has been completely re-linked from existing spare physical blocks, although the blocks inplanes
In the cases marked * where the re-linking is due to a bad block inplane 0. In this case, the physical address refers to the location where the original metablock existed. Due to the large number of blocks in the example ofFIG. 22 , there are nometablocks
-
- The compression algorithm used for block re-linking shown in
FIG. 22 can be defined as in Table 1.TABLE 1 Repeated values to match Total Meta- number of items bytes block in Meta-block Number of re-linked Physical in Diagram number items in entry Plane address entry 2 bytes 1 byte 1 byte 2 bytes 1 0x0001 0x02 0x00 0x0002 0x01 0x0005 9 4 0x0004 0x02 0x00 0x0003 0x05 0x0001 9 5 0x0005 0x03 0x01 0x0004 0x03 0x0004 0x04 0x0007 12 7 0x0007 0x01 0x00 0x0006 6 9 0x0009 0x06 0x01 0x0008 0x02 0x0007 0x03 0x0007 0x04 0x0008 0x05 0x0008 0x06 0x0007 21
The size of any link table entry can be defined as:
Number of bytes=3+(3*number of re-linked blocks)
For example, formetablock 1, the first three bytes identifymetablock 1 and that it has two re-linkings, with three bytes being allotted to specify each of these re-linkings. The re-linkings are specified by which of the eight planes the re-linked block corresponds (1 byte) and the row number to which that it has been re-linked. - The full set of entries in the link table may be spread across multiple link table sectors. A link table sector is created or modified by writing it to the next available sector position in the block linkage management block. Multiple copies of a link table sector may therefore exist, with only the latest version being valid. An index to the positions of valid link table sectors in the block linkage management block can be contained in a field in the spare physical block list sector in the block linkage management block, which is described below. The metablock number relating to the first entry in each valid link table sector can be held in a list in controller RAM, to allow easy identification of the relevant link table sector for any metablock number. If an additional entry must be added to a link table sector which already contains the maximum number of entries, the sector is split into two new sectors, each with half the entries, and the new entry is inserted in the appropriate new sector.
- The block addresses of all spare physical blocks are held as entries in an unordered list in the spare physical block list sector. In some embodiments, it may be convenient to limit the maximum number of spare blocks per plane per chip. In an exemplary embodiment, this is limited to 16, as in most cases this should be large enough. If there are more than 16 spare blocks in a plane, they will be “lost”.
- Blocks that become spare, because either a standard metablock cannot be created during initial configuration of the flash memory into metablocks or because a physical block linked into a standard or re-linked metablock has failed, are added as new entries to the end of the spare physical block list. When a spare block is required for creation of a re-linked metablock, the first block in the relevant plane closest to the beginning of the spare physical block list can be used. The spare physical block list sector also contains a field with an index to valid link table sector locations.
- When a metablock re-link operation takes place and link table sectors are created or modified, the spare physical block list and link table sector index fields can both be modified in the spare physical block list sector. A valid spare physical block list sector is therefore the last written sector in the block linkage management block. When the block linkage management block is full, it can be compacted during a control write operation by rewriting all valid sectors to a new block location, and the full block can be subsequently erased.
- To simplify the saving of spare physical block sectors and limit the amount of searching that is required when looking for a replacement block the spare physical block list can be stored by chip, die, and plane. The actual number of sectors required depends on the size of memory device, number of devices, and the interleaving method used. As noted above, it may be convenient to store only a certain number of physical blocks per plane. The number held will depend upon the expected failure rate of blocks and the number of blocks per plane. This means that each spare physical block list sector will hold the spare physical blocks for several planes. The firmware will calculate the correct sector to load and then index into the sector to load the correct values.
- When the number of spare physical block lists changes due to re-linking or another bad block being found, a new spare physical block list sector will be written. This may mean two spare physical block list sectors covering the same physical area. The Boot Sector holds the spare physical block list Indices containing the index of the valid sector. If no spare physical blocks exist in an area covered by a spare physical block list, then the sector will not exist in the Boot Block.
- Referring back to
FIG. 22 , this refers to an 8 way interleaved card. There will therefore have to be at least 8 arrays to hold all the spare physical block list information. For every subsequent die on the card there will be an additional 8 arrays required. The spare physical block list corresponding toFIG. 22 is shown in Table 2.TABLE 2 Plane 0 0x08 1 2 0x01 0x04 0x08 3 0x01 0x08 0x09 4 0x01 0x04 0x05 5 0x04 0x07 0x09 6 0x01 0x04 0x08 7 0x01 0x04 0x07
As with the linking table, the spare physical block list can be stored as a table in non-volatile memory which can be cached into volatile RAM upon demand. - Although the various aspects of the present invention have been described in terms of a firmware based implementation, they may also be implemented in a hardware based implementation. A hardware engine on the controller or, preferably, on a memory chip itself can do the re-linking. The re-linking information can be stored on the chip itself at a special memory location. The controller can then treat all the blocks as standard, and the engine will translate the block addresses to the true internal addresses. The memory will appear to the host (or controller) as a memory with only standard blocks, or as a memory with large physical blocks, without having to know about either the smaller block structures or the details of any re-linking.
- Although specific examples of various aspects of the present invention have been described, it is understood that the present invention is entitled to protection within the scope of the appended claims.
Claims (43)
Priority Applications (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/750,157 US20050144516A1 (en) | 2003-12-30 | 2003-12-30 | Adaptive deterministic grouping of blocks into multi-block units |
AT04814563T ATE451694T1 (en) | 2003-12-30 | 2004-12-15 | ADAPTIVE DETERMINISTIC GROUPING OF BLOCKS INTO MULTI-BLOCK UNITS |
CN2004800416810A CN1930635B (en) | 2003-12-30 | 2004-12-15 | Adaptive deterministic grouping of blocks into multi-block units |
DE602004024582T DE602004024582D1 (en) | 2003-12-30 | 2004-12-15 | ADAPTIVE DETERMINIST GROUPING OF BLOCKS IN MULTIPLE BLOCKS |
KR1020067013306A KR20060120231A (en) | 2003-12-30 | 2004-12-15 | Adaptive deterministic grouping of blocks into multi-block units |
JP2006547154A JP4960705B2 (en) | 2003-12-30 | 2004-12-15 | Adaptive deterministic grouping of blocks into multi-block units |
EP04814563A EP1700313B1 (en) | 2003-12-30 | 2004-12-15 | Adaptive deterministic grouping of blocks into multi-block units |
PCT/US2004/042400 WO2005066974A1 (en) | 2003-12-30 | 2004-12-15 | Adaptive deterministic grouping of blocks into multi-block units |
TW093140796A TWI294081B (en) | 2003-12-30 | 2004-12-27 | Memory system and operating method thereof |
US12/512,282 US7970985B2 (en) | 2003-12-30 | 2009-07-30 | Adaptive deterministic grouping of blocks into multi-block units |
US13/084,396 US8117381B2 (en) | 2003-12-30 | 2011-04-11 | Adaptive deterministic grouping of blocks into multi-block units |
US14/738,489 US20150309927A1 (en) | 2003-12-30 | 2015-06-12 | Hybrid Non-Volatile Memory System |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/750,157 US20050144516A1 (en) | 2003-12-30 | 2003-12-30 | Adaptive deterministic grouping of blocks into multi-block units |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/512,282 Division US7970985B2 (en) | 2003-12-30 | 2009-07-30 | Adaptive deterministic grouping of blocks into multi-block units |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050144516A1 true US20050144516A1 (en) | 2005-06-30 |
Family
ID=34701162
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/750,157 Abandoned US20050144516A1 (en) | 2003-12-30 | 2003-12-30 | Adaptive deterministic grouping of blocks into multi-block units |
US12/512,282 Expired - Fee Related US7970985B2 (en) | 2003-12-30 | 2009-07-30 | Adaptive deterministic grouping of blocks into multi-block units |
US13/084,396 Expired - Fee Related US8117381B2 (en) | 2003-12-30 | 2011-04-11 | Adaptive deterministic grouping of blocks into multi-block units |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/512,282 Expired - Fee Related US7970985B2 (en) | 2003-12-30 | 2009-07-30 | Adaptive deterministic grouping of blocks into multi-block units |
US13/084,396 Expired - Fee Related US8117381B2 (en) | 2003-12-30 | 2011-04-11 | Adaptive deterministic grouping of blocks into multi-block units |
Country Status (9)
Country | Link |
---|---|
US (3) | US20050144516A1 (en) |
EP (1) | EP1700313B1 (en) |
JP (1) | JP4960705B2 (en) |
KR (1) | KR20060120231A (en) |
CN (1) | CN1930635B (en) |
AT (1) | ATE451694T1 (en) |
DE (1) | DE602004024582D1 (en) |
TW (1) | TWI294081B (en) |
WO (1) | WO2005066974A1 (en) |
Cited By (157)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050188147A1 (en) * | 2004-01-28 | 2005-08-25 | Tomoharu Tanaka | Non-volatile semiconductor memory system |
US20060053252A1 (en) * | 2004-08-30 | 2006-03-09 | Stefano Ghezzi | Embedded storage device with integrated data-management functions and storage system incorporating it |
US20060161728A1 (en) * | 2005-01-20 | 2006-07-20 | Bennett Alan D | Scheduling of housekeeping operations in flash memory systems |
US20070033376A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Data Consolidation and Garbage Collection in Direct Data File Storage Memories |
US20070033331A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | NonVolatile Memory With Block Management |
US20070033332A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Methods of Managing Blocks in NonVolatile Memory |
US20070159897A1 (en) * | 2006-01-06 | 2007-07-12 | Dot Hill Systems Corp. | Method and apparatus for preventing permanent data loss due to single failure of a fault tolerant array |
US20070198769A1 (en) * | 2006-02-17 | 2007-08-23 | Samsung Electronics Co., Ltd. | Method and apparatus for managing blocks according to update type of data in block-type memory |
US20070201289A1 (en) * | 2006-02-24 | 2007-08-30 | Samsung Electronics Co. Ltd. | Embedded memory and methods thereof |
US20070245070A1 (en) * | 2006-04-17 | 2007-10-18 | Takuma Mitsunaga | Memory controller and flash memory system |
US20080010510A1 (en) * | 2006-06-19 | 2008-01-10 | Tony Turner | Method and system for using multiple memory regions for redundant remapping |
US20080052446A1 (en) * | 2006-08-28 | 2008-02-28 | Sandisk Il Ltd. | Logical super block mapping for NAND flash memory |
US20080101119A1 (en) * | 2006-10-31 | 2008-05-01 | Hynix Semiconductor Inc. | Non-volatile memory device and method of erasing the same |
US20080162612A1 (en) * | 2006-12-28 | 2008-07-03 | Andrew Tomlin | Method for block relinking |
US20080162787A1 (en) * | 2006-12-28 | 2008-07-03 | Andrew Tomlin | System for block relinking |
WO2008082950A1 (en) * | 2006-12-28 | 2008-07-10 | Sandisk Corporation | System for block relinking |
US20080189493A1 (en) * | 2005-12-28 | 2008-08-07 | Fujitsu Limited | Memory controlling method, program and device |
US20080209107A1 (en) * | 2007-02-26 | 2008-08-28 | Micron Technology, Inc. | Apparatus, method, and system of NAND defect management |
US20080273388A1 (en) * | 2007-03-21 | 2008-11-06 | Henry Chin | Adjusting resistance of non-volatile memory using dummy memory cells |
US7464306B1 (en) * | 2004-08-27 | 2008-12-09 | Lexar Media, Inc. | Status of overall health of nonvolatile memory |
US20090006436A1 (en) * | 2007-06-29 | 2009-01-01 | Alqudah Yazan A | Automated yield analysis system |
US20090043948A1 (en) * | 2005-04-15 | 2009-02-12 | Thomson Licensing Llc | Method and System for Storing Logical Data Blocks Into Flash-Blocks in Multiple Non-Volatile Memories Which Are Connected to At Least One Common Data I/0 Bus |
US20090059695A1 (en) * | 2007-09-04 | 2009-03-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device and block management method of the same |
US20090059667A1 (en) * | 2007-08-27 | 2009-03-05 | Samsung Electronics Co., Ltd. | Memory cell array and non-volatile memory device |
US20090070547A1 (en) * | 2007-09-11 | 2009-03-12 | Samsung Electronics Co., Ltd. | Method and apparatus for performing address mapping in virtual file system of storage unit having a plurality of non-volatile data storage media |
US20090070518A1 (en) * | 2007-09-07 | 2009-03-12 | Shai Traister | Adaptive Block List Management |
US20090089482A1 (en) * | 2007-09-28 | 2009-04-02 | Shai Traister | Dynamic metablocks |
US7536627B2 (en) | 2005-12-27 | 2009-05-19 | Sandisk Corporation | Storing downloadable firmware on bulk media |
US7546515B2 (en) | 2005-12-27 | 2009-06-09 | Sandisk Corporation | Method of storing downloadable firmware on bulk media |
US20090182932A1 (en) * | 2008-01-11 | 2009-07-16 | Phison Electronics Corp. | Method for managing flash memory blocks and controller using the same |
US20090292876A1 (en) * | 2008-05-22 | 2009-11-26 | Winbond Electronics Corporation | In-System Programming to Switch Memory Access from One Area to Another in Memory Cards |
US20100023677A1 (en) * | 2008-07-28 | 2010-01-28 | Shin Young Kyun | Solid state storage system that evenly allocates data writing/erasing operations among blocks and method of controlling the same |
US20100095148A1 (en) * | 2008-10-15 | 2010-04-15 | Silicon Motion, Inc. | Link table recovery method |
US20100174847A1 (en) * | 2009-01-05 | 2010-07-08 | Alexander Paley | Non-Volatile Memory and Method With Write Cache Partition Management Methods |
US20100172180A1 (en) * | 2009-01-05 | 2010-07-08 | Alexander Paley | Non-Volatile Memory and Method With Write Cache Partitioning |
US20100174845A1 (en) * | 2009-01-05 | 2010-07-08 | Sergey Anatolievich Gorobets | Wear Leveling for Non-Volatile Memories: Maintenance of Experience Count and Passive Techniques |
US20100172179A1 (en) * | 2009-01-05 | 2010-07-08 | Sergey Anatolievich Gorobets | Spare Block Management of Non-Volatile Memories |
US20100174846A1 (en) * | 2009-01-05 | 2010-07-08 | Alexander Paley | Nonvolatile Memory With Write Cache Having Flush/Eviction Methods |
US20100195398A1 (en) * | 2006-12-30 | 2010-08-05 | Deepak Chandra Sekar | Applying different body bias to different substrate portions for non-volatile storage |
CN101819821A (en) * | 2010-03-25 | 2010-09-01 | 清华大学深圳研究生院 | Dynamic loss balancing method for solid state disk |
US20100228928A1 (en) * | 2009-03-04 | 2010-09-09 | Micron Technology, Inc. | Memory block selection |
US20100306451A1 (en) * | 2009-06-01 | 2010-12-02 | Joshua Johnson | Architecture for nand flash constraint enforcement |
US20100313097A1 (en) * | 2009-06-04 | 2010-12-09 | Lsi Corporation | Flash Memory Organization |
US20100313100A1 (en) * | 2009-06-04 | 2010-12-09 | Lsi Corporation | Flash Memory Organization |
EP2260391A1 (en) * | 2008-03-01 | 2010-12-15 | Kabushiki Kaisha Toshiba | Memory system |
US20110022779A1 (en) * | 2009-07-24 | 2011-01-27 | Lsi Corporation | Skip Operations for Solid State Disks |
US20110022784A1 (en) * | 2008-03-01 | 2011-01-27 | Kabushiki Kaisha Toshiba | Memory system |
US20110055626A1 (en) * | 2008-05-15 | 2011-03-03 | The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations | Systems and methods for recovering information from nand gates array memory systems |
US20110072198A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Accessing logical-to-physical address translation data for solid state disks |
US20110087855A1 (en) * | 2009-08-11 | 2011-04-14 | Texas Memory Systems, Inc. | Method and Apparatus for Protecting Data Using Variable Size Page Stripes in a FLASH-Based Storage System |
US20110087890A1 (en) * | 2009-10-09 | 2011-04-14 | Lsi Corporation | Interlocking plain text passwords to data encryption keys |
US20110131346A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Context Processing for Multiple Active Write Commands in a Media Controller Architecture |
US20110145475A1 (en) * | 2009-12-15 | 2011-06-16 | International Business Machines Corporation | Reducing access contention in flash-based memory systems |
US20110161552A1 (en) * | 2009-12-30 | 2011-06-30 | Lsi Corporation | Command Tracking for Direct Access Block Storage Devices |
US20110197037A1 (en) * | 2008-07-08 | 2011-08-11 | Siliconmotion Inc. | Downgrade memory apparatus, and method for accessing a downgrade memory |
US20110238971A1 (en) * | 2008-09-30 | 2011-09-29 | Jin Gyu Heo | Method of managing a solid state drive, associated systems and implementations |
US20110307646A1 (en) * | 2008-06-13 | 2011-12-15 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US20110314234A1 (en) * | 2010-06-17 | 2011-12-22 | Oki Semiconductor Co., Ltd. | Multi-chip package semiconductor memory device |
US20120005451A1 (en) * | 2010-07-02 | 2012-01-05 | Samsung Electronics Co., Ltd | Data storage device and bad block managing method thereof |
US20120079169A1 (en) * | 2010-09-27 | 2012-03-29 | Yang-Chih Shen | Method for performing meta block management, and associated memory device and controller thereof |
JP2012519900A (en) * | 2009-03-04 | 2012-08-30 | マイクロン テクノロジー, インク. | Memory block management |
US20120246383A1 (en) * | 2011-03-24 | 2012-09-27 | Kabushiki Kaisha Toshiba | Memory system and computer program product |
US20120284469A1 (en) * | 2011-05-03 | 2012-11-08 | Seo Dong-Young | Memory system and bad block management method |
WO2012158521A1 (en) | 2011-05-17 | 2012-11-22 | Sandisk Technologies Inc. | Non-volatile memory and method having block management with hot/cold data sorting |
WO2012158514A1 (en) | 2011-05-17 | 2012-11-22 | Sandisk Technologies Inc. | Non-volatile memory and method with small logical groups distributed among active slc and mlc memory partitions |
TWI399642B (en) * | 2005-08-03 | 2013-06-21 | Sandisk Technologies Inc | Nonvolatile memory with block management |
US20130205102A1 (en) * | 2012-02-07 | 2013-08-08 | SMART Storage Systems, Inc. | Storage control system with erase block mechanism and method of operation thereof |
TWI425357B (en) * | 2010-09-27 | 2014-02-01 | Silicon Motion Inc | Method for performing block management, and associated memory device and controller thereof |
US20140063952A1 (en) * | 2012-08-31 | 2014-03-06 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US8700961B2 (en) | 2011-12-20 | 2014-04-15 | Sandisk Technologies Inc. | Controller and method for virtual LUN assignment for improved memory bank mapping |
US20140149804A1 (en) * | 2011-01-13 | 2014-05-29 | Micron Technology, Inc. | Determining location of error detection data |
US20140181621A1 (en) * | 2012-12-26 | 2014-06-26 | Skymedi Corporation | Method of arranging data in a non-volatile memory and a memory control system thereof |
US20140237168A1 (en) * | 2007-12-27 | 2014-08-21 | Sandisk Enterprise Ip Llc | Mass Storage Controller Volatile Memory Containing Metadata Related to Flash Memory Storage |
US8904089B2 (en) | 2010-12-31 | 2014-12-02 | Silicon Motion Inc. | Method for performing block management/Flash memory management, and associated memory device and controller thereof |
US9021319B2 (en) | 2011-09-02 | 2015-04-28 | SMART Storage Systems, Inc. | Non-volatile memory management system with load leveling and method of operation thereof |
US9063844B2 (en) | 2011-09-02 | 2015-06-23 | SMART Storage Systems, Inc. | Non-volatile memory management system with time measure mechanism and method of operation thereof |
US9098399B2 (en) | 2011-08-31 | 2015-08-04 | SMART Storage Systems, Inc. | Electronic system with storage management mechanism and method of operation thereof |
US9123445B2 (en) | 2013-01-22 | 2015-09-01 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US9141528B2 (en) | 2011-05-17 | 2015-09-22 | Sandisk Technologies Inc. | Tracking and handling of super-hot data in non-volatile memory systems |
US9146850B2 (en) | 2013-08-01 | 2015-09-29 | SMART Storage Systems, Inc. | Data storage system with dynamic read threshold mechanism and method of operation thereof |
US9152555B2 (en) | 2013-11-15 | 2015-10-06 | Sandisk Enterprise IP LLC. | Data management with modular erase in a data storage system |
US9170941B2 (en) | 2013-04-05 | 2015-10-27 | Sandisk Enterprises IP LLC | Data hardening in a storage system |
US9183137B2 (en) | 2013-02-27 | 2015-11-10 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US20150339223A1 (en) * | 2014-05-22 | 2015-11-26 | Kabushiki Kaisha Toshiba | Memory system and method |
KR101573089B1 (en) * | 2007-07-03 | 2015-11-30 | 마이크론 테크놀로지, 인크. | Block addressing for parallel memory arrays |
US9214965B2 (en) | 2013-02-20 | 2015-12-15 | Sandisk Enterprise Ip Llc | Method and system for improving data integrity in non-volatile storage |
US9244519B1 (en) | 2013-06-25 | 2016-01-26 | Smart Storage Systems. Inc. | Storage system with data transfer rate adjustment for power throttling |
US9262077B2 (en) * | 2009-05-18 | 2016-02-16 | Samsung Electronics Co., Ltd. | Solid state drive device |
CN105488722A (en) * | 2015-11-30 | 2016-04-13 | 布比(北京)网络技术有限公司 | Asset data processing method and device based on derivation chain |
US9329928B2 (en) | 2013-02-20 | 2016-05-03 | Sandisk Enterprise IP LLC. | Bandwidth optimization in a non-volatile memory system |
US9355929B2 (en) | 2012-04-25 | 2016-05-31 | Sandisk Technologies Inc. | Data storage based upon temperature considerations |
US9361222B2 (en) | 2013-08-07 | 2016-06-07 | SMART Storage Systems, Inc. | Electronic system with storage drive life estimation mechanism and method of operation thereof |
US9367353B1 (en) | 2013-06-25 | 2016-06-14 | Sandisk Technologies Inc. | Storage control system with power throttling mechanism and method of operation thereof |
US9431113B2 (en) | 2013-08-07 | 2016-08-30 | Sandisk Technologies Llc | Data storage system with dynamic erase block grouping mechanism and method of operation thereof |
US9430373B2 (en) | 2011-05-31 | 2016-08-30 | Micron Technology, Inc. | Apparatus including memory channel control circuit and related methods for relaying commands to logical units |
US9436831B2 (en) | 2013-10-30 | 2016-09-06 | Sandisk Technologies Llc | Secure erase in a memory device |
US9442662B2 (en) | 2013-10-18 | 2016-09-13 | Sandisk Technologies Llc | Device and method for managing die groups |
US9443601B2 (en) | 2014-09-08 | 2016-09-13 | Sandisk Technologies Llc | Holdup capacitor energy harvesting |
US9448946B2 (en) | 2013-08-07 | 2016-09-20 | Sandisk Technologies Llc | Data storage system with stale data mechanism and method of operation thereof |
US9448876B2 (en) | 2014-03-19 | 2016-09-20 | Sandisk Technologies Llc | Fault detection and prediction in storage devices |
US9454420B1 (en) | 2012-12-31 | 2016-09-27 | Sandisk Technologies Llc | Method and system of reading threshold voltage equalization |
US9454448B2 (en) | 2014-03-19 | 2016-09-27 | Sandisk Technologies Llc | Fault testing in storage devices |
US9507523B1 (en) * | 2012-10-12 | 2016-11-29 | Western Digital Technologies, Inc. | Methods, devices and systems for variable size logical page management in a solid state drive |
US9520162B2 (en) | 2013-11-27 | 2016-12-13 | Sandisk Technologies Llc | DIMM device controller supervisor |
US9520197B2 (en) | 2013-11-22 | 2016-12-13 | Sandisk Technologies Llc | Adaptive erase of a storage device |
US9524235B1 (en) | 2013-07-25 | 2016-12-20 | Sandisk Technologies Llc | Local hash value generation in non-volatile data storage systems |
US9543025B2 (en) | 2013-04-11 | 2017-01-10 | Sandisk Technologies Llc | Storage control system with power-off time estimation mechanism and method of operation thereof |
US9582058B2 (en) | 2013-11-29 | 2017-02-28 | Sandisk Technologies Llc | Power inrush management of storage devices |
US9612948B2 (en) | 2012-12-27 | 2017-04-04 | Sandisk Technologies Llc | Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device |
US9626399B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Conditional updates for reducing frequency of data modification operations |
US9626292B2 (en) | 2013-06-17 | 2017-04-18 | Micron Technology, Inc. | Memory tile access and selection patterns |
US9626289B2 (en) | 2014-08-28 | 2017-04-18 | Sandisk Technologies Llc | Metalblock relinking to physical blocks of semiconductor memory in adaptive wear leveling based on health |
US9626400B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Compaction of information in tiered data structure |
US9632712B2 (en) | 2014-07-02 | 2017-04-25 | Sandisk Technologies Llc | System and method of updating metablocks associated with multiple memory dies |
US9639463B1 (en) | 2013-08-26 | 2017-05-02 | Sandisk Technologies Llc | Heuristic aware garbage collection scheme in storage systems |
US9652381B2 (en) | 2014-06-19 | 2017-05-16 | Sandisk Technologies Llc | Sub-block garbage collection |
US9671962B2 (en) | 2012-11-30 | 2017-06-06 | Sandisk Technologies Llc | Storage control system with data management mechanism of parity and method of operation thereof |
US9697267B2 (en) | 2014-04-03 | 2017-07-04 | Sandisk Technologies Llc | Methods and systems for performing efficient snapshots in tiered data structures |
US9699263B1 (en) | 2012-08-17 | 2017-07-04 | Sandisk Technologies Llc. | Automatic read and write acceleration of data accessed by virtual machines |
US9703636B2 (en) | 2014-03-01 | 2017-07-11 | Sandisk Technologies Llc | Firmware reversion trigger and control |
US9703816B2 (en) | 2013-11-19 | 2017-07-11 | Sandisk Technologies Llc | Method and system for forward reference logging in a persistent datastore |
US9703491B2 (en) | 2014-05-30 | 2017-07-11 | Sandisk Technologies Llc | Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device |
US9870830B1 (en) | 2013-03-14 | 2018-01-16 | Sandisk Technologies Llc | Optimal multilevel sensing for reading data from a storage medium |
US9875053B2 (en) | 2015-06-05 | 2018-01-23 | Western Digital Technologies, Inc. | Scheduling scheme(s) for a multi-die storage device |
CN108196795A (en) * | 2017-12-30 | 2018-06-22 | 惠龙易通国际物流股份有限公司 | A kind of date storage method, equipment and computer storage media |
US20180188960A1 (en) * | 2016-12-30 | 2018-07-05 | Intel Corporation | Method and apparatus for redirecting memory access commands sent to unusable memory partitions |
US10049037B2 (en) | 2013-04-05 | 2018-08-14 | Sandisk Enterprise Ip Llc | Data management in a storage system |
US20180267895A1 (en) * | 2017-03-17 | 2018-09-20 | SK Hynix Inc. | Memory system |
US10114557B2 (en) | 2014-05-30 | 2018-10-30 | Sandisk Technologies Llc | Identification of hot regions to enhance performance and endurance of a non-volatile storage device |
US10126970B2 (en) * | 2015-12-11 | 2018-11-13 | Sandisk Technologies Llc | Paired metablocks in non-volatile storage device |
TWI641988B (en) * | 2017-07-21 | 2018-11-21 | 慧榮科技股份有限公司 | Method for performing programming management in a memory device, and associated memory device and controller thereof |
US10146448B2 (en) | 2014-05-30 | 2018-12-04 | Sandisk Technologies Llc | Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device |
US10162748B2 (en) | 2014-05-30 | 2018-12-25 | Sandisk Technologies Llc | Prioritizing garbage collection and block allocation based on I/O history for logical address regions |
US20180373438A1 (en) * | 2017-06-26 | 2018-12-27 | Western Digital Technologies, Inc. | Dynamically resizing logical storage blocks |
US10223022B2 (en) * | 2017-01-27 | 2019-03-05 | Western Digital Technologies, Inc. | System and method for implementing super word line zones in a memory device |
US10229751B2 (en) | 2017-05-01 | 2019-03-12 | Western Digital Technologies, Inc. | Storage system and method for bad block recycling |
US10289327B2 (en) | 2015-06-05 | 2019-05-14 | Western Digital Technologies, Inc. | Scheduling scheme(s) for a multi-die storage device |
US20190171576A1 (en) * | 2017-12-01 | 2019-06-06 | Micron Technology, Inc. | Logical block mapping based on an offset |
CN109933467A (en) * | 2017-12-18 | 2019-06-25 | 爱思开海力士有限公司 | Storage system and its operating method |
US10372613B2 (en) | 2014-05-30 | 2019-08-06 | Sandisk Technologies Llc | Using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device |
US20190377514A1 (en) * | 2018-06-06 | 2019-12-12 | Phison Electronics Corp. | Memory management method, memory control circuit unit and memory storage apparatus |
CN110609795A (en) * | 2018-06-14 | 2019-12-24 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
US10546648B2 (en) | 2013-04-12 | 2020-01-28 | Sandisk Technologies Llc | Storage control system with data management mechanism and method of operation thereof |
CN111061653A (en) * | 2018-10-16 | 2020-04-24 | 爱思开海力士有限公司 | Data storage device and operation method thereof |
US10635515B2 (en) | 2017-12-06 | 2020-04-28 | Sandisk Technologies Llc | Recovery of partial memory die |
US10656842B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device |
US10656840B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Real-time I/O pattern recognition to enhance performance and endurance of a storage device |
CN111208939A (en) * | 2018-11-22 | 2020-05-29 | 爱思开海力士有限公司 | Memory system and operation method of memory system |
US20210055878A1 (en) * | 2019-08-20 | 2021-02-25 | Micron Technology, Inc. | Data compaction within the same plane of a memory component |
US20210365200A1 (en) * | 2020-05-21 | 2021-11-25 | Western Digital Technologies, Inc. | Use Of Surplus Erase Block Pairs In Super Block Formation |
US11436154B2 (en) | 2017-12-01 | 2022-09-06 | Micron Technology, Inc. | Logical block mapping based on an offset |
CN115687171A (en) * | 2022-10-26 | 2023-02-03 | 深圳三地一芯电子有限责任公司 | Flash block binding method, device, equipment and storage medium |
US20230103004A1 (en) * | 2021-09-29 | 2023-03-30 | Yangtze Memory Technologies Co., Ltd. | Data protection method for memory and storage device thereof |
US11698742B2 (en) | 2019-08-28 | 2023-07-11 | Micron Technology, Inc. | Garbage collection in a memory component using an adjusted parameter |
US11726908B2 (en) | 2019-08-20 | 2023-08-15 | Micron Technology, Inc. | Garbage collection in a memory sub-system during a low battery state |
US11726869B2 (en) | 2019-08-20 | 2023-08-15 | Micron Technology, Inc. | Performing error control operation on memory component for garbage collection |
US11776615B2 (en) | 2019-08-20 | 2023-10-03 | Micron Technology, Inc. | Sequential SLC read optimization |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7441068B2 (en) | 2006-01-06 | 2008-10-21 | Phison Electronics Corp. | Flash memory and method for utilizing the same |
GB2434460B (en) * | 2006-01-24 | 2007-12-05 | Phison Electronics Corp | Flash memory and method for utilizing the same |
KR100809069B1 (en) * | 2006-11-03 | 2008-03-03 | 삼성전자주식회사 | Optical disk drive having non-volatile memory and method of operating the same |
DE112007003388T5 (en) * | 2007-03-21 | 2009-12-24 | Intel Corporation, Santa Clara | Method for managing sectors of a non-volatile memory |
US9373362B2 (en) * | 2007-08-14 | 2016-06-21 | Dell Products L.P. | System and method for implementing a memory defect map |
KR101372245B1 (en) * | 2007-08-30 | 2014-03-10 | 삼성전자주식회사 | Architecture of memory cell array, non-volatile memory device having the same, and method of constructing a memory cell array |
JP4632180B2 (en) | 2008-10-15 | 2011-02-16 | Tdk株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
US8214579B2 (en) | 2008-09-30 | 2012-07-03 | Tdk Corporation | Memory controller, flash memory system with memory controller, and method of controlling flash memory |
JP4720891B2 (en) * | 2008-09-30 | 2011-07-13 | Tdk株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
JP4582232B2 (en) * | 2008-09-30 | 2010-11-17 | Tdk株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
JP2010092200A (en) * | 2008-10-07 | 2010-04-22 | Tdk Corp | Memory controller, flash memory system equipped with memory controller and method of controlling flash memory |
US8261174B2 (en) | 2009-01-13 | 2012-09-04 | International Business Machines Corporation | Protecting and migrating memory lines |
JP4762323B2 (en) | 2009-03-03 | 2011-08-31 | 富士通株式会社 | Access control apparatus, information processing apparatus, access control program, and access control method |
US8688894B2 (en) * | 2009-09-03 | 2014-04-01 | Pioneer Chip Technology Ltd. | Page based management of flash storage |
TWI547872B (en) * | 2010-04-01 | 2016-09-01 | 鴻海精密工業股份有限公司 | Media data playback device and reboot method thereof |
CN102456401B (en) * | 2010-10-26 | 2015-04-22 | 群联电子股份有限公司 | Block management method, memory controller and memory storage device |
CN102479156B (en) * | 2010-11-22 | 2015-03-11 | 慧荣科技股份有限公司 | Method for carrying out block management and memory device and controller thereof |
CN102479154B (en) * | 2010-11-30 | 2015-03-11 | 慧荣科技股份有限公司 | Superblock management method, memory device and controller of memory device |
US20120262815A1 (en) * | 2011-04-15 | 2012-10-18 | Lsi Corporation | Method and system for dynamically expandable software based bad block management |
KR101269557B1 (en) * | 2011-05-20 | 2013-06-04 | 연세대학교 산학협력단 | A semiconductor memory reparing device and a repairing method thereof |
US8924636B2 (en) * | 2012-02-23 | 2014-12-30 | Kabushiki Kaisha Toshiba | Management information generating method, logical block constructing method, and semiconductor memory device |
JP5952036B2 (en) * | 2012-03-13 | 2016-07-13 | 株式会社メガチップス | Semiconductor memory reuse processing apparatus and semiconductor memory |
JP5956791B2 (en) * | 2012-03-13 | 2016-07-27 | 株式会社メガチップス | Semiconductor memory reuse processing apparatus and semiconductor memory |
US8891305B2 (en) | 2012-08-21 | 2014-11-18 | Micron Technology, Inc. | Apparatuses and methods involving accessing distributed sub-blocks of memory cells |
US9032244B2 (en) * | 2012-11-16 | 2015-05-12 | Microsoft Technology Licensing, Llc | Memory segment remapping to address fragmentation |
CN104919433B (en) * | 2013-01-11 | 2017-10-31 | 英派尔科技开发有限公司 | The page for flash memory is distributed |
KR102225989B1 (en) | 2014-03-04 | 2021-03-10 | 삼성전자주식회사 | Nonvolatile memory system and operation method thereof |
US9595352B2 (en) * | 2014-03-17 | 2017-03-14 | Seagate Technology Llc | Manufacturer self-test for solid-state drives |
KR102257031B1 (en) | 2015-03-13 | 2021-05-27 | 삼성전자주식회사 | Method for designing a semiconductor integrated circuit |
WO2017170679A1 (en) * | 2016-03-31 | 2017-10-05 | 株式会社bitFlyer | Private node, processing method for private node, and program for same |
CN106372533B (en) * | 2016-09-14 | 2020-04-21 | 中国银联股份有限公司 | Content storage method based on block chain technology |
CN106529924A (en) * | 2016-09-29 | 2017-03-22 | 马龙 | Color block chain management method and management system |
KR20180047329A (en) * | 2016-10-31 | 2018-05-10 | 에스케이하이닉스 주식회사 | Memory system and opration method for the same |
KR20180047778A (en) | 2016-11-01 | 2018-05-10 | 삼성전자주식회사 | Memory device with stepwise low power states |
CN106844523B (en) * | 2016-12-29 | 2020-05-08 | 北京瑞卓喜投科技发展有限公司 | Generation method and system of sequential multi-dimensional expanded block chain |
CN106874440B (en) * | 2017-02-07 | 2019-11-12 | 杭州秘猿科技有限公司 | A kind of block chain state storage method based on SQL database |
KR102395434B1 (en) * | 2017-03-20 | 2022-05-09 | 삼성전자주식회사 | Nonvolatile memory device and memory system including the same |
CN107451011B (en) * | 2017-03-24 | 2020-12-25 | 北京瑞卓喜投科技发展有限公司 | Error correction method and system for block chain of parallel added blocks |
TWI646554B (en) * | 2017-03-28 | 2019-01-01 | 慧榮科技股份有限公司 | Data storage device and operating method therefor |
DE102017209381A1 (en) * | 2017-06-02 | 2018-12-06 | Bundesdruckerei Gmbh | Bidirectionally linked blockchain structure |
TWI617917B (en) * | 2017-08-28 | 2018-03-11 | 慧榮科技股份有限公司 | Data storage method for optimizing data storage device and its data storage device |
US10445230B2 (en) * | 2017-12-08 | 2019-10-15 | Macronix International Co., Ltd. | Managing block arrangement of super blocks |
KR20190072306A (en) | 2017-12-15 | 2019-06-25 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
US10372355B2 (en) * | 2017-12-29 | 2019-08-06 | Micron Technology, Inc. | Managing partial superblocks in a NAND device |
JP7051484B2 (en) | 2018-02-22 | 2022-04-11 | キオクシア株式会社 | Semiconductor memory |
CN108846749B (en) * | 2018-05-31 | 2021-09-07 | 杭州溪塔科技有限公司 | Partitioned transaction execution system and method based on block chain technology |
CN108984645B (en) * | 2018-06-25 | 2021-02-02 | 百度在线网络技术(北京)有限公司 | Block chain processing method, device, equipment and storage medium |
CN109032802A (en) * | 2018-07-26 | 2018-12-18 | 国信优易数据有限公司 | A kind of block catenary system and management method |
KR102592803B1 (en) * | 2018-10-31 | 2023-10-24 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
US11416161B2 (en) | 2019-06-28 | 2022-08-16 | Western Digital Technologies, Inc. | Zone formation for zoned namespaces |
KR20210017481A (en) | 2019-08-08 | 2021-02-17 | 에스케이하이닉스 주식회사 | Controller and operation method thereof |
CN112530494B (en) * | 2019-09-17 | 2024-06-25 | 硅存储技术股份有限公司 | Nonvolatile memory device with stored index information |
CN113268519A (en) * | 2020-12-28 | 2021-08-17 | 上海能链众合科技有限公司 | Data sharing method based on block chain |
KR20220165074A (en) * | 2021-06-07 | 2022-12-14 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5428621A (en) * | 1992-09-21 | 1995-06-27 | Sundisk Corporation | Latent defect handling in EEPROM devices |
US5835935A (en) * | 1995-09-13 | 1998-11-10 | Lexar Media, Inc. | Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory |
US5978808A (en) * | 1995-12-27 | 1999-11-02 | Intel Corporation | Virtual small block file manager for flash memory array |
US6034897A (en) * | 1999-04-01 | 2000-03-07 | Lexar Media, Inc. | Space management for managing high capacity nonvolatile memory |
US6260156B1 (en) * | 1998-12-04 | 2001-07-10 | Datalight, Inc. | Method and system for managing bad areas in flash memory |
US6360293B1 (en) * | 1998-06-24 | 2002-03-19 | Oki Electric Industry Co., Ltd. | Solid state disk system having electrically erasable and programmable read only memory |
US20020049740A1 (en) * | 2000-08-17 | 2002-04-25 | International Business Machines Corporation | Method and system for detecting deviations in data tables |
US20020099904A1 (en) * | 2001-01-19 | 2002-07-25 | Conley Kevin M. | Partial block data programming and reading operations in a non-volatile memory |
US6426893B1 (en) * | 2000-02-17 | 2002-07-30 | Sandisk Corporation | Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
US6563734B2 (en) * | 2000-08-30 | 2003-05-13 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory device capable of executing erasable, writable and readable functions simultaneously |
US6574705B1 (en) * | 2000-11-16 | 2003-06-03 | International Business Machines Corporation | Data processing system and method including a logical volume manager for storing logical volume data |
US6581132B1 (en) * | 1997-12-16 | 2003-06-17 | Tdk Corporation | Flash memory system including a memory manager for managing data |
US6742078B1 (en) * | 1999-10-05 | 2004-05-25 | Feiya Technology Corp. | Management, data link structure and calculating method for flash memory |
US6763480B2 (en) * | 1989-04-13 | 2004-07-13 | Sandisk Corporation | Flash EEprom system |
US6901498B2 (en) * | 2002-12-09 | 2005-05-31 | Sandisk Corporation | Zone boundary adjustment for defects in non-volatile memories |
US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
US20060242212A1 (en) * | 2002-08-08 | 2006-10-26 | Andre Brinkmann | Method and arrangement for randomly storing data |
US7478096B2 (en) * | 2003-02-26 | 2009-01-13 | Burnside Acquisition, Llc | History preservation in a computer storage system |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3105092B2 (en) * | 1992-10-06 | 2000-10-30 | 株式会社東芝 | Semiconductor memory device |
WO1999032977A1 (en) * | 1997-12-22 | 1999-07-01 | Tdk Corporation | Flash memory system |
GB9903490D0 (en) | 1999-02-17 | 1999-04-07 | Memory Corp Plc | Memory system |
KR100330164B1 (en) * | 1999-04-27 | 2002-03-28 | 윤종용 | A method for simultaneously programming plural flash memories having invalid blocks |
JP4248772B2 (en) * | 2001-07-05 | 2009-04-02 | Tdk株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
JP4220690B2 (en) * | 2001-07-05 | 2009-02-04 | Tdk株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
JP2003058417A (en) * | 2001-08-21 | 2003-02-28 | Matsushita Electric Ind Co Ltd | Storage device |
GB0123412D0 (en) | 2001-09-28 | 2001-11-21 | Memquest Ltd | Memory system sectors |
JP2004265162A (en) * | 2003-03-03 | 2004-09-24 | Renesas Technology Corp | Storage device and address management method |
-
2003
- 2003-12-30 US US10/750,157 patent/US20050144516A1/en not_active Abandoned
-
2004
- 2004-12-15 KR KR1020067013306A patent/KR20060120231A/en not_active Application Discontinuation
- 2004-12-15 DE DE602004024582T patent/DE602004024582D1/en active Active
- 2004-12-15 CN CN2004800416810A patent/CN1930635B/en not_active Expired - Fee Related
- 2004-12-15 JP JP2006547154A patent/JP4960705B2/en active Active
- 2004-12-15 WO PCT/US2004/042400 patent/WO2005066974A1/en active Application Filing
- 2004-12-15 AT AT04814563T patent/ATE451694T1/en not_active IP Right Cessation
- 2004-12-15 EP EP04814563A patent/EP1700313B1/en not_active Not-in-force
- 2004-12-27 TW TW093140796A patent/TWI294081B/en not_active IP Right Cessation
-
2009
- 2009-07-30 US US12/512,282 patent/US7970985B2/en not_active Expired - Fee Related
-
2011
- 2011-04-11 US US13/084,396 patent/US8117381B2/en not_active Expired - Fee Related
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6763480B2 (en) * | 1989-04-13 | 2004-07-13 | Sandisk Corporation | Flash EEprom system |
US5428621A (en) * | 1992-09-21 | 1995-06-27 | Sundisk Corporation | Latent defect handling in EEPROM devices |
US5835935A (en) * | 1995-09-13 | 1998-11-10 | Lexar Media, Inc. | Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory |
US5978808A (en) * | 1995-12-27 | 1999-11-02 | Intel Corporation | Virtual small block file manager for flash memory array |
US6581132B1 (en) * | 1997-12-16 | 2003-06-17 | Tdk Corporation | Flash memory system including a memory manager for managing data |
US6360293B1 (en) * | 1998-06-24 | 2002-03-19 | Oki Electric Industry Co., Ltd. | Solid state disk system having electrically erasable and programmable read only memory |
US6260156B1 (en) * | 1998-12-04 | 2001-07-10 | Datalight, Inc. | Method and system for managing bad areas in flash memory |
US6034897A (en) * | 1999-04-01 | 2000-03-07 | Lexar Media, Inc. | Space management for managing high capacity nonvolatile memory |
US6742078B1 (en) * | 1999-10-05 | 2004-05-25 | Feiya Technology Corp. | Management, data link structure and calculating method for flash memory |
US6426893B1 (en) * | 2000-02-17 | 2002-07-30 | Sandisk Corporation | Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
US20020049740A1 (en) * | 2000-08-17 | 2002-04-25 | International Business Machines Corporation | Method and system for detecting deviations in data tables |
US6563734B2 (en) * | 2000-08-30 | 2003-05-13 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory device capable of executing erasable, writable and readable functions simultaneously |
US6574705B1 (en) * | 2000-11-16 | 2003-06-03 | International Business Machines Corporation | Data processing system and method including a logical volume manager for storing logical volume data |
US20020099904A1 (en) * | 2001-01-19 | 2002-07-25 | Conley Kevin M. | Partial block data programming and reading operations in a non-volatile memory |
US6763424B2 (en) * | 2001-01-19 | 2004-07-13 | Sandisk Corporation | Partial block data programming and reading operations in a non-volatile memory |
US20060242212A1 (en) * | 2002-08-08 | 2006-10-26 | Andre Brinkmann | Method and arrangement for randomly storing data |
US6901498B2 (en) * | 2002-12-09 | 2005-05-31 | Sandisk Corporation | Zone boundary adjustment for defects in non-volatile memories |
US7478096B2 (en) * | 2003-02-26 | 2009-01-13 | Burnside Acquisition, Llc | History preservation in a computer storage system |
US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
Cited By (281)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090279365A1 (en) * | 2004-01-28 | 2009-11-12 | Tomoharu Tanaka | Non-volatile semiconductor memory system |
US20050188147A1 (en) * | 2004-01-28 | 2005-08-25 | Tomoharu Tanaka | Non-volatile semiconductor memory system |
US7464306B1 (en) * | 2004-08-27 | 2008-12-09 | Lexar Media, Inc. | Status of overall health of nonvolatile memory |
US7743290B2 (en) | 2004-08-27 | 2010-06-22 | Lexar Media, Inc. | Status of overall health of nonvolatile memory |
US20060053252A1 (en) * | 2004-08-30 | 2006-03-09 | Stefano Ghezzi | Embedded storage device with integrated data-management functions and storage system incorporating it |
US7565478B2 (en) | 2005-01-20 | 2009-07-21 | Sandisk Corporation | Scheduling of housekeeping operations in flash memory systems |
US20090265508A1 (en) * | 2005-01-20 | 2009-10-22 | Alan David Bennett | Scheduling of Housekeeping Operations in Flash Memory Systems |
US20080091872A1 (en) * | 2005-01-20 | 2008-04-17 | Bennett Alan D | Scheduling of Housekeeping Operations in Flash Memory Systems |
US8364883B2 (en) | 2005-01-20 | 2013-01-29 | Sandisk Technologies Inc. | Scheduling of housekeeping operations in flash memory systems |
US7315917B2 (en) | 2005-01-20 | 2008-01-01 | Sandisk Corporation | Scheduling of housekeeping operations in flash memory systems |
US20060161728A1 (en) * | 2005-01-20 | 2006-07-20 | Bennett Alan D | Scheduling of housekeeping operations in flash memory systems |
US20090043948A1 (en) * | 2005-04-15 | 2009-02-12 | Thomson Licensing Llc | Method and System for Storing Logical Data Blocks Into Flash-Blocks in Multiple Non-Volatile Memories Which Are Connected to At Least One Common Data I/0 Bus |
US8301825B2 (en) * | 2005-04-15 | 2012-10-30 | Thomson Licensing | Method and system for storing logical data blocks into flash-blocks in multiple non-volatile memories which are connected to at least one common data I/O bus |
TWI399642B (en) * | 2005-08-03 | 2013-06-21 | Sandisk Technologies Inc | Nonvolatile memory with block management |
US7450420B2 (en) | 2005-08-03 | 2008-11-11 | Sandisk Corporation | Reclaiming data storage capacity in flash memories |
US7552271B2 (en) * | 2005-08-03 | 2009-06-23 | Sandisk Corporation | Nonvolatile memory with block management |
US20070033376A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Data Consolidation and Garbage Collection in Direct Data File Storage Memories |
US20070033331A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | NonVolatile Memory With Block Management |
US20070033330A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Reclaiming Data Storage Capacity in Flash Memory Systems |
US20070033332A1 (en) * | 2005-08-03 | 2007-02-08 | Sinclair Alan W | Methods of Managing Blocks in NonVolatile Memory |
US7558906B2 (en) * | 2005-08-03 | 2009-07-07 | Sandisk Corporation | Methods of managing blocks in nonvolatile memory |
US7546515B2 (en) | 2005-12-27 | 2009-06-09 | Sandisk Corporation | Method of storing downloadable firmware on bulk media |
US7536627B2 (en) | 2005-12-27 | 2009-05-19 | Sandisk Corporation | Storing downloadable firmware on bulk media |
US8219881B2 (en) * | 2005-12-28 | 2012-07-10 | Fujitsu Limited | Memory controlling method, program and device |
US20080189493A1 (en) * | 2005-12-28 | 2008-08-07 | Fujitsu Limited | Memory controlling method, program and device |
US7774643B2 (en) * | 2006-01-06 | 2010-08-10 | Dot Hill Systems Corporation | Method and apparatus for preventing permanent data loss due to single failure of a fault tolerant array |
US20070159897A1 (en) * | 2006-01-06 | 2007-07-12 | Dot Hill Systems Corp. | Method and apparatus for preventing permanent data loss due to single failure of a fault tolerant array |
US20070198769A1 (en) * | 2006-02-17 | 2007-08-23 | Samsung Electronics Co., Ltd. | Method and apparatus for managing blocks according to update type of data in block-type memory |
US7702845B2 (en) * | 2006-02-17 | 2010-04-20 | Samsung Electronics Co., Ltd. | Method and apparatus for managing blocks according to update type of data in block-type memory |
US7518943B2 (en) * | 2006-02-24 | 2009-04-14 | Samsung Electronics Co., Ltd. | Embedded memory and methods thereof |
US20070201289A1 (en) * | 2006-02-24 | 2007-08-30 | Samsung Electronics Co. Ltd. | Embedded memory and methods thereof |
US7870328B2 (en) * | 2006-04-17 | 2011-01-11 | Tdk Corporation | Memory controller and flash memory system |
US20070245070A1 (en) * | 2006-04-17 | 2007-10-18 | Takuma Mitsunaga | Memory controller and flash memory system |
US20080010510A1 (en) * | 2006-06-19 | 2008-01-10 | Tony Turner | Method and system for using multiple memory regions for redundant remapping |
WO2008026204A2 (en) * | 2006-08-28 | 2008-03-06 | Sandisk Il Ltd. | Logical super block mapping for nand flash memory |
WO2008026204A3 (en) * | 2006-08-28 | 2008-06-19 | Sandisk Il Ltd | Logical super block mapping for nand flash memory |
US20080052446A1 (en) * | 2006-08-28 | 2008-02-28 | Sandisk Il Ltd. | Logical super block mapping for NAND flash memory |
US7623381B2 (en) * | 2006-10-31 | 2009-11-24 | Seong Hun Park | Non-volatile memory device and method of erasing the same |
US20080101119A1 (en) * | 2006-10-31 | 2008-05-01 | Hynix Semiconductor Inc. | Non-volatile memory device and method of erasing the same |
US20080162612A1 (en) * | 2006-12-28 | 2008-07-03 | Andrew Tomlin | Method for block relinking |
WO2008082950A1 (en) * | 2006-12-28 | 2008-07-10 | Sandisk Corporation | System for block relinking |
US20080162787A1 (en) * | 2006-12-28 | 2008-07-03 | Andrew Tomlin | System for block relinking |
US8164957B2 (en) | 2006-12-30 | 2012-04-24 | Sandisk Technologies Inc. | Reducing energy consumption when applying body bias to substrate having sets of nand strings |
USRE46498E1 (en) | 2006-12-30 | 2017-08-01 | Sandisk Technologies Llc | Reducing energy consumption when applying body bias to substrate having sets of NAND strings |
US20100195398A1 (en) * | 2006-12-30 | 2010-08-05 | Deepak Chandra Sekar | Applying different body bias to different substrate portions for non-volatile storage |
US8000146B2 (en) * | 2006-12-30 | 2011-08-16 | Sandisk Technologies Inc. | Applying different body bias to different substrate portions for non-volatile storage |
US20100153793A1 (en) * | 2007-02-26 | 2010-06-17 | Michael Murray | Apparatus, methods, and system of nand defect management |
US8365028B2 (en) | 2007-02-26 | 2013-01-29 | Micron Technology, Inc. | Apparatus, methods, and system of NAND defect management |
US7992060B2 (en) | 2007-02-26 | 2011-08-02 | Micron Technology, Inc. | Apparatus, methods, and system of NAND defect management |
US8621294B2 (en) * | 2007-02-26 | 2013-12-31 | Micron Technology, Inc. | Apparatus, methods, and system of NAND defect management |
WO2008106095A1 (en) * | 2007-02-26 | 2008-09-04 | Micron Technology, Inc. | Apparatus, method, system of nand defect management |
US20080209107A1 (en) * | 2007-02-26 | 2008-08-28 | Micron Technology, Inc. | Apparatus, method, and system of NAND defect management |
KR101576898B1 (en) | 2007-02-26 | 2015-12-11 | 마이크론 테크놀로지, 인크. | Apparatus method system of nand defect management |
US7669092B2 (en) | 2007-02-26 | 2010-02-23 | Micron Technology, Inc. | Apparatus, method, and system of NAND defect management |
US8892969B2 (en) | 2007-02-26 | 2014-11-18 | Micron Technology, Inc. | Apparatus, methods, and system of NAND defect management |
US20080273388A1 (en) * | 2007-03-21 | 2008-11-06 | Henry Chin | Adjusting resistance of non-volatile memory using dummy memory cells |
US7535764B2 (en) * | 2007-03-21 | 2009-05-19 | Sandisk Corporation | Adjusting resistance of non-volatile memory using dummy memory cells |
US20090006436A1 (en) * | 2007-06-29 | 2009-01-01 | Alqudah Yazan A | Automated yield analysis system |
US9436609B2 (en) | 2007-07-03 | 2016-09-06 | Micron Technology, Inc. | Block addressing for parallel memory arrays |
KR101573089B1 (en) * | 2007-07-03 | 2015-11-30 | 마이크론 테크놀로지, 인크. | Block addressing for parallel memory arrays |
US20090059667A1 (en) * | 2007-08-27 | 2009-03-05 | Samsung Electronics Co., Ltd. | Memory cell array and non-volatile memory device |
US8127071B2 (en) * | 2007-09-04 | 2012-02-28 | Samsung Electronics Co., Ltd. | Semiconductor memory device and block management method of the same |
US20090059695A1 (en) * | 2007-09-04 | 2009-03-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device and block management method of the same |
US7818493B2 (en) | 2007-09-07 | 2010-10-19 | Sandisk Corporation | Adaptive block list management |
US20090070518A1 (en) * | 2007-09-07 | 2009-03-12 | Shai Traister | Adaptive Block List Management |
US8332573B2 (en) * | 2007-09-11 | 2012-12-11 | Samsung Electronics Co., Ltd. | Method and apparatus for performing address mapping in virtual file system of storage unit having a plurality of non-volatile data storage media |
US20090070547A1 (en) * | 2007-09-11 | 2009-03-12 | Samsung Electronics Co., Ltd. | Method and apparatus for performing address mapping in virtual file system of storage unit having a plurality of non-volatile data storage media |
US8566504B2 (en) | 2007-09-28 | 2013-10-22 | Sandisk Technologies Inc. | Dynamic metablocks |
US20090089482A1 (en) * | 2007-09-28 | 2009-04-02 | Shai Traister | Dynamic metablocks |
US20140237168A1 (en) * | 2007-12-27 | 2014-08-21 | Sandisk Enterprise Ip Llc | Mass Storage Controller Volatile Memory Containing Metadata Related to Flash Memory Storage |
US9483210B2 (en) | 2007-12-27 | 2016-11-01 | Sandisk Technologies Llc | Flash storage controller execute loop |
US9448743B2 (en) * | 2007-12-27 | 2016-09-20 | Sandisk Technologies Llc | Mass storage controller volatile memory containing metadata related to flash memory storage |
US20090182932A1 (en) * | 2008-01-11 | 2009-07-16 | Phison Electronics Corp. | Method for managing flash memory blocks and controller using the same |
US20110022784A1 (en) * | 2008-03-01 | 2011-01-27 | Kabushiki Kaisha Toshiba | Memory system |
US8209471B2 (en) | 2008-03-01 | 2012-06-26 | Kabushiki Kaisha Toshiba | Memory system |
US8447914B2 (en) | 2008-03-01 | 2013-05-21 | Kabushiki Kaisha Toshiba | Memory system managing the number of times of erasing |
EP2260391A4 (en) * | 2008-03-01 | 2012-11-14 | Toshiba Kk | Memory system |
EP2260391A1 (en) * | 2008-03-01 | 2010-12-15 | Kabushiki Kaisha Toshiba | Memory system |
US8661191B2 (en) | 2008-03-01 | 2014-02-25 | Kabushiki Kaisha Toshiba | Memory system |
US8650436B2 (en) * | 2008-05-15 | 2014-02-11 | The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations | Systems and methods for recovering information from NAND gates array memory systems |
US20110055626A1 (en) * | 2008-05-15 | 2011-03-03 | The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations | Systems and methods for recovering information from nand gates array memory systems |
US8327182B2 (en) * | 2008-05-15 | 2012-12-04 | The Board Of Governors For Higher Education, The State Of Rhode Island And Providence Plantations | Systems and methods for recovering information from NAND gates array memory systems |
US20090292876A1 (en) * | 2008-05-22 | 2009-11-26 | Winbond Electronics Corporation | In-System Programming to Switch Memory Access from One Area to Another in Memory Cards |
US8074023B2 (en) * | 2008-05-22 | 2011-12-06 | Nuvoton Technology Corporation | In-system programming to switch memory access from one area to another in memory cards |
US8625344B2 (en) | 2008-06-13 | 2014-01-07 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US8705272B2 (en) | 2008-06-13 | 2014-04-22 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US20110307646A1 (en) * | 2008-06-13 | 2011-12-15 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US8614919B2 (en) | 2008-06-13 | 2013-12-24 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US8760918B2 (en) | 2008-06-13 | 2014-06-24 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US8638585B2 (en) * | 2008-06-13 | 2014-01-28 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US8565021B2 (en) | 2008-06-13 | 2013-10-22 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US20110197037A1 (en) * | 2008-07-08 | 2011-08-11 | Siliconmotion Inc. | Downgrade memory apparatus, and method for accessing a downgrade memory |
US20100023677A1 (en) * | 2008-07-28 | 2010-01-28 | Shin Young Kyun | Solid state storage system that evenly allocates data writing/erasing operations among blocks and method of controlling the same |
US20110238971A1 (en) * | 2008-09-30 | 2011-09-29 | Jin Gyu Heo | Method of managing a solid state drive, associated systems and implementations |
US8904088B2 (en) | 2008-09-30 | 2014-12-02 | Samsung Electronics Co., Ltd. | Method of managing a solid state drive, associated systems and implementations |
US20110238900A1 (en) * | 2008-09-30 | 2011-09-29 | Jin Gyu Heo | Method of managing a solid state drive, associated systems and implementations |
US9542199B2 (en) | 2008-09-30 | 2017-01-10 | Samsung Electronics Co., Ltd. | Method of managing a solid state drive, associated systems and implementations |
US20100095148A1 (en) * | 2008-10-15 | 2010-04-15 | Silicon Motion, Inc. | Link table recovery method |
US7962801B2 (en) * | 2008-10-15 | 2011-06-14 | Silicon Motion, Inc. | Link table recovery method |
US8094500B2 (en) | 2009-01-05 | 2012-01-10 | Sandisk Technologies Inc. | Non-volatile memory and method with write cache partitioning |
US8244960B2 (en) | 2009-01-05 | 2012-08-14 | Sandisk Technologies Inc. | Non-volatile memory and method with write cache partition management methods |
US20100172180A1 (en) * | 2009-01-05 | 2010-07-08 | Alexander Paley | Non-Volatile Memory and Method With Write Cache Partitioning |
US8700840B2 (en) | 2009-01-05 | 2014-04-15 | SanDisk Technologies, Inc. | Nonvolatile memory with write cache having flush/eviction methods |
US20100174845A1 (en) * | 2009-01-05 | 2010-07-08 | Sergey Anatolievich Gorobets | Wear Leveling for Non-Volatile Memories: Maintenance of Experience Count and Passive Techniques |
US20100172179A1 (en) * | 2009-01-05 | 2010-07-08 | Sergey Anatolievich Gorobets | Spare Block Management of Non-Volatile Memories |
US20100174846A1 (en) * | 2009-01-05 | 2010-07-08 | Alexander Paley | Nonvolatile Memory With Write Cache Having Flush/Eviction Methods |
US20100174847A1 (en) * | 2009-01-05 | 2010-07-08 | Alexander Paley | Non-Volatile Memory and Method With Write Cache Partition Management Methods |
US8040744B2 (en) * | 2009-01-05 | 2011-10-18 | Sandisk Technologies Inc. | Spare block management of non-volatile memories |
JP2012519900A (en) * | 2009-03-04 | 2012-08-30 | マイクロン テクノロジー, インク. | Memory block management |
US8239614B2 (en) * | 2009-03-04 | 2012-08-07 | Micron Technology, Inc. | Memory super block allocation |
US8751731B2 (en) | 2009-03-04 | 2014-06-10 | Micron Technology, Inc. | Memory super block allocation |
TWI455139B (en) * | 2009-03-04 | 2014-10-01 | Micron Technology Inc | Memory block selection |
US20100228928A1 (en) * | 2009-03-04 | 2010-09-09 | Micron Technology, Inc. | Memory block selection |
US9063561B2 (en) | 2009-05-06 | 2015-06-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Direct memory access for loopback transfers in a media controller architecture |
US20110131374A1 (en) * | 2009-05-06 | 2011-06-02 | Noeldner David R | Direct Memory Access for Loopback Transfers in a Media Controller Architecture |
US9262077B2 (en) * | 2009-05-18 | 2016-02-16 | Samsung Electronics Co., Ltd. | Solid state drive device |
US20100306451A1 (en) * | 2009-06-01 | 2010-12-02 | Joshua Johnson | Architecture for nand flash constraint enforcement |
US20100313100A1 (en) * | 2009-06-04 | 2010-12-09 | Lsi Corporation | Flash Memory Organization |
US8555141B2 (en) | 2009-06-04 | 2013-10-08 | Lsi Corporation | Flash memory organization |
US20100313097A1 (en) * | 2009-06-04 | 2010-12-09 | Lsi Corporation | Flash Memory Organization |
US8245112B2 (en) | 2009-06-04 | 2012-08-14 | Lsi Corporation | Flash memory organization |
US20110022779A1 (en) * | 2009-07-24 | 2011-01-27 | Lsi Corporation | Skip Operations for Solid State Disks |
US20110087855A1 (en) * | 2009-08-11 | 2011-04-14 | Texas Memory Systems, Inc. | Method and Apparatus for Protecting Data Using Variable Size Page Stripes in a FLASH-Based Storage System |
US9128871B2 (en) | 2009-08-11 | 2015-09-08 | International Business Machines Corporation | Memory system with variable length page stripes including data protection information |
US9983927B2 (en) | 2009-08-11 | 2018-05-29 | International Business Machines Corporation | Memory system with variable length page stripes including data protection information |
US8443136B2 (en) * | 2009-08-11 | 2013-05-14 | International Business Machines Corporation | Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system |
US20110072198A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Accessing logical-to-physical address translation data for solid state disks |
US20110072194A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Logical-to-Physical Address Translation for Solid State Disks |
US8898371B2 (en) | 2009-09-23 | 2014-11-25 | Lsi Corporation | Accessing logical-to-physical address translation data for solid state disks |
US20110072209A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Processing Diagnostic Requests for Direct Block Access Storage Devices |
US20110072162A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Serial Line Protocol for Embedded Devices |
US8352690B2 (en) | 2009-09-23 | 2013-01-08 | Lsi Corporation | Cache synchronization for solid state disks |
US8458381B2 (en) | 2009-09-23 | 2013-06-04 | Lsi Corporation | Processing host transfer requests for direct block access storage devices |
US8316178B2 (en) | 2009-09-23 | 2012-11-20 | Lsi Corporation | Buffering of data transfers for direct access block devices |
US8504737B2 (en) | 2009-09-23 | 2013-08-06 | Randal S. Rysavy | Serial line protocol for embedded devices |
US20110072187A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Dynamic storage of cache data for solid state disks |
US8762789B2 (en) | 2009-09-23 | 2014-06-24 | Lsi Corporation | Processing diagnostic requests for direct block access storage devices |
US8312250B2 (en) | 2009-09-23 | 2012-11-13 | Lsi Corporation | Dynamic storage of cache data for solid state disks |
US20110072197A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Buffering of Data Transfers for Direct Access Block Devices |
US8301861B2 (en) | 2009-09-23 | 2012-10-30 | Lsi Corporation | Startup reconstruction of logical-to-physical address translation data for solid state disks |
US20110072199A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Startup reconstruction of logical-to-physical address translation data for solid state disks |
US8219776B2 (en) * | 2009-09-23 | 2012-07-10 | Lsi Corporation | Logical-to-physical address translation for solid state disks |
US20110072173A1 (en) * | 2009-09-23 | 2011-03-24 | Lsi Corporation | Processing Host Transfer Requests for Direct Block Access Storage Devices |
US20110087898A1 (en) * | 2009-10-09 | 2011-04-14 | Lsi Corporation | Saving encryption keys in one-time programmable memory |
US20110087890A1 (en) * | 2009-10-09 | 2011-04-14 | Lsi Corporation | Interlocking plain text passwords to data encryption keys |
US8286004B2 (en) | 2009-10-09 | 2012-10-09 | Lsi Corporation | Saving encryption keys in one-time programmable memory |
US8516264B2 (en) | 2009-10-09 | 2013-08-20 | Lsi Corporation | Interlocking plain text passwords to data encryption keys |
US8296480B2 (en) | 2009-11-30 | 2012-10-23 | Lsi Corporation | Context execution in a media controller architecture |
US8583839B2 (en) | 2009-11-30 | 2013-11-12 | Lsi Corporation | Context processing for multiple active write commands in a media controller architecture |
US20110131346A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Context Processing for Multiple Active Write Commands in a Media Controller Architecture |
US20110131357A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Interrupt Queuing in a Media Controller Architecture |
US8352689B2 (en) | 2009-11-30 | 2013-01-08 | Lsi Corporation | Command tag checking in a multi-initiator media controller architecture |
US20110131375A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Command Tag Checking in a Multi-Initiator Media Controller Architecture |
US8868809B2 (en) | 2009-11-30 | 2014-10-21 | Lsi Corporation | Interrupt queuing in a media controller architecture |
US20110131360A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Context Execution in a Media Controller Architecture |
US20110145475A1 (en) * | 2009-12-15 | 2011-06-16 | International Business Machines Corporation | Reducing access contention in flash-based memory systems |
WO2011073902A1 (en) * | 2009-12-15 | 2011-06-23 | International Business Machines Corporation | Reducing access contention in flash-based memory systems |
US8285946B2 (en) | 2009-12-15 | 2012-10-09 | International Business Machines Corporation | Reducing access contention in flash-based memory systems |
US8725957B2 (en) | 2009-12-15 | 2014-05-13 | International Business Machines Corporation | Reducing access contention in flash-based memory systems |
US8321639B2 (en) | 2009-12-30 | 2012-11-27 | Lsi Corporation | Command tracking for direct access block storage devices |
US20110161552A1 (en) * | 2009-12-30 | 2011-06-30 | Lsi Corporation | Command Tracking for Direct Access Block Storage Devices |
CN101819821A (en) * | 2010-03-25 | 2010-09-01 | 清华大学深圳研究生院 | Dynamic loss balancing method for solid state disk |
US9070482B2 (en) * | 2010-06-17 | 2015-06-30 | Lapis Semiconductor Co., Ltd. | Multi-chip package semiconductor memory device |
US20110314234A1 (en) * | 2010-06-17 | 2011-12-22 | Oki Semiconductor Co., Ltd. | Multi-chip package semiconductor memory device |
US20120005451A1 (en) * | 2010-07-02 | 2012-01-05 | Samsung Electronics Co., Ltd | Data storage device and bad block managing method thereof |
US8949507B2 (en) | 2010-09-27 | 2015-02-03 | Silicon Motion Inc. | Method for performing block management, and associated memory device and controller thereof |
TWI425357B (en) * | 2010-09-27 | 2014-02-01 | Silicon Motion Inc | Method for performing block management, and associated memory device and controller thereof |
US20120079169A1 (en) * | 2010-09-27 | 2012-03-29 | Yang-Chih Shen | Method for performing meta block management, and associated memory device and controller thereof |
US8856425B2 (en) * | 2010-09-27 | 2014-10-07 | Silicon Motion Inc. | Method for performing meta block management, and associated memory device and controller thereof |
US8904089B2 (en) | 2010-12-31 | 2014-12-02 | Silicon Motion Inc. | Method for performing block management/Flash memory management, and associated memory device and controller thereof |
US20140149804A1 (en) * | 2011-01-13 | 2014-05-29 | Micron Technology, Inc. | Determining location of error detection data |
US8996907B2 (en) * | 2011-01-13 | 2015-03-31 | Micron Technology, Inc. | Determining location of error detection data |
US8812774B2 (en) * | 2011-03-24 | 2014-08-19 | Kabushiki Kaisha Toshiba | Memory system and computer program product |
US20120246383A1 (en) * | 2011-03-24 | 2012-09-27 | Kabushiki Kaisha Toshiba | Memory system and computer program product |
US20120284469A1 (en) * | 2011-05-03 | 2012-11-08 | Seo Dong-Young | Memory system and bad block management method |
WO2012158521A1 (en) | 2011-05-17 | 2012-11-22 | Sandisk Technologies Inc. | Non-volatile memory and method having block management with hot/cold data sorting |
US9141528B2 (en) | 2011-05-17 | 2015-09-22 | Sandisk Technologies Inc. | Tracking and handling of super-hot data in non-volatile memory systems |
US9176864B2 (en) | 2011-05-17 | 2015-11-03 | SanDisk Technologies, Inc. | Non-volatile memory and method having block management with hot/cold data sorting |
WO2012158514A1 (en) | 2011-05-17 | 2012-11-22 | Sandisk Technologies Inc. | Non-volatile memory and method with small logical groups distributed among active slc and mlc memory partitions |
US9430373B2 (en) | 2011-05-31 | 2016-08-30 | Micron Technology, Inc. | Apparatus including memory channel control circuit and related methods for relaying commands to logical units |
US9098399B2 (en) | 2011-08-31 | 2015-08-04 | SMART Storage Systems, Inc. | Electronic system with storage management mechanism and method of operation thereof |
US9063844B2 (en) | 2011-09-02 | 2015-06-23 | SMART Storage Systems, Inc. | Non-volatile memory management system with time measure mechanism and method of operation thereof |
US9021319B2 (en) | 2011-09-02 | 2015-04-28 | SMART Storage Systems, Inc. | Non-volatile memory management system with load leveling and method of operation thereof |
US8700961B2 (en) | 2011-12-20 | 2014-04-15 | Sandisk Technologies Inc. | Controller and method for virtual LUN assignment for improved memory bank mapping |
US9239781B2 (en) * | 2012-02-07 | 2016-01-19 | SMART Storage Systems, Inc. | Storage control system with erase block mechanism and method of operation thereof |
US20130205102A1 (en) * | 2012-02-07 | 2013-08-08 | SMART Storage Systems, Inc. | Storage control system with erase block mechanism and method of operation thereof |
US9355929B2 (en) | 2012-04-25 | 2016-05-31 | Sandisk Technologies Inc. | Data storage based upon temperature considerations |
US9699263B1 (en) | 2012-08-17 | 2017-07-04 | Sandisk Technologies Llc. | Automatic read and write acceleration of data accessed by virtual machines |
US20140063952A1 (en) * | 2012-08-31 | 2014-03-06 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US8902670B2 (en) * | 2012-08-31 | 2014-12-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US9507523B1 (en) * | 2012-10-12 | 2016-11-29 | Western Digital Technologies, Inc. | Methods, devices and systems for variable size logical page management in a solid state drive |
US9671962B2 (en) | 2012-11-30 | 2017-06-06 | Sandisk Technologies Llc | Storage control system with data management mechanism of parity and method of operation thereof |
US20140181621A1 (en) * | 2012-12-26 | 2014-06-26 | Skymedi Corporation | Method of arranging data in a non-volatile memory and a memory control system thereof |
US9612948B2 (en) | 2012-12-27 | 2017-04-04 | Sandisk Technologies Llc | Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device |
US9454420B1 (en) | 2012-12-31 | 2016-09-27 | Sandisk Technologies Llc | Method and system of reading threshold voltage equalization |
US9123445B2 (en) | 2013-01-22 | 2015-09-01 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US9329928B2 (en) | 2013-02-20 | 2016-05-03 | Sandisk Enterprise IP LLC. | Bandwidth optimization in a non-volatile memory system |
US9214965B2 (en) | 2013-02-20 | 2015-12-15 | Sandisk Enterprise Ip Llc | Method and system for improving data integrity in non-volatile storage |
US9183137B2 (en) | 2013-02-27 | 2015-11-10 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US9870830B1 (en) | 2013-03-14 | 2018-01-16 | Sandisk Technologies Llc | Optimal multilevel sensing for reading data from a storage medium |
US10049037B2 (en) | 2013-04-05 | 2018-08-14 | Sandisk Enterprise Ip Llc | Data management in a storage system |
US9170941B2 (en) | 2013-04-05 | 2015-10-27 | Sandisk Enterprises IP LLC | Data hardening in a storage system |
US9543025B2 (en) | 2013-04-11 | 2017-01-10 | Sandisk Technologies Llc | Storage control system with power-off time estimation mechanism and method of operation thereof |
US10546648B2 (en) | 2013-04-12 | 2020-01-28 | Sandisk Technologies Llc | Storage control system with data management mechanism and method of operation thereof |
US9959220B2 (en) | 2013-06-17 | 2018-05-01 | Micron Technology, Inc | Memory tile access and selection patterns |
US10942873B2 (en) | 2013-06-17 | 2021-03-09 | Micron Technology, Inc. | Memory tile access and selection patterns |
US10387338B2 (en) | 2013-06-17 | 2019-08-20 | Micron Technology, Inc. | Memory tile access and selection patterns |
US9626292B2 (en) | 2013-06-17 | 2017-04-18 | Micron Technology, Inc. | Memory tile access and selection patterns |
US9244519B1 (en) | 2013-06-25 | 2016-01-26 | Smart Storage Systems. Inc. | Storage system with data transfer rate adjustment for power throttling |
US9367353B1 (en) | 2013-06-25 | 2016-06-14 | Sandisk Technologies Inc. | Storage control system with power throttling mechanism and method of operation thereof |
US9524235B1 (en) | 2013-07-25 | 2016-12-20 | Sandisk Technologies Llc | Local hash value generation in non-volatile data storage systems |
US9146850B2 (en) | 2013-08-01 | 2015-09-29 | SMART Storage Systems, Inc. | Data storage system with dynamic read threshold mechanism and method of operation thereof |
US9665295B2 (en) | 2013-08-07 | 2017-05-30 | Sandisk Technologies Llc | Data storage system with dynamic erase block grouping mechanism and method of operation thereof |
US9448946B2 (en) | 2013-08-07 | 2016-09-20 | Sandisk Technologies Llc | Data storage system with stale data mechanism and method of operation thereof |
US9361222B2 (en) | 2013-08-07 | 2016-06-07 | SMART Storage Systems, Inc. | Electronic system with storage drive life estimation mechanism and method of operation thereof |
US9431113B2 (en) | 2013-08-07 | 2016-08-30 | Sandisk Technologies Llc | Data storage system with dynamic erase block grouping mechanism and method of operation thereof |
US9639463B1 (en) | 2013-08-26 | 2017-05-02 | Sandisk Technologies Llc | Heuristic aware garbage collection scheme in storage systems |
US9442662B2 (en) | 2013-10-18 | 2016-09-13 | Sandisk Technologies Llc | Device and method for managing die groups |
US9436831B2 (en) | 2013-10-30 | 2016-09-06 | Sandisk Technologies Llc | Secure erase in a memory device |
US9152555B2 (en) | 2013-11-15 | 2015-10-06 | Sandisk Enterprise IP LLC. | Data management with modular erase in a data storage system |
US9703816B2 (en) | 2013-11-19 | 2017-07-11 | Sandisk Technologies Llc | Method and system for forward reference logging in a persistent datastore |
US9520197B2 (en) | 2013-11-22 | 2016-12-13 | Sandisk Technologies Llc | Adaptive erase of a storage device |
US9520162B2 (en) | 2013-11-27 | 2016-12-13 | Sandisk Technologies Llc | DIMM device controller supervisor |
US9582058B2 (en) | 2013-11-29 | 2017-02-28 | Sandisk Technologies Llc | Power inrush management of storage devices |
US9703636B2 (en) | 2014-03-01 | 2017-07-11 | Sandisk Technologies Llc | Firmware reversion trigger and control |
US9448876B2 (en) | 2014-03-19 | 2016-09-20 | Sandisk Technologies Llc | Fault detection and prediction in storage devices |
US9454448B2 (en) | 2014-03-19 | 2016-09-27 | Sandisk Technologies Llc | Fault testing in storage devices |
US9626400B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Compaction of information in tiered data structure |
US9626399B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Conditional updates for reducing frequency of data modification operations |
US9697267B2 (en) | 2014-04-03 | 2017-07-04 | Sandisk Technologies Llc | Methods and systems for performing efficient snapshots in tiered data structures |
US20150339223A1 (en) * | 2014-05-22 | 2015-11-26 | Kabushiki Kaisha Toshiba | Memory system and method |
US10114557B2 (en) | 2014-05-30 | 2018-10-30 | Sandisk Technologies Llc | Identification of hot regions to enhance performance and endurance of a non-volatile storage device |
US10146448B2 (en) | 2014-05-30 | 2018-12-04 | Sandisk Technologies Llc | Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device |
US9703491B2 (en) | 2014-05-30 | 2017-07-11 | Sandisk Technologies Llc | Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device |
US10656840B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Real-time I/O pattern recognition to enhance performance and endurance of a storage device |
US10656842B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device |
US10162748B2 (en) | 2014-05-30 | 2018-12-25 | Sandisk Technologies Llc | Prioritizing garbage collection and block allocation based on I/O history for logical address regions |
US10372613B2 (en) | 2014-05-30 | 2019-08-06 | Sandisk Technologies Llc | Using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device |
US9652381B2 (en) | 2014-06-19 | 2017-05-16 | Sandisk Technologies Llc | Sub-block garbage collection |
US9632712B2 (en) | 2014-07-02 | 2017-04-25 | Sandisk Technologies Llc | System and method of updating metablocks associated with multiple memory dies |
US9626289B2 (en) | 2014-08-28 | 2017-04-18 | Sandisk Technologies Llc | Metalblock relinking to physical blocks of semiconductor memory in adaptive wear leveling based on health |
US9443601B2 (en) | 2014-09-08 | 2016-09-13 | Sandisk Technologies Llc | Holdup capacitor energy harvesting |
US10572169B2 (en) | 2015-06-05 | 2020-02-25 | Western Digital Technologies, Inc. | Scheduling scheme(s) for a multi-die storage device |
US9875053B2 (en) | 2015-06-05 | 2018-01-23 | Western Digital Technologies, Inc. | Scheduling scheme(s) for a multi-die storage device |
US10289327B2 (en) | 2015-06-05 | 2019-05-14 | Western Digital Technologies, Inc. | Scheduling scheme(s) for a multi-die storage device |
CN105488722A (en) * | 2015-11-30 | 2016-04-13 | 布比(北京)网络技术有限公司 | Asset data processing method and device based on derivation chain |
US10126970B2 (en) * | 2015-12-11 | 2018-11-13 | Sandisk Technologies Llc | Paired metablocks in non-volatile storage device |
US10725933B2 (en) * | 2016-12-30 | 2020-07-28 | Intel Corporation | Method and apparatus for redirecting memory access commands sent to unusable memory partitions |
US20180188960A1 (en) * | 2016-12-30 | 2018-07-05 | Intel Corporation | Method and apparatus for redirecting memory access commands sent to unusable memory partitions |
US10223022B2 (en) * | 2017-01-27 | 2019-03-05 | Western Digital Technologies, Inc. | System and method for implementing super word line zones in a memory device |
US10671523B2 (en) * | 2017-03-17 | 2020-06-02 | SK Hynix Inc. | Memory system |
US20180267895A1 (en) * | 2017-03-17 | 2018-09-20 | SK Hynix Inc. | Memory system |
US10229751B2 (en) | 2017-05-01 | 2019-03-12 | Western Digital Technologies, Inc. | Storage system and method for bad block recycling |
US10649661B2 (en) * | 2017-06-26 | 2020-05-12 | Western Digital Technologies, Inc. | Dynamically resizing logical storage blocks |
US20180373438A1 (en) * | 2017-06-26 | 2018-12-27 | Western Digital Technologies, Inc. | Dynamically resizing logical storage blocks |
US11069409B2 (en) | 2017-07-21 | 2021-07-20 | Silicon Motion, Inc. | Method, associated memory device and controller thereof for performing programming management |
US11488671B2 (en) | 2017-07-21 | 2022-11-01 | Silicon Motion, Inc. | Method, associated memory device and controller thereof for performing programming management |
TWI641988B (en) * | 2017-07-21 | 2018-11-21 | 慧榮科技股份有限公司 | Method for performing programming management in a memory device, and associated memory device and controller thereof |
US10977182B2 (en) * | 2017-12-01 | 2021-04-13 | Micron Technology, Inc. | Logical block mapping based on an offset |
US11436154B2 (en) | 2017-12-01 | 2022-09-06 | Micron Technology, Inc. | Logical block mapping based on an offset |
EP3718013A4 (en) * | 2017-12-01 | 2021-08-25 | Micron Technology, INC. | Logical block mapping based on an offset |
US20190171576A1 (en) * | 2017-12-01 | 2019-06-06 | Micron Technology, Inc. | Logical block mapping based on an offset |
US10635515B2 (en) | 2017-12-06 | 2020-04-28 | Sandisk Technologies Llc | Recovery of partial memory die |
CN109933467A (en) * | 2017-12-18 | 2019-06-25 | 爱思开海力士有限公司 | Storage system and its operating method |
US10977144B2 (en) * | 2017-12-18 | 2021-04-13 | SK Hynix Inc. | Memory system and method of operating the same |
CN108196795A (en) * | 2017-12-30 | 2018-06-22 | 惠龙易通国际物流股份有限公司 | A kind of date storage method, equipment and computer storage media |
US10678477B2 (en) * | 2018-06-06 | 2020-06-09 | Phison Electronics Corp. | Memory management method, memory control circuit unit and memory storage apparatus |
US20190377514A1 (en) * | 2018-06-06 | 2019-12-12 | Phison Electronics Corp. | Memory management method, memory control circuit unit and memory storage apparatus |
CN110609795A (en) * | 2018-06-14 | 2019-12-24 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
CN111061653A (en) * | 2018-10-16 | 2020-04-24 | 爱思开海力士有限公司 | Data storage device and operation method thereof |
CN111208939A (en) * | 2018-11-22 | 2020-05-29 | 爱思开海力士有限公司 | Memory system and operation method of memory system |
US20210055878A1 (en) * | 2019-08-20 | 2021-02-25 | Micron Technology, Inc. | Data compaction within the same plane of a memory component |
US11776615B2 (en) | 2019-08-20 | 2023-10-03 | Micron Technology, Inc. | Sequential SLC read optimization |
US11726869B2 (en) | 2019-08-20 | 2023-08-15 | Micron Technology, Inc. | Performing error control operation on memory component for garbage collection |
US11726908B2 (en) | 2019-08-20 | 2023-08-15 | Micron Technology, Inc. | Garbage collection in a memory sub-system during a low battery state |
US11698742B2 (en) | 2019-08-28 | 2023-07-11 | Micron Technology, Inc. | Garbage collection in a memory component using an adjusted parameter |
US20210365200A1 (en) * | 2020-05-21 | 2021-11-25 | Western Digital Technologies, Inc. | Use Of Surplus Erase Block Pairs In Super Block Formation |
US11640259B2 (en) * | 2020-05-21 | 2023-05-02 | Western Digital Technologies, Inc. | Use of surplus erase block pairs in super block formation |
US20230103004A1 (en) * | 2021-09-29 | 2023-03-30 | Yangtze Memory Technologies Co., Ltd. | Data protection method for memory and storage device thereof |
US12032860B2 (en) * | 2021-09-29 | 2024-07-09 | Yangtze Memory Technologies Co., Ltd. | Data protection method for memory and storage device thereof |
CN115687171A (en) * | 2022-10-26 | 2023-02-03 | 深圳三地一芯电子有限责任公司 | Flash block binding method, device, equipment and storage medium |
Also Published As
Publication number | Publication date |
---|---|
US8117381B2 (en) | 2012-02-14 |
WO2005066974A1 (en) | 2005-07-21 |
US20090292944A1 (en) | 2009-11-26 |
CN1930635A (en) | 2007-03-14 |
TW200540621A (en) | 2005-12-16 |
CN1930635B (en) | 2012-10-10 |
ATE451694T1 (en) | 2009-12-15 |
KR20060120231A (en) | 2006-11-24 |
TWI294081B (en) | 2008-03-01 |
DE602004024582D1 (en) | 2010-01-21 |
JP2007520842A (en) | 2007-07-26 |
US20110191530A1 (en) | 2011-08-04 |
US7970985B2 (en) | 2011-06-28 |
JP4960705B2 (en) | 2012-06-27 |
EP1700313A1 (en) | 2006-09-13 |
EP1700313B1 (en) | 2009-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8117381B2 (en) | Adaptive deterministic grouping of blocks into multi-block units | |
US8312245B2 (en) | Memory block management | |
US8041884B2 (en) | Controller for non-volatile memories and methods of operating the memory controller | |
US8300465B2 (en) | Semiconductor and flash memory systems | |
US8407397B2 (en) | Block management method for flash memory and controller and storage system using the same | |
EP1410399B1 (en) | Method and apparatus for decreasing block write operation times performed on nonvolatile memory | |
US6763424B2 (en) | Partial block data programming and reading operations in a non-volatile memory | |
US7509471B2 (en) | Methods for adaptively handling data writes in non-volatile memories | |
US8285916B2 (en) | Storage device | |
US20070103978A1 (en) | Memory with retargetable memory cell redundancy | |
US20100146239A1 (en) | Continuous address space in non-volatile-memories (nvm) using efficient embedded management of array deficiencies |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SANDISK CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GONZALEZ, CARLOS J.;BRYCE, ALAN DOUGLAS;GOROBETS, SERGEY ANATOLIEVICH;AND OTHERS;REEL/FRAME:014851/0192;SIGNING DATES FROM 20040706 TO 20040709 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026325/0212 Effective date: 20110404 |
|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES LLC, TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038807/0980 Effective date: 20160516 |