US20050133886A1 - Integrated circuit for differential variable capacitors - Google Patents
Integrated circuit for differential variable capacitors Download PDFInfo
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- US20050133886A1 US20050133886A1 US10/780,712 US78071204A US2005133886A1 US 20050133886 A1 US20050133886 A1 US 20050133886A1 US 78071204 A US78071204 A US 78071204A US 2005133886 A1 US2005133886 A1 US 2005133886A1
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- Prior art keywords
- integrated circuit
- ion implant
- differential variable
- type ion
- gate
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- 239000003990 capacitor Substances 0.000 title claims abstract description 68
- 239000007943 implant Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 230000009699 differential effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 244000045947 parasite Species 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/93—Variable capacitance diodes, e.g. varactors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
- H01L27/0808—Varactor diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Definitions
- the present invention relates to an integrated circuit design for differential variable capacitors, more particularly to an integrated circuit being integrated with differential variable capacitors and having no asymmetric coil for reducing the chip size, lowering the circuit inaccuracy, and controlling the overall loading quality of variable capacitors effectively.
- VCO voltage control oscillator
- differential variable capacitors become an essential component.
- the conventional differential variable capacitor usually consists of two independent capacitors, and such arrangement not only increases the chip size, but also enhances a circuitry inaccuracy due to the parasitic effect occurring between the two independent capacitors.
- a conventional differential variable capacitor is consisted of a first capacitor 1 and a second capacitor 2 .
- the circuit design of the conventional differential variable capacitor is as following: respectively forming n+ implant points 12 , 22 in n-well regions 11 , 21 on p-substrates 10 , 20 ; connecting the n+ implant points 12 , 22 to form a bias voltage control point Vc; employing P 1 and P 2 as the contacts for connecting to other circuits; and employing p+ implant points 13 , 23 as the grounding point.
- the primary object of the present invention is to provide an integrated circuit design of a differential variable capacitor, using an integrated method to design an integrated circuit of a differential variable capacitor with the consideration of solving the parasitic effect occurred therein so as to reduce the circuitry inaccuracy.
- Another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, using an integrated method to design an integrated circuit of a differential variable capacitor to effectively reduce the chip size and lower the manufacturing cost.
- Another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, using an integrated method to design an integrated circuit of a differential variable capacitor to prevent the happening of asymmetric coils.
- Another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, capable of knowing the factor of overall loading quality of the variable capacitors, and thus further effectively controlling the overall loading quality of the variable capacitors.
- Another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, which is integrally formed without the need of repositioning for achieving a symmetrical connection, and thus has a very precise positioning so as to reduce the level of difficulty of manufacturing the same.
- the present invention provides an integrated circuit design of a differential variable capacitor, which comprises: a p-substrate; an n-well region disposed on the top surface of the p-substrate; at least three n-type ion implant regions, each disposed on the top surface of the n-well region; a metal wire for connecting the three n-type ion implant regions; a bias voltage control point, coupled to the n-type ion implant region; a first gate; and a second gate being coupled with the first gate; wherein the first gate and second gate use the bias control point as center to be disposed symmetrically on both sides of the bias voltage control point.
- the integrated circuit uses an integrated design to integrally form the differential variable capacitor, and the parasite effect is also taken into consideration in the manufacturing process for reducing the circuitry inaccuracy, lowering the manufacturing cost, and preventing asymmetric coils from happening.
- the present invention provides the knowledge about the factor of overall loading quality of the variable capacitors, and thus further effectively controls the overall loading quality of the variable capacitors during manufacturing the same. Furthermore, the present invention does not require repositioning for the symmetric connection, and thus has a very precise positioning so as to reduce the level of difficulty of manufacturing the same.
- FIG. 1A is a top view of a conventional differential variable capacitor.
- FIG. 1B is a cross-sectional view of a conventional differential variable capacitor.
- FIG. 2A is a top view of a differential variable capacitor according to a first preferred embodiment of the present invention.
- FIG. 2B is a cross-sectional view of a differential variable capacitor according to a first preferred embodiment of the present invention.
- FIG. 3A is a top view of a differential variable capacitor according to a second preferred embodiment of the present invention.
- FIG. 3B is a cross-sectional view of a differential variable capacitor according to a second preferred embodiment of the present invention.
- FIGS. 2A and 2B Please refer to FIGS. 2A and 2B for the top view and cross-sectional view of a preferred embodiment of the present invention respectively, wherein the integrated circuit of a differential variable capacitor 3 forms an n-well 31 , using an ion implant method to implant at least three n-type ion implant regions 32 disposed on the top surface of the n-well.
- the n-type ion implant regions 32 include a first n-type ion implant region 32 a , a second n-type ion implant region 32 b , and a third n-type ion implant region 32 c ; wherein the first n-type ion implant region 32 a and the third n-type ion implant region 32 c use the second n-type ion implant region 32 b as the center to be disposed symmetrically on both sides of the second n-type ion implant region 32 b .
- the conventional lithographic and etching technologies are used to form a structure using the contact point of an oxide layer to connect the connecting points and metal wire; wherein the metal wire 33 connects the foregoing n-type ion implant region 32 b ; the first gate 34 is disposed in the metal wire 33 and between the first n-type ion implant region 32 a and the second n-type ion implant region 32 b ; the second gate 35 is also disposed in the metal wire 33 and between the second n-type ion implant region 32 b and the third n-type ion implant region 32 c ; the bias voltage control point 36 is coupled to the first n-type ion implant region 32 a , the second n-type ion implant region 32 b , and the third n-type ion implant region 32 c ; the first contact point 37 is coupled to the first gate 34 ; the second connecting point 38 is coupled to the second gate 35 , wherein the first connecting point 37 and the second connecting point 38 use the bias voltage
- the p-substrate at its top surface further comprises a p-type ion implant region 39 coupled to a grounding point 40 for the purpose of grounding.
- the first gate 34 and the second gate 35 according to a preferred embodiment of the present invention is made of a poly-silicon material.
- FIGS. 3A and 3B Please refer to FIGS. 3A and 3B for the top view and the cross-sectional view according to a second preferred embodiment of this invention respectively, wherein the integrated circuit of the differential variable capacity 5 forms a p-well 51 at the top surface of a n-type substrate 50 and uses at least three p-type ion implant regions 52 disposed on the top surface of the p-well 51 .
- the three p-type ion implant regions 52 include a first p-type ion implant region 52 a , a second p-type ion implant region 52 b , and a third p-type ion implant region 52 c , wherein the first p-type ion implant region 52 a and the third p-type ion implant region 52 c use the second p-type ion implant region 52 b as the center to be disposed symmetrically on both sides of the second p-type ion implant region 52 b .
- the differential variable capacitor 5 is designed as a whole, and does not require repositioning for the symmetrical connection at a later manufacturing process.
- the conventional lithographic and etching technologies are used to form a structure using the contact point of an oxide layer to connect the connecting points and metal wire; wherein the metal wire 53 connects the foregoing at least three p-type ion implant points 52 ; the first gate 54 is disposed in the metal wire 53 and between the first p-type ion implant region 52 a and the second p-type ion implant region 52 b ; the second gate 55 is also disposed in the metal wire 53 and between the second p-type ion implant region 52 b and the third p-type ion implant region 52 c .
- the bias voltage control point 56 is coupled to the first p-type ion implant region 52 a , the second p-type ion implant region 52 b , and the third p-type ion implant region 52 c ; the first connecting point 57 is coupled to the first gate 54 ; the second connecting point 58 is coupled to the second gate 55 , wherein the first connecting point 57 and the second connecting point 58 use the bias voltage control point 56 as the center to be disposed symmetrically on both sides of the bias voltage control point 56 , which are also the first gate 54 and the second gate 55 and use the bias voltage control point 56 as the center to be disposed symmetrically on both sides of the bias voltage control point 56 .
- the n-type substrate 50 at its top surface comprises an n-type ion implant region 59 coupled to a grounding point 60 for the purpose of grounding.
- the differential variable capacitor 5 is also designed as a whole, which has the same effect as the first preferred embodiment, and thus will not be described here.
- the present invention discloses an integrated circuit design of a differential variable capacitor, which is applicable for both the n-type semiconductor substrate and the p-type semiconductor substrate.
- the present invention uses an integrated method to design an integrated circuit of the differential variable capacitor to effectively reduce the chip size and lower the manufacturing cost.
- the present invention can prevent asymmetrical coils, and allows us to know about the factor of overall loading quality of the variable capacitor, and further effectively control the overall loading quality of the variable capacitor.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
An integrated circuit design for differential variable capacitors uses an integration method to integrate an integrated circuit having differential variable capacitors as a whole, and takes the parasitic effect into consideration for the manufacturing process to lower the circuit inaccuracy and reduce the chip size effectively. Such arrangement lowers the manufacturing cost, identifies the quality of loading quality of the overall variable capacitance during the manufacture, and further controls the quality of loading capacity of the overall variable capacitance effectively. Furthermore, this invention does not need to reposition for the symmetrical position of the coils, and thus giving a very precise positioning to reduce the level of difficulty for the manufacture.
Description
- The present invention relates to an integrated circuit design for differential variable capacitors, more particularly to an integrated circuit being integrated with differential variable capacitors and having no asymmetric coil for reducing the chip size, lowering the circuit inaccuracy, and controlling the overall loading quality of variable capacitors effectively.
- A voltage control oscillator (VCO) is an important circuit indispensable to the applications of radio frequency (RF)/microwave and wireless communication, which uses a bias voltage to enable the variable capacitor therein to vary its capacitance, and thus further changes the oscillating frequency.
- More and more people adopt differential circuit design for the circuit of voltage control oscillators (VCO) to reduce the interference caused by common-mode noises. To achieve the differential effect, differential variable capacitors become an essential component. However, the conventional differential variable capacitor usually consists of two independent capacitors, and such arrangement not only increases the chip size, but also enhances a circuitry inaccuracy due to the parasitic effect occurring between the two independent capacitors.
- As seen in
FIGS. 1A and 1B , a conventional differential variable capacitor is consisted of afirst capacitor 1 and asecond capacitor 2. The circuit design of the conventional differential variable capacitor is as following: respectively formingn+ implant points well regions substrates n+ implant points p+ implant points - In view of the circuit design of the conventional differential variable capacitor, there exists at least the following shortcomings:
- 1. The conventional differential variable capacitor adopts two independent capacitors. Therefore, a larger chip is required for the making of the differential variable capacitor such that the manufacturing cost is increased.
- 2. Parasitic effects will occur at the connection between the two independent variable capacitors of the conventional differential variable capacitor, and thus increasing the circuitry inaccuracy.
- 3. Since the connection between two variable capacitors must be symmetrical, therefore the positioning has to be very precise, and thus increasing the level of difficulty of the manufacture.
- 4. Asymmetry usually occurs in the connection between the two variable capacitors, and thus greatly reducing the differential effect.
- 5. In the conventional differential variable capacitor, there is no way of knowing the factor of overall loading quality of the variable capacitor.
- In view of the shortcomings of the prior arts, the primary object of the present invention is to provide an integrated circuit design of a differential variable capacitor, using an integrated method to design an integrated circuit of a differential variable capacitor with the consideration of solving the parasitic effect occurred therein so as to reduce the circuitry inaccuracy.
- Another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, using an integrated method to design an integrated circuit of a differential variable capacitor to effectively reduce the chip size and lower the manufacturing cost.
- Yet, another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, using an integrated method to design an integrated circuit of a differential variable capacitor to prevent the happening of asymmetric coils.
- Yet, another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, capable of knowing the factor of overall loading quality of the variable capacitors, and thus further effectively controlling the overall loading quality of the variable capacitors.
- Yet, another object of the present invention is to provide an integrated circuit design of a differential variable capacitor, which is integrally formed without the need of repositioning for achieving a symmetrical connection, and thus has a very precise positioning so as to reduce the level of difficulty of manufacturing the same.
- To achieve the foregoing objectives, the present invention provides an integrated circuit design of a differential variable capacitor, which comprises: a p-substrate; an n-well region disposed on the top surface of the p-substrate; at least three n-type ion implant regions, each disposed on the top surface of the n-well region; a metal wire for connecting the three n-type ion implant regions; a bias voltage control point, coupled to the n-type ion implant region; a first gate; and a second gate being coupled with the first gate; wherein the first gate and second gate use the bias control point as center to be disposed symmetrically on both sides of the bias voltage control point. Therefore, the integrated circuit uses an integrated design to integrally form the differential variable capacitor, and the parasite effect is also taken into consideration in the manufacturing process for reducing the circuitry inaccuracy, lowering the manufacturing cost, and preventing asymmetric coils from happening. The present invention provides the knowledge about the factor of overall loading quality of the variable capacitors, and thus further effectively controls the overall loading quality of the variable capacitors during manufacturing the same. Furthermore, the present invention does not require repositioning for the symmetric connection, and thus has a very precise positioning so as to reduce the level of difficulty of manufacturing the same.
-
FIG. 1A is a top view of a conventional differential variable capacitor. -
FIG. 1B is a cross-sectional view of a conventional differential variable capacitor. -
FIG. 2A is a top view of a differential variable capacitor according to a first preferred embodiment of the present invention. -
FIG. 2B is a cross-sectional view of a differential variable capacitor according to a first preferred embodiment of the present invention. -
FIG. 3A is a top view of a differential variable capacitor according to a second preferred embodiment of the present invention. -
FIG. 3B is a cross-sectional view of a differential variable capacitor according to a second preferred embodiment of the present invention. - For your esteemed members of reviewing committee to further understand and recognize the objectives, the characteristics, and the functions of the invention, a detailed description in matching with corresponding drawings are presented as the following.
- Please refer to
FIGS. 2A and 2B for the top view and cross-sectional view of a preferred embodiment of the present invention respectively, wherein the integrated circuit of adifferential variable capacitor 3 forms an n-well 31, using an ion implant method to implant at least three n-typeion implant regions 32 disposed on the top surface of the n-well. The n-typeion implant regions 32 include a first n-typeion implant region 32 a, a second n-typeion implant region 32 b, and a third n-typeion implant region 32 c; wherein the first n-typeion implant region 32 a and the third n-typeion implant region 32 c use the second n-typeion implant region 32 b as the center to be disposed symmetrically on both sides of the second n-typeion implant region 32 b. Since the relative positions of the first n-typeion implant region 32 a, second n-typeion implant region 32 b, and third n-typeion implant region 32 c can be confirmed in the ion implantation, so that thedifferential variable capacitor 3 is designed as a whole, which no longer needs to reposition for the symmetric connection. - The conventional lithographic and etching technologies are used to form a structure using the contact point of an oxide layer to connect the connecting points and metal wire; wherein the
metal wire 33 connects the foregoing n-typeion implant region 32 b; thefirst gate 34 is disposed in themetal wire 33 and between the first n-typeion implant region 32 a and the second n-typeion implant region 32 b; thesecond gate 35 is also disposed in themetal wire 33 and between the second n-typeion implant region 32 b and the third n-typeion implant region 32 c; the biasvoltage control point 36 is coupled to the first n-typeion implant region 32 a, the second n-typeion implant region 32 b, and the third n-typeion implant region 32 c; thefirst contact point 37 is coupled to thefirst gate 34; the second connectingpoint 38 is coupled to thesecond gate 35, wherein the first connectingpoint 37 and thesecond connecting point 38 use the biasvoltage control point 36 as the center to be disposed symmetrically on both sides of the biasvoltage control point 36. - Since the
differential variable capacitor 3 is designed as a whole, therefore asymmetric coils will not occur, and we can know about the factor of overall loading quality of the variable capacitor to effectively control the overall loading quality of the variable capacitor. Further, the p-substrate at its top surface further comprises a p-typeion implant region 39 coupled to agrounding point 40 for the purpose of grounding. Thefirst gate 34 and thesecond gate 35 according to a preferred embodiment of the present invention is made of a poly-silicon material. - Please refer to
FIGS. 3A and 3B for the top view and the cross-sectional view according to a second preferred embodiment of this invention respectively, wherein the integrated circuit of thedifferential variable capacity 5 forms a p-well 51 at the top surface of a n-type substrate 50 and uses at least three p-typeion implant regions 52 disposed on the top surface of the p-well 51. The three p-typeion implant regions 52 include a first p-typeion implant region 52 a, a second p-typeion implant region 52 b, and a third p-typeion implant region 52 c, wherein the first p-typeion implant region 52 a and the third p-typeion implant region 52 c use the second p-typeion implant region 52 b as the center to be disposed symmetrically on both sides of the second p-typeion implant region 52 b. Since the positions of the first p-typeion implant region 52 a, the second p-typeion implant region 52 b, and the third p-typeion implant region 52 c are confirmed during the ion implantation, so that thedifferential variable capacitor 5 is designed as a whole, and does not require repositioning for the symmetrical connection at a later manufacturing process. - The conventional lithographic and etching technologies are used to form a structure using the contact point of an oxide layer to connect the connecting points and metal wire; wherein the
metal wire 53 connects the foregoing at least three p-typeion implant points 52; thefirst gate 54 is disposed in themetal wire 53 and between the first p-typeion implant region 52 a and the second p-typeion implant region 52 b; thesecond gate 55 is also disposed in themetal wire 53 and between the second p-typeion implant region 52 b and the third p-typeion implant region 52 c. The biasvoltage control point 56 is coupled to the first p-typeion implant region 52 a, the second p-typeion implant region 52 b, and the third p-typeion implant region 52 c; the first connectingpoint 57 is coupled to thefirst gate 54; the second connectingpoint 58 is coupled to thesecond gate 55, wherein the first connectingpoint 57 and the second connectingpoint 58 use the biasvoltage control point 56 as the center to be disposed symmetrically on both sides of the biasvoltage control point 56, which are also thefirst gate 54 and thesecond gate 55 and use the biasvoltage control point 56 as the center to be disposed symmetrically on both sides of the biasvoltage control point 56. - Further, the n-
type substrate 50 at its top surface comprises an n-typeion implant region 59 coupled to agrounding point 60 for the purpose of grounding. Thedifferential variable capacitor 5 is also designed as a whole, which has the same effect as the first preferred embodiment, and thus will not be described here. - In view of the description above, the present invention discloses an integrated circuit design of a differential variable capacitor, which is applicable for both the n-type semiconductor substrate and the p-type semiconductor substrate. The present invention uses an integrated method to design an integrated circuit of the differential variable capacitor to effectively reduce the chip size and lower the manufacturing cost. The present invention can prevent asymmetrical coils, and allows us to know about the factor of overall loading quality of the variable capacitor, and further effectively control the overall loading quality of the variable capacitor.
Claims (12)
1. An integrated circuit for differential variable capacitors, comprising:
a p-substrate;
an n-well region, disposed at the top surface of said p-substrate;
at least three n-type ion implant regions, each disposed on the top surface of said n-well region;
a metal wire, for connecting said at least three n-type ion implant regions;
a bias voltage control terminal, coupled to said n-type ion implant region;
a first gate; and
a second gate, being coupled to said first gate.
2. The integrated circuit for differential variable capacitors of claim 1 , wherein said first gate and second gate are disposed symmetrically on opposite side of said voltage control terminal in respective.
3. The integrated circuit for differential variable capacitors of claim 1 , wherein said first gate is made of a polysilicon.
4. The integrated circuit for differential variable capacitors of claim 1 , wherein said second gate is made of a polysilicon.
5. The integrated circuit for differential variable capacitors of claim 1 , wherein said p-substrate further comprises a p-type ion implant region arranged at the top surface thereof.
6. The integrated circuit for differential variable capacitors of claim 5 , wherein said p-type ion implant region is coupled to a grounding terminal.
7. An integrated circuit for differential variable capacitors, comprising:
an n-type substrate;
a p-type well region, disposed on the top surface of said n-type substrate;
at least three p-type ion implant regions, each disposed on the top surface of said p-type well region;
a metal wire, for connecting said at least three p-type ion implant regions;
a bias voltage control terminal, coupled to said p-type ion implant regions;
a first gate; and
a second gate, being coupled to said first gate.
8. The integrated circuit for differential variable capacitors of claim 7 , wherein said first and second gates are disposed symmetrically on both sides of said bias voltage control terminal.
9. The integrated circuit for differential variable capacitors of claim 7 , wherein said first gate is made of a polysilicon.
10. The integrated circuit for differential variable capacitors of claim 7 , wherein said second gate is made of a polysilicon.
11. The integrated circuit for differential variable capacitors of claim 7 , wherein said n-type substrate further comprises an n-type ion implant region arranged at the top surface thereof.
12. The integrated circuit for differential variable capacitors of claim 11 , wherein said n-type ion implant region is coupled to a grounding ternimal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/420,118 US7569912B2 (en) | 2003-12-23 | 2006-05-24 | Differential variable capacitors and their applications |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092136464A TWI231007B (en) | 2003-12-23 | 2003-12-23 | IC design of differential varactors |
TW92136464 | 2003-12-23 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/048,151 Continuation-In-Part US7298225B2 (en) | 2003-12-23 | 2005-01-31 | Signal modulated voltage controlled oscillator system |
US11/420,118 Continuation-In-Part US7569912B2 (en) | 2003-12-23 | 2006-05-24 | Differential variable capacitors and their applications |
Publications (1)
Publication Number | Publication Date |
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US20050133886A1 true US20050133886A1 (en) | 2005-06-23 |
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ID=34676164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/780,712 Abandoned US20050133886A1 (en) | 2003-12-23 | 2004-02-19 | Integrated circuit for differential variable capacitors |
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US (1) | US20050133886A1 (en) |
TW (1) | TWI231007B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110215388A1 (en) * | 2010-03-03 | 2011-09-08 | Jeong-Soo Kim | Pin capacitor of semiconductor device and method for fabricating the same |
US9685908B1 (en) * | 2016-03-16 | 2017-06-20 | Soongsil University Research Consortium Techno-Park | Variable capacitor used in integrated circuit of differential structure |
CN111081701A (en) * | 2018-10-19 | 2020-04-28 | 珠海格力电器股份有限公司 | Differential circuit and analog integrated circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040100752A1 (en) * | 2002-11-20 | 2004-05-27 | Matsushita Electric Industrial Co., Ltd. | Variable capacitor element and integrated circuit having variable capacitor element |
-
2003
- 2003-12-23 TW TW092136464A patent/TWI231007B/en not_active IP Right Cessation
-
2004
- 2004-02-19 US US10/780,712 patent/US20050133886A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040100752A1 (en) * | 2002-11-20 | 2004-05-27 | Matsushita Electric Industrial Co., Ltd. | Variable capacitor element and integrated circuit having variable capacitor element |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110215388A1 (en) * | 2010-03-03 | 2011-09-08 | Jeong-Soo Kim | Pin capacitor of semiconductor device and method for fabricating the same |
US8659063B2 (en) * | 2010-03-03 | 2014-02-25 | Hynix Semiconductor Inc. | Pin capacitor of semiconductor device and method for fabricating the same |
US9685908B1 (en) * | 2016-03-16 | 2017-06-20 | Soongsil University Research Consortium Techno-Park | Variable capacitor used in integrated circuit of differential structure |
CN111081701A (en) * | 2018-10-19 | 2020-04-28 | 珠海格力电器股份有限公司 | Differential circuit and analog integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
TWI231007B (en) | 2005-04-11 |
TW200522269A (en) | 2005-07-01 |
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