US20050112895A1 - Method of chemical-mechanical polishing - Google Patents
Method of chemical-mechanical polishing Download PDFInfo
- Publication number
- US20050112895A1 US20050112895A1 US10/975,863 US97586304A US2005112895A1 US 20050112895 A1 US20050112895 A1 US 20050112895A1 US 97586304 A US97586304 A US 97586304A US 2005112895 A1 US2005112895 A1 US 2005112895A1
- Authority
- US
- United States
- Prior art keywords
- slurry
- polishing
- layer
- remove
- conducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000005498 polishing Methods 0.000 title claims description 46
- 238000000034 method Methods 0.000 title claims description 36
- 239000002002 slurry Substances 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- 239000000203 mixture Substances 0.000 claims abstract description 19
- 239000010949 copper Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 8
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 239000003112 inhibitor Substances 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000002378 acidificating effect Effects 0.000 claims 4
- 239000004020 conductor Substances 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 claims 1
- 238000007517 polishing process Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 12
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000000126 substance Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 241000282376 Panthera tigris Species 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012964 benzotriazole Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24D—TOOLS FOR GRINDING, BUFFING OR SHARPENING
- B24D13/00—Wheels having flexibly-acting working parts, e.g. buffing wheels; Mountings therefor
- B24D13/14—Wheels having flexibly-acting working parts, e.g. buffing wheels; Mountings therefor acting by the front face
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Definitions
- the present invention relates generally to semiconductor fabrication and more specifically to polishing semiconductor metal layers.
- a patterned dielectric layer usually silicon oxide (oxide), within which an opening is formed; 2) a barrier layer which lines the oxide layer opening and covers the top of the patterned oxide layer; and 3) a metal layer, usually copper, formed over the patterned dielectric layer, filling the barrier lined opening.
- a variety of polishing steps with various slurries are employed.
- U.S. Pat. No. 6,217,416 B1 to Kaufman describes a first and second CMP slurry wherein the second slurry includes an abrasive, an oxidizing agent and acetic acid wherein the weight ratio of oxidizing agent/acetic agent is at least 10 and wherein the two slurries are sequentially used in a method to polish a substrate containing copper and containing tantalum or tantalum oxide or both tantalum and tantalum oxide.
- a structure having an upper patterned dielectric layer with an opening therein is provided.
- a barrier layer is formed over the patterned upper dielectric layer and lining the opening.
- a metal layer is formed over the barrier layer, filling the opening.
- a first polish step employing a first slurry composition is conducted to remove a portion of the overlying metal layer.
- a second polish step employing the first slurry composition is conducted to: polish the partially removed overlying metal layer; and to expose portions of the barrier layer overlying the patterned upper dielectric layer.
- a third polish step employing a second slurry composition is conducted to remove the exposed barrier layer portions and exposing underlying portions of the patterned upper dielectric layer.
- a fourth polish step employing the second slurry composition and BTA is conducted to buff the exposed upper dielectric layer portions.
- FIGS. 1 to 5 schematically illustrate a preferred embodiment of the present invention.
- the barrier layer is tantalum nitride (TaN)
- the dielectric layer is silicon oxide (oxide)
- the metal layer is copper (Cu)
- options (1) and (2) require consumption of an expensive TaN slurry in order to remove the TaN barrier layer from over the top of the patterned oxide layer; and option (3) requires extra dry etch tools to remove the TaN barrier layer from over the top of the patterned oxide layer.
- option (3) requires extra dry etch tools to remove the TaN barrier layer from over the top of the patterned oxide layer.
- the use of either of these three methods makes it difficult to improve the throughput of the Cu CMP process.
- FIG. 1 illustrates the initial structure of the present invention.
- Structure 10 includes patterned dielectric layer 12 formed thereover to a thickness of preferably from about 10,000 to 12,000 ⁇ and more preferably about 11,100 ⁇ .
- Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface.
- semiconductor structure is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.
- Patterned dielectric layer 12 is preferably comprised of silicon oxide, silicon nitride (SiN), FSG or silicon oxynitride (SiON) and is more preferably silicon oxide.
- Patterned dielectric layer 12 includes an opening 14 formed therein which may be a dual damascene opening as shown in the figures.
- a barrier layer 16 is preferably formed over patterned dielectric 12 , lining opening 14 .
- Barrier layer 16 is preferably formed by electrochemical plating (ECP) or physical vapor deposition (PVD) and more preferably by physical vapor deposition (PVD).
- Barrier layer 16 has a thickness of preferably from about 250 to 350 ⁇ and more preferably about 300 ⁇ .
- Barrier layer 16 is preferably comprised of TaN or Ta and is more preferably TaN.
- a metal layer 18 is then formed over barrier layer 16 , at least filling barrier layer-lined-opening 14 .
- Metal layer 18 is preferably formed by electro-chemical plating (ECP).
- Metal layer 18 has a thickness of preferably from about 6000 to 8000 ⁇ and more preferably about 7000 ⁇ .
- Metal layer 18 is preferably comprised of copper (Cu), aluminum (Al) or gold (Au) and is more preferably copper (Cu).
- the wafer/structure of FIG. 1 may be placed upon a first platen in a polisling tool and polished with a First Slurry Composition to polish/remove the bulk of metal layer 18 leaving reduced metal layer 18 ′ having a thickness of preferably from about 2000 to 4000 ⁇ and more preferably about 3000 ⁇ above the barrier-layer- 16 -lined patterned dielectric layer 12 .
- the First Slurry Composition is comprised of 600y-73 Slurry wherein:
- Al 2 O 3 preferably from about 0.4 to 0.6 wt. % and more preferably about 0.5 wt. %;
- H 2 O 2 preferably from about 2.6 to 3.4 wt. % and more preferably from about 2.8 to 3.2 wt. %;
- benzotriazole (1-H benzotriazole or BTA) as a corrosion behavior inhibitor
- This first, bulk metal layer 18 , polish is a high rate, bulk metal removal using an iScan Endpoint (Applied Material real time Cu In Situ Rate Monitor (ISRM) Endpoint System thickness monitor using eddy current to catch polishing end time) at:
- ISRM Applied Material real time Cu In Situ Rate Monitor
- the wafer/structure of FIG. 2 may be transferred to a second platen in the polishing tool and then polished with the First Slurry Composition described above to polish the metal layer 18 ′ surface 19 and to expose the portions 20 , 22 of barrier layer 16 overlying the patterned dielectric layer 12 .
- This second, final metal layer 18 ′′ polish/barrier layer 16 exposure, polish is a low pressure polish using Full Scan Endpoint (Applied Material In Situ Rate Monitor (ISRM) Endpoint System using a laser beam to catch polishing end time) at preferably from about 1.0 to 1.4 psi and more preferably about 1.2 psi for preferably from about 41 to 49 seconds and more preferably about 45 seconds (by end-point).
- ISRM Applied Material In Situ Rate Monitor
- the wafer/structure of FIG. 3 is then polished with a Second Slurry Composition on the second platen to remove the portions 20 , 22 of barrier layer 16 overlying the patterned dielectric layer 12 to expose potions 24 , 26 of the underlying patterned dielectric layer 12 .
- the Second Slurry Composition is comprised of SS6 Slurry wherein:
- SiO 2 preferably from about 5.8 to 6.2 wt. % and more preferably about 6.0 wt. %;
- This third polish step is conducted at preferably from about 1.8 to 2.2 psi and more preferably about 2.0 psi for preferably from about 31 to 39 seconds and more preferably about 35 seconds (by time).
- the wafer/structure of FIG. 4 may be transferred to a third platen within the polishing tool and polished with the Second Slurry Composition with BTA to buff the exposed portions 24 , 26 of the patterned dielectric layer 12 to form buffed exposed portions 24 ′, 26 ′ of the buffed patterned dielectric layer 12 ′.
- This fourth polish step is conducted at preferably from about 1.8 to 2.2 psi and more preferably about 2.0 psi for preferably from about 40 to 60 seconds and more preferably about 50 seconds (by time).
- FIG. 5 may be cleaned and a silicon nitride (Si 3 N 4 or nitride) layer may be deposited.
- Si 3 N 4 or nitride silicon nitride
- the inventors have found that besides: (1) being less expensive and simpler that the processes known to the inventors since neither a specific barrier-layer-slurry nor an extra barrier-layer-etch-step are required; and (2) the throughput, i.e. the wafers per hour, is improved; the same performance is achieved when polishing copper metal layers 18 in accordance with their present invention including defects, resistance (Rs) value and stress migration (SM) test.
- Rs resistance
- SM stress migration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of polishing a metal layer comprising the following steps. A structure having an upper patterned dielectric layer with an opening therein is provided. A barrier layer is formed over the patterned upper dielectric layer and lining the opening. A metal layer is formed over the barrier layer, filling the opening. A first polish step employing a first slurry composition is conducted to remove a portion of the overlying metal layer. A second polish step employing the first slurry composition is conducted to: polish the partially removed overlying metal layer; and to expose portions of the barrier layer overlying the patterned upper dielectric layer. A third polish step employing a second slurry composition is conducted to remove the exposed barrier layer portions and exposing underlying portions of the patterned upper dielectric layer. A fourth polish step employing the second slurry composition and BTA is conducted to buff the exposed upper dielectric layer portions.
Description
- This is a continuation of co-pending U.S. nonprovisional patent application Ser. No. 10/627,795, filed Jul. 25, 2003, to Chen et al., titled “Barrier-Slurry-Free Copper CMP Process,” which is related to co-pending application Ser. No. 10/714,985, filed Nov. 17, 2003, titled “Copper CMP Defect Reduction by Extra Slurry Polish;” the entirety of which applications are incorporated herein by reference.
- The present invention relates generally to semiconductor fabrication and more specifically to polishing semiconductor metal layers.
- During metal/copper chemical mechanical polishing processes, three films/materials are encountered. 1) A patterned dielectric layer, usually silicon oxide (oxide), within which an opening is formed; 2) a barrier layer which lines the oxide layer opening and covers the top of the patterned oxide layer; and 3) a metal layer, usually copper, formed over the patterned dielectric layer, filling the barrier lined opening. In order to planarize, or polish, the metal layer to form a planarized metal structure within the barrier lined opening in the dielectric layer, a variety of polishing steps with various slurries are employed.
- U.S. Pat. No. 6,217,416 B1 to Kaufman describes a first and second CMP slurry wherein the second slurry includes an abrasive, an oxidizing agent and acetic acid wherein the weight ratio of oxidizing agent/acetic agent is at least 10 and wherein the two slurries are sequentially used in a method to polish a substrate containing copper and containing tantalum or tantalum oxide or both tantalum and tantalum oxide.
- U.S. Pat. No. 6,338,744 B1 to Tateyama et al. describe a high purity polishing slurry comprising water and dispersed silica particles.
- U.S. Pat. No. 6,261,158 B1 to Holland et al. describes a multi-step CMP system used to polish a wafer to form metal interconnects in a dielectric layer upon which barrier and metal layers have been formed.
- U.S. Pat. No. 6,447,371 B2 to Brusic Kaufman et al. describes a chemical mechanical polishing slurry useful for copper/tantalum substrates.
- U.S. Pat. No. 6,313,039 B1 to Small et al. describes a chemical mechanical polishing composition and process.
- U.S. Pat. No. 6,530,968 B2 to Tsuchiya et al. describes a chemical mechanical polishing slurry.
- Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of polishing metal layers.
- Other objects will appear hereinafter.
- It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having an upper patterned dielectric layer with an opening therein is provided. A barrier layer is formed over the patterned upper dielectric layer and lining the opening. A metal layer is formed over the barrier layer, filling the opening. A first polish step employing a first slurry composition is conducted to remove a portion of the overlying metal layer. A second polish step employing the first slurry composition is conducted to: polish the partially removed overlying metal layer; and to expose portions of the barrier layer overlying the patterned upper dielectric layer. A third polish step employing a second slurry composition is conducted to remove the exposed barrier layer portions and exposing underlying portions of the patterned upper dielectric layer. A fourth polish step employing the second slurry composition and BTA is conducted to buff the exposed upper dielectric layer portions.
- The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
- FIGS. 1 to 5 schematically illustrate a preferred embodiment of the present invention.
- Processes Known to the Inventors—Not to be Considered Prior Art
- The following metal/copper chemical mechanical polishing processes are known to the inventors and are not to be considered prior art for the purposes of this invention.
- For example, when the barrier layer is tantalum nitride (TaN), the dielectric layer is silicon oxide (oxide) and the metal layer is copper (Cu), three polishing options are currently used:
-
- (1) Cu slurry polish→TaN slurry polish (w/or w/o oxide rate);
- (2) Cu slurry polish→TaN slurry polish→oxide slurry buff (w/BTA to selectively not remove Cu); and
- (3) Cu slurry polish→(clean)→TaN dry etch.
- However, options (1) and (2) require consumption of an expensive TaN slurry in order to remove the TaN barrier layer from over the top of the patterned oxide layer; and option (3) requires extra dry etch tools to remove the TaN barrier layer from over the top of the patterned oxide layer. The use of either of these three methods makes it difficult to improve the throughput of the Cu CMP process.
-
FIG. 1 illustrates the initial structure of the present invention.Structure 10 includes patterneddielectric layer 12 formed thereover to a thickness of preferably from about 10,000 to 12,000 Å and more preferably about 11,100 Å. -
Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer. - Patterned
dielectric layer 12 is preferably comprised of silicon oxide, silicon nitride (SiN), FSG or silicon oxynitride (SiON) and is more preferably silicon oxide. - Patterned
dielectric layer 12 includes anopening 14 formed therein which may be a dual damascene opening as shown in the figures. - A
barrier layer 16 is preferably formed over patterned dielectric 12, lining opening 14.Barrier layer 16 is preferably formed by electrochemical plating (ECP) or physical vapor deposition (PVD) and more preferably by physical vapor deposition (PVD). -
Barrier layer 16 has a thickness of preferably from about 250 to 350 Å and more preferably about 300 Å.Barrier layer 16 is preferably comprised of TaN or Ta and is more preferably TaN. - A
metal layer 18 is then formed overbarrier layer 16, at least filling barrier layer-lined-opening 14.Metal layer 18 is preferably formed by electro-chemical plating (ECP). -
Metal layer 18 has a thickness of preferably from about 6000 to 8000 Å and more preferably about 7000Å.Metal layer 18 is preferably comprised of copper (Cu), aluminum (Al) or gold (Au) and is more preferably copper (Cu). - As discovered by the inventors of the present invention, neither a barrier-layer-specific slurry nor a barrier-layer-etch are necessary to remove the
barrier layer 16 over the patterneddielectric layer 12. Only two different slurries are needed to polish/remove three different types of films (metal layer 18,barrier layer 16 and patterned dielectric layer 12). - First Step Polish—First Platen—First Slurry Composition—
FIG. 2 - As shown in
FIG. 2 , the wafer/structure ofFIG. 1 may be placed upon a first platen in a polisling tool and polished with a First Slurry Composition to polish/remove the bulk ofmetal layer 18 leaving reducedmetal layer 18′ having a thickness of preferably from about 2000 to 4000 Å and more preferably about 3000 Å above the barrier-layer-16-linedpatterned dielectric layer 12. - The First Slurry Composition is comprised of 600y-73 Slurry wherein:
- 600y-73 Slurry—Cabot Copper (Cu) Film Polishing Slurry (Manufactured by Cabot Microelectronics. 8A-7. No. 26, Tai-Yuan St., Chu Pei. Hsin Chu Hsien. Taiwan. 203 R.O.C.) Comprised of:
- Al2O3: preferably from about 0.4 to 0.6 wt. % and more preferably about 0.5 wt. %;
- H2O2: preferably from about 2.6 to 3.4 wt. % and more preferably from about 2.8 to 3.2 wt. %;
- KOH to adjust pH value; and
- benzotriazole (1-H benzotriazole or BTA) as a corrosion behavior inhibitor; and having
- a) pH: preferably from about 2.8 to 4.3 and more preferably about 4.1; and
- b) size of particles: preferably from about 115 to 155 nm, weight basis and more preferably from about 120 to 150 nm, weight basis.
- This first,
bulk metal layer 18, polish is a high rate, bulk metal removal using an iScan Endpoint (Applied Material real time Cu In Situ Rate Monitor (ISRM) Endpoint System thickness monitor using eddy current to catch polishing end time) at: - (1) preferably from about 2.0 to 2.4 psi and more preferably about 2.2 psi for preferably from about 36 to 44 seconds and more preferably about 40 seconds (by end-point); and then
- (2) preferably from about 1.0 to 1.4 psi and more preferably about 1.2 psi for preferably from about 18 to 22 seconds and more preferably about 20 seconds (by time).
- Second Step Polish—Second Platen—First Slurry Composition—
FIG. 3 - As shown in
FIG. 3 , the wafer/structure ofFIG. 2 may be transferred to a second platen in the polishing tool and then polished with the First Slurry Composition described above to polish themetal layer 18′surface 19 and to expose theportions barrier layer 16 overlying the patterneddielectric layer 12. - This second,
final metal layer 18″ polish/barrier layer 16 exposure, polish is a low pressure polish using Full Scan Endpoint (Applied Material In Situ Rate Monitor (ISRM) Endpoint System using a laser beam to catch polishing end time) at preferably from about 1.0 to 1.4 psi and more preferably about 1.2 psi for preferably from about 41 to 49 seconds and more preferably about 45 seconds (by end-point). - Third Step Polish—Second Platen—Second Slurry Composition—
FIG. 4 - As shown in
FIG. 4 , the wafer/structure ofFIG. 3 is then polished with a Second Slurry Composition on the second platen to remove theportions barrier layer 16 overlying the patterneddielectric layer 12 to exposepotions patterned dielectric layer 12. - The Second Slurry Composition is comprised of SS6 Slurry wherein:
- SS6 Slurry—Cabot Semi-Sperse® Polishing Slurry (also Manufactured by Cabot Microelectronics. 8A-7, No. 26 Tai-Yuan St., Chu Pei, Hsin Chu Hsien. Taiwan, 203R.O.C.) Diluted to 25% for Solids for Polishing Comprised of:
- SiO2: preferably from about 5.8 to 6.2 wt. % and more preferably about 6.0 wt. %; and
- KOH to adjust pH value; and having
- a) pH: preferably from about 9.8 to 11.4 and more preferably from about 10.0 to 11.2; and
- b) size of particles: preferably from about 125 to 185 nm, weight basis and more preferably from about 130 to 180 nm, weight basis.
- This third polish step is conducted at preferably from about 1.8 to 2.2 psi and more preferably about 2.0 psi for preferably from about 31 to 39 seconds and more preferably about 35 seconds (by time).
- Fourth Step Polish—Third Platen—Second Slurry Composition+BTA—
FIG. 5 - As shown in
FIG. 5 , the wafer/structure ofFIG. 4 may be transferred to a third platen within the polishing tool and polished with the Second Slurry Composition with BTA to buff the exposedportions dielectric layer 12 to form buffed exposedportions 24′, 26′ of the buffed patterneddielectric layer 12′. - From about 0.10 to 0.14% and more preferably about 0.12% benzotriazole (1-H benzotriazole or BTA) (corrosion behavior inhibitor) is added to the SS6 Second Slurry Composition described above as to be selective to
polished metal layer 18′″ so as to not appreciably removepolished metal layer 18″″. - This fourth polish step is conducted at preferably from about 1.8 to 2.2 psi and more preferably about 2.0 psi for preferably from about 40 to 60 seconds and more preferably about 50 seconds (by time).
- Further processing may then proceed. For example, the structure of
FIG. 5 may be cleaned and a silicon nitride (Si3N4 or nitride) layer may be deposited. - The inventors have found that besides: (1) being less expensive and simpler that the processes known to the inventors since neither a specific barrier-layer-slurry nor an extra barrier-layer-etch-step are required; and (2) the throughput, i.e. the wafers per hour, is improved; the same performance is achieved when polishing copper metal layers 18 in accordance with their present invention including defects, resistance (Rs) value and stress migration (SM) test. One of the most serious problems in Cu-based multilevel integration is the failures in stacked via resistance caused by stress-induced voids in via holes. So passing the SM test by the structure(s) formed in accordance with the method of the present invention is the index for Cu-based process.
- A better slope of pattern density correlating with the Rs value is also achieved as compared to the current processes known to the inventors. Further, when polishing copper metal layers 18 in accordance with their present invention, the inventors have found that dishing, erosion and tiger teeth were appreciably reduced.
- Advantages of the Present Invention
- The advantages of one or more embodiments of the present invention include:
- 1. simpler method;
- 2. less expensive method;
- 3. improved dishing, erosion and tiger teeth;
- 4. increased wafers/hour is achieved;
- 5. SM test passed; and
- 6. Rs value acceptable.
- While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.
Claims (23)
1. A method for polishing a semiconductor structure, comprising:
providing a semiconductor structure having first, second and third material layers;
conducting a first polishing step to remove a first portion of the first material layer;
conducting a second polishing step to remove a second portion of the first material layer and to expose a surface of the second material layer;
conducting a third polishing step to remove at least a portion of the second material layer and to expose a surface of the third material layer;
conducting a fourth polishing step to buff the exposed surface of the third material layer;
wherein the first polishing step comprises using a first slurry, and the third polishing step comprises using a second slurry, and wherein the first and second slurries have different compositions.
2. The method of claim 1 , wherein the second polishing step comprises using the first slurry and the fourth polishing step comprises using the second slurry.
3. The method of claim 1 , wherein the first slurry has a pH of from about 2.8 to about 4.3 and a particle size of from about 115 nm to about 155 nm; and the second slurry has a pH of from about 9.8 to about 11.4 and a particle size of from about 125 to about 185 nm.
4. The method of claim 1 , wherein the second slurry comprises a corrosion inhibitor.
5. The method of claim 1 , wherein the first material layer comprises a dielectric material, the second layer comprises a barrier material and the third material layer comprises a conductive material.
6. The method of claim 4 , wherein the conductive material comprises copper, aluminum or gold.
7. The method of claim 4 , wherein the barrier material comprises Tantalum or Tantalum Nitride.
8. A method for polishing a multi-layered structure, comprising:
providing a semiconductor structure having a plurality of material layers;
conducting a first polishing step using a first slurry to remove a first portion of the plurality of material layers;
conducting a second polishing step using the first slurry to remove a second portion of the plurality of material layers;
conducting a third polishing step using a second slurry to remove a third portion of the plurality of material layers;
conducting a fourth polishing step using the second slurry to remove a fourth portion of the plurality of material layers;
wherein the first and second slurries have substantially different compositions.
9. The method of claim 8 , wherein the first slurry is acidic.
10. The method of claim 9 , wherein the first slurry has a pH of from about 2.8 to about 4.3.
11. The method of claim 8 , wherein the second slurry is alkaline.
12. The method of claim 11 , wherein the second slurry has a pH of from about 9.8 to about 11.4.
13. The method of claim 8 , wherein the first slurry comprises particles having a size of from about 115 nm to about 155 nm; and the second slurry comprises particles having a size of from about 125 to about 185 nm.
14. The method of claim 8 , wherein the first polishing step is performed at a first polishing pressure for a first time period and a second polishing pressure for a second time period, wherein the first polishing pressure is greater than the second polishing pressure.
15. The method of claim 14 , wherein the first polishing pressure is from about 2.0 to about 2.4 psi, and the second polishing pressure is from about 1.0 psi to about 1.4 psi.
16. The method of claim 8 , wherein the second slurry further comprises a corrosion inhibitor.
17. A method for performing chemical-mechanical polishing (CMP), comprising:
providing a semiconductor structure having a dielectric layer, a barrier layer overlying at least a portion of the dielectric layer, and a metal layer overlying at least a portion of the barrier layer;
conducting a first CMP step using an acidic slurry to remove a first thickness of the semiconductor structure;
conducting a second CMP step the acidic slurry to remove a second thickness of the semiconductor structure;
conducting a third CMP step using an alkaline slurry to remove a third thickness of the semiconductor structure;
conducting a fourth CMP step using the alkaline slurry to remove a fourth thickness of the semiconductor structure;
wherein the first CMP step comprises removing at least a portion of the metal layer and the fourth CMP step comprises buffing a surface of the dielectric layer.
18. The method of claim 17 , wherein the acidic slurry has a pH of from about 2.8 to about 4.3.
19. The method of claim 17 , wherein the alkaline slurry has a pH of from about 9.8 to about 11.4.
20. The method of claim 17 , wherein the first slurry comprises particles having a size of from about 115 nm to about 155 nm; and the second slurry comprises particles having a size of from about 125 to about 185 nm.
21. The method of claim 17 , wherein the first CMP step is carried out at a first polishing pressure for a first time period and a second polishing pressure for a second time period, wherein the first polishing pressure is greater than the second polishing pressure.
22. The method of claim 17 , wherein the first polishing pressure is from about 2.0 psi to about 2.4 psi, and the second polishing pressure is from about 1.0 to about 1.4 psi.
23. The method of claim 17 , wherein the alkaline slurry further comprises a corrosion inhibitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/975,863 US20050112895A1 (en) | 2003-07-25 | 2004-10-28 | Method of chemical-mechanical polishing |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/627,795 US6830504B1 (en) | 2003-07-25 | 2003-07-25 | Barrier-slurry-free copper CMP process |
US10/975,863 US20050112895A1 (en) | 2003-07-25 | 2004-10-28 | Method of chemical-mechanical polishing |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/627,795 Continuation US6830504B1 (en) | 2003-07-25 | 2003-07-25 | Barrier-slurry-free copper CMP process |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050112895A1 true US20050112895A1 (en) | 2005-05-26 |
Family
ID=33490923
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/627,795 Ceased US6830504B1 (en) | 2003-07-25 | 2003-07-25 | Barrier-slurry-free copper CMP process |
US10/975,863 Abandoned US20050112895A1 (en) | 2003-07-25 | 2004-10-28 | Method of chemical-mechanical polishing |
US11/494,754 Expired - Fee Related USRE45468E1 (en) | 2003-07-25 | 2006-07-27 | Barrier-slurry-free copper CMP process |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/627,795 Ceased US6830504B1 (en) | 2003-07-25 | 2003-07-25 | Barrier-slurry-free copper CMP process |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/494,754 Expired - Fee Related USRE45468E1 (en) | 2003-07-25 | 2006-07-27 | Barrier-slurry-free copper CMP process |
Country Status (4)
Country | Link |
---|---|
US (3) | US6830504B1 (en) |
CN (1) | CN1295762C (en) |
SG (1) | SG111180A1 (en) |
TW (1) | TWI254372B (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7354332B2 (en) * | 2003-08-04 | 2008-04-08 | Applied Materials, Inc. | Technique for process-qualifying a semiconductor manufacturing tool using metrology data |
US7232362B2 (en) * | 2004-10-12 | 2007-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chemical mechanical polishing process for manufacturing semiconductor devices |
JP2006135072A (en) * | 2004-11-05 | 2006-05-25 | Fujimi Inc | Polishing method |
KR100660916B1 (en) * | 2006-02-09 | 2006-12-26 | 삼성전자주식회사 | Method of fabricating a semiconductor device including planarizing a conductive layer using parameters of pattern density and depth of trenches |
KR100796513B1 (en) * | 2006-08-22 | 2008-01-21 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
JP5015696B2 (en) * | 2006-09-04 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and manufacturing apparatus |
US7763517B2 (en) * | 2007-02-12 | 2010-07-27 | Macronix International Co., Ltd. | Method of forming non-volatile memory cell |
CN102528638A (en) * | 2010-12-29 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Chemical-mechanical grinding method and equipment for copper |
US9010417B2 (en) | 2012-02-09 | 2015-04-21 | Baker Hughes Incorporated | Downhole screen with exterior bypass tubes and fluid interconnections at tubular joints therefore |
JP5941763B2 (en) * | 2012-06-15 | 2016-06-29 | 株式会社荏原製作所 | Polishing method |
CN105081891A (en) * | 2014-05-07 | 2015-11-25 | 盛美半导体设备(上海)有限公司 | Method of preventing abrasive particles from embedding into wafer surface in chemical mechanical grinding process |
CN110491790B (en) * | 2018-05-09 | 2021-11-09 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
CN117855037B (en) * | 2024-03-07 | 2024-06-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5676587A (en) * | 1995-12-06 | 1997-10-14 | International Business Machines Corporation | Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride |
US5913712A (en) * | 1995-08-09 | 1999-06-22 | Cypress Semiconductor Corp. | Scratch reduction in semiconductor circuit fabrication using chemical-mechanical polishing |
US6217416B1 (en) * | 1998-06-26 | 2001-04-17 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper/tantalum substrates |
US6261158B1 (en) * | 1998-12-16 | 2001-07-17 | Speedfam-Ipec | Multi-step chemical mechanical polishing |
US6313039B1 (en) * | 1996-07-25 | 2001-11-06 | Ekc Technology, Inc. | Chemical mechanical polishing composition and process |
US6319833B1 (en) * | 1998-12-07 | 2001-11-20 | Advanced Micro Devices, Inc. | Chemically preventing copper dendrite formation and growth by spraying |
US6338744B1 (en) * | 1999-01-11 | 2002-01-15 | Tokuyama Corporation | Polishing slurry and polishing method |
US6376009B1 (en) * | 1999-11-01 | 2002-04-23 | Hans Bergvall | Display unit and method of preparing same |
US6530968B2 (en) * | 2000-11-24 | 2003-03-11 | Nec Electronics Corporation | Chemical mechanical polishing slurry |
US6555477B1 (en) * | 2002-05-22 | 2003-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing Cu CMP corrosion |
US6595832B2 (en) * | 1999-06-03 | 2003-07-22 | Micron Technology, Inc. | Chemical mechanical polishing methods |
US6692546B2 (en) * | 2001-08-14 | 2004-02-17 | Advanced Technology Materials, Inc. | Chemical mechanical polishing compositions for metal and associated materials and method of using same |
US6709316B1 (en) * | 2000-10-27 | 2004-03-23 | Applied Materials, Inc. | Method and apparatus for two-step barrier layer polishing |
US6736701B1 (en) * | 2001-11-20 | 2004-05-18 | Taiwan Semiconductor Manufacturing Company | Eliminate broken line damage of copper after CMP |
US6740591B1 (en) * | 2000-11-16 | 2004-05-25 | Intel Corporation | Slurry and method for chemical mechanical polishing of copper |
US6749487B2 (en) * | 2001-08-27 | 2004-06-15 | Hoya Corporation | Method of polishing glass substrate for information recording media, and glass substrate for information recording media |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5738574A (en) | 1995-10-27 | 1998-04-14 | Applied Materials, Inc. | Continuous processing system for chemical mechanical polishing |
US6573173B2 (en) | 1999-07-13 | 2003-06-03 | Motorola, Inc. | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process |
US6274478B1 (en) | 1999-07-13 | 2001-08-14 | Motorola, Inc. | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process |
US6602724B2 (en) * | 2000-07-27 | 2003-08-05 | Applied Materials, Inc. | Chemical mechanical polishing of a metal layer with polishing rate monitoring |
US6579798B2 (en) | 2001-09-24 | 2003-06-17 | Texas Instruments Incorporated | Processes for chemical-mechanical polishing of a semiconductor wafer |
-
2003
- 2003-07-25 US US10/627,795 patent/US6830504B1/en not_active Ceased
-
2004
- 2004-04-05 SG SG200401878A patent/SG111180A1/en unknown
- 2004-07-21 CN CNB2004100709616A patent/CN1295762C/en not_active Expired - Fee Related
- 2004-07-23 TW TW93122018A patent/TWI254372B/en not_active IP Right Cessation
- 2004-10-28 US US10/975,863 patent/US20050112895A1/en not_active Abandoned
-
2006
- 2006-07-27 US US11/494,754 patent/USRE45468E1/en not_active Expired - Fee Related
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5913712A (en) * | 1995-08-09 | 1999-06-22 | Cypress Semiconductor Corp. | Scratch reduction in semiconductor circuit fabrication using chemical-mechanical polishing |
US5676587A (en) * | 1995-12-06 | 1997-10-14 | International Business Machines Corporation | Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride |
US6313039B1 (en) * | 1996-07-25 | 2001-11-06 | Ekc Technology, Inc. | Chemical mechanical polishing composition and process |
US6447371B2 (en) * | 1998-06-26 | 2002-09-10 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper/tantalum substrates |
US6217416B1 (en) * | 1998-06-26 | 2001-04-17 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper/tantalum substrates |
US6319833B1 (en) * | 1998-12-07 | 2001-11-20 | Advanced Micro Devices, Inc. | Chemically preventing copper dendrite formation and growth by spraying |
US6261158B1 (en) * | 1998-12-16 | 2001-07-17 | Speedfam-Ipec | Multi-step chemical mechanical polishing |
US6338744B1 (en) * | 1999-01-11 | 2002-01-15 | Tokuyama Corporation | Polishing slurry and polishing method |
US6595832B2 (en) * | 1999-06-03 | 2003-07-22 | Micron Technology, Inc. | Chemical mechanical polishing methods |
US6376009B1 (en) * | 1999-11-01 | 2002-04-23 | Hans Bergvall | Display unit and method of preparing same |
US6709316B1 (en) * | 2000-10-27 | 2004-03-23 | Applied Materials, Inc. | Method and apparatus for two-step barrier layer polishing |
US6740591B1 (en) * | 2000-11-16 | 2004-05-25 | Intel Corporation | Slurry and method for chemical mechanical polishing of copper |
US6530968B2 (en) * | 2000-11-24 | 2003-03-11 | Nec Electronics Corporation | Chemical mechanical polishing slurry |
US6692546B2 (en) * | 2001-08-14 | 2004-02-17 | Advanced Technology Materials, Inc. | Chemical mechanical polishing compositions for metal and associated materials and method of using same |
US6749487B2 (en) * | 2001-08-27 | 2004-06-15 | Hoya Corporation | Method of polishing glass substrate for information recording media, and glass substrate for information recording media |
US6736701B1 (en) * | 2001-11-20 | 2004-05-18 | Taiwan Semiconductor Manufacturing Company | Eliminate broken line damage of copper after CMP |
US6555477B1 (en) * | 2002-05-22 | 2003-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing Cu CMP corrosion |
Also Published As
Publication number | Publication date |
---|---|
SG111180A1 (en) | 2005-05-30 |
TW200511418A (en) | 2005-03-16 |
US6830504B1 (en) | 2004-12-14 |
CN1295762C (en) | 2007-01-17 |
CN1577769A (en) | 2005-02-09 |
TWI254372B (en) | 2006-05-01 |
USRE45468E1 (en) | 2015-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE45468E1 (en) | Barrier-slurry-free copper CMP process | |
US5954975A (en) | Slurries for chemical mechanical polishing tungsten films | |
US6350694B1 (en) | Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials | |
US6946397B2 (en) | Chemical mechanical polishing process with reduced defects in a copper process | |
US7033409B2 (en) | Compositions for chemical mechanical planarization of tantalum and tantalum nitride | |
JP2001230230A (en) | Planarized copper cleaning for reducing defects | |
JP2001156029A (en) | POST Cu CMP POLISHING FOR REDUCED DEFECTS | |
US20020061635A1 (en) | Solution for chemical mechanical polishing and method of manufacturing copper metal interconnection layer using the same | |
US20070105247A1 (en) | Method And Apparatus For Detecting The Endpoint Of A Chemical-Mechanical Polishing Operation | |
US6555477B1 (en) | Method for preventing Cu CMP corrosion | |
US6736701B1 (en) | Eliminate broken line damage of copper after CMP | |
US6316364B1 (en) | Polishing method and polishing solution | |
US6403466B1 (en) | Post-CMP-Cu deposition and CMP to eliminate surface voids | |
US6919276B2 (en) | Method to reduce dishing and erosion in a CMP process | |
US20040110370A1 (en) | Method of manufacturing a semiconductor device | |
JP2002064070A (en) | Chemomechanical polishing method and slurry composition therefor | |
US6436832B1 (en) | Method to reduce polish initiation time in a polish process | |
JP2003347299A (en) | Method for manufacturing semiconductor integrated circuit device | |
US6413869B1 (en) | Dielectric protected chemical-mechanical polishing in integrated circuit interconnects | |
US6461230B1 (en) | Chemical-mechanical polishing method | |
US6737348B2 (en) | Method for forming buried interconnect | |
KR100830744B1 (en) | Metal chemical mechanical polishing process for minimizing dishing during semiconductor wafer fabrication | |
US6699785B2 (en) | Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects | |
US20040043611A1 (en) | Method of reducing a defect level after chemically mechanically polishing a copper-containing substrate by rinsing the substrate with an oxidizing solution | |
US7025661B2 (en) | Chemical mechanical polishing process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |