US20050083721A1 - Granularity memory column access - Google Patents

Granularity memory column access Download PDF

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US20050083721A1
US20050083721A1 US10/970,947 US97094704A US2005083721A1 US 20050083721 A1 US20050083721 A1 US 20050083721A1 US 97094704 A US97094704 A US 97094704A US 2005083721 A1 US2005083721 A1 US 2005083721A1
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column
memory array
data
storage units
address
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US10/970,947
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Craig Hampel
Richard Warmke
Frederick Ware
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Hampel Craig E.
Warmke Richard E.
Ware Frederick A.
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Priority to US09/949,464 priority Critical patent/US6825841B2/en
Application filed by Hampel Craig E., Warmke Richard E., Ware Frederick A. filed Critical Hampel Craig E.
Priority to US10/970,947 priority patent/US20050083721A1/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/122Tiling
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory

Abstract

A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.

Description

    CROSS-REFERENCE(S) TO RELATED APPLICATION(S)
  • This U.S. Patent Application is a continuation application of prior application Ser. No. 09/949,464, filed Sep. 7, 2001.
  • TECHNICAL FIELD
  • The invention relates to memory devices and in particular to memory devices in which variable, overlapping groups of storage units can be accessed.
  • BACKGROUND
  • Typical DRAM memory is accessed using sequential row and column operations, typically referred to as RAS (row address strobe) and CAS (column address strobe) operations. RAS operations specify row addresses, and CAS operations specify column addresses to select columns within the previously addressed rows.
  • FIG. 1 illustrates pertinent components of a typical DRAM memory device 10. DRAM 10 comprises a plurality of memory arrays 12, each having a plurality of memory storage units (represented as squares within arrays 12). In this simplified example, there are eight rows of memory storage units. There are six columns of storage units within each array. Each storage unit comprises one or a plurality of individual memory cells.
  • Memory device 10 has a row decoder 14 that receives a row address during a RAS operation. The row decoder is sometimes referred to as an “X” decoder.
  • The row address specifies a particular row of storage units. The RAS operation causes this row of storage units to be read into sense amplifiers (not shown). The same row is typically read from each of the multiple memory arrays 12. In FIG. 1, a row of storage units is highlighted to indicate that this row has been selected by row decoder 14.
  • For purposes of discussion, the storage units are labeled with identifiers comprising an alphabetic character with a numeric subscript. The alphabetic character indicates the array in which the storage unit resides, and the subscript indicates the column within the array. For example, storage unit B3 is the storage unit at column 3 of array B.
  • The DRAM device 10 also has column decoders 16, which are also sometimes referred to as “Y” decoders or lane decoders. In this example, there is a column decoder associated with each of the four memory arrays 12. The column decoders correspond to data I/O lanes 18 through which data is communicated to and from memory device 10. Each data I/O lane comprises a number of individual I/O lines corresponding to the number of memory cells in each data storage unit. For example, each I/O lane might be a thirty-two bits in width. Combined, four I/O lanes of this width would allow 128 bits or 16 bytes of parallel data access.
  • The column decoders receive a column address that is specified during a CAS operation. Each column decoder is responsive to the specified column address to generate a column select signal (not specifically shown in FIG. 1) that selects a column of storage units from the row that was previously selected during a RAS operation. In the example shown, the specified column address has resulted in a column select signal corresponding to column 2—this is illustrated by the vertical line extending downward from the selected row and column within each of arrays 12.
  • In response to a column selection during a CAS operation, the column decoders transfer data from the selected storage units to or from I/O pins or connectors corresponding to the individual bit lines of the data lanes 18.
  • The data contained in a single row, which is specified during a RAS operation, is sometimes referred to as a page. Once a RAS operation has been completed, it is possible to complete multiple subsequent CAS operations to read various portions of the specified row or page, without the necessity of intervening RAS operations. Each CAS operation is carried out with a specified column address, and each column address corresponds to a unique set of storage units. In the example discussed above, where there are four data lanes of 32 bits each, each 11 column address corresponds to a unique 16 bytes of information that can be read from or written to the memory device in parallel.
  • Note that some memory devices contain multiple banks of storage cells that may or may not share row and column decoders, although each bank does have dedicated sense amplifiers.
  • FIG. 2 shows an entire row or page of storage units 20, delineated by CAS boundaries that define the unique sets or groups of storage units that can be accessed during any given CAS cycle. With a CAS address of 0, the column decoders 16 of FIG. 1 select the first column of each memory array and transfer information to or from the storage units of those columns. With a CAS address of 1, the column decoders 16 select the second column of each memory array. For each CAS address, the lane decoders select a corresponding unique set or group of the storage units. Each unique set is formed by corresponding columns of the memory arrays that are presented in parallel at data I/O lanes 18.
  • Thus, the size of the data I/O path typically dictates the alignment at which data can be accessed. More specifically, the alignment of data access is fixed by the CAS boundaries; the addressing scheme divides the storage units into discrete, mutually exclusive groups corresponding to different CAS addresses, and access of any individual storage unit requires accessing the entire group to which the storage unit belongs. For example, storage unit C2 can only be retrieved in a group that contains storage units A2, B2, C2, and D2.
  • In some cases, it is desired to access a relatively small number of storage units that span multiple groups. Even though the number of desired storage units might be less than the number of storage units within any given group, it is 11 necessary to perform two or more CAS operations if the desired storage units span two or more groups.
  • In FIG. 2, for example, suppose it is desired to access storage units D0 and A1. Because these two storage units fall under different CAS addresses, two CAS operations are required to access the two storage units. A first CAS operation accesses storage units A0, B0, C0, and D0, and a second CAS operation accesses storage units A1, B1, C1, and D1.
  • This has not been a significant limitation in the past, because the width of the data I/O path has been relatively limited, and most I/O accesses span several CAS addresses. However, current speed requirements are resulting in memory devices having relatively wide data paths, such as 16 bytes or wider. When the data path becomes this wide, many data accesses involve a number of contiguous storage units that is smaller than width of the data path. Furthermore, the nature of some data storage applications makes it difficult to ensure that memory accesses will be aligned at CAS boundaries. Memory accesses tend to be less efficient in applications such as this.
  • A computer graphics subsystem is an example of an application that might utilize small transfers at an alignment that does not necessarily correspond to CAS boundaries within a memory device. Computer graphics systems typically use DRAM memory to store pixel information. Such pixel information might include color component intensities, Z buffer data, texture information, video data, and other information related to an array of displayed pixels.
  • Computer graphics systems typically include a graphics controller that interacts with one or more DRAM devices. Access speed is very important in 11 graphics subsystems, and a variety of techniques might be employed to optimize the efficiency of memory access cycles.
  • One such optimization technique is referred to as “tiling,” in which rectangular tiles of graphics pixels are represented by portions of memory that can be accessed during a single CAS cycle. For example, in a system allowing data transfers of 16 bytes during each CAS operation, each graphics tile might be defined as a four-by-four square, represented by 16 bytes of data. Within the memory controller, memory is mapped in such a way that each four-by-four square is represented by 16 bytes that can be read or written in a single CAS cycle. In other words, the tiles are aligned at CAS boundaries.
  • FIG. 3 illustrates an example of tiling where each tile is defined as a four-by-four square of 16 pixels, and represented within DRAM memory by 16 bytes of data. The layout of storage units in FIG. 3 indicates their mapping to physical pixel locations—the storage units represent a two-dimensional array of pixels corresponding to the two-dimensional arrangement shown in FIG. 3. The storage units shown in FIG. 3 correspond to a row or page of data, in a DRAM whose rows or pages each include 128 bytes of data that can be accessed in mutually exclusive groups of 16 bytes per CAS operation. FIG. 3 shows the CAS addresses corresponding to individual tiles, ranging from 0 to 7. This arrangement allows eight tiles per row or page of DRAM memory.
  • Tiling works well because access to graphics data tends to be localized in two dimensions; a two-dimensional graphical object can often be efficiently accessed through one or more rectangular tiles such as illustrated in FIG. 3. Increasing DRAM bandwidths, however, threaten to actually decrease the efficiency with which such data can be accessed. This is because larger data paths result in larger tiles. In some cases, the size of the tile is larger than the actual graphical objects that need to be accessed. In other cases, the size of the tile is comparable in size to that of graphical objects in the system, but those objects are positioned across several tiles. In other words, the objects are not aligned at CAS boundaries. Thus, it might be necessary to access two or more tiles of data in situations where much less data is actually needed by the graphics processor.
  • FIG. 3 illustrates a situation such as this, in which a graphics processor requires access to a small triangular object that is represented by the hatched storage units shown in FIG. 3. Although the triangle has only six pixels, they are spread across three tiles. To process this object requires three CAS operations. Although the three CAS operations access forty-eight bytes, forty-two will not be used. This represents a significant inefficiency.
  • Other DRAM operations suffer from similar inefficiencies. Routers, for example, utilize DRAM memory to store data packets. Each packet, which typically includes a small header and a larger payload, is optimally stored in a region of DRAM memory that can be accessed in a single CAS operation. In other words, packets are aligned at CAS boundaries. During much of its operation, however, the router needs access only to the header, because the header contains the information needed by the router to determine how to handle the packet as a whole. Even though only the relatively small header is needed, the organization of DRAM memory typically requires retrieval of the entire packet in order to read the header information. In order to retrieve multiple headers, multiple CAS operations must be performed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a simplified block diagram showing pertinent components of a prior art DRAM.
  • FIG. 2 illustrates the concept of CAS boundaries in the prior art.
  • FIG. 3 illustrates an example of graphics tiling as used in the prior art.
  • FIG. 4 is a simplified block diagram showing pertinent components of a memory device allowing variable offsets.
  • FIG. 5 illustrate an arrangement of memory storage units and how they are accessed when using a variable offset.
  • FIG. 6 is a simplified block diagram showing pertinent components of a graphics subsystem incorporating a memory device similar to that shown in FIG. 4.
  • FIG. 7 illustrates an arrangement of memory storage units when used in conjunction with graphics tiling techniques.
  • FIG. 8 illustrates an example of a horizontal offset in the system of FIG. 6.
  • FIG. 9 illustrates an example of a vertical offset in the system of FIG. 6.
  • FIG. 10 illustrates an example of both a horizontal offset and a vertical offset in the system of FIG. 6.
  • FIG. 11 is a simplified block diagram showing pertinent components of a packet routing device incorporating a memory device similar to that shown in FIG. 4.
  • FIG. 12 illustrates an arrangement of memory storage units used to store information packets and headers of such information packets in the system shown by FIG. 11.
  • FIG. 13 illustrates an example of accessing information packet headers in the system shown by FIG. 11.
  • DETAILED DESCRIPTION
  • Variable Offset Column Access
  • FIG. 4 shows pertinent components of an integrated circuit memory device 100 that allows variable-offset CAS operations. Memory device 100 comprises a plurality of memory arrays 112(A)-112(D) each of which comprises a plurality of storage units or memory cells 113 arranged in rows and columns. A row decoder 114 receives a row address 115 during a RAS cycle or operation to specify a row of the arrays to be read into sense amplifiers (not shown) for subsequent CAS access cycles or operations. A row of storage units is shown highlighted to indicate an example of row selection as a result of a RAS operation. In this example, the sixth row of storage units has been selected.
  • Row decoder 114 is sometimes referred to as a Y decoder. A row of storage units is sometimes referred to as a memory page.
  • Each storage unit comprises one or more memory cells. For example, a storage unit might comprise eight memory cells, or a byte. Alternatively, a storage unit might comprise multiple bytes of memory cells.
  • In FIG. 4 and in the following discussion and figures, an individual storage unit will be referred to by an alphabetic character and a numeric subscript, such as “B2.” The alphabetic character indicates the memory array of the storage unit, and the subscript indicates the column within that array. Thus, storage unit B2 is the storage unit at column 2 of memory array 112(B). It will be assumed that row selection has already taken place, and that the indicated storage unit is from the previously selected row.
  • Memory device 100 further comprises column selection logic that selects one or more columns of storage units from the currently selected row. The column selection logic includes a plurality of column decoders 116(A)-116(D). In this example, an individual column decoder 116 corresponds to and is associated with each of memory arrays 112. The column decoders correspond respectively to parallel data I/O lanes 118(A)-18(D) through which data is communicated to and from memory device 100. Each data I/O lane 118 comprises a number of individual I/O lines corresponding to the number of memory cells in an individual data storage unit. For example, each I/O lane might be eight bits or a byte in width. The column decoders are responsive to decoder addresses or column addresses received during a memory cycle to select columns from the respective memory arrays for access through the data I/O lanes.
  • The collective data I/O lanes form a parallel data I/O path through which groups of storage units are accessed in parallel. Although only four I/O lanes are shown in FIG. 4, a memory device might desirably have a larger number of memory arrays 112, column decoders 116, and data I/O lanes 118. For example, a 32 byte wide data path might be implemented with 32 memory arrays, column decoders, and I/O lanes, each of which is one byte in width. Alternatively, a data path of the same width might be implemented by four memory arrays as shown in FIG. 4, where each storage unit is eight bytes or 32 bits in width. Note also that the internal data width of the memory device may be different than the external interface.
  • Column decoders 116 are sometimes referred to as X decoders, and are also referred to herein as lane decoders.
  • The column selection logic of memory device 100 further comprises 11 column decoder address specification logic 120 from which the column decoders 116 are configured to receive decoder addresses or column specifications. The decoder address specification logic is responsive to a received address specification to select the groups of memory cells for access through the data I/O path formed by the collective data I/O lanes 118. The address specification logic 120 allows selection of memory cells at a granularity that is different than and preferably less than the width of the data I/O path. This is accomplished in the described embodiment by calculating potentially different decoder addresses for the multiple column decoders 116(A)-116(D). Specifically, at least two of the calculated decoder addresses supplied to the column decoders during a given memory cycle can be different from each other.
  • The column selection logic allows specification and selection of overlapping groups of memory cells for parallel access through data I/O lanes 118. The term “overlapping” is used herein to indicate groups of memory cells or storage units that are not mutually exclusive. That is, different groups can include one or more common memory cells or storage units. For example, a first group might include a particular storage unit such as storage unit C1, and another, different group might also include the same storage unit C1. To make the example more specific, storage unit C, might be accessible as part of any of the following four, different, non-mutually-exclusive groups: {D0, A1, B1, C1}, {A1, B1, C1, D1}, {B1, C1, D1, A2}, and {C1, D1, A2, B2}. Other configurations of the column selection logic might of course allow different group compositions. Thus; the concept of a “group” of storage units is not limited to storage units that are “adjacent” each other in a linear arrangement of storage units such as depicted in FIG. 2.
  • In one embodiment, address specification logic 120 receives a column address 121 and one or more adjustment values 122 during a CAS operation. In response to the column address and adjustment value(s), the decoder logic 120 calculates or derives decoder addresses or specifications for the individual column decoders 116. In this example, the adjustment value is a column offset or lane offset, indicating the number of columns or I/O lanes by which an offset is desired from a base column address. As shown in FIG. 4, the respective column decoders are configured to receive potentially different decoder addresses during a single memory access cycle. The column decoders are responsive to the received decoder addresses to respectively select different columns or sets of memory cells for access through I/O lanes 117 during a memory cycle. Thus, in contrast to the prior art device described above in the “Background” section, the column decoders are not all responsive to a common column address. Rather, different addresses can be provided to different column decoders, depending on the specified offset.
  • Although the disclosed embodiment is configured to receive both an address and an offset as part of a CAS operation, the offset can be provided in different ways. For example, the offset can be provided to the memory device using a command other than a CAS command and stored in a memory device register before an actual CAS operation or other memory access operation. In one embodiment, a special command can be used to instruct the memory device regarding whether or not a previously provided offset should be applied in combination with a CAS or other memory address during a memory access operation. Alternatively, the CAS command itself might indicate whether the offset should be applied. As yet another alternative, the memory device might be set by a command or through some other means into one of a plurality of addressing modes, in which at least one of the addressing modes uses supplied or stored offsets in combination with received CAS addresses. At least one other of the addressing modes would ignore offset values, in which case the memory cells would be accessed in mutually exclusive groups. A similar result could be obtained by setting the offset value to zero.
  • Furthermore, although the column selection logic is implemented in FIG. 4 by providing independent column addresses to the four column decoders 116, other embodiments might be configured differently. For example, each column decoder might be configured to receive the column address and offset, and to individually account for the offset when making a column selection.
  • FIG. 5, in conjunction with FIG. 4, illustrates an example of how different storage units can be selected. FIG. 5 shows the storage units of the row that has been selected in FIG. 4 by way of a previous RAS operation. As explained in the “Background” section, above, such a row comprises a page of storage units. FIG. 5 shows the memory page arranged in a linear sequence, as it might be viewed in many systems. A column address equal to 0 corresponds to storage units A0, B0, C0, and D0; a column address equal to 1 corresponds to storage units A1, B1, C1, and D1; a column address equal to 2 corresponds to storage units A2, B2, C2, and D2; and so on. Column or lane offsets are specified relative to the illustrated linear sequence of storage units.
  • In this case, assume it is desired to access storage units C1, D1, A2, and B2. This set of storage units is not aligned at a CAS boundary, but spans two column addresses. However, these storage units can be accessed in a single memory access operation by specifying a column address equal to 1 and a column or lane offset equal to 2. It should be noted that each of the requested storage units corresponds to a different data I/O lane 118 and associated lane decoder 116. This will be the case for any contiguous set of storage units whose number is less than or equal to the number of data I/O lanes.
  • Decoder address specification logic 120 receives the column address of 1 and an adjustment value or lane offset value of 2. In response to receiving these values, logic 120 calculates decoder addresses for the respective column or lane decoders 116.
  • Vertical arrows in FIG. 4 indicate the column specified by logic 120 for each column decoder in this example. In response to the different column specifications, a different column can potentially be selected from each of the respective arrays 112. In this example, the two left-most column decoders 116(A) and 116(B) are supplied with column specifications corresponding to column 2 of each of the respective arrays 112(A) and 112(B), thereby accessing storage units A2 and B2 (column 2 of arrays 112(A) and 112(B)). The two right-most column decoders 116(C) and 116(D) are supplied with column specifications corresponding to column 1 of each of the respective arrays 112(C) and 112(D), thereby accessing storage units C1 and D1 (column 1 of arrays 112(C) and 112(D)). Thus, as illustrated at the bottom of FIG. 4, storage units C1, D1, A2, and B2 are transferred through I/O lanes 118.
  • Note that the storage units at I/O lanes 118 are out of their normal order, due to their natural lane assignments. That is, a storage unit from array 112(A) will always be accessed through I/O lane 118(A), a storage unit from array 112(B) will always be accessed through I/O lane 118(B), and so on. This is because any given storage unit is accessible in this implementation through one and only one I/O lane, and each storage unit is always accessible through the same I/O lane. Additional logic may be implemented within memory device 100 to restore the normal ordering at pins 118. However, memory device 100 preferably does not include such additional logic; devices that access memory device 100 are preferably configured to account for the variable ordering when using this mode of memory access.
  • The configuration shown in FIG. 4 improves upon the CAS alignment of the prior art by allowing column offsets at a granularity that is equal to that of the column decoders and data I/O lanes. Stated alternatively, memory accesses do not need to be aligned at CAS boundaries. By reducing the size of individual I/O lanes and increasing their number, alignment granularity can be reduced to whatever level is desired. Furthermore, such small granularity can be achieved with very little in the way of additional hardware and without increasing the number of core I/O data bits. Additional hardware is kept to a minimum by utilizing existing column I/O lines rather than creating new data paths.
  • Although this embodiment illustrates one example of how a particular storage unit might be available in one of four different groups, other embodiments might provide for different group configurations in which a storage unit is accessible as part of two or more selectable groups of storage units. In other words, the storage units comprising a group are not necessarily limited to storage units that appear “adjacent” each other in the linear arrangement illustrated in FIG. 5. A good example of this is described below, in the subsection entitled “Packet Router”.
  • Column logic 120 can be implemented in different ways, such as with an arithmetic logic unit or through the use of a lookup table. Actual parameters will depend the number of data I/O lanes 118. In this example, decoder addresses are calculated or derived from the column address and lane offset as indicated in the following table, where COL is the received column address; OFFSET is the received adjustment value, column offset, or lane offset; and DEC(a), DEC(b), DEC(c), and DEC(d) are the decoder addresses that are calculated by logic 120 and supplied to the four column decoders 116(A), 116(B), 116(C), and 116(D), respectively. Each row of the table indicates how a decoder address is calculated for a particular lane decoder as a function of the four possible OFFSET values. TABLE 2 OFFSET 0 1 2 3 DEC(a) COL COL + 1 COL + 1 COL + 1 DEC(b) COL COL COL + 1 COL + 1 DEC(c) COL COL COL COL + 1 DEC(d) COL COL COL COL
  • The table can be extended to cover situations in which there are more than four I/O lanes and corresponding column decoders.
  • 2-D Spatial Offset In a Graphics System
  • FIG. 6 shows a graphics system 200 that includes a graphics controller 202 and one or more DRAM memory devices 204 configured for use as graphics memory. Each memory device 204 is configured similarly to the device described above with reference to FIG. 4, to allow variable offsets. In this embodiment, the memory storage units are configured and mapped to represent rectangular tiles of graphics pixels having at least two pixel dimensions. As will become apparent in the following discussion, the offsets in this embodiment can be specified in terms of horizontal and/or vertical pixel rows, relative to the rectangular graphics tiles. The offsets are not constrained to multiples of the two pixel dimensions.
  • Each memory device includes a plurality of memory arrays 212 and an associated row decoder 214. Each memory array 212 comprises a plurality of memory storage units configured to store graphics memory data.
  • Memory device 200 includes column or lane selection logic that includes a lane decoder 216 associated with each array 212. There is a data I/O lane 218 corresponding to each array 212 and lane decoder 216. The data I/O lanes are accessed in parallel by graphics controller 202. The column or lane selection logic also includes address specification logic 220, also referred to herein as decoder logic, which calculates decoder addresses for each of lane decoders 216. As described above, the lane decoders are configured to receive independent address specifications from decoder logic 220. The address specifications provided by decoder logic 220 are calculated or derived from a CAS column address and one or more adjustment values provided by graphics controller 202. In this example, the adjustment values comprise one or more dimensional offset values specified in terms of pixel columns and rows, as will be described in more detail below. The lane decoders are responsive to the address specifications to select memory storage units for transfer through data lanes 218. As with the embodiment previously described, the column selection logic is not constrained to accessing corresponding columns of the arrays in parallel. Rather, a single memory operation can potentially access, in parallel, a different column from each of the available arrays.
  • In the described embodiment, each storage unit, data I/O lane, and lane decoder is a single byte in width, although other embodiments might utilize different widths. For example, each storage unit, data I/O lane, and lane decoder might be multiple bytes in width.
  • Graphics controller 202 implements tiling, in which the storage units retrieved in a single CAS operation are mapped to a two-dimensional rectangle of display pixels. During each memory cycle, the parallel data I/O lanes collectively transfer memory data corresponding to a rectangular tile of graphics pixels.
  • FIG. 7 shows an example of how a graphics controller might map storage units to physical display locations. Although only four memory arrays are shown in FIG. 6 for purposes of illustration, it is assumed in FIG. 7 that memory device 204 has sixteen memory arrays, “A” through “P”. It is further assumed that there is a dedicated lane and lane decoder for each of the sixteen memory arrays. Thus, sixteen storage units can be accessed in parallel during a single CAS operation.
  • In this example, each set of sixteen storage units is mapped to a four-by-four square of pixels. FIG. 7 shows a row or page 300 of such mapped storage units, comprising a total of twelve four-by-four tiles. The tiles are arranged with a width W of four tiles. FIG. 7 uses similar nomenclature as used above in designating storage units, an alphabetic character with a numeric subscript: the character indicates the array of the storage unit (A through P) and the subscript indicates the column within the array. Thus, the first or upper left tile contains storage units A0 through P0; the second tile contains storage units A1 through P1; and so on; continuing in order from left to right and from top to bottom.
  • In a conventional system, it would be possible to access this memory only at the granularity of a tile. That is, each CAS operation could specify a single column address, which would correspond to one of the twelve tiles shown in FIG. 7. In the system of FIG. 6, however, memory device 204 is configured to allow X (horizontal) and Y (vertical) spatial offsets so that any four-by-four group of storage units can be accessed in a CAS operation, regardless of tile boundaries or alignment. As in the previously described embodiment, this is accomplished by calculating decoder addresses for the individual lane decoders such that two or more of the decoder addresses are potentially different from each other, or by otherwise selecting columns of arrays 212 in a way that allows different columns to be selected for at least two of the arrays 212. This allows for selection and access, during respective memory operations, of overlapping tiles—a given storage unit can be accessed as part of a number of different tiles. As an example, storage unit K1 of FIG. 7 can be accessed as part of a 4 by 4 tile whose upper left corner is formed by storage unit D0, by a 4 by 4 tile whose upper left corner is formed by storage unit F1, or as part of a number of different overlapping tiles. As above, the term “overlapping” is used to indicate groups of memory cells or storage units that are not mutually exclusive. That is, different groups can include one or more common memory cells or storage units. Although the described example defines such groups in terms of two-dimensional tiles, groups could be defined in other ways and are not necessarily limited to storage units that are “adjacent” each other in a two-dimensional arrangement of storage units such as depicted in FIG. 7. Offsets are specified by graphics controller 202 to memory device 204 during or prior to CAS operations. The offsets are specified in terms of the pixel columns and rows of the current tiling scheme, and thus comprise a horizontal or X pixel offset value and/or a vertical or Y pixel offset value. In response to receiving X and Y offsets, the decoder logic 220 calculates appropriate decoder addresses for each of the lane decoders 216. The offsets are not constrained to multiples of the tiling pixel dimensions. In the described embodiment, for example, the offsets are not constrained multiples of four, which is both the horizontal and vertical dimension of the tiles.
  • FIG. 8 illustrates an example of a horizontal offset. Specifically, it is desired in this example to access a tile 310 whose upper left corner is formed by the D0 storage unit. This corresponds to column address 0, with an offset of three columns in the X or horizontal direction. More specifically, this tile comprises the following four-by-four array of storage units, in order from left to right and then top to bottom: D0, A1, B1, C1, H0, E1, F1, G1, L0, I1 J1, K1, P0, M1, N1, and O1.
  • The result of this selection at the data I/O lanes of memory device 204 is shown by an array 312 of storage units corresponding to data I/O lanes 218. As in the previous, one-dimensional example, the storage units appear out of their normal order due to their natural lane assignments. For example, storage unit A1 will always appear on the data I/O lane corresponding to array “A”, even when this storage unit does not correspond to the upper left corner of the tile being accessed. Thus, as with the previous example, any given storage unit is accessible in this implementation through one and only one I/O lane. Graphics controller 202 preferably has logic for internally dealing with the storage units in this format.
  • The following table indicates the logic implemented by decoder logic 220 to perform an X or horizontal offset with respect to the illustrated configuration. Specifically, each row of the table indicates how a decoder address is calculated for a particular lane decoder DEC(n) as a function of the four possible X OFFSET values. TABLE 2 OFFSET 0 1 2 3 DEC(a) COL COL + 1 COL + 1 COL + 1 DEC(b) COL COL COL + 1 COL + 1 DEC(c) COL COL COL COL + 1 DEC(d) COL COL COL COL DEC(e) COL COL + 1 COL + 1 COL + 1 DEC(f) COL COL COL + 1 COL + 1 DEC(g) COL COL COL COL + 1 DEC(h) COL COL COL COL DEC(i) COL COL + 1 COL + 1 COL + 1 DEC(j) COL COL COL + 1 COL + 1 DEC(k) COL COL COL COL + 1 DEC(l) COL COL COL COL DEC(m) COL COL + 1 COL + 1 COL + 1 DEC(n) COL COL COL + 1 COL + 1 DEC(o) COL COL COL COL + 1 DEC(p) COL COL COL COL
  • The details of this table will of course vary depending on the particular tiling arrangement in use and on the number of individual lane decoders. Note that tiles need not always be square: the tiling arrangement could utilize tiles that are longer in one dimension than the other.
  • FIG. 9 illustrates an example of a vertical offset. Specifically, it is desired in this example to access a tile 320 whose upper left corner is formed by the E0 storage unit. This corresponds to column address 0, with an offset of one column in the Y or vertical direction. More specifically, this tile comprises the following four-by-four array of storage units, in order from left to right and then top to bottom: E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, A4, B4, C4, and D4.
  • The result of this selection at the data I/O lanes of memory device 204 is shown by array 322. Again, the storage units appear out of their normal order due to their natural lane assignments. For example, storage unit A4 will always appear on the data I/O lane corresponding to array “A”, even when this storage unit does not correspond to the upper left corner of the tile being accessed. Thus, as with the previous example, any given storage unit is accessible in this implementation through one and only one I/O lane. Graphics controller 202 preferably has logic for internally dealing with the storage units in this format.
  • The following table indicates the logic implemented by decoder logic 220 to perform a Y or vertical offset with respect to the illustrated configuration. Specifically, each row of the table indicates how a decoder address is calculated for a particular lane decoder DEC(n) as a function of the four possible Y OFFSET values. W is number of tiles in the horizontal direction. For example, W is equal to four in the tiling scheme illustrated in FIG. 7. TABLE 3 OFFSET 0 1 2 3 DEC(a) COL COL + W COL + W COL + W DEC(b) COL COL + W COL + W COL + W DEC(c) COL COL + W COL + W COL + W DEC(d) COL COL + W COL + W COL + W DEC(e) COL COL COL + W COL + W DEC(f) COL COL COL + W COL + W DEC(g) COL COL COL + W COL + W DEC(h) COL COL COL + W COL + W DEC(i) COL COL COL COL + W DEC(j) COL COL COL COL + W DEC(k) COL COL COL COL + W DEC(l) COL COL COL COL + W DEC(m) COL COL COL COL DEC(n) COL COL COL COL DEC(o) COL COL COL COL DEC(p) COL COL COL COL
  • FIG. 10 illustrates an example of a combination of a horizontal and a vertical offset. Specifically, it is desired in this example to access a tile 330 whose upper left corner is formed by the Ho storage unit. This corresponds to column address 0, with a horizontal or X offset of three and a vertical or Y offset of one. More specifically, this tile comprises the following four-by-four array of storage units, in order from left to right and then top to bottom: H0, E1, F1, G1, L0, I1, J1, K1, P0, M1, N1, O1, D4, A5, B5, and C5.
  • The result of this selection at the data I/O lanes of memory device 204 is shown by array 332, which corresponds to data I/O lanes 218 of FIG. 6. The storage units appear out of their normal order due to their natural lane assignments. For example, storage unit A5 will always appear on the data I/O lane corresponding to array “A”, even when this storage unit does not correspond to the upper left corner of the tile being accessed. Graphics controller 202 preferably has logic for internally rearranging the data to account for this characteristic.
  • In order to perform an X and Y offset, decoder logic 220 is configured to 11 calculate individual column decoder addresses in accordance with the preceding two tables. Specifically, decoder logic first performs the logic of Table 2 with respect to the received column address, and then performs the logic of Table 3 with respect to the column addresses resulting from Table 2.
  • The tables set forth above assume that the tiling configuration is fixed. However, decoder logic 220 can optionally be configured with storage registers 340 that can be programmed dynamically by graphics controller 202 to indicate tiling parameters or parameters such as the width and height of an individual tile and the number of tiles in each horizontal row of tiles. When this is the case, decoder logic 220 calculates the column addresses based the received memory address, any received offsets or adjustment values, and on any programmed and stored tiling parameters. Lookup tables can be used as described above, but become more complex due to the larger numbers of variables.
  • Furthermore, although the disclosed embodiment is configured to receive both an address and one or more offsets as part of a CAS operation, the offsets can be provided in different ways. For example, the offsets can be provided to the memory device using a command other than a CAS command and stored in memory device registers prior to an actual CAS operation. In one embodiment, a special command might be used to instruct the memory device regarding whether or not previously provided offsets should be applied in combination with a CAS address. Alternatively, the CAS command itself might indicate whether the offsets should be applied. As yet another alternative, the memory device might be set by a command or through some other means into one of a plurality of addressing modes, in which at least one of the addressing modes uses supplied or stored offsets in combination with received CAS addresses. At least one other of the addressing modes would ignore offset values, in which case the memory cells would be accessed in mutually exclusive or non-overlapping tiles. A similar result could be obtained by setting the offset values to zero.
  • The ability to specify spatial offsets relative to graphics tiles allows for greatly increased memory access efficiency in many situations. In the situation illustrated by FIG. 3, for example, the graphics triangle can be accessed in a single memory operation by specifying a column or CAS address of 1, a horizontal offset of two pixels, and a vertical offset of three pixels. Three memory access cycles would have been required in prior art systems.
  • Furthermore, the improvements in efficiency are gained with very little in the way of additional hardware. Existing I/O paths are utilized and no additional logic is introduced in the I/O paths. Instead, minimal logic is added to calculate appropriate addresses for the column decoders. In some situations, it will be desirable to increase the number of independent column decoders. In other situations, however, existing designs will already utilize a sufficient number of column decoders, and only the address calculation logic will need to be added to such designs.
  • Packet Router
  • FIG. 11 shows a packet router or packet routing system 400 that includes a packet routing logic 402 and one or more DRAM memory devices 404 configured for use as intermediate storage of information packets as they are handled by routing logic 402. Each memory device 404 is configured similarly to the device described above with reference to FIG. 4, in that memory may be accessed at alignments that are not necessarily multiples of the data I/O path width. Packet 1 routing logic 402 receives packets and routes them in accordance with information contained in headers of the packets.
  • Each memory device includes a plurality of memory arrays 412 and an associated row decoder 414. Each memory array 412 comprises a plurality of memory storage units configured to store information packets.
  • Memory device 400 has column or lane selection logic that includes a lane decoder 416 associated with each array 412. There is a data I/O lane 418 corresponding to each array 412 and lane decoder 416. The data I/O lanes are accessed in parallel by routing logic 402. The column or lane selection logic also includes address specification logic 420, also referred to herein as decoder logic, which calculates decoder addresses for each of lane decoders 416. The lane decoders are configured to receive independent address specifications from decoder logic 420. The address specifications provided by decoder logic 420 are calculated or derived from a CAS column address and one or more adjustment or mode values provided by routing logic 402. The lane decoders are responsive to the address specifications to select memory storage units for transfer through data lanes 418. Each storage unit, data I/O lane, and lane decoder is one or more bytes in width.
  • Routing logic 402 is configured to store routable packets such as TCP or IP packets, or packets formatted in accordance with some other communications protocol. The packets are preferably arranged in memory so that each packet can be accessed in a single CAS operation—the packets are aligned at CAS boundaries.
  • FIG. 12 shows a preferred alignment of packets within the memory illustrated in FIG. 11, in a simplified example in which it is assumed that each packet occupies four storage units, and that the header of each packet is contained within a single storage unit. This example assumes four parallel data I/O lanes, A, B, C, and D. The nomenclature used to designate storage units in FIG. 12 is the same as that used above.
  • The packets are aligned with CAS access boundaries, so that an entire packet can be accessed in parallel in a single memory operation. For example, Packet 0 is stored in memory storage units A0, B0, C0, and D0; Packet 1 is stored in memory storage units A1, B1, C1, and D1; and so on. As illustrated, however, the headers are rearranged within the packets so that the headers are dispersed across the four memory arrays: the header of Packet 0 is stored in A0, the header of Packet 1 is stored at B1, the header of Packet 2 is stored at C2, and the header of Packet 4 is stored at D3. This pattern repeats itself, so that the headers of any four adjacent packets are stored in the four different memory arrays of memory device 202, corresponding to the four data lanes 418 of memory device 202.
  • Decoder logic 420 has one or more mode registers that can be dynamically programmed to set different operation modes. In the normal mode, conventional CAS cycles are performed to read individual packets. However, the decoding logic can be dynamically configured to set a header mode in which different column addresses are provided to the respective column decoders 416, so that a plurality of packet headers can be read through data I/O lanes 418 during a CAS memory access cycle. In this mode, a column is specified by routing logic 402 during the CAS cycle. In response to the column specification, the decoder logic calculates individual column addresses in a manner that is determined by the predefined layout of headers within adjacent portions of memory. In particular, the column addresses are calculated to select the column from each memory array that holds the packet header.
  • FIG. 13 shows such a selection, assuming that column 0 has been specified during the CAS operation. As shown, the decoder logic selects storage units A0, B1, C2, and D3—those storage units in which the packet headers are stored—and allows access to those storage units through data I/O lanes 418.
  • The header mode can be set in various ways. For example, the CAS command itself might indicate whether or not the header mode is to be used. As another example, an address bit might be used to indicate whether normal or header mode is to be used. Alternatively, a command might be used to set the memory device into a header mode. As yet another alternative, the memory device might include a register that is programmable to indicate whether or not the header mode is to be employed.
  • This represents a significant improvement in the ability to access header information. Specifically, the ability to access—in a single memory cycle—either an entire packet or a plurality of packet headers allow much more efficient router operation.
  • Conclusion
  • Although details of specific implementations and embodiments are described above, such details are intended to satisfy statutory disclosure obligations rather than to limit the scope of the following claims. Thus, the invention as defined by the claims is not limited to the specific features described above. Rather, the invention is claimed in any of its forms or modifications that fall within the proper scope of the appended claims, appropriately interpreted in accordance with the doctrine of equivalents.

Claims (28)

1-2. (canceled)
3. An integrated circuit memory device comprising:
first and second memory arrays;
a first column decoder, coupled to the first memory array, to select first data in response to a first column address received during a column operation; and
a second column decoder, coupled to the second memory array, to select second data in response to a second column access received during the column operation.
4. The integrated circuit memory device of claim 3, further comprising a row decoder circuit to enable, based on a row address, a first row of data to be output from the first memory array and a second row of data to be output from the second memory array, wherein the first data is selected by the first column decoder from the first row of data and the second data is selected by the second column decoder from the second row of data.
5. The integrated circuit memory device of claim 4, further comprising:
first sense amplifiers to store the first row of data output from the first memory array; and
second sense amplifiers to store the second row of data output from the second memory array.
6. The integrated circuit memory device of claim 5 further comprising:
a first plurality of internal signal lines coupled to the first sense amplifiers to enable the first data selected by the first column decoder to be output from the integrated circuit memory device during the column operation; and
a second plurality of internal signal lines coupled to the second sense amplifiers to enable the second data selected by the second column decoder to be output from the integrated circuit memory device during the column operation.
7. The integrated circuit memory device of claim 3, wherein the second column address is different than the first column address.
8. The integrated circuit memory device of claim 3, further comprising address specification logic coupled to the first column decoder and the second column decoder, the address specification logic to receive a third column address and a first adjustment value and generate the first column address based, at least in part, on the first adjustment value and the third column address.
9. The integrated circuit memory device of claim 8, wherein the address specification logic is to receive a second adjustment value and generate the second column address based, at least in part, on the second adjustment value and the third column address.
10. The integrated circuit memory device of claim 8, further comprising a register to store the first adjustment value.
11. The integrated circuit memory device of claim 10, wherein the memory device stores the first adjustment value in the register in response to a command.
12. The integrated circuit memory device of claim 3, wherein:
the first column decoder derives the first column address at least in part from a third column address and a first offset; and
the second column decoder derives the second column address at least in part from the third column address and a second offset.
13. A graphics system comprising:
a dynamic random access memory device including:
a first memory array having storage cells and a second memory array having storage cells;
a first column decoder coupled to the first memory array, the first column decoder to access first data from a column of storage units in the first memory array based on a first column address; and
a second column decoder coupled to the second memory array, the second column decoder to access second data from a column of storage units in the second memory array based on a second column address; and
a graphics controller, coupled to the dynamic random access memory device, to access in parallel, the first data from the column of storage units in the first memory array, and the second data from the column of storage units in the second memory array.
14. The graphics system of claim 13, wherein the graphics controller is coupled to the dynamic random access memory to access in parallel during a column access cycle, both the first data from the column of storage units in the first memory array, and the second data from the column of storage units in the second memory array.
15. The graphics system of claim 13, wherein the dynamic random access memory device further includes a first data lane coupled to the first column decoder and a second data lane coupled to the second column decoder, wherein the graphics controller is to access the column of storage units in the first memory array through the first data lane and the memory controller is to access the column of storage units in the second memory array through the second data lane.
16. The graphics system of claim 15, wherein the first data lane is a byte in width and the second data lane is a byte in width.
17. The graphics system of claim 13 wherein the dynamic random access memory device further includes a row decoder circuit to select, based on a row address, a first row in the first memory array and a second row in the second memory array, wherein the column of storage units in the first memory array is located in the first row and the column of storage units in the second memory array is located in the second row.
18. The graphics system of claim 13, wherein the second column address is different than the first column address.
19. The graphics system of claim 13, further comprising address specification logic coupled to the first column decoder and the second column decoder, the address specification logic to generate the first column address using the first adjustment value and a third column address.
20. The graphics system of claim 13, wherein the dynamic random access memory device comprises a register to store the first adjustment value in response to a command from the graphics controller.
21. The graphics system of claim 13, wherein:
the first column decoder derives the first column address using a third column address and a first offset; and
the second column decoder derives the second column address using the third column address and a second offset.
22. A method of operation in a system having a memory device and a controller device coupled to one another, wherein the memory device includes a first memory array and a second memory array, the method comprising:
selecting a column of storage units in the first memory array based on a first column address;
selecting a column of storage units in the second memory array based on a second column address; and
the controller device accessing, in parallel, data from the column of storage units in the first memory array and data from the column of storage units in the second memory array.
23. The method of claim 22, further comprising selecting, based on a row address, a first row in the first memory array and a second row in the second memory array, wherein the column of storage units in the first memory array is located in the first row and the column of storage units in the second memory array is located in the second row.
24. The method of claim 22, faker comprising:
the memory device receiving a third column address from the controller device;
the memory device receiving a first adjustment value from the controller device; and
the memory device generating the first column address using the first adjustment value and the third column address.
25. The method of claim 24, further comprising:
the memory device receiving a second adjustment value from the controller device; and
the memory device generating the second column address using the second adjustment value and the third column address.
26. The method of claim 24, further comprising:
the memory device receiving a command from the controller device; and
the memory device storing the first adjustment value in the register in response to the command.
27. The method of claim 22, further comprising:
the controller device providing, to the memory device, a third column address, a first offset and a second offset;
the memory device deriving the first column address using the third column address and the first offset; and
the memory device deriving the second column address using the third column address and the second offset.
28. The method of claim 22, wherein selecting the column of storage units in the first memory array based on the first column address is performed concurrently with selecting the column of storage units in the second memory array based on the second column address.
29. A memory device comprising:
a first memory array having storage units and a second memory array having storage units;
a first column decoder coupled to the first memory array, the first column decoder to select during a column operation, a column of storage units in the first memory array based on a first column address; and
a second column decoder coupled to the second memory array, the second column decoder to select, during the column operation, a column of storage units in the second memory array based on a second column address,
a row decoder circuit to select, based on a row address, a first row in the first memory array and a second row in the second memory array, wherein the column of storage units in the first memory array is located in the first row and the column of storage units in the second memory array is located in the second row;
first sense amplifiers, coupled to the first memory array, to sense data stored in the first row;
second sense amplifiers, coupled to the second memory array, to sense data stored in the second row;
a first plurality of internal lines to transfer first data corresponding to the column of storage units in the first memory array with the first sense amplifiers during the column operation;
a second plurality of internal lines to transfer second data corresponding to the column of storage units in the second memory array with the second sense amplifiers during the column operation; and
an external interface to provide access to the first data and the second data during the column operation.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070250677A1 (en) * 2004-11-29 2007-10-25 Ware Frederick A Multi-Mode Memory
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US8432766B2 (en) 2004-09-30 2013-04-30 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US20180285253A1 (en) * 2017-03-31 2018-10-04 Samsung Electronics Co., Ltd. Hybrid dram array including dissimilar memory cells

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6889304B2 (en) * 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
US7610447B2 (en) * 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
US6769050B1 (en) * 2001-09-10 2004-07-27 Rambus Inc. Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
US7296112B1 (en) * 2002-12-10 2007-11-13 Greenfield Networks, Inc. High bandwidth memory management using multi-bank DRAM devices
KR100529670B1 (en) * 2003-10-01 2005-11-17 동부아남반도체 주식회사 Cmos image sensor and manufacturing method thereof
US8190808B2 (en) 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7254075B2 (en) 2004-09-30 2007-08-07 Rambus Inc. Integrated circuit memory system having dynamic memory bank count and page size
CN1870873A (en) * 2005-05-28 2006-11-29 深圳富泰宏精密工业有限公司 Hinge device and portable electronic device with the hinge device
JP5604894B2 (en) * 2010-02-16 2014-10-15 セイコーエプソン株式会社 Image processing apparatus, image processing method, and computer program
US8332511B1 (en) 2010-07-31 2012-12-11 Cisco Technology, Inc. System and method for providing a script-based collection for devices in a network environment
US8873329B1 (en) 2012-01-17 2014-10-28 Rambus Inc. Patterned memory page activation
US20170192783A1 (en) * 2015-12-30 2017-07-06 Elmoustapha Ould-Ahmed-Vall Systems, Apparatuses, and Methods for Stride Load

Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377855A (en) * 1980-11-06 1983-03-22 National Semiconductor Corporation Content-addressable memory
US4542483A (en) * 1983-12-02 1985-09-17 At&T Bell Laboratories Dual stage sense amplifier for dynamic random access memory
US4569036A (en) * 1982-02-26 1986-02-04 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor dynamic memory device
US4636982A (en) * 1984-05-04 1987-01-13 Fujitsu Limited Semiconductor memory device
US4646268A (en) * 1983-10-13 1987-02-24 Nec Corporation Semiconductor bipolar memory device operating in high speed
US4670745A (en) * 1983-11-15 1987-06-02 Motorola Inc. Video display address generator
US4698788A (en) * 1985-07-01 1987-10-06 Motorola, Inc. Memory architecture with sub-arrays
US4700328A (en) * 1985-07-11 1987-10-13 Intel Corporation High speed and high efficiency layout for dram circuits
US4740921A (en) * 1985-10-04 1988-04-26 Motorola, Inc. Precharge of a dram data line to an intermediate voltage
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4766157A (en) * 1984-09-03 1988-08-23 Sumitomo Chemical Company, Limited Foamed particles of propylene-type polymer
US4766538A (en) * 1984-12-11 1988-08-23 Kabushiki Kaisha Toshiba Microprocessor having variable data width
US4796230A (en) * 1987-06-24 1989-01-03 Intel Corporation Folded-cascode configured differential current steering column decoder circuit
US4800525A (en) * 1984-10-31 1989-01-24 Texas Instruments Incorporated Dual ended folded bit line arrangement and addressing scheme
US4811302A (en) * 1986-06-24 1989-03-07 Nec Corporation Dynamic semiconductor memory with improved sensing scheme
US4825413A (en) * 1987-02-24 1989-04-25 Texas Instruments Incorporated Bipolar-CMOS static ram memory device
US4837743A (en) * 1987-08-17 1989-06-06 Texas Instruments Incorporated Architecture for memory multiplexing
US4837465A (en) * 1985-01-16 1989-06-06 Digital Equipment Corp Single rail CMOS register array and sense amplifier circuit therefor
US4843264A (en) * 1987-11-25 1989-06-27 Visic, Inc. Dynamic sense amplifier for CMOS static RAM
US4862421A (en) * 1988-02-16 1989-08-29 Texas Instruments Incorporated Sensing and decoding scheme for a BiCMOS read/write memory
US4903344A (en) * 1987-07-07 1990-02-20 Oki Electric Industry Co., Ltd. Semiconductor memory device with staggered sense amplifiers
US4961168A (en) * 1987-02-24 1990-10-02 Texas Instruments Incorporated Bipolar-CMOS static random access memory device with bit line bias control
US4982370A (en) * 1985-10-04 1991-01-01 Mitsubishi Denki Kabushiki Kaisha Shared sense amplifier semiconductor memory
US4984196A (en) * 1988-05-25 1991-01-08 Texas Instruments, Incorporated High performance bipolar differential sense amplifier in a BiCMOS SRAM
US4985867A (en) * 1988-09-14 1991-01-15 Kawasaki Steel Corporation Semiconductor memory circuit
US4991141A (en) * 1990-02-08 1991-02-05 Texas Instruments Incorporated Sense amplifier and method for sensing the outputs of static random access memory cells
US5046050A (en) * 1990-04-10 1991-09-03 National Semiconductor Corporation Shared BiCMOS sense amplifier
US5093806A (en) * 1988-02-16 1992-03-03 Tran Hiep V Sensing and decoding scheme for a bicmos read/write memory
US5111434A (en) * 1988-12-20 1992-05-05 Ltd. SamSung Electronics Co. Semiconductor memory device
US5119340A (en) * 1990-09-26 1992-06-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having latched repeaters for memory row line selection
US5121358A (en) * 1990-09-26 1992-06-09 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with power-on reset controlled latched row line repeaters
US5124951A (en) * 1990-09-26 1992-06-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequenced latched row line repeaters
US5124610A (en) * 1989-03-03 1992-06-23 E. F. Johnson Company Tritiated light emitting polymer electrical energy source
US5128897A (en) * 1990-09-26 1992-07-07 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having improved latched repeaters for memory row line selection
US5132931A (en) * 1990-08-28 1992-07-21 Analog Devices, Inc. Sense enable timing circuit for a random access memory
US5146592A (en) * 1987-09-14 1992-09-08 Visual Information Technologies, Inc. High speed image processing computer with overlapping windows-div
US5150330A (en) * 1990-01-24 1992-09-22 Vlsi Technology, Inc. Interblock dispersed-word memory architecture
US5181205A (en) * 1990-04-10 1993-01-19 National Semiconductor Corporation Short circuit detector circuit for memory arrays
US5193074A (en) * 1990-02-09 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having hierarchical row selecting lines
US5193072A (en) * 1990-12-21 1993-03-09 Vlsi Technology, Inc. Hidden refresh of a dynamic random access memory
US5214610A (en) * 1989-09-22 1993-05-25 Texas Instruments Incorporated Memory with selective address transition detection for cache operation
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
US5241503A (en) * 1991-02-25 1993-08-31 Motorola, Inc. Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers
US5249165A (en) * 1991-03-07 1993-09-28 Kabushiki Kaisha Toshiba Memory cell array divided type multi-port semiconductor memory device
US5251178A (en) * 1991-03-06 1993-10-05 Childers Jimmie D Low-power integrated circuit memory
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array
US5301162A (en) * 1992-03-26 1994-04-05 Nec Corporation Semiconductor random access memory device having shared sense amplifiers serving as a cache memory
US5305280A (en) * 1991-04-04 1994-04-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having on the same chip a plurality of memory circuits among which data transfer is performed to each other and an operating method thereof
US5321646A (en) * 1991-04-09 1994-06-14 Mitsubishi Denki Kabushiki Kaisha Layout of a semiconductor memory device
US5337283A (en) * 1991-12-27 1994-08-09 Nec Corporation Dynamic random access memory device
US5343438A (en) * 1992-01-31 1994-08-30 Samsung Electronics Co., Ltd. Semiconductor memory device having a plurality of row address strobe signals
US5383159A (en) * 1992-09-17 1995-01-17 Sharp Kabushiki Kaisha Semiconductor memory device of alternately-activated open bit-line architecture
US5390308A (en) * 1992-04-15 1995-02-14 Rambus, Inc. Method and apparatus for address mapping of dynamic random access memory
US5394528A (en) * 1991-11-05 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Data processor with bus-sizing function
US5406526A (en) * 1992-10-01 1995-04-11 Nec Corporation Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed
US5414662A (en) * 1990-04-06 1995-05-09 Mosaid Technologies Incorporated Dynamic random access memory using imperfect isolating transistors
US5418737A (en) * 1990-09-17 1995-05-23 Texas Instruments Incorporated DRAM with sub data lines and match lines for test
US5428389A (en) * 1990-06-14 1995-06-27 Fuji Photo Film Co., Ltd. Image data storage/processing apparatus
US5432743A (en) * 1992-06-30 1995-07-11 Nec Corporation Semiconductor dynamic RAM for image processing
US5455802A (en) * 1992-12-22 1995-10-03 Sgs-Thomson Microelectronics, Inc. Dual dynamic sense amplifiers for a memory array
US5485430A (en) * 1992-12-22 1996-01-16 Sgs-Thomson Microelectronics, Inc. Multiple clocked dynamic sense amplifier
US5517456A (en) * 1993-11-02 1996-05-14 Nec Corporation Semiconductor memory device including a word line driving circuit of the divisional decoding type
US5530814A (en) * 1991-10-30 1996-06-25 I-Cube, Inc. Bi-directional crossbar switch with control memory for selectively routing signals between pairs of signal ports
US5546346A (en) * 1993-12-06 1996-08-13 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
US5559970A (en) * 1993-05-06 1996-09-24 Nec Corporation Crossbar switch for multi-processor, multi-memory system for resolving port and bank contention through the use of aligners, routers, and serializers
US5614855A (en) * 1994-02-15 1997-03-25 Rambus, Inc. Delay-locked loop
US5652870A (en) * 1995-04-11 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Microcomputer having multiplexable input-output port
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5717871A (en) * 1995-08-17 1998-02-10 I-Cube, Inc. Crossbar switch with input/output buffers having multiplexed control inputs
US5717901A (en) * 1995-05-17 1998-02-10 Altera Corporation Variable depth and width memory device
US5748561A (en) * 1994-08-23 1998-05-05 Sharp Kabushiki Kaisha Semiconductor memory device with fast successive read operation
US5751657A (en) * 1996-01-26 1998-05-12 Sharp Kabushiki Kaisha Semiconductor memory device
US5793998A (en) * 1996-04-17 1998-08-11 Digital Equipment Corporation Method and apparatus for interconnection of multiple modules
US5801985A (en) * 1995-07-28 1998-09-01 Micron Technology, Inc. Memory system having programmable control parameters
US5825713A (en) * 1995-02-08 1998-10-20 Samsung Electronics Co., Ltd. Dual port memory device and a method therefor
US5893927A (en) * 1996-09-13 1999-04-13 International Business Machines Corporation Memory device having programmable device width, method of programming, and method of setting device width for memory device
US5903509A (en) * 1995-12-29 1999-05-11 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
US5912846A (en) * 1997-02-28 1999-06-15 Ramtron International Corporation Serial ferroelectric random access memory architecture to equalize column accesses and improve data retention reliability by mitigating imprint effects
US5933387A (en) * 1998-03-30 1999-08-03 Richard Mann Divided word line architecture for embedded memories using multiple metal layers
US5936885A (en) * 1998-02-23 1999-08-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory capable of preventing erroneous inversion of data read from memory transistors
US5958033A (en) * 1997-08-13 1999-09-28 Hewlett Packard Company On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies
US5963488A (en) * 1997-03-07 1999-10-05 Sharp Kabushiki Kaisha Semiconductor memory device
US6034878A (en) * 1996-12-16 2000-03-07 Hitachi, Ltd. Source-clock-synchronized memory system and memory unit
US6047347A (en) * 1997-02-04 2000-04-04 Advanced Micro Devices, Inc. Computer system with programmable bus size
US6075728A (en) * 1997-02-28 2000-06-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device accessible at high speed
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6138185A (en) * 1998-10-29 2000-10-24 Mcdata Corporation High performance crossbar switch
US6141273A (en) * 1998-12-31 2000-10-31 Hyundai Electronics Industries Co., Ltd. Circuit for setting width of input/output data in semiconductor memory device
US6240039B1 (en) * 1999-06-26 2001-05-29 Samsung Electronics Co., Ltd. Semiconductor memory device and driving signal generator therefor
US6247084B1 (en) * 1997-10-08 2001-06-12 Lsi Logic Corporation Integrated circuit with unified memory system and dual bus architecture
US6366995B1 (en) * 1998-08-19 2002-04-02 Acuid Corporation Limited System and a method for defining transforms of memory device addresses
US6393543B1 (en) * 1998-11-12 2002-05-21 Acuid Corporation Limited System and a method for transformation of memory device addresses
US20030052885A1 (en) * 2001-09-07 2003-03-20 Hampel Craig E. Granularity memory column access
US20030174573A1 (en) * 2002-03-13 2003-09-18 Fujitsu Limited Semiconductor memory device
US6625687B1 (en) * 2000-09-18 2003-09-23 Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
US6680736B1 (en) * 1998-09-03 2004-01-20 Samsung Electronics Co., Ltd. Graphic display systems having paired memory arrays therein that can be row accessed with 2(2n) degrees of freedom
US20040019756A1 (en) * 2001-02-28 2004-01-29 Perego Richard E. Memory device supporting a dynamically configurable core organization
US6754120B1 (en) * 2003-02-11 2004-06-22 Rambus Inc. DRAM output circuitry supporting sequential data capture to reduce core access times
US20040120197A1 (en) * 2002-01-11 2004-06-24 Tetsujiro Kondo Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2566950B1 (en) * 1984-06-29 1986-12-26 Texas Instruments France Processor of video image points, visualization system comprising application and process for its implementation
US6128700A (en) * 1995-05-17 2000-10-03 Monolithic System Technology, Inc. System utilizing a DRAM array as a next level cache memory and method for operating same

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377855A (en) * 1980-11-06 1983-03-22 National Semiconductor Corporation Content-addressable memory
US4569036A (en) * 1982-02-26 1986-02-04 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor dynamic memory device
US4646268A (en) * 1983-10-13 1987-02-24 Nec Corporation Semiconductor bipolar memory device operating in high speed
US4670745A (en) * 1983-11-15 1987-06-02 Motorola Inc. Video display address generator
US4542483A (en) * 1983-12-02 1985-09-17 At&T Bell Laboratories Dual stage sense amplifier for dynamic random access memory
US4636982A (en) * 1984-05-04 1987-01-13 Fujitsu Limited Semiconductor memory device
US4766157A (en) * 1984-09-03 1988-08-23 Sumitomo Chemical Company, Limited Foamed particles of propylene-type polymer
US4800525A (en) * 1984-10-31 1989-01-24 Texas Instruments Incorporated Dual ended folded bit line arrangement and addressing scheme
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4766538A (en) * 1984-12-11 1988-08-23 Kabushiki Kaisha Toshiba Microprocessor having variable data width
US4837465A (en) * 1985-01-16 1989-06-06 Digital Equipment Corp Single rail CMOS register array and sense amplifier circuit therefor
US4698788A (en) * 1985-07-01 1987-10-06 Motorola, Inc. Memory architecture with sub-arrays
US4700328A (en) * 1985-07-11 1987-10-13 Intel Corporation High speed and high efficiency layout for dram circuits
US4740921A (en) * 1985-10-04 1988-04-26 Motorola, Inc. Precharge of a dram data line to an intermediate voltage
US4982370A (en) * 1985-10-04 1991-01-01 Mitsubishi Denki Kabushiki Kaisha Shared sense amplifier semiconductor memory
US4811302A (en) * 1986-06-24 1989-03-07 Nec Corporation Dynamic semiconductor memory with improved sensing scheme
US4825413A (en) * 1987-02-24 1989-04-25 Texas Instruments Incorporated Bipolar-CMOS static ram memory device
US4961168A (en) * 1987-02-24 1990-10-02 Texas Instruments Incorporated Bipolar-CMOS static random access memory device with bit line bias control
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
US4796230A (en) * 1987-06-24 1989-01-03 Intel Corporation Folded-cascode configured differential current steering column decoder circuit
US4903344A (en) * 1987-07-07 1990-02-20 Oki Electric Industry Co., Ltd. Semiconductor memory device with staggered sense amplifiers
US4837743A (en) * 1987-08-17 1989-06-06 Texas Instruments Incorporated Architecture for memory multiplexing
US5146592A (en) * 1987-09-14 1992-09-08 Visual Information Technologies, Inc. High speed image processing computer with overlapping windows-div
US4843264A (en) * 1987-11-25 1989-06-27 Visic, Inc. Dynamic sense amplifier for CMOS static RAM
US4862421A (en) * 1988-02-16 1989-08-29 Texas Instruments Incorporated Sensing and decoding scheme for a BiCMOS read/write memory
US5093806A (en) * 1988-02-16 1992-03-03 Tran Hiep V Sensing and decoding scheme for a bicmos read/write memory
US4984196A (en) * 1988-05-25 1991-01-08 Texas Instruments, Incorporated High performance bipolar differential sense amplifier in a BiCMOS SRAM
US4985867A (en) * 1988-09-14 1991-01-15 Kawasaki Steel Corporation Semiconductor memory circuit
US5111434A (en) * 1988-12-20 1992-05-05 Ltd. SamSung Electronics Co. Semiconductor memory device
US5124610A (en) * 1989-03-03 1992-06-23 E. F. Johnson Company Tritiated light emitting polymer electrical energy source
US5214610A (en) * 1989-09-22 1993-05-25 Texas Instruments Incorporated Memory with selective address transition detection for cache operation
US5150330A (en) * 1990-01-24 1992-09-22 Vlsi Technology, Inc. Interblock dispersed-word memory architecture
US4991141A (en) * 1990-02-08 1991-02-05 Texas Instruments Incorporated Sense amplifier and method for sensing the outputs of static random access memory cells
US5193074A (en) * 1990-02-09 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having hierarchical row selecting lines
US5414662A (en) * 1990-04-06 1995-05-09 Mosaid Technologies Incorporated Dynamic random access memory using imperfect isolating transistors
US5046050A (en) * 1990-04-10 1991-09-03 National Semiconductor Corporation Shared BiCMOS sense amplifier
US5181205A (en) * 1990-04-10 1993-01-19 National Semiconductor Corporation Short circuit detector circuit for memory arrays
US5428389A (en) * 1990-06-14 1995-06-27 Fuji Photo Film Co., Ltd. Image data storage/processing apparatus
US5132931A (en) * 1990-08-28 1992-07-21 Analog Devices, Inc. Sense enable timing circuit for a random access memory
US5418737A (en) * 1990-09-17 1995-05-23 Texas Instruments Incorporated DRAM with sub data lines and match lines for test
US5128897A (en) * 1990-09-26 1992-07-07 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having improved latched repeaters for memory row line selection
US5119340A (en) * 1990-09-26 1992-06-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having latched repeaters for memory row line selection
US5124951A (en) * 1990-09-26 1992-06-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequenced latched row line repeaters
US5121358A (en) * 1990-09-26 1992-06-09 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with power-on reset controlled latched row line repeaters
US5193072A (en) * 1990-12-21 1993-03-09 Vlsi Technology, Inc. Hidden refresh of a dynamic random access memory
US5241503A (en) * 1991-02-25 1993-08-31 Motorola, Inc. Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers
US5251178A (en) * 1991-03-06 1993-10-05 Childers Jimmie D Low-power integrated circuit memory
US5249165A (en) * 1991-03-07 1993-09-28 Kabushiki Kaisha Toshiba Memory cell array divided type multi-port semiconductor memory device
US5305280A (en) * 1991-04-04 1994-04-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having on the same chip a plurality of memory circuits among which data transfer is performed to each other and an operating method thereof
US5321646A (en) * 1991-04-09 1994-06-14 Mitsubishi Denki Kabushiki Kaisha Layout of a semiconductor memory device
US5530814A (en) * 1991-10-30 1996-06-25 I-Cube, Inc. Bi-directional crossbar switch with control memory for selectively routing signals between pairs of signal ports
US5394528A (en) * 1991-11-05 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Data processor with bus-sizing function
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array
US5337283A (en) * 1991-12-27 1994-08-09 Nec Corporation Dynamic random access memory device
US5343438A (en) * 1992-01-31 1994-08-30 Samsung Electronics Co., Ltd. Semiconductor memory device having a plurality of row address strobe signals
US5301162A (en) * 1992-03-26 1994-04-05 Nec Corporation Semiconductor random access memory device having shared sense amplifiers serving as a cache memory
US5390308A (en) * 1992-04-15 1995-02-14 Rambus, Inc. Method and apparatus for address mapping of dynamic random access memory
US5432743A (en) * 1992-06-30 1995-07-11 Nec Corporation Semiconductor dynamic RAM for image processing
US5383159A (en) * 1992-09-17 1995-01-17 Sharp Kabushiki Kaisha Semiconductor memory device of alternately-activated open bit-line architecture
US5406526A (en) * 1992-10-01 1995-04-11 Nec Corporation Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed
US5485430A (en) * 1992-12-22 1996-01-16 Sgs-Thomson Microelectronics, Inc. Multiple clocked dynamic sense amplifier
US5455802A (en) * 1992-12-22 1995-10-03 Sgs-Thomson Microelectronics, Inc. Dual dynamic sense amplifiers for a memory array
US5559970A (en) * 1993-05-06 1996-09-24 Nec Corporation Crossbar switch for multi-processor, multi-memory system for resolving port and bank contention through the use of aligners, routers, and serializers
US5517456A (en) * 1993-11-02 1996-05-14 Nec Corporation Semiconductor memory device including a word line driving circuit of the divisional decoding type
US5546346A (en) * 1993-12-06 1996-08-13 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
US5614855A (en) * 1994-02-15 1997-03-25 Rambus, Inc. Delay-locked loop
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5748561A (en) * 1994-08-23 1998-05-05 Sharp Kabushiki Kaisha Semiconductor memory device with fast successive read operation
US5825713A (en) * 1995-02-08 1998-10-20 Samsung Electronics Co., Ltd. Dual port memory device and a method therefor
US5652870A (en) * 1995-04-11 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Microcomputer having multiplexable input-output port
US5717901A (en) * 1995-05-17 1998-02-10 Altera Corporation Variable depth and width memory device
US5801985A (en) * 1995-07-28 1998-09-01 Micron Technology, Inc. Memory system having programmable control parameters
US5717871A (en) * 1995-08-17 1998-02-10 I-Cube, Inc. Crossbar switch with input/output buffers having multiplexed control inputs
US5903509A (en) * 1995-12-29 1999-05-11 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
US5751657A (en) * 1996-01-26 1998-05-12 Sharp Kabushiki Kaisha Semiconductor memory device
US5793998A (en) * 1996-04-17 1998-08-11 Digital Equipment Corporation Method and apparatus for interconnection of multiple modules
US5893927A (en) * 1996-09-13 1999-04-13 International Business Machines Corporation Memory device having programmable device width, method of programming, and method of setting device width for memory device
US6034878A (en) * 1996-12-16 2000-03-07 Hitachi, Ltd. Source-clock-synchronized memory system and memory unit
US6047347A (en) * 1997-02-04 2000-04-04 Advanced Micro Devices, Inc. Computer system with programmable bus size
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6075728A (en) * 1997-02-28 2000-06-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device accessible at high speed
US5912846A (en) * 1997-02-28 1999-06-15 Ramtron International Corporation Serial ferroelectric random access memory architecture to equalize column accesses and improve data retention reliability by mitigating imprint effects
US5963488A (en) * 1997-03-07 1999-10-05 Sharp Kabushiki Kaisha Semiconductor memory device
US5958033A (en) * 1997-08-13 1999-09-28 Hewlett Packard Company On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies
US6247084B1 (en) * 1997-10-08 2001-06-12 Lsi Logic Corporation Integrated circuit with unified memory system and dual bus architecture
US5936885A (en) * 1998-02-23 1999-08-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory capable of preventing erroneous inversion of data read from memory transistors
US5933387A (en) * 1998-03-30 1999-08-03 Richard Mann Divided word line architecture for embedded memories using multiple metal layers
US6366995B1 (en) * 1998-08-19 2002-04-02 Acuid Corporation Limited System and a method for defining transforms of memory device addresses
US6680736B1 (en) * 1998-09-03 2004-01-20 Samsung Electronics Co., Ltd. Graphic display systems having paired memory arrays therein that can be row accessed with 2(2n) degrees of freedom
US6138185A (en) * 1998-10-29 2000-10-24 Mcdata Corporation High performance crossbar switch
US6393543B1 (en) * 1998-11-12 2002-05-21 Acuid Corporation Limited System and a method for transformation of memory device addresses
US6141273A (en) * 1998-12-31 2000-10-31 Hyundai Electronics Industries Co., Ltd. Circuit for setting width of input/output data in semiconductor memory device
US6240039B1 (en) * 1999-06-26 2001-05-29 Samsung Electronics Co., Ltd. Semiconductor memory device and driving signal generator therefor
US6625687B1 (en) * 2000-09-18 2003-09-23 Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
US20040019756A1 (en) * 2001-02-28 2004-01-29 Perego Richard E. Memory device supporting a dynamically configurable core organization
US20030052885A1 (en) * 2001-09-07 2003-03-20 Hampel Craig E. Granularity memory column access
US20040120197A1 (en) * 2002-01-11 2004-06-24 Tetsujiro Kondo Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device
US20030174573A1 (en) * 2002-03-13 2003-09-18 Fujitsu Limited Semiconductor memory device
US6754120B1 (en) * 2003-02-11 2004-06-22 Rambus Inc. DRAM output circuitry supporting sequential data capture to reduce core access times

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8432766B2 (en) 2004-09-30 2013-04-30 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8908466B2 (en) 2004-09-30 2014-12-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US20070250677A1 (en) * 2004-11-29 2007-10-25 Ware Frederick A Multi-Mode Memory
US9652176B2 (en) 2004-11-29 2017-05-16 Rambus Inc. Memory controller for micro-threaded memory operations
US9292223B2 (en) 2004-11-29 2016-03-22 Rambus Inc. Micro-threaded memory
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US10331379B2 (en) 2004-11-29 2019-06-25 Rambus Inc. Memory controller for micro-threaded memory operations
US9256557B2 (en) 2006-05-02 2016-02-09 Rambus Inc. Memory controller for selective rank or subrank access
US8364926B2 (en) 2006-05-02 2013-01-29 Rambus Inc. Memory module with reduced access granularity
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US10191866B2 (en) 2006-05-02 2019-01-29 Rambus Inc. Memory controller for selective rank or subrank access
US9666250B2 (en) 2011-08-05 2017-05-30 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US20180285253A1 (en) * 2017-03-31 2018-10-04 Samsung Electronics Co., Ltd. Hybrid dram array including dissimilar memory cells
US10223252B2 (en) * 2017-03-31 2019-03-05 Samsung Electronics Co., Ltd. Hybrid DRAM array including dissimilar memory cells

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