US20050064608A1 - Versatile system for controlling semiconductor topography - Google Patents
Versatile system for controlling semiconductor topography Download PDFInfo
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- US20050064608A1 US20050064608A1 US10/654,063 US65406303A US2005064608A1 US 20050064608 A1 US20050064608 A1 US 20050064608A1 US 65406303 A US65406303 A US 65406303A US 2005064608 A1 US2005064608 A1 US 2005064608A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- the goal of the CMP process is to achieve a flat post-CMP topography, as excessive dishing can negatively impact process yields.
- some processes may achieve optimal yields with a slight, or even moderate, amount of dishing. Regardless of whether a flat or slightly dished topology is desired, the ability to monitor and actively control the amount of dishing is critical to achieving optimal process yields.
- the present invention also provides a method for controlling post-processing topology of semiconductor wafers that utilize copper metallization.
- the method includes providing a semiconductor wafer having copper metallization.
- a processing function performs a process on the semiconductor wafer.
- a profilometry function renders a characterization of actual surface topology of the semiconductor wafer after the process is performed.
- An input data set is provided, comprising a desired post-processing topology for the semiconductor wafer.
- a control system receives the input data set and the characterization.
- the control system identifies a differential, if any, between the actual surface topology and the desired post-processing topology.
- the control system then alters the process performed by the processing function to eliminate the differential.
- the modeling and control subsystems of the present invention cooperate with a comprehensive profilometry evaluation system.
- the profilometry system of the present invention must provide accurate and timely data regarding wafer topologies, especially recent post-CMP topologies.
- the present invention utilizes this data to determine the CMP modifications necessary to effect a desired post-CMP topology.
- the present invention thus optimizes CMP processing to provide desired post-CMP topologies in an efficient and effective manner, overcoming certain limitations commonly associated with most conventional systems.
- System 100 further comprises control system 108 , communicatively interfaced with functions 102 and 104 .
- System 108 comprises a processing control function 110 and a data integrity function 112 .
- Functions 110 and 112 are communicatively interfaced with functions 102 and 104 , respectively.
- the communicative interfaces with functions 110 and 112 may comprise separate direct interfaces or a single shared interface, as appropriate.
- System 108 further comprises a control modeling function 114 communicatively interfaced with functions 110 and 112 .
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Abstract
The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator. A processing control function (210) receives the processing target, and alters the copper overpolish or barrier polish responsive to the processing target.
Description
- The present invention relates generally to the field of semiconductor manufacturing processes and, more particularly, to apparatus and methods for controlling processing to effect a desired post-processing topography.
- The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
- The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, and low power consumption, with good reliability and long operation life must be maintained without any functional device degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
- As integrated circuits become denser, the widths of interconnect layers that connect transistors and other semiconductor devices of the integrated circuit are reduced. As the widths of interconnect layers and semiconductor devices decrease, their resistance increases. As a result, semiconductor manufacturers seek to create smaller and faster devices by using, for example, a copper interconnect instead of a traditional aluminum interconnect. Unfortunately, copper is very difficult to etch in most semiconductor process flows. Therefore, damascene processes have been proposed and implemented to form copper interconnects.
- Damascene methods usually involve forming a trench and/or an opening in a dielectric layer that lies beneath and on either side of the copper-containing structures. Once the trenches or openings are formed, a blanket layer of the copper-containing material is formed over the entire device. Electrochemical deposition (ECD) is typically the only practical method to form a blanket layer of copper. The thickness of such a layer must be at least as thick as the deepest trench or opening. After the trenches or openings are filled with the copper-containing material, the copper-containing material over them is removed, e.g., by chemical-mechanical planarization (CMP), so as to leave the copper containing material in the trenches and openings but not over the dielectric or over the uppermost portion of the trench or opening.
- During CMP, copper and the adjacent dielectric are removed from the wafer at different rates. Typically, a copper-selective chemical slurry is applied, after which a first round of polishing occurs. Then, a dielectric-selective slurry is applied, followed by more polishing. This process creates certain surface anomalies, and a varying post-CMP topography. A number of factors, including pattern geometry (e.g., copper line density), affect the removal rates and add to the surface anomalies. One common surface anomaly that occurs with copper CMP is dishing. Dishing occurs when the copper recedes below or protrudes above the level of the adjacent dielectric. Theoretically, the goal of the CMP process is to achieve a flat post-CMP topography, as excessive dishing can negatively impact process yields. In practice, however, some processes may achieve optimal yields with a slight, or even moderate, amount of dishing. Regardless of whether a flat or slightly dished topology is desired, the ability to monitor and actively control the amount of dishing is critical to achieving optimal process yields.
- A number of conventional methods exist by which post-CMP topography can be measured or profiled. Typically, such characterization is referred to as metrology. Unfortunately, a number of such conventional methods are destructive in nature, or are limited in scope to very small test areas on a wafer. As such, these approaches are not of much use for high-volume, in-process applications. More common in these applications is the use of profilometry—a typically non-destructive process that involves physical movement of a stylus along the surface of a wafer. Unfortunately, however, current profilometry approaches provide only the ability to render a relative physical measurement or characterization of post-CMP topography. They do not provide the ability to actively control the CMP process based on metrology data.
- There are some existing methods that attempt to modify post-CMP topologies in response to profilometry data. Unfortunately, there are certain drawbacks associated with each. Most conventional methods either require additional processing steps or changes to device layout and design—adding costs to and reducing the efficiency of production processes. These approaches augment, instead of optimize, the already existing process steps. Additionally, many such conventional methods tend to be rather static in nature. Dynamic modification of CMP on a wafer-to-wafer, or even lot-to-lot, basis in order to address subtle variations in metrology data is simply not possible or not operationally feasible. The substantial effort and cost associated with modifying the CMP process often translates into substantial yield losses to dishing before a change can be justified. Furthermore, many such approaches are not designed for concurrent, cooperative use with comprehensive profilometry systems and methods.
- As a result, there is a need for a versatile system for controlling the post-CMP topology of semiconductor wafer—a system that provides direct and dynamic control of CMP processing, and concurrent, cooperative use with comprehensive profilometry evaluation, in an easy, efficient and cost-effective manner.
- The present invention provides a versatile system for controlling the post-processing topology of a semiconductor wafer in an easy, efficient and cost-effective manner. The present invention is particularly applicable to controlling the post-CMP topology of a semiconductor wafer. The present invention provides direct control of CMP processing, responsive—in a dynamic or quasi-dynamic fashion—to a comprehensive profilometry evaluation.
- The present invention provides a system that is readily integratable with high-volume semiconductor manufacturing processes. The system of the present invention does not require additional device processing steps but, rather, provides modeling and control subsystems that direct CMP processes in a desired manner. The modeling and control subsystems of the present invention cooperate with a profilometry evaluation system—one that provides accurate and timely data regarding current post-CMP topology—to determine the CMP modifications necessary to effect a desired post-CMP topology. The present invention thus optimizes CMP processing to provide desired post-CMP topologies in an efficient and effective manner, overcoming certain limitations commonly associated with most conventional systems.
- More specifically, the present invention provides a system for controlling post-CMP topology of semiconductor wafers, comprising a CMP processing function that performs CMP on a semiconductor wafer. A profilometry function renders a characterization of the actual surface topology of the semiconductor wafer after CMP. An input data set indicates a number of process variables and data points, including desired post-CMP topology for the semiconductor wafer. A control system receives the input data set and the characterization. The control system identifies any differential between the actual surface topology and the desired post-CMP topology, and eliminate that differential by altering the processing performed by the CMP processing function.
- The present invention also provides a method for controlling post-processing topology of semiconductor wafers that utilize copper metallization. The method includes providing a semiconductor wafer having copper metallization. A processing function performs a process on the semiconductor wafer. A profilometry function renders a characterization of actual surface topology of the semiconductor wafer after the process is performed. An input data set is provided, comprising a desired post-processing topology for the semiconductor wafer. A control system receives the input data set and the characterization. The control system identifies a differential, if any, between the actual surface topology and the desired post-processing topology. The control system then alters the process performed by the processing function to eliminate the differential.
- The present invention further provides a system for selectively controlling post-CMP dishing effects occurring in semiconductor wafers that utilize copper metallization. The system includes a CMP processing system performing polishing, including copper overpolish and barrier polish, on a semiconductor wafer having copper metallization. A profilometer is adapted to render a measurement of actual dishing occurring in the copper metallization of the semiconductor wafer after polishing. The system receives an input data set, comprising a dishing target for the semiconductor wafer. A data integrity function evaluates the profilometer's measurement, and generates some indicator of the reliability of this measurement. A control modeling function receives the measurement, the indicator of reliability, and the input data set. The control modeling function determines what, if any, differential exists between the dishing target and actual dishing. Based on the differential, the control modeling function generates a processing target for eliminating the differential. The control modeling function is further configured to modify its generation of processing targets responsive to the indicator of reliability. The system further comprises a processing control function that receives the processing target, and translates that target into alterations of the copper overpolish, barrier polish, or both copper overpolish and barrier polish processes.
- Other features and advantages of the present invention will be apparent to those of ordinary skill in the art upon reference to the following detailed description taken in conjunction with the accompanying drawings.
- For a better understanding of the invention, and to show by way of example how the same may be carried into effect, reference is now made to the detailed description of the invention along with the accompanying figures in which corresponding numerals in the different figures refer to corresponding parts and in which:
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FIG. 1 is an illustration of one embodiment of a semiconductor processing system according to the present invention; -
FIG. 2 is an illustration of another embodiment of a semiconductor processing system according to the present invention; -
FIGS. 3 a-3 d depict progressive stages of processing performed on a semiconductor wafer by one member of the system depicted inFIG. 2 ; and -
FIG. 4 provides an illustrative example of one embodiment of data analysis that may be utilized in accordance with the present invention. - While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts, which can be embodied in a wide variety of specific contexts. The invention will now be described in conjunction with providing a system for controlling CMP processing during the manufacture of semiconductor devices utilizing copper interconnects and vias. The specific embodiments discussed herein are, however, merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.
- The present invention provides a versatile system for controlling the post-processing topology of a semiconductor wafer—particularly the post-CMP topology of a semiconductor wafer. The present invention provides direct control of a CMP process, responsive to a comprehensive profilometry evaluation system. Depending upon the sophistication of the manufacturing and metrology tools available, the present invention may be applied to provide such direct control in a quasi-dynamic or fully dynamic manner.
- The present invention provides a system that is easily integrated into high-volume semiconductor manufacturing processes. The system of the present invention does not require additional device processing steps. Instead, the present invention provides modeling and control subsystems that direct CMP processes in a desired manner.
- The modeling and control subsystems of the present invention cooperate with a comprehensive profilometry evaluation system. Although there are a number of possible embodiments, the profilometry system of the present invention must provide accurate and timely data regarding wafer topologies, especially recent post-CMP topologies. The present invention utilizes this data to determine the CMP modifications necessary to effect a desired post-CMP topology. The present invention thus optimizes CMP processing to provide desired post-CMP topologies in an efficient and effective manner, overcoming certain limitations commonly associated with most conventional systems.
- The present invention is described in greater detail now with reference to
FIG. 1 , which depicts one embodiment of asemiconductor processing system 100 according to the present invention.System 100 comprises aprocessing function 102 and aprofilometry function 104. A semiconductor substrate orwafer 106 is queued up for processing byfunction 102. After some level of processing byfunction 102,wafer 106 undergoes a topological evaluation byprofilometry function 104. After that,wafer 106 continues on for further processing. - Depending upon the nature and sophistication of the processing and profilometry tools and devices utilized by
functions wafer 106 is physically transferred from the CMP apparatus to the profilometry apparatus. In an alternative embodiment,profilometry function 104 may be provided as an integrated subsystem or component ofprocessing function 102. For example, function 104 may comprise a profilometer that has been integrated as a component within aCMP apparatus 102. In this embodiment, function 104 may be configured to provide profilometry data aboutwafer 106 at various stages during CMP (e.g., after overpolish, before barrier polish). Other variations, and combinations thereof, are comprehended by the present invention. -
System 100 further comprisescontrol system 108, communicatively interfaced withfunctions System 108 comprises aprocessing control function 110 and adata integrity function 112.Functions functions functions functions System 108 further comprises acontrol modeling function 114 communicatively interfaced withfunctions -
Function 114 comprises two functional modules. The first istopology modeling function 116. The second is modelingupdate function 118.Function 114 receives aninput data set 120 that comprises a number of input variables utilized byfunction Input data set 120 may be provided manually (e.g., input by an operator) or automatically (e.g., loaded from a storage device or host processor).Function 112 communicates withfunction 114 to provide data, as described hereafter, for use byfunctions system 100, function 114 may be configured to provide certain data, as described hereafter, to function 112 fromfunction 118.Function 114 communicates withfunction 110 to provide data, as described hereafter, relating to necessary modifications in the operation offunction 102. -
System 108 and each of its constituent functions and modules may be implemented in a variety of ways. Each such entity may comprise various hardware or software constructs, or combinations of both, implemented as stand-alone or integrated functions. Although the constituent functions and modules ofsystem 108 are functionally interrelated, they may be implemented in physically collocated or separate structures. For example, in one embodiment,system 108 may comprise a stand-alone computer communicatively interfaced withprocessing function 102 andprofilometry function 104. Functions 110-118 may be implemented as software constructs stored and executed by the computer. In an alternative embodiment, function 110 may comprise a software construct residing within some processor onboard function 102, whilefunction 112 comprises a software construct residing within some processor onboard function 104.Function 114 is implemented in a physically separate computer communicatively interfaced withfunctions - Operationally,
system 100 functions as follows. A semiconductor wafer orsubstrate 106 is queued for processing. For purposes of the present invention,wafer 106 may be queued individually or in lots, depending upon the relative complexity and desired performance ofsystem 100. Typically, semiconductor processes in current use queue semiconductor wafers in lots. Thus, for purposes of explanation and illustration,wafer 106 inFIG. 1 is considered to be queued as part of a semiconductor wafer lot. Certain input variables (e.g., die density, processing equipment characteristics, desired topology characteristics) corresponding to thelot containing wafer 106 are input tosystem 108 asdata set 120. -
System 108 communicates some desired processing level, described in greater detail hereinafter, toprocessing function 102.Processing function 102 performs the desired processing onwafer 106.Profilometry function 104 assesses the resulting topology onwafer 106, and generates some measurement or other profile characteristic indicating the outcome of processing byfunction 102. This measurement or other profile characteristic is evaluated for accuracy byfunction 112. Generally, function 112 compares the measured value to some expected value (e.g., a target topology correlating the desired processing level), determines a differential between the two values, and generates some indicia (e.g., goodness-of-fit metric, % confidence metric, etc.) of the reliability or accuracy of the measurement.Function 112 may internally determine or generate the expected value from, for example, extrapolated historical data, a modeling scheme, or combinations thereof; or the expected value may be communicated or transferred from another device or function within system 100 (e.g., function 114). - As depicted in
FIG. 1 , certain embodiments ofsystem 100 may comprise acommunicative link 122 by which function 118 can provide orupdate function 112 with historical or modeling data.Function 112 provides, via communicative link 124, the profilometry measurement fromfunction 104, together with the accuracy indicia, to function 114. Other variations and combinations may be utilized in accordance with the present invention, as long asfunction 112 delivers the profilometry measurement data, together with some reliability or accuracy indicia, to function 114. -
Function 114 receives a number of data inputs, fromdata set 120 and fromfunction 112. Among those received, one particular input characterizes the topology target or goal. In certain embodiments, for example, this may comprise a narrow target range for dishing. Other data inputs may comprise information relating to various aspects of the semiconductor wafers being processed and the processing materials and components being used (e.g., slurry composition, pad life/wear data).Modeling function 116 comprises a data model characterizing nominal dishing values for varying die densities.Function 116 accesses this model fromfunction 118, which may correct or modify the model over time as described hereinafter. This data model provides a baseline reference for processing conditions (e.g., overpolish and barrier polish times). - When a
lot containing wafer 106 is queued for processing,system 108 analyzes theinput data set 120 that accompanies that lot.System 108 utilizes one or more algorithms, or similar methodologies, to cross-reference and compile the various data inputs received, compare those inputs to the baseline model infunction 116, determine any differentials between the input values and the baseline model, and develop those differentials into a processing target. - In certain embodiments, for example, the model of
function 116 may indicate that, in order to achieve the desired topology target, function 102 should perform a certain amount (X) of processing to remove a desired amount of material. After processing data input regarding die density ofwafer 106, however, function 110 may determine that some additional amount of processing (Y) should occur.Function 110 may next evaluate data regarding the correlation between process time and physical characteristics of certain processing equipment being used (e.g., historical wear data on polishing pads), and determine that processing should be reduced by some amount (Z). In this simplified example,system 108 thus develops a processing target of (X+Y−Z). -
Function 114 may evaluate the reliability indicator received fromfunction 112. Iffunction 114 determines that the indictor falls within an acceptable range, thensystem 108 adjusts the processing parameters offunction 102 in accordance with the processing target. If the indicator is not within an acceptable range, then function 118 processes or updates one or more of the models or data references that it utilizes to update the model offunction 116.Function 114 may be configured to store some or all of the data inputs and references that it utilizes for its evaluations or, alternatively, it may access and retrieve those data sources from some external source. - Even when the reliability indicator falls within an acceptable range, function 118 may be utilized to alter the model of
function 116 to effect a desired change insystem 100.Function 118 may be configured to passively store and record historical performance data from withinsystem 100. In particular, function 118 may be configured to receive and store the profilometry measurement received fromfunction 112.Function 118 may also be configured to generate correlation references, relating the historical metrology measurements to a variety of other process variables. It may also be configured to receive and store historical data, or model data, references from an external source (e.g., a host processor environment, an operator entry).Function 110 may be similarly configured to store and generate references. - Based upon the processing target, function 110 determines the process settings necessary to achieve the desired topology target within
function 102.Function 110 communicates these necessary process settings (e.g., maximum time for each process step) to function 102. The process offunction 102 is modified accordingly, prior to processing of the next wafer (or lot) 106. This entire cycle restarts, and continues iterating on a constant or periodic basis, as desired. - The present invention is described in greater detail now with reference to one specific processing system application, as depicted by
system 200 ofFIG. 2 .System 200 comprises aCMP system 202 and aprofilometer system 204. Asemiconductor wafer lot 206 is queued up for processing bysystem 202. -
System 200 further comprisescontrol system 208, implemented within a separate computer system, communicatively interfaced withsystems System 208 comprises aprocessing control function 210 and adata integrity function 212.Functions systems System 208 further comprises acontrol modeling function 214 communicatively interfaced withfunctions -
Function 214 comprises two functional modules. The first istopology modeling function 216. The second is modelingupdate function 218.Function 214 receives aninput data set 220 that comprises a number of input variables utilized byfunction Input data set 220 may be provided manually (e.g., input by an operator) or automatically (e.g., loaded from a storage device or host processor).Function 212 communicates withfunction 214 to provide data for use byfunctions system 200, function 212 may reside withinfunction - The operation of
system 202 is described in greater detail with reference now toFIGS. 3 a-3 d. InFIG. 3 a, aportion 300 of a wafer fromlot 206 is depicted.Portion 300 comprises a semiconductor device structure loaded intosystem 202 after copper ECD.Portion 300 comprise three regions: acopper region 302, abarrier region 304, and adielectric region 306.Region 306 comprises two trench features, feature 308 and feature 310, which will-after CMP-become copper interconnects within a semiconductor device.System 202 is used to polish unwanted material fromportion 300, until a final desired topology is achieved. A copper-selective slurry 312, or some other suitable compound, is applied to the upper surface ofregion 302. A polishing apparatus having apolishing pad 314 appliesdownward force 316 while polishing (generally in a rotational manner)slurry 312 intoregion 302.Region 302 is thus abraded until the copper begins to clear fromportion 300, specifically until some portion ofregion 304 is exposed. - The current appearance of
portion 300 is now depicted inFIG. 3 b. Although some portion ofregion 302 has been cleared, the copper-selective polishing continues untilplanar portions 318 ofregion 304 have been exposed, as depicted now inFIG. 3c . This is referred to as overpolish. Overpolish is necessary to completely remove the copper from all areas, excepttrenches trench 308. This due to a combination of factors, including the to copper-selectivity ofslurry 312, the polishing time, the degree of flexion inpad 314, and theforce 316 applied during polishing. Generally, longer polishing times, slurries of higher copper selectivity, polishing pads having greater flexion, and greater polishing forces may all increase dishing. - Referring now to
FIG. 3 c, once theplanar portions 318 ofregion 304 have been 1exposed, a barrier-selective slurry or some other suitable compound (not shown) is applied to the upper surface ofregion 304 and polishing begins again. This process is referred to as barrier polish. Barrier polishing continues just until the lateral portions of region 304 (i.e., the portions outsidetrenches 308 and 310) have been cleared away, as depicted now inFIG. 3 d. Excessive barrier polish can strip away dielectric 306, or excessive portions oftrenches FIG. 3 d, some degree of dishing 320 remains, although the barrier polish process actually reduces that degree of dishing present after overpolish (as depicted inFIG. 3 c). - Data concerning this phenomenon can be logged and utilized by
system 208 in modeling and controlling the operation ofsystem 202. This is illustrated now in reference toFIG. 4 .FIG. 4 depicts agraph 400 illustrating dishing data that may be logged and analyzed bysystem 208 during the operation ofsystem 200.Graph 400 plots dishing, as measured in Angstroms (Å), alongaxis 402 against copper overpolish time, measured in seconds (s), alongaxis 404. Twodata sets Set 406 comprises twodata points Set 408 comprises twodata points -
Graph 400 is merely illustrative of the data that may be logged, recorded or analyzed bysystem 208 during operation. In most applications,system 208 would implement algorithms or other analytical processes to analyze such data in purely numerical form. Nonetheless,system 208 identifies from the data that increasing overpolish time increases dishing, while increasing barrier polish time decreases dishing. This trend is extrapolated to model desired topology based on processing times withinsystem 202. Thus,system 208 can directsystem 202 to selectively increase or decrease overpolish or barrier polish times to achieve a desired dishing result. - For example, assume that, for
process 200, dishing of 400 Å results in optimal product yield.Data set 220 communicates tosystem 208 that dishing of 400 Å is desired. This becomes the topology target.System 208 may determine, for example, that the model offunction 216 is currently configured for dishing of 600 Å.Function 214 identifies a differential of 200 Å.Function 214 forwards this result to function 210 as the processing target.Function 210 translates the processing target into specific overpolish and barrier polish times, and adjusts the operation ofsystem 202 accordingly. In this manner,system 208 utilizes process-specific data to evaluate andcontrol system 202 to deliver a desired post-CMP topology. - In similar fashion,
system 208 may be configured to compile or utilize a variety of historical or comparative data relating certain process characteristics to dishing results (i.e., product yields). For example, data may be compiled correlating average die densities to dishing results. For a givenlot 206, the average die density may be input indata set 220.System 208 evaluates, for the given die density, what degree of dishing may be expected based on historical data. Assume, for example, that dishing of 800 Å is to be expected for the given die density.Input data set 220 indicates, however, that a target topology having dishing of 600 Å is desired.System 208 alters the dishing model offunction 216 to reduce dishing to 600 Å by decreasing overpolish, increasing barrier polish, or doing both in combination, and the operation ofsystem 202 is altered accordingly. Other data relating certain process characteristics to dishing results (e.g., correlating polishing pad wear to dishing) may similarly be compiled and utilized bysystem 208. - Thus, according to the present invention, a semiconductor processing system (e.g., a CMP processing system) may be augmented to provide selective, dynamic control of resulting wafer topologies. The present invention utilizes specific historical data and models to effect very specific modifications in processing-providing precise control of semiconductor topography.
- The embodiments and examples set forth herein are presented to best explain the present invention and its practical application and to thereby enable those skilled in the art to make and utilize the invention. However, those skilled in the art will recognize that the foregoing description and examples have been presented for the purpose of illustration and example only. The description as set forth is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching without departing from the spirit and scope of the following claims.
Claims (24)
1. A system for controlling post-processing topology of semiconductor wafers, the system comprising:
a processing function adapted to perform a process on a semiconductor wafer;
a profilometry function adapted to render a characterization of actual surface topology of the semiconductor wafer after the process is performed;
an input data set indicating a desired post-processing topology for the semiconductor wafer; and
a control system adapted to receive the input data set and the characterization, to identify a differential between the actual surface topology and the desired post-processing topology, and to eliminate the differential by altering the process performed by the processing function.
2. The system of claim 1 , wherein the semiconductor wafer comprises copper.
3. The system of claim 1 , wherein the process comprises CMP.
4. The system of claim 3 , wherein the processing function performs a barrier polish on the semiconductor wafer.
5. The system of claim 3 , wherein the processing function performs an overpolish on the semiconductor wafer.
6. The system of claim 1 , wherein the profilometry function comprises a profilometer.
7. The system of claim 6 , wherein the profilometer comprises a stylus-type profilometer.
8. The system of claim 1 , wherein the profilometry function is adapted to render a measurement of dishing.
9. The system of claim 8 , wherein the input data set indicates a desired amount of dishing.
10. The system of claim 1 , wherein the control system further comprises:
a data integrity function, adapted to evaluate reliability of the characterization and provide some indicia of the reliability,
a control function adapted to alter performance of the process within the processing function; and
a control modeling function, adapted to receive and evaluate the characterization, the indicia, and the desired post-processing topology, and adapted to provide to the control function a processing target for alteration of the process within the processing function.
11. The system of claim 10 , wherein at least one of the data integrity, control, or control modeling functions is implemented utilizing software.
12. The system of claim 11 , wherein at least one of the data integrity, control, or control modeling functions is implemented utilizing hardware.
13. A method for controlling post-processing topology of semiconductor wafers that utilize copper metallization, the method comprising the steps of:
providing a semiconductor wafer having copper metallization;
providing a processing function to perform a process on the semiconductor wafer;
providing a profilometry function to render a characterization of actual surface topology of the semiconductor wafer after the process is performed;
providing an input data set comprising a desired post-processing topology for the semiconductor wafer;
providing a control system to receive the input data set and the characterization;
utilizing the control system to identify a differential between the actual surface topology and the desired post-processing topology; and
utilizing the control system to alter the process performed by the processing function to eliminate the differential.
14. The method of claim 13 , wherein the step of providing a processing function further comprises providing a CMP processing function.
15. The method of claim 14 , wherein the step of providing a processing function further comprises providing a CMP processing function that performs a barrier polish on the semiconductor wafer.
16. The method of claim 14 , wherein the step of providing a processing function further comprises providing a CMP processing function that performs an overpolish on the semiconductor wafer.
17. The method of claim 13 , wherein the step of providing a profilometry function further comprises providing a profilometer.
18. The method of claim 17 , wherein the step of providing a profilometry function further comprises providing a stylus-type profilometer.
19. The method of claim 13 , wherein the profilometry function renders a measurement of dishing.
20. The method of claim 19 , wherein the step of providing an input data set further comprises providing a desired amount of dishing.
21. The method of claim 13 , wherein the step of providing a control system further comprises providing a data integrity function, to evaluate reliability of the characterization and provide some indicia of the reliability.
22. The method of claim 13 , wherein the step of providing a control system further comprises providing a control function to alter performance of the process within the processing function.
23. The method of claim 13 , wherein the step of providing a control system further comprises providing a control modeling function to receive and evaluate the characterization, the indicia, and the desired post-processing topology, and to generate a processing target for alteration of the process within the processing function.
24. A system for selectively controlling post-CMP dishing effects occurring in semiconductor wafers utilizing copper metallization, the system comprising:
a CMP processing system adapted to perform polishing, comprising copper overpolish and barrier polish, on a semiconductor wafer utilizing copper metallization;
a profilometer adapted to render a measurement of actual dishing occurring in the copper metallization of the semiconductor wafer after polishing;
an input data set comprising a dishing target for the semiconductor wafer;
a data integrity function adapted to evaluate the measurement and to generate indicia of the reliability of the measurement;
a control modeling function adapted to receive the measurement, the indicia of reliability and the input data set, to determine a differential between the dishing target and actual dishing, to generate a processing target for eliminating the differential, and to modify its processing target generation responsive to the indicia of reliability; and
a processing control function adapted to receive the processing target and to alter the copper overpolish, barrier polish, or both copper overpolish and barrier polish, responsive to the processing target.
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