US20050052855A9 - Methods for producing passive components on a semiconductor substrate - Google Patents

Methods for producing passive components on a semiconductor substrate Download PDF

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US20050052855A9
US20050052855A9 US10/344,653 US34465303A US2005052855A9 US 20050052855 A9 US20050052855 A9 US 20050052855A9 US 34465303 A US34465303 A US 34465303A US 2005052855 A9 US2005052855 A9 US 2005052855A9
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layer
resistor
produced
insulator
contact
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US20040080919A1 (en
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Dag Behammer
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United Monolithic Semiconductors GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49082—Resistor making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • the invention relates to a method for producing passive components in particular thin-film resistor elements and/or capacitor elements on a semiconductor substrate.
  • resistors and/or capacitors also to be produced in addition to active semiconductor components (HBT, FET, . . . ) on the same substrate and to be connected to one another and to the active components to form complex circuits.
  • the resistors are typically produced as thin-film resistors, and the capacitors as MIM (metal-insulator-metal) film capacitors.
  • the layers or regions used for the active components can also be used at the same time to produce the passive components
  • the formation of the passive components typically necessitates the deposition of further layers on the substrate surface, which has usually been passivated beforehand.
  • the generally high complexity of the production processes and the associated costs are disadvantageous.
  • the lift-off processes that are often used lead to unsatisfactory yields.
  • U.S. Pat. No. 3,996,551 describes the production of high-resistance and low-resistance resistors on an insulating substrate, a first mask being used in a lift-off process to deposit a patterned double layer comprising high-resistance resistor material on the substrate and a low-resistance resistor material in the overlying layer. Partial removal of the low-resistance layer using a further mask creates high-resistance resistor regions, which are covered by a passivation layer. Contact cartridges to the low-resistance layer and metallic contacts are produced in the passivation layer by means of further masks.
  • U.S. Pat. No. 4,878,770 describes the self-aligning production of precise thin-film resistors in a high-resistance resistor layer which is deposited on a substrate and above which a contact layer and, if required, a barrier layer as diffusion barrier between contact layer and resistor layer are applied over the whole area.
  • the entire layer sequence is etched as far as the substrate using a first mask uniformly in order to define resistor geometries.
  • central regions between contact regions are etched selectively as far as the resistor layer by means of a second mask in the multilayer resistor geometries.
  • WO 96/27210 discloses inter alia a method for producing resistors and capacitors in which a double layer comprising a resistor layer and a contact layer is deposited onto a substrate. In the double layer, component regions for resistors and capacitors are separated, within which resistors are formed in a subsequent step by removal of the contact layer. This first component plane is covered with an insulator layer in which contact holes are uncovered. A conductor layer deposited thereon is patterned in order to form terminal contacts to the contact layer and from the capacitor areas thereof.
  • the invention is based on the object of specifying a method for producing passive components on a semiconductor substrate by means of which different passive components can be produced with a low outlay.
  • the use of a common mask to produce structures for capacitors and resistors in the first insulator layer results in a procedure that has a low level of complexity and is thus cost-effective.
  • the first insulator layer lies above the contact layer as lower metallization plane for MIM capacitors in the case of the capacitor structures and above a resistor layer in the case of the resistor structures.
  • the first insulator layer is then removed selectively both with respect to the contact layer and with respect to the resistor layer.
  • the invention makes it possible, in a particularly simple and advantageous manner, to produce both different groups of capacitor elements distinguished by the capacitance per unit length, i.e. the capacitance related to area, and different groups of resistor elements.
  • a second insulator layer that is subsequently deposited may advantageously comprise a material which acts as corrosion protection for the resistor layer.
  • the first insulator layer which are produced for first capacitor elements above bottom capacitor electrodes of the contact layer, it is possible to deposit a second insulator layer whose properties can be designed for a high capacitance per unit length according to material and layer thickness.
  • the material of the second insulator layer can have a relatively high dielectric constant.
  • first capacitor elements having a high capacitance per unit length with only the second insulator layer as dielectric or second capacitor elements having a lower capacitance per unit length with the insulator double layer as dielectric by means of a common mask.
  • a material which serves, on the one hand, as diffusion barrier between the contact layer and a material lying below the barrier layer and, on the other hand, simultaneously as resistor material is advantageously chosen for at least one of the resistor layers, and at least one resistor element is also produced in the barrier later, preferably at least one resistor element is in each case produced in each of the two resistor layers.
  • the second resistor layer is preferably formed as a low-resistance barrier layer.
  • the barrier layer is advantageous particularly by virtue of the fact that the layer sequence of first resistor layer, second resistor layer and contact layer can also be deposited on contact windows opened in the passivation layer above active components, without impairments of the active semiconductor component occurring due to diffusion between contact layer deposited above the contact windows and an active semiconductor region.
  • the current flow to the active semiconductor region takes place with low resistance perpendicular to the resistor layers.
  • the production method according to the invention can dispense with lift-off processes entirely or to the greatest possible extent and can advantageously largely use dry- or wet-chemical etching methods to form structures in a layer, it being possible to use, in particular, etchants which act selectively on individual layer materials and automatically stop the etching process at the underlying layer.
  • FIG. 1 The successive situations of a first advantageous embodiment of a production process are designated in FIG. 1 with figures a to k.
  • FIG. 2 Advantageous variants of the introductory steps of the production process are described using FIG. 2, figs a to d.
  • the surface of the substrate and of the active components is passivated by a dielectric 2 (FIG. 1a).
  • a dielectric 2 FOG. 1a
  • contact windows are opened in the passivation layer and, under certain circumstances, a thin layer of a metal is applied.
  • a first resistor layer 3 made of high-resistance resistor material, preferably WSi x N y , a second resistor layer 4 made of lower-resistance resistor material by comparison therewith, and a metal layer 5 are successively deposited onto the passivated substrate (including active components) over the whole area (FIG. 1b).
  • the second resistor layer may comprise, in particular, (WTi)N z and simultaneously forms a diffusion barrier between the metal layer 5 and the first resistor layer 3 or the active semiconductor material or a layer—situated thereon—of a different metal in a contact window.
  • a first photoresist layer 6 is applied to the metal layer 5 , and electrode regions are uncovered in said photoresist layer.
  • the metal layer is reinforced by a thicker contact metallization 7 , for example by electrodeposition or by vapor deposition of a metal which preferably has a composition identical or similar to that of the metal layer 5 (fig. c).
  • Contact metal deposited on the photoresist layer 6 during vapor deposition is removed by stripping away the residual photoresist in a lift-off method.
  • the conductive double layer shall be designated as contact layer and forms a first electrode plane.
  • the metal layer 5 may also comprise a layer sequence of titanium on gold. In this case, the titanium layer improves the adhesion properties of the photoresist 6 that is subsequently applied.
  • the titanium layer is patterned wet-chemically after the patterning of the photoresist before the contact metallization 7 is applied.
  • the layer 5 can be dispensed with in the case of vapor deposition of the layer 7 .
  • a sputtering etching process directly before the vapor deposition of the layer 7 onto the layer 4 can minimize the contact resistance between the layers 7 and 4 .
  • the thin metal layer 5 in the gaps 6 * between the electrodes 7 of the contact metallization is removed wet-chemically selectively with respect to the layer 4 (fig. d) and electrodes are produced on the second resistor layer, which electrodes may be provided for example as bottom electrodes 71 , 72 for MIM capacitor elements or as terminal electrodes 73 , 74 for thin-film resistors.
  • a further photoresist mask 8 the contours of different components and possibly of connecting lines in the electrode plane of the layer 7 are patterned and the different components are separated by selective etching of the resistor layers 3 and 4 as far as the passivation layer 2 (fig. e).
  • a first insulator layer 9 is applied over the whole area (fig. f) and covered with a further photoresist layer 10 .
  • an opening 11 a above the capacitor electrode 71 and a further opening 11 b above the second resistor layer 4 between the terminal electrodes 74 are etched free in the first insulator layer (fig. g).
  • the etching operation stops automatically at the electrode layer 7 and the second resistor layer 4 , respectively.
  • the opening 11 b uncovered in the first insulator layer 9 serves as a mask for the selective etching of an opening 12 in the second resistor layer 4 with respect to the first resistor layer 3 .
  • a second insulator layer 13 is deposited (fig. i) over the whole area of the arrangement outlined in fig. h, which insulator layer serves, in the opening 11 a above the electrode 71 , as dielectric for first MIM capacitors having a high capacitance per unit length and, advantageously in the opening 12 , as corrosion protection for the first resistor layer 3 that is uncovered there.
  • a thicker insulator double layer 9 + 13 is produced by virtue of the second insulator layer above the electrode 72 , and serves as dielectric for second MIM capacitor elements with a lower capacitance per unit length than in the case of the first MIM capacitor elements.
  • the top electrodes 141 and 142 (fig. j) produced on the second insulator layer in a common process step form, with the bottom electrodes 71 and 72 , respectively, the abovementioned capacitor elements having a higher capacitance per unit length ( 71 / 141 ) and, respectively, lower capacitance per unit length ( 72 / 142 ), the values of the capacitances per unit length being adjustable through the layer thicknesses and material properties of the insulator layers 9 and 13 .
  • the insulator layers 9 , 13 can be constructed from identical or different materials.
  • a material having a lower dielectric constant may be advantageous for the first insulator layer 9 and a material having a higher dielectric constant may be advantageous for the second insulator layer 13 , thereby amplifying the differences in the capacitances per unit length which are already prescribed by the different layer thicknesses.
  • Capacitor elements having a high capacitance per unit length are particularly suitable for example for capacitor elements having a high quality factor in RF circuits, while the capacitor elements having a lower capacitance per unit length by virtue of the thicker insulator double layer may advantageously serve for DC isolation.
  • the component structures according to fig. j can be planarized, in a manner that is customary per se, by means of a dielectric 15 (e.g. BCB) and, after contact holes 16 have been opened, can be contact-connected via a further patterned metallization 17 (fig. k).
  • a dielectric 15 e.g. BCB
  • contact holes 16 after contact holes 16 have been opened, can be contact-connected via a further patterned metallization 17 (fig. k).
  • the metal layer 5 applied in step b of FIG. 1 serves, in particular, as a conductive start layer for the electrodeposition of the reinforcement metallization 7 .
  • the layer 5 as conductor plane can therefore also be obviated.
  • the substrate 1 is again passivated by a dielectric 2 (FIG. 2a).
  • a first resistor layer 3 , a second resistor layer 4 , a conductor layer 25 , a contact metallization 7 and a photoresist layer 26 are successively applied to the passivated substrate over the whole area (FIG. 2b).
  • the structures 71 , 72 , 73 , 74 are produced in the layer 7 (FIG. 2c), the conductor layer 25 acting as an etching stop layer.
  • the layer 25 is subsequently removed selectively with respect to the layer 4 (FIG. 2d).
  • the further steps of the production process correspond to the steps explained with reference to FIG. 1, figs e to k.
  • the layer 5 can also be dispensed with.
  • the layer 5 may possibly also serve as an adhesion promoter, diffusion barrier, etc.

Abstract

Methods are specified for producing passive components on a substrate, which methods permit, with a low outlay and a good yield, the production of different components, in particular high-resistance and low-resistance resistor elements and/or capacitor elements having a higher and those having a lower capacitance per unit length on a substrate. In this case, lift-off processes can largely be dispensed with, particularly in the case of critical patternings, and selective dry-and/or wet-chemical etching can be effected.

Description

    DESCRIPTION
  • The invention relates to a method for producing passive components in particular thin-film resistor elements and/or capacitor elements on a semiconductor substrate.
  • During the production of monolithic integrated semiconductor circuits, it is advantageously possible for passive components in particular resistors and/or capacitors, also to be produced in addition to active semiconductor components (HBT, FET, . . . ) on the same substrate and to be connected to one another and to the active components to form complex circuits. The resistors are typically produced as thin-film resistors, and the capacitors as MIM (metal-insulator-metal) film capacitors.
  • Whereas in silicon-based technologies the layers or regions used for the active components can also be used at the same time to produce the passive components, in compound semiconductors the formation of the passive components typically necessitates the deposition of further layers on the substrate surface, which has usually been passivated beforehand. In this case, although it is possible to produce components with high accuracy, good reproducibility and adjustable properties over wide ranges, the generally high complexity of the production processes and the associated costs are disadvantageous. The lift-off processes that are often used lead to unsatisfactory yields.
  • U.S. Pat. No. 3,996,551 describes the production of high-resistance and low-resistance resistors on an insulating substrate, a first mask being used in a lift-off process to deposit a patterned double layer comprising high-resistance resistor material on the substrate and a low-resistance resistor material in the overlying layer. Partial removal of the low-resistance layer using a further mask creates high-resistance resistor regions, which are covered by a passivation layer. Contact cartridges to the low-resistance layer and metallic contacts are produced in the passivation layer by means of further masks.
  • U.S. Pat. No. 4,878,770 describes the self-aligning production of precise thin-film resistors in a high-resistance resistor layer which is deposited on a substrate and above which a contact layer and, if required, a barrier layer as diffusion barrier between contact layer and resistor layer are applied over the whole area. The entire layer sequence is etched as far as the substrate using a first mask uniformly in order to define resistor geometries. In a further step, central regions between contact regions are etched selectively as far as the resistor layer by means of a second mask in the multilayer resistor geometries.
  • WO 96/27210 discloses inter alia a method for producing resistors and capacitors in which a double layer comprising a resistor layer and a contact layer is deposited onto a substrate. In the double layer, component regions for resistors and capacitors are separated, within which resistors are formed in a subsequent step by removal of the contact layer. This first component plane is covered with an insulator layer in which contact holes are uncovered. A conductor layer deposited thereon is patterned in order to form terminal contacts to the contact layer and from the capacitor areas thereof.
  • The invention is based on the object of specifying a method for producing passive components on a semiconductor substrate by means of which different passive components can be produced with a low outlay.
  • Solutions according to the invention are described in the independent claims. The dependent claims contain advantageous refinements and developments of the invention.
  • The use of a common mask to produce structures for capacitors and resistors in the first insulator layer results in a procedure that has a low level of complexity and is thus cost-effective. In this case, the first insulator layer lies above the contact layer as lower metallization plane for MIM capacitors in the case of the capacitor structures and above a resistor layer in the case of the resistor structures. The first insulator layer is then removed selectively both with respect to the contact layer and with respect to the resistor layer.
  • In this case, in accordance with one development, the invention makes it possible, in a particularly simple and advantageous manner, to produce both different groups of capacitor elements distinguished by the capacitance per unit length, i.e. the capacitance related to area, and different groups of resistor elements.
  • By selective removal of the second, upper low-resistance resistor layer in the structure produced in the first insulator layer as far as the first, lower high-resistance resistor layer, it is possible to produce a high-resistance resistor element, in which case, by combining the mask for the separation of the components and the mask for the production of the structure in the first insulator layer, it is possible to produce, in a self-aligning manner, resistor elements with high geometrical precision in a manner similar to the procedure disclosed in U.S. Pat. No. 4,878,770. A second insulator layer that is subsequently deposited may advantageously comprise a material which acts as corrosion protection for the resistor layer.
  • In the structures in the first insulator layer which are produced for first capacitor elements above bottom capacitor electrodes of the contact layer, it is possible to deposit a second insulator layer whose properties can be designed for a high capacitance per unit length according to material and layer thickness. In particular, the material of the second insulator layer can have a relatively high dielectric constant. By virtue of the preferred whole-area deposition of the second insulator layer, an insulator double layer is produced outside the structures that are uncovered in the first insulator layer. By virtue of metal areas deposited on the second insulator layer as top capacitor electrodes of MIM capacitors, it is then possible to produce first capacitor elements having a high capacitance per unit length with only the second insulator layer as dielectric or second capacitor elements having a lower capacitance per unit length with the insulator double layer as dielectric by means of a common mask.
  • The production of capacitors having a different capacitance per unit length in this way is also particularly advantageous independently of the simultaneous production of capacitor structures and resistor structures by means of a common mask.
  • In the production of thin-film resistor elements by successive deposition of a first resistor layer, a second resistor layer and a contact layer, as a material which serves, on the one hand, as diffusion barrier between the contact layer and a material lying below the barrier layer and, on the other hand, simultaneously as resistor material is advantageously chosen for at least one of the resistor layers, and at least one resistor element is also produced in the barrier later, preferably at least one resistor element is in each case produced in each of the two resistor layers. The second resistor layer is preferably formed as a low-resistance barrier layer. The barrier layer is advantageous particularly by virtue of the fact that the layer sequence of first resistor layer, second resistor layer and contact layer can also be deposited on contact windows opened in the passivation layer above active components, without impairments of the active semiconductor component occurring due to diffusion between contact layer deposited above the contact windows and an active semiconductor region. The current flow to the active semiconductor region takes place with low resistance perpendicular to the resistor layers.
  • The production method according to the invention can dispense with lift-off processes entirely or to the greatest possible extent and can advantageously largely use dry- or wet-chemical etching methods to form structures in a layer, it being possible to use, in particular, etchants which act selectively on individual layer materials and automatically stop the etching process at the underlying layer.
  • The invention is illustrated in still greater detail below using an example of the production of a complex band element arrangement with high-resistance and low-resistance resistor elements and MIM capacitor elements having different capacitances per unit length, with reference to the figures. The successive situations of a first advantageous embodiment of a production process are designated in FIG. 1 with figures a to k. Advantageous variants of the introductory steps of the production process are described using FIG. 2, figs a to d.
  • After the active components (not included in the figures) have been integrated in the substrate 1, the surface of the substrate and of the active components is passivated by a dielectric 2 (FIG. 1a). On the active components, contact windows are opened in the passivation layer and, under certain circumstances, a thin layer of a metal is applied.
  • A first resistor layer 3 made of high-resistance resistor material, preferably WSixNy, a second resistor layer 4 made of lower-resistance resistor material by comparison therewith, and a metal layer 5 are successively deposited onto the passivated substrate (including active components) over the whole area (FIG. 1b). The second resistor layer may comprise, in particular, (WTi)Nz and simultaneously forms a diffusion barrier between the metal layer 5 and the first resistor layer 3 or the active semiconductor material or a layer—situated thereon—of a different metal in a contact window. In the resistor layers 3 and 4, it is advantageously possible, in each case for the materials specified by way of example, to influence the sheet resistance and/or the temperature coefficient of the resistor material by way of the nitrogen content. The metal layer 5 may be composed of gold, for example. The layers 3, 4 and 5 may advantageously be applied in one process operation, in particular by sputtering.
  • A first photoresist layer 6 is applied to the metal layer 5, and electrode regions are uncovered in said photoresist layer. In the uncovered electrode regions, the metal layer is reinforced by a thicker contact metallization 7, for example by electrodeposition or by vapor deposition of a metal which preferably has a composition identical or similar to that of the metal layer 5 (fig. c). Contact metal deposited on the photoresist layer 6 during vapor deposition is removed by stripping away the residual photoresist in a lift-off method. The conductive double layer shall be designated as contact layer and forms a first electrode plane. In a favorable embodiment, the metal layer 5 may also comprise a layer sequence of titanium on gold. In this case, the titanium layer improves the adhesion properties of the photoresist 6 that is subsequently applied. The titanium layer is patterned wet-chemically after the patterning of the photoresist before the contact metallization 7 is applied.
  • The layer 5 can be dispensed with in the case of vapor deposition of the layer 7. A sputtering etching process directly before the vapor deposition of the layer 7 onto the layer 4 can minimize the contact resistance between the layers 7 and 4.
  • After the removal of the photoresist mask 6, the thin metal layer 5 in the gaps 6* between the electrodes 7 of the contact metallization is removed wet-chemically selectively with respect to the layer 4 (fig. d) and electrodes are produced on the second resistor layer, which electrodes may be provided for example as bottom electrodes 71, 72 for MIM capacitor elements or as terminal electrodes 73, 74 for thin-film resistors.
  • In a further photoresist mask 8, the contours of different components and possibly of connecting lines in the electrode plane of the layer 7 are patterned and the different components are separated by selective etching of the resistor layers 3 and 4 as far as the passivation layer 2 (fig. e).
  • After the second photoresist mask 8 has been stripped away, a first insulator layer 9 is applied over the whole area (fig. f) and covered with a further photoresist layer 10. By means of the photoresist layer 10, an opening 11 a above the capacitor electrode 71 and a further opening 11 b above the second resistor layer 4 between the terminal electrodes 74 are etched free in the first insulator layer (fig. g). The etching operation stops automatically at the electrode layer 7 and the second resistor layer 4, respectively. The opening 11 b uncovered in the first insulator layer 9 serves as a mask for the selective etching of an opening 12 in the second resistor layer 4 with respect to the first resistor layer 3. As a result, a high-resistance thin-film resistor element is produced between the terminal electrodes 74, the properties of which element are critically determined by the first resistor layer 3, whereas a low-resistance resistor element is formed between the terminal electrodes 73, the properties of which element are primarily given by the material of the second resistor layer 4 (fig. h).
  • A second insulator layer 13 is deposited (fig. i) over the whole area of the arrangement outlined in fig. h, which insulator layer serves, in the opening 11 a above the electrode 71, as dielectric for first MIM capacitors having a high capacitance per unit length and, advantageously in the opening 12, as corrosion protection for the first resistor layer 3 that is uncovered there. At the same time, a thicker insulator double layer 9+13 is produced by virtue of the second insulator layer above the electrode 72, and serves as dielectric for second MIM capacitor elements with a lower capacitance per unit length than in the case of the first MIM capacitor elements.
  • The top electrodes 141 and 142 (fig. j) produced on the second insulator layer in a common process step form, with the bottom electrodes 71 and 72, respectively, the abovementioned capacitor elements having a higher capacitance per unit length (71/141) and, respectively, lower capacitance per unit length (72/142), the values of the capacitances per unit length being adjustable through the layer thicknesses and material properties of the insulator layers 9 and 13. The insulator layers 9, 13 can be constructed from identical or different materials. In particular, a material having a lower dielectric constant may be advantageous for the first insulator layer 9 and a material having a higher dielectric constant may be advantageous for the second insulator layer 13, thereby amplifying the differences in the capacitances per unit length which are already prescribed by the different layer thicknesses. Capacitor elements having a high capacitance per unit length are particularly suitable for example for capacitor elements having a high quality factor in RF circuits, while the capacitor elements having a lower capacitance per unit length by virtue of the thicker insulator double layer may advantageously serve for DC isolation.
  • The component structures according to fig. j can be planarized, in a manner that is customary per se, by means of a dielectric 15 (e.g. BCB) and, after contact holes 16 have been opened, can be contact-connected via a further patterned metallization 17 (fig. k).
  • The metal layer 5 applied in step b of FIG. 1 serves, in particular, as a conductive start layer for the electrodeposition of the reinforcement metallization 7. In the case of vapor deposition of the metallization 7, the layer 5 as conductor plane can therefore also be obviated.
  • In the procedure outlined in FIG. 2, the substrate 1 is again passivated by a dielectric 2 (FIG. 2a). A first resistor layer 3, a second resistor layer 4, a conductor layer 25, a contact metallization 7 and a photoresist layer 26 are successively applied to the passivated substrate over the whole area (FIG. 2b). By patterning the photoresist layer 26 with covered electrode regions 261 as etching mask for the layer 7, the structures 71, 72, 73, 74 are produced in the layer 7 (FIG. 2c), the conductor layer 25 acting as an etching stop layer. In the uncovered regions 262, the layer 25 is subsequently removed selectively with respect to the layer 4 (FIG. 2d). The further steps of the production process correspond to the steps explained with reference to FIG. 1, figs e to k.
  • If the layer 7 can be etched selectively with respect to the second resistor layer 4, the layer 5 can also be dispensed with. However, the layer 5 may possibly also serve as an adhesion promoter, diffusion barrier, etc.
  • The features above and the features which are specified in the claims and the features which can be gathered from the figures can advantageously be realized both individually and in different combinations. The invention is not restricted to the examples described, but rather can be modified in various ways within the scope of expert ability.

Claims (15)

1. A method for producing at least one thin-film resistor element and at least one capacitor element on a substrate, wherein
1a) a first high-resistance resistor layer (3), a second low-resistance resistor layer (4) and a contact layer (5, 7) are deposited successively on the, if appropriate passivated (2), substrate (1),
1b) structures (71, 72, 73, 74) for terminals and bottom electrodes of capacitor elements are produced in the contact layer (5, 7),
1c) components are separated by isolating regions being etched free,
1d) a first insulator layer (9) is applied on the contact layer (5, 7) and resistor layers (4), and
1e) structures (11 a, 11 b) for first capacitors and for first resistors are produced in the first insulator layer (9) by means of a common mask.
2. The method as claimed in claim 1, characterized in that a second insulator layer (13) is deposited on the structures produced in step 1e.
3. The method as claimed in claim 2, characterized in that a material which effects corrosion protection for the underlying resistor layer (3) is chosen for the second insulator layer (13).
4. The method as claimed in one of claims 1 to 3, characterized in that the structures (71, 72, 73, 74) of the contact layer (5, 7) are produced as a conductor plane (5) deposited over the whole area with patterned reinforcement metallization (7) and removal of non-reinforced conductor areas of the conductor plane (5).
5. The method as claimed in one of claims 1 to 3, characterized in that the contact layer (5, 7) is deposited over the whole area and then removed in patterned fashion in order to produce the structures (71, 72, 73, 74).
6. The method as claimed in one of claims 1 to 3, characterized in that the structures (71, 72, 73, 74) are produced by patterned deposition of a contact metallization (7) on the second resistor layer (4).
7. The method as claimed in one of claims 1 to 6, characterized in that high-resistance resistors are produced by removal of the low-resistance resistor layer (4) in separated resistor components with the structures according to 1e.
8. The method as claimed in one of claims 1 to 7, characterized in that top electrodes (141, 142) for capacitor elements are produced in a metallization layer lying above the second insulator layer (13).
9. The method as claimed in claim 8, characterized in that top electrodes (141) for first capacitor elements of higher specific capacitance are produced above bottom electrodes (71) which are uncovered in 1e and covered with the second insulator layer (13).
10. The method as claimed in claim 8, characterized in that top capacitor electrodes (142) for second capacitor elements of lower specific capacitance are produced above bottom capacitor electrodes (72) which are not uncovered in 1e and are covered with the first and second insulator layers.
11. The method as claimed in one of claims 2 to 10, characterized in that a material with a higher dielectric constant is chosen for the second insulator layer (13) for the first insulator layer (9).
12. A method for producing at least one film resistor element on a semiconductor substrate, a first, high-resistance resistor layer (3), a second, low-resistance resistor layer (4), and a contact layer (5, 7) being successively deposited over the whole area on a substrate, a material which acts as a diffusion barrier between the contact layer and a material lying below the barrier layer being chosen at least for one of the resistor layers, and at least one resistor element being produced with layer-parallel current flow in the barrier layer.
13. The method as claimed in claim 12, characterized in that the layer sequence comprising first resistor layer, second resistor layer and contact layer is also deposited on active component regions, and in that at least one current path to a terminal of an active component is produced through the layer sequence perpendicular to the layer plane.
14. The method as claimed in claim 12 or 13, characterized in that first resistor layer, second resistor layer and contact layer can be etched selectively with respect to one another.
15. The method as claimed in one of claims 1 to 11 and one of claims 12 to 14.
US10/344,653 2000-08-14 2001-08-01 Methods for producing passive components on a semiconductor substrate Expired - Lifetime US7059041B2 (en)

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WO2002015273A2 (en) 2002-02-21
EP1312118B1 (en) 2013-10-16

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