US20050013175A1 - Semiconductor memory device having over-driving scheme - Google Patents

Semiconductor memory device having over-driving scheme Download PDF

Info

Publication number
US20050013175A1
US20050013175A1 US10/737,546 US73754603A US2005013175A1 US 20050013175 A1 US20050013175 A1 US 20050013175A1 US 73754603 A US73754603 A US 73754603A US 2005013175 A1 US2005013175 A1 US 2005013175A1
Authority
US
United States
Prior art keywords
voltage
driving
over
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/737,546
Other versions
US6853593B1 (en
Inventor
Seung-Cheol Bae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAE, SEUNG-CHEOL
Publication of US20050013175A1 publication Critical patent/US20050013175A1/en
Application granted granted Critical
Publication of US6853593B1 publication Critical patent/US6853593B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/065—Sense amplifier drivers

Definitions

  • the present invention relates to semiconductor design technology; and, more particularly, to a semiconductor memory device having an over-driving scheme.
  • DRAM dynamic random access memory
  • bit-line sense amplifier senses and amplifies a voltage difference between corresponding two bit-lines constructing a bit-line pair.
  • a driving time of the bit-line sense amplifiers is determined according to whether or not it is possible to supply a sufficient amount of current as much as driving the bit-line sense amplifiers.
  • the over-driving scheme is adopted so as to instantly supply a voltage higher than a normal voltage, i.e., internal core voltage, onto a power line RTO of the bit-line sense amplifier at an initiative operating period of the bit-line sense amplifier (immediately after the charge sharing between a cell and a bit-line).
  • FIG. 1 there is provided a block diagram of a semiconductor memory device having a conventional over-driving scheme.
  • the semiconductor memory device includes a memory cell array block 10 , a bit-line sense amplifier array block 12 for sensing and amplifying voltage differences of bit-line pairs of the memory cell array block 10 , a driver PM 2 for driving a power line RTO with a voltage on a connection node N 1 attached to a core power supply terminal Vcore in response to a driving control signal SAP, a pulse generating unit 11 for producing an over-driving enable signal over_enb based on an over-driving startup signal over_on, and an over-driver PM 1 for driving the connection node N 1 with an external voltage Vdd which is higher than the internal core voltage Vcore.
  • a separate driver is employed to drive a power line SB of the bit-line sense amplifier array block 12 with a ground voltage Vss.
  • FIG. 2 shows a detailed circuit diagram of the pulse generating unit 11 in FIG. 1 .
  • the pulse generating unit 11 includes a delay sector 20 for delaying the over-driving startup signal over_on for a constant time and inverting the delayed signal to thereby output a signal over_onb_dl, and a NAND gate ND 1 for generating the over-driving enable signal over_enb based on the over-driving startup signal over_on and an output signal over_onb_dl of the delay sector 20 .
  • the delay sector 20 can be implemented with an inverter chain consisting of inverters I 1 , I 2 and I 3 by using the over-driving startup signal over_on as an input. That is, the output signal over_onb_dl of the delay sector 20 is an inverted signal delayed by a delay time of the inverter chain compared to the over-driving startup signal over_on.
  • FIG. 3 describes a waveform diagram showing the operation of the circuit in FIG. 1 .
  • bit-lines e.g., BL and /BL.
  • the driver PM 2 drives the power line RTO of the bit-line sense amplifier with the voltage of the connection node N 1 in response to the driving control signal SAP. At this time, the power line RTO is driven by a voltage higher than the internal core voltage Vcore.
  • the delay sector 20 delays the over-driving startup signal over_on by a fixed time and inverts the delayed signal to thereby produce the signal over_onb_dl.
  • the NAND gate ND 1 is coupled with the over-driving startup signal over_on and the signal over_onb_dl outputted from the delay sector 20 to thereby generate the over-driving enable signal over_enb having a pulse width which corresponds to the delay time of the delay sector 20 . Namely, the pulse width of the over-driving enable signal over_enb determines the driving time of the over-driver PM 1 .
  • the power line RTO of the bit-line sense amplifier is driven by the internal core voltage Vcore and the data restoring is accomplished during this period.
  • the word-line WL is inactivated and the over-driving startup signal over_on and the driving control signal SAP are disabled.
  • the bit-lines BL and /BL are pre-charged.
  • the conventional pulse generating unit 11 for producing the over-driving enable signal over_enb has an activated time corresponding to the delay time of the delay sector 20 , the over-driving period is always maintained to have a constant time.
  • the over-driving period is maintained constantly as shown above, there are required lots of modifications and repeated tests for a metal layer. Therefore, if the driving time of the over-driver PM 1 is short, it is difficult to increase the driving voltage of the bit-line sense amplifier to a sufficient voltage level, so that the driving time of the bit-line sense amplifier cannot be improved. On the other hand, if the driving time is long, a level of the driving voltage of the bit-line sense amplifier is substantially increased, resulting in a bad effect on a high margin of data. As a result, to find an appropriate over-driving time, lots of modifications and repeated tests are required for the metal layer. This leads high cost and time consumption.
  • an object of the present invention to provide a semiconductor memory device having an over-driving scheme capable of performing effective over-driving regardless of the fluctuation of manufacturing and driving environment.
  • a semiconductor memory device including a first power supplying block for providing a normal voltage, a first driving block for driving a power line of a bit-line amplifier with a voltage on a connection node attached to the first power supplying block, a second driving block for driving the connection node with a voltage higher than the normal voltage, and a control block for generating an over-driving control signal which controls the second driving block by detecting a level of the voltage on the connection node to that of a preset reference voltage.
  • an over-driver controlled by sensing a voltage level compares a voltage level of a power line with that of a reference voltage (ascending limit of the power line) and is enabled during the voltage level of the power line is lower than that of the reference voltage.
  • FIG. 1 is a block diagram of a semiconductor memory device having a conventional over-driving scheme
  • FIG. 2 shows a detailed circuit diagram of a pulse generating unit in FIG. 1 ;
  • FIG. 3 describes a waveform diagram showing the operation of circuits in FIGS. 1 and 2 ;
  • FIG. 4 provides a circuit diagram of a semiconductor memory device having an over-driving scheme in accordance with the present invention.
  • FIG. 5 represents a waveform diagram showing the operation of the circuit in FIG. 4 .
  • FIG. 4 there is provided a circuit diagram of a semiconductor memory device having an over-driving scheme in accordance with an embodiment of the present invention.
  • the inventive semiconductor memory device includes a driver PM 2 for driving a power supply line RTO of a bit-line sense amplifier with a voltage V N1 on a connection node N 1 attached to a core power supply terminal Vcore, a control unit 40 for generating an over-driving control signal over_ctr by detecting a level of the voltage V N1 to that of a preset reference voltage Vref, and an over-driver PM 1 for driving the connection node N 1 with an external voltage VDD in response to the over-driving control signal over_ctr.
  • the control unit 40 contains a reference voltage generating sector 41 for producing the reference voltage Vref which is an ascending limit of the voltage V N1 of the connection node N 1 , a voltage level detecting sector 42 for generating an over-driver off signal over_off by comparing the reference voltage Vref with the voltage V N1 in response to an over-driving startup signal over_on, and a pulse generating sector 43 for producing the over-driving control signal over_ctr based on the over-driver off signal over_off and the over-driving startup signal over_on.
  • the reference voltage generating sector 41 produces the reference voltage Vref through the voltage dividing performed by using two resistors R 1 and R 2 serially connected between a ground voltage and the external voltage VDD higher than the internal core voltage Vcore.
  • the reference voltage Vref is lower than the external voltage VDD and higher than the internal core voltage Vcore.
  • the voltage level detecting sector 42 has a current source transistor NM 1 for providing a bias voltage to differential input transistors NM 2 and NM 3 based on the over-driving startup signal over_on, the differential input transistors NM 2 and NM 3 connected to the current source transistor NM 1 and coupled with differential inputs, i.e., the reference voltage Vref and the connection node voltage V N1 , respectively, a current mirror consisting of transistors PM 4 and PM 5 coupled to the differential input transistors NM 2 and NM 3 , respectively, pre-charge transistors PM 3 and PM 6 for pre-charging drains of the differential input transistors NM 2 and NM 3 by receiving the over-driving startup signal over_on as their gate input, and an inverter I 4 for inverting a signal outputted through the drain of the transistor NM 3 whose gate is coupled with the connection node voltage V N1 .
  • a current source transistor NM 1 for providing a bias voltage to differential input transistors NM 2 and NM 3 based on
  • the pulse generating sector 43 has a NAND gate ND 2 for logically combining the over-driving startup signal over_on and the over-driver off signal over_off, and a NAND gate ND 3 for logically combining the over-driving startup signal over_on and an output signal of the NAND gate ND 2 .
  • the over-driver PM 1 is implemented with a PMOS transistor whose gate receives the over-driving control signal over_ctr, source is connected to the external voltage VDD and drain is attached to the connection node N 1 .
  • the driver PM 2 is implemented with a PMOS transistor whose gate is coupled with a driving control signal SAP, source is connected to the connection node N 1 and drain is attached to the power line RTO of the bit-line sense amplifier.
  • FIG. 5 represents a waveform diagram showing the operation of the circuit in FIG. 4 .
  • the over-driver off signal over_off is in a logic low state.
  • the over-driving startup signal over_on is actuated to a logic high state (simultaneously, the signal SAP is also activated to a logic low state although it is not shown)
  • the over-driving control signal over_ctr is enabled to a logic low state, making the over-driver PM 1 turned-on and, as a result, the level of the connection node voltage V N1 starts to ascend. That is, the power line RTO of the bit-line sense amplifier is driven by the ascending connection node voltage V N1 .
  • the voltage level detecting sector 42 detects it and, thus, the over-driver off signal over_off is activated to a logic high state. Furthermore, the over-driving control signal over_ctr is inactivated to a logic high state. If the over-driving control signal over_ctr is disabled, the over-driver PM 1 is turned-off and the power line RTO of the bit-line sense amplifier is driven by the internal core voltage Vcore.
  • bit-line sensing and amplification, and restoring are performed and, sequentially, the word-line is inactivated.
  • the over-driving period is decided by sensing the voltage level of the connection node N 1 . Since the over-driving period is varied by the fluctuation of memory environment, manufacturing processes and so on, the inventive device determines the over-driving period by considering the above factors and, thus, it is possible to maintain an optimized over-driving period without a separate test process or repeated modifications for a metal layer.
  • the voltage level detecting sector 42 is implemented with an NMOS type differential amplifier in accordance with the preferred embodiment of the present invention, it can be implemented with a PMOS type differential amplifier in accordance with another embodiment.
  • the present invention is applicable when the pulse generating sector 43 is implemented with other logic gates instead of the NAND gates shown in FIG. 4 .

Abstract

A semiconductor memory device has an over-driving scheme through which it is possible to perform effective over-driving regardless of the fluctuation of manufacturing and driving environment. The semiconductor memory device includes a first power supplying block for providing a normal voltage, a first driving block for driving a power line of a bit-line amplifier with a voltage on a connection node attached to the first power supplying block, a second driving block for driving the connection node with a voltage higher than the normal voltage, and a control block for generating an over-driving control signal which controls the second driving block by detecting a level of the voltage on the connection node to that of a preset reference voltage.

Description

    FIELD OF THE INVENTION
  • The present invention relates to semiconductor design technology; and, more particularly, to a semiconductor memory device having an over-driving scheme.
    • DESCRIPTION OF RELATED ART
  • As a low driving voltage is used to implement the low power of a memory device, various technical supplements have been used to improve the operation of a sense amplifier in the memory device such as a dynamic random access memory (DRAM). One of such supplements is an over-driving scheme of the sense-amplifier.
  • In general, if data of a plurality of memory cells are transferred onto bit-lines, wherein the memory cells are connected to a certain word-line activated by a row address, a bit-line sense amplifier senses and amplifies a voltage difference between corresponding two bit-lines constructing a bit-line pair.
  • In the above process, since thousands of bit-line sense amplifiers start to operate simultaneously, a driving time of the bit-line sense amplifiers is determined according to whether or not it is possible to supply a sufficient amount of current as much as driving the bit-line sense amplifiers.
  • However, since the operating voltage is lowered according to a trend of the low power of the memory device, it is difficult to supply the sufficient current in a moment. To overcome that kind of obstacle, the over-driving scheme is adopted so as to instantly supply a voltage higher than a normal voltage, i.e., internal core voltage, onto a power line RTO of the bit-line sense amplifier at an initiative operating period of the bit-line sense amplifier (immediately after the charge sharing between a cell and a bit-line).
  • In FIG. 1, there is provided a block diagram of a semiconductor memory device having a conventional over-driving scheme.
  • Referring to FIG. 1, the semiconductor memory device includes a memory cell array block 10, a bit-line sense amplifier array block 12 for sensing and amplifying voltage differences of bit-line pairs of the memory cell array block 10, a driver PM2 for driving a power line RTO with a voltage on a connection node N1 attached to a core power supply terminal Vcore in response to a driving control signal SAP, a pulse generating unit 11 for producing an over-driving enable signal over_enb based on an over-driving startup signal over_on, and an over-driver PM1 for driving the connection node N1 with an external voltage Vdd which is higher than the internal core voltage Vcore. Meanwhile, a separate driver is employed to drive a power line SB of the bit-line sense amplifier array block 12 with a ground voltage Vss.
  • FIG. 2 shows a detailed circuit diagram of the pulse generating unit 11 in FIG. 1.
  • Referring to FIG. 2, the pulse generating unit 11 includes a delay sector 20 for delaying the over-driving startup signal over_on for a constant time and inverting the delayed signal to thereby output a signal over_onb_dl, and a NAND gate ND1 for generating the over-driving enable signal over_enb based on the over-driving startup signal over_on and an output signal over_onb_dl of the delay sector 20.
  • The delay sector 20 can be implemented with an inverter chain consisting of inverters I1, I2 and I3 by using the over-driving startup signal over_on as an input. That is, the output signal over_onb_dl of the delay sector 20 is an inverted signal delayed by a delay time of the inverter chain compared to the over-driving startup signal over_on.
  • FIG. 3 describes a waveform diagram showing the operation of the circuit in FIG. 1.
  • Hereinafter, with reference to FIG. 3, there will be explained the operation of the circuits in FIGS. 1 and 2.
  • First of all, if a word-line WL is activated, data of memory cells in the memory cell array block 10 corresponding to the word-line WL are transferred onto bit-lines, e.g., BL and /BL.
  • Then, if the driving control signal SAP and the over-driving startup signal over_on are actuated, the driver PM2 drives the power line RTO of the bit-line sense amplifier with the voltage of the connection node N1 in response to the driving control signal SAP. At this time, the power line RTO is driven by a voltage higher than the internal core voltage Vcore.
  • In the meantime, the delay sector 20 delays the over-driving startup signal over_on by a fixed time and inverts the delayed signal to thereby produce the signal over_onb_dl. The NAND gate ND1 is coupled with the over-driving startup signal over_on and the signal over_onb_dl outputted from the delay sector 20 to thereby generate the over-driving enable signal over_enb having a pulse width which corresponds to the delay time of the delay sector 20. Namely, the pulse width of the over-driving enable signal over_enb determines the driving time of the over-driver PM1.
  • Subsequently, as becoming the over-driving enable signal over_enb inactivated, the power line RTO of the bit-line sense amplifier is driven by the internal core voltage Vcore and the data restoring is accomplished during this period.
  • After then, the word-line WL is inactivated and the over-driving startup signal over_on and the driving control signal SAP are disabled. The bit-lines BL and /BL are pre-charged.
  • As described above, since the conventional pulse generating unit 11 for producing the over-driving enable signal over_enb has an activated time corresponding to the delay time of the delay sector 20, the over-driving period is always maintained to have a constant time.
  • However, if the over-driving period is maintained constantly as shown above, there are required lots of modifications and repeated tests for a metal layer. Therefore, if the driving time of the over-driver PM1 is short, it is difficult to increase the driving voltage of the bit-line sense amplifier to a sufficient voltage level, so that the driving time of the bit-line sense amplifier cannot be improved. On the other hand, if the driving time is long, a level of the driving voltage of the bit-line sense amplifier is substantially increased, resulting in a bad effect on a high margin of data. As a result, to find an appropriate over-driving time, lots of modifications and repeated tests are required for the metal layer. This leads high cost and time consumption.
  • Meanwhile, although the appropriate driving time was determined through the repeated modifications and tests, it is difficult to get an expected effect by the fluctuation of driving and manufacturing environment of the memory device.
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a semiconductor memory device having an over-driving scheme capable of performing effective over-driving regardless of the fluctuation of manufacturing and driving environment.
  • In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a first power supplying block for providing a normal voltage, a first driving block for driving a power line of a bit-line amplifier with a voltage on a connection node attached to the first power supplying block, a second driving block for driving the connection node with a voltage higher than the normal voltage, and a control block for generating an over-driving control signal which controls the second driving block by detecting a level of the voltage on the connection node to that of a preset reference voltage.
  • In accordance with the present invention, an over-driver controlled by sensing a voltage level compares a voltage level of a power line with that of a reference voltage (ascending limit of the power line) and is enabled during the voltage level of the power line is lower than that of the reference voltage. By driving the over-driver through the voltage level sensing, there are not required the repeated modifications and test processes for the metal layer. Furthermore, the effective over-driving can be performed without being influenced by the fluctuation of the manufacturing and driving environment.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a block diagram of a semiconductor memory device having a conventional over-driving scheme;
  • FIG. 2 shows a detailed circuit diagram of a pulse generating unit in FIG. 1;
  • FIG. 3 describes a waveform diagram showing the operation of circuits in FIGS. 1 and 2;
  • FIG. 4 provides a circuit diagram of a semiconductor memory device having an over-driving scheme in accordance with the present invention; and
  • FIG. 5 represents a waveform diagram showing the operation of the circuit in FIG. 4.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
  • In FIG. 4, there is provided a circuit diagram of a semiconductor memory device having an over-driving scheme in accordance with an embodiment of the present invention.
  • Referring to FIG. 4, the inventive semiconductor memory device includes a driver PM2 for driving a power supply line RTO of a bit-line sense amplifier with a voltage VN1 on a connection node N1 attached to a core power supply terminal Vcore, a control unit 40 for generating an over-driving control signal over_ctr by detecting a level of the voltage VN1 to that of a preset reference voltage Vref, and an over-driver PM1 for driving the connection node N1 with an external voltage VDD in response to the over-driving control signal over_ctr.
  • The control unit 40 contains a reference voltage generating sector 41 for producing the reference voltage Vref which is an ascending limit of the voltage VN1 of the connection node N1, a voltage level detecting sector 42 for generating an over-driver off signal over_off by comparing the reference voltage Vref with the voltage VN1 in response to an over-driving startup signal over_on, and a pulse generating sector 43 for producing the over-driving control signal over_ctr based on the over-driver off signal over_off and the over-driving startup signal over_on.
  • The reference voltage generating sector 41 produces the reference voltage Vref through the voltage dividing performed by using two resistors R1 and R2 serially connected between a ground voltage and the external voltage VDD higher than the internal core voltage Vcore. The reference voltage Vref is lower than the external voltage VDD and higher than the internal core voltage Vcore.
  • The voltage level detecting sector 42 has a current source transistor NM1 for providing a bias voltage to differential input transistors NM2 and NM3 based on the over-driving startup signal over_on, the differential input transistors NM2 and NM3 connected to the current source transistor NM1 and coupled with differential inputs, i.e., the reference voltage Vref and the connection node voltage VN1, respectively, a current mirror consisting of transistors PM4 and PM5 coupled to the differential input transistors NM2 and NM3, respectively, pre-charge transistors PM3 and PM 6 for pre-charging drains of the differential input transistors NM2 and NM3 by receiving the over-driving startup signal over_on as their gate input, and an inverter I4 for inverting a signal outputted through the drain of the transistor NM3 whose gate is coupled with the connection node voltage VN1.
  • The pulse generating sector 43 has a NAND gate ND2 for logically combining the over-driving startup signal over_on and the over-driver off signal over_off, and a NAND gate ND3 for logically combining the over-driving startup signal over_on and an output signal of the NAND gate ND2.
  • Meanwhile, it is preferable that the over-driver PM1 is implemented with a PMOS transistor whose gate receives the over-driving control signal over_ctr, source is connected to the external voltage VDD and drain is attached to the connection node N1. The driver PM2 is implemented with a PMOS transistor whose gate is coupled with a driving control signal SAP, source is connected to the connection node N1 and drain is attached to the power line RTO of the bit-line sense amplifier.
  • FIG. 5 represents a waveform diagram showing the operation of the circuit in FIG. 4.
  • If a word-line WL is activated, data of memory cells corresponding to the word-line WL are transmitted onto bit-lines and, as a result, there occurs a delicate voltage difference between corresponding bit-lines in each bit-line pair (this is called charge-sharing).
  • At this time, since the connection node N1 maintains a voltage level identical to that of the internal core voltage Vcore, the over-driver off signal over_off is in a logic low state.
  • Then, if the over-driving startup signal over_on is actuated to a logic high state (simultaneously, the signal SAP is also activated to a logic low state although it is not shown), the over-driving control signal over_ctr is enabled to a logic low state, making the over-driver PM1 turned-on and, as a result, the level of the connection node voltage VN1 starts to ascend. That is, the power line RTO of the bit-line sense amplifier is driven by the ascending connection node voltage VN1.
  • In the meantime, if the connection node voltage VN1 continuously ascends to a level higher than the reference voltage Vref, the voltage level detecting sector 42 detects it and, thus, the over-driver off signal over_off is activated to a logic high state. Furthermore, the over-driving control signal over_ctr is inactivated to a logic high state. If the over-driving control signal over_ctr is disabled, the over-driver PM1 is turned-off and the power line RTO of the bit-line sense amplifier is driven by the internal core voltage Vcore.
  • After then, the processes of bit-line sensing and amplification, and restoring are performed and, sequentially, the word-line is inactivated.
  • As described above, in accordance with the present invention, the over-driving period is decided by sensing the voltage level of the connection node N1. Since the over-driving period is varied by the fluctuation of memory environment, manufacturing processes and so on, the inventive device determines the over-driving period by considering the above factors and, thus, it is possible to maintain an optimized over-driving period without a separate test process or repeated modifications for a metal layer.
  • Although the voltage level detecting sector 42 is implemented with an NMOS type differential amplifier in accordance with the preferred embodiment of the present invention, it can be implemented with a PMOS type differential amplifier in accordance with another embodiment.
  • In addition, the present invention is applicable when the pulse generating sector 43 is implemented with other logic gates instead of the NAND gates shown in FIG. 4.
  • By determining an optimized over-driving period through the use of the present invention, it is possible to have advantages of improving the operating performance of the semiconductor memory device, and not requiring separate test processes or repeated modifications for the metal layer, resulting in reducing manufacturing cost and time.
  • Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (6)

1. A semiconductor memory device comprising:
a first power supplying means for providing a normal voltage;
a first driving means for driving a power line of a bit-line amplifier with a voltage on a connection node attached to the first power supplying means;
a second driving means for driving the connection node with a voltage higher than the normal voltage; and
a control means for generating an over-driving control signal, which controls the second driving means by detecting a level of the voltage on the connection node to that of a preset reference voltage.
2. The semiconductor memory device as recited in claim 1, wherein the control means includes:
a reference voltage generating means for producing the reference voltage;
a voltage level detecting means for comparing the level of the voltage on the connection node with that of the reference voltage and outputting a comparison result signal under the control of an over-driving startup signal; and
a pulse generating means for outputting the over-driving control signal, which is a pulse signal activated during an over-driving period in response to the over-driving startup signal and the comparison result signal outputted from the voltage level detecting means.
3. The semiconductor memory device as recited in claim 2, wherein the voltage level detecting means has:
a current source transistor whose gate is coupled with the over-driving startup signal;
a differential input transistor unit, connected to the current source transistor, for receiving the reference voltage and the voltage on the connection node as differential inputs;
a current mirror connected to the differential input transistor unit; and
an inverter attached to an output node of the current mirror.
4. The semiconductor memory device as recited in claim 3, wherein the pulse generating means has:
a first NAND gate receiving the over-driving startup signal and an output signal of the inverter as inputs; and
a second NAND gate receiving the over-driving startup signal and an output signal of the first NAND gate as inputs.
5. The semiconductor memory device as recited in claim 2, wherein the reference voltage generating means contains a voltage divider connected between a ground voltage and a voltage higher than the normal voltage.
6. The semiconductor memory device as recited in claim 1, wherein the normal voltage is an internal core voltage and the voltage higher than the normal voltage is an external power voltage.
US10/737,546 2003-07-15 2003-12-15 Semiconductor memory device having over-driving scheme Expired - Fee Related US6853593B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030048253A KR100541367B1 (en) 2003-07-15 2003-07-15 Semiconductor device having over driving scheme
KR2003-48253 2003-07-15

Publications (2)

Publication Number Publication Date
US20050013175A1 true US20050013175A1 (en) 2005-01-20
US6853593B1 US6853593B1 (en) 2005-02-08

Family

ID=34056854

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/737,546 Expired - Fee Related US6853593B1 (en) 2003-07-15 2003-12-15 Semiconductor memory device having over-driving scheme

Country Status (2)

Country Link
US (1) US6853593B1 (en)
KR (1) KR100541367B1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060245284A1 (en) * 2005-04-30 2006-11-02 Hynix Semiconductor Inc. Semiconductor memory device
US20080002501A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Over driving pulse generator
US20080191748A1 (en) * 2007-02-09 2008-08-14 Hynix Semiconductor Inc. Apparatus for supplying overdriving signal
US20080298141A1 (en) * 2005-09-29 2008-12-04 Hynix Semiconductor Inc. Bit line control circuit for semiconductor memory device
US20090296508A1 (en) * 2006-02-28 2009-12-03 Hynix Semiconductor Inc. Semiconductor memory apparatus
US8687447B2 (en) 2009-09-30 2014-04-01 SK Hynix Inc. Semiconductor memory apparatus and test method using the same
TWI452573B (en) * 2007-12-20 2014-09-11 Hynix Semiconductor Inc Circuit providing compensated power for sense amplifier and driving method thereof
TWI584302B (en) * 2016-08-15 2017-05-21 円星科技股份有限公司 Control device for semiconductor memory
US11735264B2 (en) 2018-11-20 2023-08-22 National University Corporation Shizuoka University Drive circuit and electronic device

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604660B1 (en) * 2004-04-30 2006-07-26 주식회사 하이닉스반도체 Semiconductor memory device controlled drivability of over-driver
KR100695524B1 (en) * 2004-05-06 2007-03-15 주식회사 하이닉스반도체 Semiconductor memory device and operation method thereof
KR100743623B1 (en) * 2004-12-22 2007-07-27 주식회사 하이닉스반도체 Controller for driving current of semiconductor device
KR100571648B1 (en) * 2005-03-31 2006-04-17 주식회사 하이닉스반도체 Over driver control signal generator in semiconductor memory device
KR100586557B1 (en) * 2005-04-01 2006-06-08 주식회사 하이닉스반도체 Sense amplifier overdriving circuit and semiconductor device
US7599243B2 (en) * 2005-09-28 2009-10-06 Hynix Semiconductor, Inc. Sense amplifier over driver control circuit and method for controlling sense amplifier of semiconductor device
US7447100B2 (en) 2005-09-29 2008-11-04 Hynix Semiconductor Inc. Over-driving circuit for semiconductor memory device
KR100798765B1 (en) * 2005-09-29 2008-01-29 주식회사 하이닉스반도체 Over-driving SCHEME OF SEMICONDUCTOR MEMORY DEVICE
US7701786B2 (en) * 2005-09-29 2010-04-20 Hynix Semiconductor, Inc. Semiconductor memory device
US7505297B2 (en) * 2005-09-29 2009-03-17 Hynix Semiconductor, Inc. Semiconductor memory device
KR100798736B1 (en) * 2005-09-29 2008-01-29 주식회사 하이닉스반도체 Semiconductor memory device
US7583547B2 (en) 2005-09-29 2009-09-01 Hynix Semiconductor, Inc. Over-driving circuit in semiconductor memory device
US7532530B2 (en) * 2005-09-29 2009-05-12 Hynix Semiconductor, Inc. Semiconductor memory device
JP2007207404A (en) * 2006-02-06 2007-08-16 Elpida Memory Inc Over-drive writing method, write amplifier power supply generating circuit, and semiconductor storage device furnished therewith
KR100738959B1 (en) 2006-02-09 2007-07-12 주식회사 하이닉스반도체 Circuit and method for supplying voltage source of sense amplifier in semiconductor memory apparatus
US7957213B2 (en) 2006-02-09 2011-06-07 Hynix Semiconductor, Inc. Semiconductor memory apparatus
KR100761381B1 (en) * 2006-09-06 2007-09-27 주식회사 하이닉스반도체 Memory device that can detect bit line sense amp mismatch
KR100772701B1 (en) * 2006-09-28 2007-11-02 주식회사 하이닉스반도체 Semiconductor memory device
US7573777B2 (en) * 2006-10-02 2009-08-11 Hynix Semiconductor Inc. Over driver control signal generator in semiconductor memory device
KR100780641B1 (en) * 2006-10-02 2007-11-30 주식회사 하이닉스반도체 Semiconductor memory device having double over driver
KR20080065100A (en) * 2007-01-08 2008-07-11 주식회사 하이닉스반도체 Semiconductor memory device and operation method thereof
KR100889320B1 (en) 2007-03-05 2009-03-18 주식회사 하이닉스반도체 Semiconductor memory device
KR100849074B1 (en) * 2007-09-10 2008-07-30 주식회사 하이닉스반도체 Semiconductor memory device
US8014214B2 (en) * 2007-11-08 2011-09-06 Hynix Semiconductor Inc. Semiconductor memory device
KR101097444B1 (en) * 2009-12-29 2011-12-23 주식회사 하이닉스반도체 Internal voltage generator and method of generating internal voltage
US9715905B2 (en) * 2015-08-12 2017-07-25 International Business Machines Corporation Detecting maximum voltage between multiple power supplies for memory testing

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315556A (en) * 1991-03-20 1994-05-24 Fujitsu Limited Semiconductor memory having improved sense amplifier
US5526322A (en) * 1994-09-23 1996-06-11 Xilinx, Inc. Low-power memory device with accelerated sense amplifiers
US5544110A (en) * 1994-02-16 1996-08-06 Hyundai Electronics Industries Co. Ltd. Sense amplifier for semiconductor memory device having pull-up and pull-down driving circuits controlled by a power supply voltage detection circuitry
US5841706A (en) * 1996-02-28 1998-11-24 Nec Corporation Semiconductor memory device capable of high speed operation in low power supply voltage
US6115316A (en) * 1998-06-29 2000-09-05 Fujitsu Limited Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
US6304494B1 (en) * 1999-09-10 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with decreased power consumption
US20010048625A1 (en) * 2000-05-25 2001-12-06 Robert Patti Dynamically configurated storage array with improved data access
US6347058B1 (en) * 2000-05-19 2002-02-12 International Business Machines Corporation Sense amplifier with overdrive and regulated bitline voltage
US6487133B2 (en) * 2000-07-05 2002-11-26 Kabushiki Kaisha Toshiba Semiconductor device
US6741514B2 (en) * 2000-11-09 2004-05-25 Fujitsu Limited Semiconductor memory device and method of controlling the same
US6754122B2 (en) * 2002-02-05 2004-06-22 Kabushiki Kaisha Toshiba Semiconductor memory device having overdriven bit-line sense amplifiers

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315556A (en) * 1991-03-20 1994-05-24 Fujitsu Limited Semiconductor memory having improved sense amplifier
US5544110A (en) * 1994-02-16 1996-08-06 Hyundai Electronics Industries Co. Ltd. Sense amplifier for semiconductor memory device having pull-up and pull-down driving circuits controlled by a power supply voltage detection circuitry
US5526322A (en) * 1994-09-23 1996-06-11 Xilinx, Inc. Low-power memory device with accelerated sense amplifiers
US5841706A (en) * 1996-02-28 1998-11-24 Nec Corporation Semiconductor memory device capable of high speed operation in low power supply voltage
US6115316A (en) * 1998-06-29 2000-09-05 Fujitsu Limited Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
US6304494B1 (en) * 1999-09-10 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with decreased power consumption
US6347058B1 (en) * 2000-05-19 2002-02-12 International Business Machines Corporation Sense amplifier with overdrive and regulated bitline voltage
US20010048625A1 (en) * 2000-05-25 2001-12-06 Robert Patti Dynamically configurated storage array with improved data access
US6487133B2 (en) * 2000-07-05 2002-11-26 Kabushiki Kaisha Toshiba Semiconductor device
US6741514B2 (en) * 2000-11-09 2004-05-25 Fujitsu Limited Semiconductor memory device and method of controlling the same
US6754122B2 (en) * 2002-02-05 2004-06-22 Kabushiki Kaisha Toshiba Semiconductor memory device having overdriven bit-line sense amplifiers

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060245284A1 (en) * 2005-04-30 2006-11-02 Hynix Semiconductor Inc. Semiconductor memory device
US7450448B2 (en) 2005-04-30 2008-11-11 Hynix Semiconductor Inc. Semiconductor memory device
US20080298141A1 (en) * 2005-09-29 2008-12-04 Hynix Semiconductor Inc. Bit line control circuit for semiconductor memory device
US7800962B2 (en) 2005-09-29 2010-09-21 Hynix Semiconductor Inc. Bit line control circuit for semiconductor memory device
US20090296508A1 (en) * 2006-02-28 2009-12-03 Hynix Semiconductor Inc. Semiconductor memory apparatus
US7869295B2 (en) * 2006-02-28 2011-01-11 Hynix Semiconductor Inc. Semiconductor memory apparatus
US7567469B2 (en) * 2006-06-29 2009-07-28 Hynix Semiconductor Inc. Over driving pulse generator
US20080002501A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Over driving pulse generator
US20080191748A1 (en) * 2007-02-09 2008-08-14 Hynix Semiconductor Inc. Apparatus for supplying overdriving signal
US7800424B2 (en) 2007-02-09 2010-09-21 Hynix Semiconductor Inc. Apparatus for supplying overdriving signal
TWI452573B (en) * 2007-12-20 2014-09-11 Hynix Semiconductor Inc Circuit providing compensated power for sense amplifier and driving method thereof
US8687447B2 (en) 2009-09-30 2014-04-01 SK Hynix Inc. Semiconductor memory apparatus and test method using the same
TWI584302B (en) * 2016-08-15 2017-05-21 円星科技股份有限公司 Control device for semiconductor memory
US11735264B2 (en) 2018-11-20 2023-08-22 National University Corporation Shizuoka University Drive circuit and electronic device

Also Published As

Publication number Publication date
KR100541367B1 (en) 2006-01-11
KR20050009012A (en) 2005-01-24
US6853593B1 (en) 2005-02-08

Similar Documents

Publication Publication Date Title
US6853593B1 (en) Semiconductor memory device having over-driving scheme
US6754121B2 (en) Sense amplifying circuit and method
US7843755B2 (en) Circuit and method for controlling sense amplifier of semiconductor memory apparatus
US6226215B1 (en) Semiconductor memory device having reduced data access time and improve speed
JP5197241B2 (en) Semiconductor device
US7298660B2 (en) Bit line sense amplifier control circuit
US7020043B1 (en) Semiconductor memory device
US7196965B2 (en) Over driving control signal generator in semiconductor memory device
US7023749B2 (en) Semiconductor integrated circuit device
US20080159045A1 (en) Semiconductor memory device capable of controlling drivability of overdriver
US20190206482A1 (en) Semiconductor device
JP2006309916A (en) Semiconductor memory device and method for driving bit line sensing amplifier of the same
US6791897B2 (en) Word line driving circuit
US7349274B2 (en) Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same
US6236605B1 (en) Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier
KR20050023537A (en) Semiconductor memory device having VSS/VDD bitline precharge scheme without reference cell
US7649790B2 (en) Semiconductor memory device
KR100438237B1 (en) Semiconductor integrated circuit having test circuit
KR100780633B1 (en) Over driver control signal generator in semiconductor memory device
US5777934A (en) Semiconductor memory device with variable plate voltage generator
US7573777B2 (en) Over driver control signal generator in semiconductor memory device
US20080080273A1 (en) Over-drive control signal generator for use in semiconductor memory device
GB2314951A (en) DRAM sense amplifier arrays
KR100695287B1 (en) Control Circuit for Sense Amplifier of Semiconductor Memory Apparatus
KR100780641B1 (en) Semiconductor memory device having double over driver

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BAE, SEUNG-CHEOL;REEL/FRAME:014809/0551

Effective date: 20031209

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20170208