US20040212036A1 - Method of eliminating residual carbon from flowable oxide fill - Google Patents

Method of eliminating residual carbon from flowable oxide fill Download PDF

Info

Publication number
US20040212036A1
US20040212036A1 US10/853,063 US85306304A US2004212036A1 US 20040212036 A1 US20040212036 A1 US 20040212036A1 US 85306304 A US85306304 A US 85306304A US 2004212036 A1 US2004212036 A1 US 2004212036A1
Authority
US
United States
Prior art keywords
oxide
substrate
fill
oxygen plasma
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/853,063
Inventor
Li Li
Weimin Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US10/853,063 priority Critical patent/US20040212036A1/en
Publication of US20040212036A1 publication Critical patent/US20040212036A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Definitions

  • the invention relates generally to semiconductor processing methods of forming and utilizing insulative materials for electrical isolation in integrated circuits, and more particularly to a post-deposition treatment of flowable oxide fill materials to eliminate residual carbon from the material.
  • Insulative materials are widely used in semiconductor fabrication methods for forming structures to electrically isolate the various active components formed in integrated circuits.
  • Devices that extend into a semiconductive substrate can be electrically isolated by insulative materials formed within the substrate between the components, for example, trench isolation regions.
  • trenches are etched into a silicon substrate, usually by anisotropic etching, and the trenches are subsequently filled by the deposition of an oxide such as silicon dioxide (SiO 2 ).
  • An oxide is often deposited by chemical vapor deposition (CVD) as a conformal layer of SiO 2 .
  • CVD chemical vapor deposition
  • the conformal layers of oxide are initially formed on the sidewalls and grow in size outward into the center of the trench to where the oxide layers meet.
  • such techniques can result in voids formed in the oxide fill, which impair the isolation capability of the trench.
  • flowable oxides have been developed that provide good gapfill properties.
  • One such flowable oxide that has been employed is formed by depositing trimethylsilane ((CH 3 ) 3 SiH) (TMS) and ozone (O 3 ) by CVD to fill the gap and eliminate void formation.
  • TMS trimethylsilane
  • O 3 ozone
  • the presence of residual carbon from the hydrocarbon portion of the precursor provides a high carbon content in the oxide material that causes the fill to be soft and unstable to various processes such as wet etches, resulting in device degradation.
  • the present invention provides methods of forming and treating insulative materials, and semiconductor devices and systems incorporating the insulative materials.
  • the invention provides a method of treating a carbon-containing oxide layer disposed on a semiconductive substrate, for example, in a trench or other opening in the substrate, by exposing the oxide layer to an oxygen plasma to eliminate a substantial amount of carbon from the oxide layer.
  • the oxygen plasma can be formed in the reaction chamber or remotely in a downstream plasma system and then flowed into the chamber.
  • the post-deposition oxygen plasma treatment preferably reduces the carbon in the oxide layer to a non-detectable level, and preferably to about 5% or less.
  • the post-deposition oxygen plasma treatment can be used in a method of forming an oxide layer on a semiconductor substrate.
  • the method comprises depositing a layer of a carbon-containing flowable oxide on the substrate by chemical vapor deposition of an organosilane (e.g., trimethylsilane) and an oxygen source gas (e.g., ozone), and conducting an oxygen plasma treatment according to the invention to reduce or eliminate carbon from the oxide layer, preferably to a non-detectable level.
  • an organosilane e.g., trimethylsilane
  • an oxygen source gas e.g., ozone
  • the flowable oxide material can be deposited to substantially fill high aspect ratio gaps or openings (e.g., a trench) without leaving voids, and the oxygen plasma treatment is then conducted to reduce the carbon content of the fill material to a desired level, preferably to about 5% or less.
  • the method comprises forming a flowable oxide on a substrate, for example, by spin-coating or flow coating, and then exposing the carbon-containing oxide material to an oxygen plasma in accordance with the invention to drive out a substantial amount of the carbon from the oxide layer.
  • the method of the invention comprises depositing an oxide material into a high aspect ratio opening such as a deep trench with a flowable oxide material to partially fill the opening (e.g., about one-half of the depth), and then depositing oxide material by high density plasma chemical vapor deposition (HDPCVD) to fill the rest of the opening.
  • a high aspect ratio opening such as a deep trench with a flowable oxide material to partially fill the opening (e.g., about one-half of the depth)
  • HDPCVD high density plasma chemical vapor deposition
  • the invention provides an oxide fill disposed on a semiconductor substrate, which comprises a flowable oxide material treated with an oxygen plasma such that carbon in the oxide material is substantially reduced, preferably to a non-detectable level.
  • the oxygen plasma-treated oxide material contains substantially no voids and has a carbon content of about 5% or less.
  • the oxide fill can be disposed, for example, within a high aspect ratio opening such as a deep trench in a semiconductor substrate.
  • the oxide fill material can be formed on the substrate as a flowable oxide by chemical vapor deposition of an organosilane (e.g., trimethylsilane) and an oxygen source gas (e.g., ozone), or, in another embodiment, by a liquid application process such as a spin-on technique of a flowable oxide material.
  • the oxygen plasma-treated oxide fill can comprise a portion of a flowable oxide material and another portion of high density plasma oxide.
  • a semiconductor device comprising a substrate and an oxygen plasma-treated flowable oxide layer, the oxide layer preferably having a carbon content of about 5% or less.
  • the oxide layer can comprise a trench isolation structure, for example.
  • the oxide layer comprises chemical vapor deposited trimethylsilane and ozone.
  • the invention provides an integrated circuit device.
  • the integrated circuit device supported by a substrate comprises an oxide layer disposed on the substrate, for example, as a fill within an opening such as a trench, the oxide layer comprising an oxygen plasma-treated flowable oxide (e.g., formed by chemical vapor deposition of trimethylsilane and ozone), the oxide layer preferably having a carbon content of about 5% or less.
  • the integrated circuit device comprising the oxygen plasma-treated oxide layer can be incorporated into a die of a circuit module, for example, which can be incorporated into an electronic system.
  • the invention advantageously provides a method of readily eliminating carbon from a void-free, flowable oxide material formed in high aspect ratio openings, for example.
  • the post-deposition plasma treatment can be conducted within the same process chamber as the deposition process.
  • the process in accordance with the invention achieves a solid, void-free oxide fill having a reduced level of carbon that can be easily processed and will maintain its integrity in subsequent processing steps.
  • FIGS. 1-4 are diagrammatic cross-sectional views of a fragment of a semiconductor wafer substrate at sequential processing steps showing fabrication of a trench isolation according to an embodiment of the method of the invention.
  • FIG. 1 illustrates a processing step forming a trench in a surface of the substrate.
  • FIG. 2 shows deposition of an oxide layer into the trench.
  • FIG. 3 depicts an oxygen plasma treatment of the oxide layer.
  • FIG. 4 illustrates a processing step to remove excess material formed above the surface of the substrate.
  • FIG. 5-7 are diagrammatic cross-sectional views of a fragment of a semiconductor wafer substrate at sequential processing steps showing fabrication of a trench isolation according to another embodiment of the method of the invention.
  • FIG. 5 shows formation of a flowable oxide layer in a portion of the trench.
  • FIG. 6 depicts formation of an overlying high density plasma oxide layer.
  • FIG. 7 depicts an oxygen plasma treatment of the oxide fill within the trench.
  • FIG. 8 is a block diagram of a circuit module according to an embodiment of the present invention.
  • the terms “semiconductive substrate”, “semiconductor substrate”, wafer fragment” or “wafer” will be understood to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • the invention provides methods for forming a void-free flowable oxide layer in a semiconductor substrate and substantially eliminating carbon from the fill material.
  • the present invention addresses and solves problems of flowable oxide fill materials that contain high levels of carbon, particularly those formed from TMS and ozone, which are used, for example, as trench isolations, by treating the oxide fill material with an oxygen (O 2 ) plasma to drive out carbon from the material.
  • an oxygen (O 2 ) plasma to drive out carbon from the material.
  • FIGS. 1-4 illustrate steps in an embodiment of a method of the invention for fabricating an insulative layer for a trench isolation feature in a semiconductive substrate.
  • Other semiconductor structures than isolation trenches can also benefit from the gap filling layer of the invention.
  • the method is not limited to the specific illustrated embodiment and has broad application to a variety of applications in IC fabrication for shallow trench isolations (STI), gate spacers, spacers between wordlines, buried digit line spacers, among others.
  • STI shallow trench isolations
  • gate spacers spacers between wordlines
  • buried digit line spacers among others.
  • an exemplary semiconductor wafer fragment is indicated generally with reference numeral 10 .
  • the substrate 12 can comprise a semiconductive material such as monocrystalline silicon, polycrystalline silicon, germanium, or gallium arsenide, or epitaxial layers of silicon support by a base semiconductor foundation, for example, or an insulating layer if silicon-on-insulator (S-O-I) or a similar technology is used.
  • S-O-I silicon-on-insulator
  • the insulator may be sapphire.
  • the process of the present invention has broad application to a wide variety of substrates 12 .
  • trenches 14 have been formed into the semiconductive substrate 12 .
  • the trenches can be formed by patterning and etching the substrate around active areas of the wafer such as transistor active areas, according to known techniques.
  • the trenches 14 include a bottom surface 16 and sidewalls 18 .
  • an oxide isolation structure 20 is then formed in the trenches 14 by chemical vapor deposition (CVD) of an oxygen source gas and a carbon-substituted silane precursor gas (organosilane) to form a material having a liquid or flowable consistency that fills the trench.
  • CVD chemical vapor deposition
  • organosilanes include, for example, methylsilane (CH 3 SiH 3 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), trimethylsilane ((CH 3 ) 3 SiH) (TMS), tetramethylsilane ((CH 3 ) 4 Si), diethylsilane ((C 2 H 5 ) 2 SiH 2 ) (DES), and Si x C y H z where x is 1-2, y is 1-6, and z is 4-20), being TMS in the illustrated example.
  • oxygen source gases for reaction with the organosilane include ozone (O 3 ), hydrogen peroxide (H 2 O 2 ) vapor, nitrous oxide (N 2 O), and nitric oxide (NO), for example, being ozone (O 3 ) in the illustrated example.
  • O 3 ozone
  • H 2 O 2 hydrogen peroxide
  • N 2 O nitrous oxide
  • NO nitric oxide
  • the liquid nature of the deposited oxide material allows it to grow vertically from the bottom surfaces 16 of the trenches 14 , and fill the trench volume as a homogenous filler material without voids or minimal void formation.
  • the trenches 14 are filled by reacting TMS with O 3 in vapor form within a CVD reaction chamber.
  • the wafer is heated and a chemical reaction of the precursor gases occurs.
  • Typical deposition process parameters include a chamber pressure maintained at about 50 to about 500 torr, preferably about 300 torr, and a substrate temperature of up to about 800° C., preferably about 20 to about 450° C., preferably about 50 to about 200° C., and more preferably at about 125° C.
  • TMS and O 3 are flowed into the reaction chamber, and the TMS and O 3 react and gases condense onto the bottom surfaces 16 of the trenches to form a layer of flowable silicon dioxide material, such as layer 20 shown in FIG. 2, incorporating carbon in the form of methyl groups (CH 3 ).
  • a carrier gas e.g., argon, helium, etc.
  • the flowable oxide material fills the trenches from the bottom surface up to the top of the trench, thereby avoiding forming voids in the center of the fill.
  • the oxide fill layer 20 is then treated with an oxygen plasma (indicated by arrows 22 ) effective to drive carbon out of the fill material.
  • the oxygen plasma can be produced by flowing oxygen into a plasma generated within the reaction chamber or, in another embodiment of a deposition process, the plasma can be produced remotely from the chamber (i.e., not in the chamber) in a downstream plasma system according to known techniques.
  • downstream plasma system it is meant that a plasma is generated and used to treat a compound and create reactive constituents in a particular location and then the reactive constituents are transported downstream to another location before being used as desired, generally by acting on a target.
  • a downstream plasma system (not shown) includes a plasma chamber in flow communication by way of a conduit with the reaction chamber.
  • the oxygen gas can be dissociated, transported downstream, and introduced into the reaction chamber to react with the flowable oxide layer 20 .
  • the post-deposition oxygen plasma treatment of the invention can be conducted in the same reaction chamber subsequent to the oxide deposition whereby feeding the reactive gases (TMS and ozone) is ceased and a feed of oxygen (O 2 ) into the chamber is commenced while providing plasma conditions (or a remote plasma source is flowed into the chamber).
  • Oxygen can be flowed into the plasma-containing chamber at a rate of about 1 to about 10,000 sccm, typically at a rate of about 1,000 sccm, while an RF power of about 100 to about 5,000 watts is applied, with 1,000 watts being preferred.
  • the oxygen can be flowed together with a carrier gas such as helium, etc.
  • the oxide layer 20 is exposed to the oxygen plasma for a time effective to substantially eliminate carbon from the fill layer 20 , preferably to a non-detectable level.
  • the dissociated oxygen species diffuses into the layer 20 and reacts with carbon to form volatile byproducts (e.g., CO, CO 2 ).
  • the duration of the oxygen plasma treatment can range from about 1 to about 2 seconds to up to about 100 to about 1,000 seconds or longer, generally depending on the thickness of the oxide layer 20 and wafer temperature, an extended time period being preferred to sufficiently lower the carbon content of the oxide layer to the desired level. Elevating the temperature of the wafer can accelerate the removal of carbon from the fill material.
  • the oxygen plasma treatment is applied for at least about 10 seconds, preferably at least about 100 seconds, at a wafer temperature of up to about 800° C., preferably about 20 to about 450° C., preferably about 50 to about 200° C., and a reaction chamber pressure of about 0.1 to about 20 torr.
  • the oxygen plasma treatment preferably results in a reduction of the carbon content of the deposited oxide fill layer 20 by at least about 50%, preferably by at least about 80%, preferably by at least about 98%, such that the plasma-treated oxide layer has a carbon content of about 10% or less, preferably about 5% or less, preferably about 2% or less.
  • Further processing can be conducted, including stripping off excess of the oxide fill material and masking layers formed above the surface of the substrate, for example, using a known chemical mechanical polishing (CMP) technique, or other technique such as wet etching and/or dry etching.
  • CMP chemical mechanical polishing
  • the process according to the invention advantageously results in a substantial reduction in carbon from the fill layer 20 and also offers the advantage of filing a narrow space, e.g., a trench width of about 0.06 ⁇ m, for example, and gaps having a high aspect ratio from about 7:1 to about 10:1, for example.
  • the present application describes a method of treating oxide fill materials by contacting the fill with an oxygen plasma to substantially eliminate carbon therefrom. While illustrated in the context of removing carbon from a flowable oxide material deposited in a trench of a semiconductor substrate by CVD of TMS and oxide, the skilled artisan will recognize many other applications for the methods disclosed herein.
  • the method of the invention can be utilized to reduce the carbon level of flowable SiOC-based oxides deposited from other gases and/or by other processes.
  • Another technique of forming silicon dioxide is referred to as FlowfillTM technology, which has been developed by Trikon Technology of Bristol, U.K., as described in U.S. Pat. No. 6,156,674, and U.S. Pat. Appl. Publ. No. 2002/0098684, for example, the disclosures of which are incorporated by reference herein.
  • FlowfillTM technology has been utilized to form insulative materials comprising (CH 3 ) x SiO (2-y) , wherein y/2 is the percentage of CH 3 incorporated.
  • methylsilane (CH 3 SiH 3 ) (in a gaseous form) and hydrogen peroxide (H 2 O 2 ) (in a liquid form) can be separately introduced into a chamber, such as a parallel plate reaction chamber.
  • a reaction between CH 3 SiH 3 and H 2 O 2 can be moderated by introduction of nitrogen into the reaction chamber.
  • a wafer is provided within the chamber, and ideally maintained at a suitably low temperature, such as 0° C., at an exemplary pressure of about 1 Torr to achieve formation of a methylsilanol structure.
  • a suitably low temperature such as 0° C.
  • the deposited material is in the form of a viscous liquid, which flows to fill small gaps on the wafer surface.
  • surface tension drives the deposited layer flat, thus forming a planarized layer over the substrate.
  • the liquid methylsilanol is converted to a silicon dioxide structure by a two-step process occurring in two separate chambers from that in which the methylsilanol-type structure was deposited.
  • planarization of the liquid film is promoted by increasing the temperature to above 100° C., while maintaining the pressure at about 1 Torr, to result in solidification and formation of a polymer layer.
  • the temperature is raised to approximately 450° C., while maintaining the pressure of about 1 Torr, to form (CH 3 ) x SiO (2-y) .
  • the processing at 450° C. also provides an advantage of driving undesired water from the resultant (CH 3 ) x SiO (2-y) layer.
  • Other techniques of forming a silicon dioxide fill layer include a spin-on process by spin applying a liquid comprising an organosiloxane, by flow coating, or by using a spray technique.
  • the solvent can be removed by baking, leaving a planarized silicon dioxide layer.
  • Other flowable oxide materials are known and used in the art can also benefit from the post-deposition plasma treatment in accordance with the invention.
  • oxide materials include various polyimides, FLARE 2.0TM dielectric (a poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif.), Black-DiamondTM dielectric (available from Applied Materials, Santa Clara, Calif.), BCB (divinylsiloxane bisbenzocyclobutene) and SilkTM, an organic polymer similar to BCB (both available from Dow Chemical Co., Midland, Mich.), among others.
  • FLARE 2.0TM dielectric a poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif.
  • Black-DiamondTM dielectric available from Applied Materials, Santa Clara, Calif.
  • BCB dibenzocyclobutene
  • SilkTM an organic polymer similar to BCB (both available from Dow Chemical Co., Midland, Mich.), among others.
  • Such materials can be applied by various techniques
  • Treatment of the organic carbon-containing oxide materials in accordance with embodiments of the invention employing an oxygen plasma substantially reduces the carbon content of such carbon-containing oxide materials.
  • FIGS. 5-7 illustrate steps in another embodiment of a method in accordance with the invention for forming an oxide fill in an opening in a substrate of a wafer fragment 10 ′.
  • a portion (e.g., about one-half) of a trench 14 ′ disposed in a substrate 12 ′ is filled with an oxide layer 20 ′ comprising a flowable oxide material, as described hereinabove.
  • the remainder of the opening 14 ′ can then be filled with a high density plasma oxide material 24 ′ using a conventional high density plasma chemical vapor deposition (HDPCVD).
  • HDPCVD high density plasma chemical vapor deposition
  • the silicon oxide is deposited in a reaction zone of a HDPCVD reactor while providing a selected bias power, source power and gas mixtures.
  • Exemplary silicon source gases include, for example, silicon tetrachloride (SiCl 4 ), silicon tetrabromide (SiBr 4 ), dichlorosilane (SiH 2 Cl 2 ), and disilane (Si 2 H 6 ).
  • Exemplary gases to react with the silicon source gas include oxygen, ozone, nitrous oxide (N 2 O), and nitric oxide (NO), for example, along with a carrier gas such as argon or helium.
  • FIG. 8 is a block diagram of an embodiment of a circuit module 26 in which the present invention can be incorporated.
  • modules, devices and systems e.g., processor systems
  • incorporating the module are described and illustrated in U.S. Pat. Nos. 6,437,417 (Gilton) and 6,465,829 (Agarwal), the disclosures of which are incorporated by reference herein.
  • two or more dies 28 may be combined into a circuit module 26 to enhance or extend the functionality of an individual die 28 .
  • Circuit module 26 may be a combination of dies 28 representing a variety of functions, or a combination of dies containing the same functionality.
  • One or more dies 28 of the circuit module can contain circuitry, or integrated circuit devices, that includes at least one O 2 plasma-treated flowable oxide layer in accordance with the embodiments of the present invention.
  • the integrated circuit devices can include a memory cell that comprises an oxide layer as discussed in the various embodiments in accordance with the invention.
  • Circuit module 26 may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, among others. Circuit module 26 will have a variety of leads 30 extending therefrom and coupled to the dies 28 providing unilateral or bilateral communication and control.
  • the circuit module can be incorporated, for example, into an electronic system that comprises a user interface, for example, a keyboard, monitor, display, printer, speakers, etc.
  • a user interface for example, a keyboard, monitor, display, printer, speakers, etc.
  • One or more circuit modules can comprise a microprocessor that provides information to the user interface, or is otherwise programmed to carry out particular functions as is known in the art.
  • the electronic system can comprise, for example, a computer system including a processor and a memory system as a subcomponent, and optionally user interface components, and other associated components such as modems, device driver cards, etc.
  • Examples of memory circuits include but are not limited to DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Flash memories, a synchronous DRAM such as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging memory technologies.
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • Flash memories a synchronous DRAM such as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging memory technologies.
  • Carbon-containing oxide films were deposited from TMS and O 3 by a CVD process onto three wafer surfaces.
  • Process parameters included a chamber pressure of about 100 torr and a wafer temperature of about 125° C., utilizing a Centura DxZ CVD deposition chamber from Applied Materials, Inc.
  • results show a significant difference between the average of the bulk atomic concentrations (%) of the oxide layer of the test wafers exposed to the post-deposition treatment and the Control wafer.
  • the results demonstrate that while the untreated Control wafer had an about 30% carbon content, the oxygen plasma post-deposition treatment was successful in eliminating the carbon content of the test wafers to a non-detectable level.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)

Abstract

Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the method, and devices and systems incorporating the oxide material are provided.

Description

    FIELD OF THE INVENTION
  • The invention relates generally to semiconductor processing methods of forming and utilizing insulative materials for electrical isolation in integrated circuits, and more particularly to a post-deposition treatment of flowable oxide fill materials to eliminate residual carbon from the material. [0001]
    • BACKGROUND OF THE INVENTION
  • With advancements in semiconductor integrated circuit technology, device dimensions and component spacing continues to shrink, requiring the devices to be placed in close proximity to each other. Insulative materials are widely used in semiconductor fabrication methods for forming structures to electrically isolate the various active components formed in integrated circuits. Devices that extend into a semiconductive substrate can be electrically isolated by insulative materials formed within the substrate between the components, for example, trench isolation regions. In such a technique, trenches are etched into a silicon substrate, usually by anisotropic etching, and the trenches are subsequently filled by the deposition of an oxide such as silicon dioxide (SiO[0002] 2).
  • An oxide is often deposited by chemical vapor deposition (CVD) as a conformal layer of SiO[0003] 2. In the trenches, the conformal layers of oxide are initially formed on the sidewalls and grow in size outward into the center of the trench to where the oxide layers meet. However, as device dimensions become smaller and trench widths become narrower, such techniques can result in voids formed in the oxide fill, which impair the isolation capability of the trench.
  • In an attempt to eliminate voids in a high aspect ratio trench feature, flowable oxides have been developed that provide good gapfill properties. One such flowable oxide that has been employed is formed by depositing trimethylsilane ((CH[0004] 3)3SiH) (TMS) and ozone (O3) by CVD to fill the gap and eliminate void formation. However, the presence of residual carbon from the hydrocarbon portion of the precursor provides a high carbon content in the oxide material that causes the fill to be soft and unstable to various processes such as wet etches, resulting in device degradation.
  • Attempts to reduce the carbon content in the film have included changing the deposition process by altering the ozone composition, the ozone flow, the ratio of O[0005] 3:TMS flowed into the chamber, and staggering the inflow of gases, for example, first flowing only TMS, then flowing only ozone gas, etc. Although, in some applications, the amount of carbon in the fill was somewhat reduced, it was not completely eliminated from the material.
  • It would be desirable to develop a process for eliminating residual carbon from a flowable insulative film or fill material. [0006]
    • SUMMARY OF THE INVENTION
  • The present invention provides methods of forming and treating insulative materials, and semiconductor devices and systems incorporating the insulative materials. [0007]
  • In one aspect, the invention provides a method of treating a carbon-containing oxide layer disposed on a semiconductive substrate, for example, in a trench or other opening in the substrate, by exposing the oxide layer to an oxygen plasma to eliminate a substantial amount of carbon from the oxide layer. The oxygen plasma can be formed in the reaction chamber or remotely in a downstream plasma system and then flowed into the chamber. The post-deposition oxygen plasma treatment preferably reduces the carbon in the oxide layer to a non-detectable level, and preferably to about 5% or less. [0008]
  • In another aspect, the post-deposition oxygen plasma treatment can be used in a method of forming an oxide layer on a semiconductor substrate. In one embodiment, the method comprises depositing a layer of a carbon-containing flowable oxide on the substrate by chemical vapor deposition of an organosilane (e.g., trimethylsilane) and an oxygen source gas (e.g., ozone), and conducting an oxygen plasma treatment according to the invention to reduce or eliminate carbon from the oxide layer, preferably to a non-detectable level. The flowable oxide material can be deposited to substantially fill high aspect ratio gaps or openings (e.g., a trench) without leaving voids, and the oxygen plasma treatment is then conducted to reduce the carbon content of the fill material to a desired level, preferably to about 5% or less. [0009]
  • In another embodiment, the method comprises forming a flowable oxide on a substrate, for example, by spin-coating or flow coating, and then exposing the carbon-containing oxide material to an oxygen plasma in accordance with the invention to drive out a substantial amount of the carbon from the oxide layer. [0010]
  • In yet another embodiment, the method of the invention comprises depositing an oxide material into a high aspect ratio opening such as a deep trench with a flowable oxide material to partially fill the opening (e.g., about one-half of the depth), and then depositing oxide material by high density plasma chemical vapor deposition (HDPCVD) to fill the rest of the opening. This method advantageously eliminates the formation of voids in the fill that can occur when solely a high density plasma oxide is used to fill a high aspect ratio gap. [0011]
  • In another aspect, the invention provides an oxide fill disposed on a semiconductor substrate, which comprises a flowable oxide material treated with an oxygen plasma such that carbon in the oxide material is substantially reduced, preferably to a non-detectable level. Preferably, the oxygen plasma-treated oxide material contains substantially no voids and has a carbon content of about 5% or less. The oxide fill can be disposed, for example, within a high aspect ratio opening such as a deep trench in a semiconductor substrate. The oxide fill material can be formed on the substrate as a flowable oxide by chemical vapor deposition of an organosilane (e.g., trimethylsilane) and an oxygen source gas (e.g., ozone), or, in another embodiment, by a liquid application process such as a spin-on technique of a flowable oxide material. In another embodiment, the oxygen plasma-treated oxide fill can comprise a portion of a flowable oxide material and another portion of high density plasma oxide. [0012]
  • Also provided according to the invention is a semiconductor device comprising a substrate and an oxygen plasma-treated flowable oxide layer, the oxide layer preferably having a carbon content of about 5% or less. The oxide layer can comprise a trench isolation structure, for example. In one embodiment, the oxide layer comprises chemical vapor deposited trimethylsilane and ozone. [0013]
  • In yet another aspect, the invention provides an integrated circuit device. In one embodiment, the integrated circuit device supported by a substrate, comprises an oxide layer disposed on the substrate, for example, as a fill within an opening such as a trench, the oxide layer comprising an oxygen plasma-treated flowable oxide (e.g., formed by chemical vapor deposition of trimethylsilane and ozone), the oxide layer preferably having a carbon content of about 5% or less. The integrated circuit device comprising the oxygen plasma-treated oxide layer can be incorporated into a die of a circuit module, for example, which can be incorporated into an electronic system. [0014]
  • The invention advantageously provides a method of readily eliminating carbon from a void-free, flowable oxide material formed in high aspect ratio openings, for example. The post-deposition plasma treatment can be conducted within the same process chamber as the deposition process. The process in accordance with the invention achieves a solid, void-free oxide fill having a reduced level of carbon that can be easily processed and will maintain its integrity in subsequent processing steps.[0015]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, the reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts. [0016]
  • FIGS. 1-4 are diagrammatic cross-sectional views of a fragment of a semiconductor wafer substrate at sequential processing steps showing fabrication of a trench isolation according to an embodiment of the method of the invention. FIG. 1 illustrates a processing step forming a trench in a surface of the substrate. FIG. 2 shows deposition of an oxide layer into the trench. FIG. 3 depicts an oxygen plasma treatment of the oxide layer. FIG. 4 illustrates a processing step to remove excess material formed above the surface of the substrate. [0017]
  • FIG. 5-7 are diagrammatic cross-sectional views of a fragment of a semiconductor wafer substrate at sequential processing steps showing fabrication of a trench isolation according to another embodiment of the method of the invention. FIG. 5 shows formation of a flowable oxide layer in a portion of the trench. FIG. 6 depicts formation of an overlying high density plasma oxide layer. FIG. 7 depicts an oxygen plasma treatment of the oxide fill within the trench. [0018]
  • FIG. 8 is a block diagram of a circuit module according to an embodiment of the present invention. [0019]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The invention will be described generally with reference to the drawings for the purpose of illustrating the present preferred embodiments only and not for purposes of limiting the same. The figures illustrate processing steps for fabricating an insulative fill in a high aspect ratio opening in a semiconductor substrate in accordance with the present invention. It should be readily apparent that the processing steps are only a portion of the entire fabrication process. [0020]
  • In the current application, the terms “semiconductive substrate”, “semiconductor substrate”, wafer fragment” or “wafer” will be understood to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. [0021]
  • The invention provides methods for forming a void-free flowable oxide layer in a semiconductor substrate and substantially eliminating carbon from the fill material. [0022]
  • The present invention addresses and solves problems of flowable oxide fill materials that contain high levels of carbon, particularly those formed from TMS and ozone, which are used, for example, as trench isolations, by treating the oxide fill material with an oxygen (O[0023] 2) plasma to drive out carbon from the material.
  • FIGS. 1-4 illustrate steps in an embodiment of a method of the invention for fabricating an insulative layer for a trench isolation feature in a semiconductive substrate. Other semiconductor structures than isolation trenches can also benefit from the gap filling layer of the invention. Thus, the method is not limited to the specific illustrated embodiment and has broad application to a variety of applications in IC fabrication for shallow trench isolations (STI), gate spacers, spacers between wordlines, buried digit line spacers, among others. [0024]
  • Referring to FIG. 1, an exemplary semiconductor wafer fragment is indicated generally with [0025] reference numeral 10. The substrate 12 can comprise a semiconductive material such as monocrystalline silicon, polycrystalline silicon, germanium, or gallium arsenide, or epitaxial layers of silicon support by a base semiconductor foundation, for example, or an insulating layer if silicon-on-insulator (S-O-I) or a similar technology is used. For example, in the case of a silicon-on-sapphire (S-O-S) substrate, the insulator may be sapphire. The process of the present invention has broad application to a wide variety of substrates 12.
  • As shown, [0026] trenches 14 have been formed into the semiconductive substrate 12. The trenches can be formed by patterning and etching the substrate around active areas of the wafer such as transistor active areas, according to known techniques. The trenches 14 include a bottom surface 16 and sidewalls 18.
  • In one embodiment, an [0027] oxide isolation structure 20 is then formed in the trenches 14 by chemical vapor deposition (CVD) of an oxygen source gas and a carbon-substituted silane precursor gas (organosilane) to form a material having a liquid or flowable consistency that fills the trench. Exemplary organosilanes include, for example, methylsilane (CH3SiH3), dimethylsilane ((CH3)2SiH2), trimethylsilane ((CH3)3SiH) (TMS), tetramethylsilane ((CH3)4Si), diethylsilane ((C2H5)2SiH2) (DES), and SixCyHz where x is 1-2, y is 1-6, and z is 4-20), being TMS in the illustrated example. Exemplary oxygen source gases for reaction with the organosilane include ozone (O3), hydrogen peroxide (H2O2) vapor, nitrous oxide (N2O), and nitric oxide (NO), for example, being ozone (O3) in the illustrated example. The liquid nature of the deposited oxide material allows it to grow vertically from the bottom surfaces 16 of the trenches 14, and fill the trench volume as a homogenous filler material without voids or minimal void formation.
  • In one embodiment according to the invention, the [0028] trenches 14 are filled by reacting TMS with O3 in vapor form within a CVD reaction chamber. In the reaction chamber, the wafer is heated and a chemical reaction of the precursor gases occurs. Typical deposition process parameters include a chamber pressure maintained at about 50 to about 500 torr, preferably about 300 torr, and a substrate temperature of up to about 800° C., preferably about 20 to about 450° C., preferably about 50 to about 200° C., and more preferably at about 125° C. TMS and O3, and optionally a carrier gas (e.g., argon, helium, etc.), are flowed into the reaction chamber, and the TMS and O3 react and gases condense onto the bottom surfaces 16 of the trenches to form a layer of flowable silicon dioxide material, such as layer 20 shown in FIG. 2, incorporating carbon in the form of methyl groups (CH3). The flowable oxide material fills the trenches from the bottom surface up to the top of the trench, thereby avoiding forming voids in the center of the fill.
  • Referring now to FIG. 3, the [0029] oxide fill layer 20 is then treated with an oxygen plasma (indicated by arrows 22) effective to drive carbon out of the fill material. The oxygen plasma can be produced by flowing oxygen into a plasma generated within the reaction chamber or, in another embodiment of a deposition process, the plasma can be produced remotely from the chamber (i.e., not in the chamber) in a downstream plasma system according to known techniques. By downstream plasma system, it is meant that a plasma is generated and used to treat a compound and create reactive constituents in a particular location and then the reactive constituents are transported downstream to another location before being used as desired, generally by acting on a target. Typically, a downstream plasma system (not shown) includes a plasma chamber in flow communication by way of a conduit with the reaction chamber. Using a plasma system, the oxygen gas can be dissociated, transported downstream, and introduced into the reaction chamber to react with the flowable oxide layer 20.
  • The post-deposition oxygen plasma treatment of the invention can be conducted in the same reaction chamber subsequent to the oxide deposition whereby feeding the reactive gases (TMS and ozone) is ceased and a feed of oxygen (O[0030] 2) into the chamber is commenced while providing plasma conditions (or a remote plasma source is flowed into the chamber). Oxygen can be flowed into the plasma-containing chamber at a rate of about 1 to about 10,000 sccm, typically at a rate of about 1,000 sccm, while an RF power of about 100 to about 5,000 watts is applied, with 1,000 watts being preferred. The oxygen can be flowed together with a carrier gas such as helium, etc.
  • The [0031] oxide layer 20 is exposed to the oxygen plasma for a time effective to substantially eliminate carbon from the fill layer 20, preferably to a non-detectable level. The dissociated oxygen species diffuses into the layer 20 and reacts with carbon to form volatile byproducts (e.g., CO, CO2). The duration of the oxygen plasma treatment can range from about 1 to about 2 seconds to up to about 100 to about 1,000 seconds or longer, generally depending on the thickness of the oxide layer 20 and wafer temperature, an extended time period being preferred to sufficiently lower the carbon content of the oxide layer to the desired level. Elevating the temperature of the wafer can accelerate the removal of carbon from the fill material. Preferably, the oxygen plasma treatment is applied for at least about 10 seconds, preferably at least about 100 seconds, at a wafer temperature of up to about 800° C., preferably about 20 to about 450° C., preferably about 50 to about 200° C., and a reaction chamber pressure of about 0.1 to about 20 torr.
  • The oxygen plasma treatment preferably results in a reduction of the carbon content of the deposited [0032] oxide fill layer 20 by at least about 50%, preferably by at least about 80%, preferably by at least about 98%, such that the plasma-treated oxide layer has a carbon content of about 10% or less, preferably about 5% or less, preferably about 2% or less.
  • Further processing can be conducted, including stripping off excess of the oxide fill material and masking layers formed above the surface of the substrate, for example, using a known chemical mechanical polishing (CMP) technique, or other technique such as wet etching and/or dry etching. [0033]
  • The process according to the invention advantageously results in a substantial reduction in carbon from the [0034] fill layer 20 and also offers the advantage of filing a narrow space, e.g., a trench width of about 0.06 μm, for example, and gaps having a high aspect ratio from about 7:1 to about 10:1, for example.
  • The present application describes a method of treating oxide fill materials by contacting the fill with an oxygen plasma to substantially eliminate carbon therefrom. While illustrated in the context of removing carbon from a flowable oxide material deposited in a trench of a semiconductor substrate by CVD of TMS and oxide, the skilled artisan will recognize many other applications for the methods disclosed herein. [0035]
  • For example, the method of the invention can be utilized to reduce the carbon level of flowable SiOC-based oxides deposited from other gases and/or by other processes. Another technique of forming silicon dioxide is referred to as Flowfill™ technology, which has been developed by Trikon Technology of Bristol, U.K., as described in U.S. Pat. No. 6,156,674, and U.S. Pat. Appl. Publ. No. 2002/0098684, for example, the disclosures of which are incorporated by reference herein. Flowfill™ technology has been utilized to form insulative materials comprising (CH[0036] 3)xSiO(2-y), wherein y/2 is the percentage of CH3 incorporated. For example, in such a process, methylsilane (CH3SiH3) (in a gaseous form) and hydrogen peroxide (H2O2) (in a liquid form) can be separately introduced into a chamber, such as a parallel plate reaction chamber. A reaction between CH3SiH3 and H2O2 can be moderated by introduction of nitrogen into the reaction chamber. A wafer is provided within the chamber, and ideally maintained at a suitably low temperature, such as 0° C., at an exemplary pressure of about 1 Torr to achieve formation of a methylsilanol structure. Such material condenses on the wafer surface. Although the reaction occurs in the gas phase, the deposited material is in the form of a viscous liquid, which flows to fill small gaps on the wafer surface. In applications where deposition thickness increases, surface tension drives the deposited layer flat, thus forming a planarized layer over the substrate.
  • The liquid methylsilanol is converted to a silicon dioxide structure by a two-step process occurring in two separate chambers from that in which the methylsilanol-type structure was deposited. First, planarization of the liquid film is promoted by increasing the temperature to above 100° C., while maintaining the pressure at about 1 Torr, to result in solidification and formation of a polymer layer. Thereafter, the temperature is raised to approximately 450° C., while maintaining the pressure of about 1 Torr, to form (CH[0037] 3)xSiO(2-y). The processing at 450° C. also provides an advantage of driving undesired water from the resultant (CH3)xSiO(2-y) layer.
  • Other techniques of forming a silicon dioxide fill layer include a spin-on process by spin applying a liquid comprising an organosiloxane, by flow coating, or by using a spray technique. The solvent can be removed by baking, leaving a planarized silicon dioxide layer. [0038]
  • Other flowable oxide materials are known and used in the art can also benefit from the post-deposition plasma treatment in accordance with the invention. Examples of such oxide materials include various polyimides, FLARE 2.0™ dielectric (a poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif.), Black-Diamond™ dielectric (available from Applied Materials, Santa Clara, Calif.), BCB (divinylsiloxane bisbenzocyclobutene) and Silk™, an organic polymer similar to BCB (both available from Dow Chemical Co., Midland, Mich.), among others. Such materials can be applied by various techniques including spin-on and CVD processes. [0039]
  • Treatment of the organic carbon-containing oxide materials in accordance with embodiments of the invention employing an oxygen plasma substantially reduces the carbon content of such carbon-containing oxide materials. [0040]
  • FIGS. 5-7 illustrate steps in another embodiment of a method in accordance with the invention for forming an oxide fill in an opening in a substrate of a [0041] wafer fragment 10′. Referring to FIG. 5, a portion (e.g., about one-half) of a trench 14′ disposed in a substrate 12′ is filled with an oxide layer 20′ comprising a flowable oxide material, as described hereinabove. The remainder of the opening 14′ can then be filled with a high density plasma oxide material 24′ using a conventional high density plasma chemical vapor deposition (HDPCVD). Briefly, the silicon oxide is deposited in a reaction zone of a HDPCVD reactor while providing a selected bias power, source power and gas mixtures. Exemplary silicon source gases include, for example, silicon tetrachloride (SiCl4), silicon tetrabromide (SiBr4), dichlorosilane (SiH2Cl2), and disilane (Si2H6). Exemplary gases to react with the silicon source gas include oxygen, ozone, nitrous oxide (N2O), and nitric oxide (NO), for example, along with a carrier gas such as argon or helium.
  • FIG. 8 is a block diagram of an embodiment of a [0042] circuit module 26 in which the present invention can be incorporated. Such modules, devices and systems (e.g., processor systems) incorporating the module are described and illustrated in U.S. Pat. Nos. 6,437,417 (Gilton) and 6,465,829 (Agarwal), the disclosures of which are incorporated by reference herein. In brief, two or more dies 28 may be combined into a circuit module 26 to enhance or extend the functionality of an individual die 28. Circuit module 26 may be a combination of dies 28 representing a variety of functions, or a combination of dies containing the same functionality. One or more dies 28 of the circuit module can contain circuitry, or integrated circuit devices, that includes at least one O2 plasma-treated flowable oxide layer in accordance with the embodiments of the present invention. The integrated circuit devices can include a memory cell that comprises an oxide layer as discussed in the various embodiments in accordance with the invention.
  • Some examples of a circuit module include memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. [0043] Circuit module 26 may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, among others. Circuit module 26 will have a variety of leads 30 extending therefrom and coupled to the dies 28 providing unilateral or bilateral communication and control.
  • The circuit module can be incorporated, for example, into an electronic system that comprises a user interface, for example, a keyboard, monitor, display, printer, speakers, etc. One or more circuit modules can comprise a microprocessor that provides information to the user interface, or is otherwise programmed to carry out particular functions as is known in the art. The electronic system can comprise, for example, a computer system including a processor and a memory system as a subcomponent, and optionally user interface components, and other associated components such as modems, device driver cards, etc. Examples of memory circuits include but are not limited to DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Flash memories, a synchronous DRAM such as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging memory technologies. [0044]
    • EXAMPLE
  • Carbon-containing oxide films were deposited from TMS and O[0045] 3 by a CVD process onto three wafer surfaces. Process parameters included a chamber pressure of about 100 torr and a wafer temperature of about 125° C., utilizing a Centura DxZ CVD deposition chamber from Applied Materials, Inc.
  • The two test films were then treated with an oxygen plasma under the same process parameters. The Control film received no post-deposition treatment with oxygen plasma. Table 1 provides the average of the bulk atomic concentrations (%) of the Test oxide layers and the Control layer. [0046]
    TABLE 1
    Slot C O F Si bonded to O Si/O
    Test wafer #1 nd 63.5 0.3 36.1 0.57
    (plasma treated)
    Test wafer #2 nd 63.3 0.2 36.4 0.58
    (plasma treated)
    Control wafer 29.8 36.8 0.2 32.6 0.89
  • The results show a significant difference between the average of the bulk atomic concentrations (%) of the oxide layer of the test wafers exposed to the post-deposition treatment and the Control wafer. The results demonstrate that while the untreated Control wafer had an about 30% carbon content, the oxygen plasma post-deposition treatment was successful in eliminating the carbon content of the test wafers to a non-detectable level. [0047]
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0048]

Claims (32)

1-65. (canceled).
66. An oxide fill disposed on a semiconductor substrate, and comprising a flowable oxide material treated with an oxygen plasma such that carbon in the oxide material is non-detectable.
67. An oxide fill disposed on a semiconductor substrate, and comprising an oxygen plasma treated flowable oxide material having a carbon content of less than about 10%.
68. An oxide fill disposed within an opening in a semiconductor substrate, and comprising an oxygen plasma treated flowable oxide material having substantially no voids and a carbon content of less than about 10%.
69. The oxide fill of claim 68, disposed within a deep trench in the semiconductor substrate.
70. An oxide fill disposed within an opening in a semiconductor substrate, the opening having an aspect ratio of about 7:1 to about 10:1; the fill comprising an oxygen plasma treated flowable oxide material such that the fill comprises substantially no voids and a carbon content of less than about 10%.
71. An oxide fill disposed within an opening in a semiconductor substrate, and comprising an oxygen plasma treated flowable oxide material formed by chemical vapor deposition of an organosilane and an oxygen source gas, the fill having substantially no voids and a carbon content of less than about 10%.
72. An oxide fill disposed within an opening in a semiconductor substrate, and comprising an oxygen plasma treated flowable oxide material formed by chemical vapor deposition of an trimethylsilane and ozone, the fill having substantially no voids and a carbon content of less than about 10%.
73. An oxide fill disposed within an opening in a semiconductor substrate, and comprising an oxygen plasma treated flowable oxide material having substantially no voids and a carbon content of less than about 10%, the fill comprising a layer of a flowable oxide and an overlying layer of a high density plasma oxide.
74. A semiconductor device, comprising:
a substrate; and
an oxide material disposed on the substrate, the oxide material comprising an oxygen plasma treated flowable oxide formed by chemical vapor deposition of organosilane and an oxygen source gas, the oxide material having a carbon content of less than about 10%.
75. The device of claim 74, wherein the oxide material forms a trench isolation structure.
76. A semiconductor device, comprising:
a substrate; and
an oxygen plasma treated flowable oxide material disposed on the substrate, wherein carbon is non-detectable within the oxide material.
77. A semiconductor device, comprising:
a substrate; and
an oxygen plasma treated, flowable oxide material disposed on the substrate, the oxide material formed by chemical vapor deposition of an organosilane and an oxygen source gas, and comprising substantially no carbon.
78. A semiconductor device, comprising:
a substrate; and
an oxygen plasma treated, spin applied flowable oxide material disposed on the substrate, the oxide material comprising substantially no carbon.
79. A semiconductor device, comprising:
a substrate; and
an oxide fill disposed within an opening in the substrate, the fill comprising an oxygen plasma treated flowable oxide material formed by chemical vapor deposition of trimethylsilane and ozone, the fill having substantially no voids and substantially no carbon.
80. An integrated circuit supported by a substrate, and comprising:
an oxide layer disposed on the substrate, the oxide layer comprising an oxygen plasma treated flowable oxide and having a carbon content of less than about 10%.
81. An integrated circuit supported by a substrate, and comprising:
an oxide layer disposed on the substrate, the oxide layer comprising an oxygen plasma treated flowable oxide formed by chemical vapor deposition of an organosilane and an oxygen source gas, and having a carbon content of less than about 10%.
82. An integrated circuit supported by a substrate, and comprising:
an oxide layer disposed on the substrate, the oxide layer comprising an oxygen plasma treated flowable oxide formed by chemical vapor deposition of trimethylsilane and ozone, and having a carbon content of less than about 10%.
83. An integrated circuit supported by a substrate, and comprising:
an oxide layer disposed on the substrate, the oxide layer comprising an oxygen plasma treated, spin applied flowable oxide having a carbon content of less than about 10%.
84. An integrated circuit supported by a substrate, and comprising:
an oxide fill disposed in an opening in the substrate, the oxide fill comprising an oxygen plasma treated flowable oxide and having a carbon content of less than about 10%.
85. The integrated circuit of claim 84, wherein the oxide fill is formed by chemical vapor deposition of an organosilane and an oxygen source gas.
86. The integrated circuit of claim 85, wherein the oxide fill is formed by chemical vapor deposition of trimethylsilane and ozone.
87. The integrated circuit of claim 84, wherein the oxide fill comprises a spin applied flowable oxide.
88. The integrated circuit of claim 84, wherein the oxide fill disposed in the opening comprises a trench isolation structure.
89. The integrated circuit of claim 84, wherein the opening has an aspect ratio of about 7:1 to about 10:1.
90. An electronic system, comprising:
a processor; and
an integrated circuit in communication with the processor, the integrated circuit comprising a substrate and an oxide fill disposed in an opening in the substrate, the oxide fill comprising an oxygen plasma treated flowable oxide having a carbon content of less than about 10%.
91. The system of claim 90, wherein the integrated circuit is a memory circuit.
92. The system of claim 90, wherein the memory circuit is a DRAM memory circuit.
93. An electronic system, comprising:
a processor; and
an integrated circuit in communication with the processor, the integrated circuit comprising a substrate and an oxide fill disposed in an opening in the substrate, the oxide fill comprising an oxygen plasma treated flowable oxide formed by chemical vapor deposition of an organosilane and an oxygen source gas, and having a carbon content of less than about 10%.
94. An electronic system, comprising:
a processor; and
an integrated circuit in communication with the processor, the integrated circuit comprising a substrate and an oxide fill disposed in an opening in the substrate, the oxide fill comprising an oxygen plasma treated flowable oxide formed by chemical vapor deposition of trimethylsilane and ozone, and having a carbon content of less than about 10%.
95. An electronic system, comprising:
a processor; and
an integrated circuit in communication with the processor, the integrated circuit comprising a substrate and an oxide fill disposed in an opening in the substrate, the oxide fill comprising an oxygen plasma treated flowable oxide having a carbon content of less than about 10%, the fill comprising a layer of a flowable oxide and an overlying layer of a high density plasma oxide.
96. An electronic system, comprising:
a processor; and
an integrated circuit in communication with the processor, the integrated circuit comprising a substrate and an oxide fill disposed in an opening in the substrate, the oxide fill comprising an oxygen plasma treated, spin applied flowable oxide having a carbon content of less than about 10%.
US10/853,063 2003-02-04 2004-05-25 Method of eliminating residual carbon from flowable oxide fill Abandoned US20040212036A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/853,063 US20040212036A1 (en) 2003-02-04 2004-05-25 Method of eliminating residual carbon from flowable oxide fill

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/357,812 US7205248B2 (en) 2003-02-04 2003-02-04 Method of eliminating residual carbon from flowable oxide fill
US10/853,063 US20040212036A1 (en) 2003-02-04 2004-05-25 Method of eliminating residual carbon from flowable oxide fill

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/357,812 Division US7205248B2 (en) 2003-02-04 2003-02-04 Method of eliminating residual carbon from flowable oxide fill

Publications (1)

Publication Number Publication Date
US20040212036A1 true US20040212036A1 (en) 2004-10-28

Family

ID=32771071

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/357,812 Expired - Fee Related US7205248B2 (en) 2003-02-04 2003-02-04 Method of eliminating residual carbon from flowable oxide fill
US10/853,063 Abandoned US20040212036A1 (en) 2003-02-04 2004-05-25 Method of eliminating residual carbon from flowable oxide fill

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/357,812 Expired - Fee Related US7205248B2 (en) 2003-02-04 2003-02-04 Method of eliminating residual carbon from flowable oxide fill

Country Status (2)

Country Link
US (2) US7205248B2 (en)
WO (1) WO2004070817A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110081782A1 (en) * 2009-10-05 2011-04-07 Applied Materials, Inc. Post-planarization densification
US20110212620A1 (en) * 2009-10-05 2011-09-01 Applied Materials, Inc. Post-planarization densification
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films

Families Citing this family (189)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6939817B2 (en) * 2003-05-08 2005-09-06 Micron Technology, Inc. Removal of carbon from an insulative layer using ozone
US9257302B1 (en) 2004-03-25 2016-02-09 Novellus Systems, Inc. CVD flowable gap fill
US7524735B1 (en) 2004-03-25 2009-04-28 Novellus Systems, Inc Flowable film dielectric gap fill process
US7582555B1 (en) 2005-12-29 2009-09-01 Novellus Systems, Inc. CVD flowable gap fill
US7682977B2 (en) * 2006-05-11 2010-03-23 Micron Technology, Inc. Methods of forming trench isolation and methods of forming arrays of FLASH memory cells
US7825038B2 (en) * 2006-05-30 2010-11-02 Applied Materials, Inc. Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen
US7902080B2 (en) * 2006-05-30 2011-03-08 Applied Materials, Inc. Deposition-plasma cure cycle process to enhance film quality of silicon dioxide
US20070277734A1 (en) * 2006-05-30 2007-12-06 Applied Materials, Inc. Process chamber for dielectric gapfill
WO2007140377A2 (en) * 2006-05-30 2007-12-06 Applied Materials, Inc. A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide
US7790634B2 (en) 2006-05-30 2010-09-07 Applied Materials, Inc Method for depositing and curing low-k films for gapfill and conformal film applications
US8232176B2 (en) * 2006-06-22 2012-07-31 Applied Materials, Inc. Dielectric deposition and etch back processes for bottom up gapfill
US9245739B2 (en) 2006-11-01 2016-01-26 Lam Research Corporation Low-K oxide deposition by hydrolysis and condensation
US7888273B1 (en) 2006-11-01 2011-02-15 Novellus Systems, Inc. Density gradient-free gap fill
US7745352B2 (en) * 2007-08-27 2010-06-29 Applied Materials, Inc. Curing methods for silicon dioxide thin films deposited from alkoxysilane precursor with harp II process
US7867923B2 (en) * 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US7541297B2 (en) * 2007-10-22 2009-06-02 Applied Materials, Inc. Method and system for improving dielectric film quality for void free gap fill
US7803722B2 (en) * 2007-10-22 2010-09-28 Applied Materials, Inc Methods for forming a dielectric layer within trenches
US7943531B2 (en) * 2007-10-22 2011-05-17 Applied Materials, Inc. Methods for forming a silicon oxide layer over a substrate
US8357435B2 (en) * 2008-05-09 2013-01-22 Applied Materials, Inc. Flowable dielectric equipment and processes
US8263502B2 (en) * 2008-08-13 2012-09-11 Synos Technology, Inc. Forming substrate structure by filling recesses with deposition material
US8557712B1 (en) 2008-12-15 2013-10-15 Novellus Systems, Inc. PECVD flowable dielectric gap fill
US9431237B2 (en) * 2009-04-20 2016-08-30 Applied Materials, Inc. Post treatment methods for oxide layers on semiconductor devices
US8980382B2 (en) 2009-12-02 2015-03-17 Applied Materials, Inc. Oxygen-doping for non-carbon radical-component CVD films
US7935643B2 (en) * 2009-08-06 2011-05-03 Applied Materials, Inc. Stress management for tensile films
US8741788B2 (en) 2009-08-06 2014-06-03 Applied Materials, Inc. Formation of silicon oxide using non-carbon flowable CVD processes
US7989365B2 (en) * 2009-08-18 2011-08-02 Applied Materials, Inc. Remote plasma source seasoning
US8278224B1 (en) 2009-09-24 2012-10-02 Novellus Systems, Inc. Flowable oxide deposition using rapid delivery of process gases
US20110136347A1 (en) * 2009-10-21 2011-06-09 Applied Materials, Inc. Point-of-use silylamine generation
US8449942B2 (en) * 2009-11-12 2013-05-28 Applied Materials, Inc. Methods of curing non-carbon flowable CVD films
WO2011072143A2 (en) * 2009-12-09 2011-06-16 Novellus Systems, Inc. Novel gap fill integration
KR20120111738A (en) 2009-12-30 2012-10-10 어플라이드 머티어리얼스, 인코포레이티드 Dielectric film growth with radicals produced using flexible nitrogen/hydrogen ratio
US8329262B2 (en) * 2010-01-05 2012-12-11 Applied Materials, Inc. Dielectric film formation using inert gas excitation
JP2013517616A (en) 2010-01-06 2013-05-16 アプライド マテリアルズ インコーポレイテッド Flowable dielectrics using oxide liners
CN102714156A (en) 2010-01-07 2012-10-03 应用材料公司 In-situ ozone cure for radical-component CVD
CN102844848A (en) * 2010-03-05 2012-12-26 应用材料公司 Conformal layers by radical-component cvd
US8236708B2 (en) 2010-03-09 2012-08-07 Applied Materials, Inc. Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor
US7994019B1 (en) 2010-04-01 2011-08-09 Applied Materials, Inc. Silicon-ozone CVD with reduced pattern loading using incubation period deposition
US8476142B2 (en) 2010-04-12 2013-07-02 Applied Materials, Inc. Preferential dielectric gapfill
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US8524004B2 (en) 2010-06-16 2013-09-03 Applied Materials, Inc. Loadlock batch ozone cure
US8318584B2 (en) 2010-07-30 2012-11-27 Applied Materials, Inc. Oxide-rich liner layer for flowable CVD gapfill
US9285168B2 (en) 2010-10-05 2016-03-15 Applied Materials, Inc. Module for ozone cure and post-cure moisture treatment
US8664127B2 (en) 2010-10-15 2014-03-04 Applied Materials, Inc. Two silicon-containing precursors for gapfill enhancing dielectric liner
US8685867B1 (en) 2010-12-09 2014-04-01 Novellus Systems, Inc. Premetal dielectric integration process
US9719169B2 (en) 2010-12-20 2017-08-01 Novellus Systems, Inc. System and apparatus for flowable deposition in semiconductor fabrication
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8450191B2 (en) 2011-01-24 2013-05-28 Applied Materials, Inc. Polysilicon films by HDP-CVD
US8716154B2 (en) 2011-03-04 2014-05-06 Applied Materials, Inc. Reduced pattern loading using silicon oxide multi-layers
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US8445078B2 (en) 2011-04-20 2013-05-21 Applied Materials, Inc. Low temperature silicon oxide conversion
US8466073B2 (en) 2011-06-03 2013-06-18 Applied Materials, Inc. Capping layer for reduced outgassing
US9404178B2 (en) 2011-07-15 2016-08-02 Applied Materials, Inc. Surface treatment and deposition for reduced outgassing
US8617989B2 (en) 2011-09-26 2013-12-31 Applied Materials, Inc. Liner property improvement
US8551891B2 (en) 2011-10-04 2013-10-08 Applied Materials, Inc. Remote plasma burn-in
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8637403B2 (en) * 2011-12-12 2014-01-28 International Business Machines Corporation Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics
US8846536B2 (en) 2012-03-05 2014-09-30 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US20130288485A1 (en) * 2012-04-30 2013-10-31 Applied Materials, Inc. Densification for flowable films
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US8889566B2 (en) 2012-09-11 2014-11-18 Applied Materials, Inc. Low cost flowable dielectric films
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US8823132B2 (en) 2013-01-08 2014-09-02 United Microelectronics Corp. Two-portion shallow-trench isolation
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US20150118863A1 (en) * 2013-10-25 2015-04-30 Lam Research Corporation Methods and apparatus for forming flowable dielectric films having low porosity
US9847222B2 (en) 2013-10-25 2017-12-19 Lam Research Corporation Treatment for flowable dielectric deposition on substrate surfaces
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9786542B2 (en) 2014-01-13 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming semiconductor device having isolation structure
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9412581B2 (en) 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US10049921B2 (en) 2014-08-20 2018-08-14 Lam Research Corporation Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9355862B2 (en) * 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9362107B2 (en) 2014-09-30 2016-06-07 Applied Materials, Inc. Flowable low-k dielectric gapfill treatment
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US9916977B2 (en) 2015-11-16 2018-03-13 Lam Research Corporation Low k dielectric deposition via UV driven photopolymerization
US10388546B2 (en) 2015-11-16 2019-08-20 Lam Research Corporation Apparatus for UV flowable dielectric
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10586801B2 (en) 2018-01-12 2020-03-10 Intel Corporation Flash memory cells
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI716818B (en) 2018-02-28 2021-01-21 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
KR20210143943A (en) 2019-04-19 2021-11-29 램 리써치 코포레이션 Rapid flush purging during atomic layer deposition

Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3695647A (en) * 1970-07-16 1972-10-03 Hoke Inc Pipe coupling
US5314724A (en) * 1991-01-08 1994-05-24 Fujitsu Limited Process for forming silicon oxide film
US5436808A (en) * 1991-04-30 1995-07-25 Transducer Valley Inc. Headlamp
US5665849A (en) * 1995-02-17 1997-09-09 Texas Instruments Incorporated Modified hydrogen silsesquioxane spin-on glass
US5749975A (en) * 1995-12-28 1998-05-12 Micron Technology, Inc. Process for dry cleaning wafer surfaces using a surface diffusion layer
US5858880A (en) * 1994-05-14 1999-01-12 Trikon Equipment Limited Method of treating a semi-conductor wafer
US5874367A (en) * 1992-07-04 1999-02-23 Trikon Technologies Limited Method of treating a semi-conductor wafer
US5882981A (en) * 1996-07-30 1999-03-16 Texas Instruments Incorporated Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material
US5895272A (en) * 1996-03-06 1999-04-20 Micron Technology, Inc. Ion-implanted resist removal method
US6105588A (en) * 1998-05-27 2000-08-22 Micron Technology, Inc. Method of resist stripping during semiconductor device fabrication
US6156674A (en) * 1998-11-25 2000-12-05 Micron Technology, Inc. Semiconductor processing methods of forming insulative materials
US6174451B1 (en) * 1998-03-27 2001-01-16 Applied Materials, Inc. Oxide etch process using hexafluorobutadiene and related unsaturated hydrofluorocarbons
US6221780B1 (en) * 1999-09-29 2001-04-24 International Business Machines Corporation Dual damascene flowable oxide insulation structure and metallic barrier
US6294476B1 (en) * 1998-03-30 2001-09-25 Vanguard International Semiconductor Corporation Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US20010039125A1 (en) * 1997-06-30 2001-11-08 Masaki Hara Method for making an insulating film
US6323101B1 (en) * 1998-09-03 2001-11-27 Micron Technology, Inc. Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers
US20020001219A1 (en) * 1999-08-30 2002-01-03 Leonard Forbes Discrete devices including eaprom transistor and nvram memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatus including same
US6355580B1 (en) * 1998-09-03 2002-03-12 Micron Technology, Inc. Ion-assisted oxidation methods and the resulting structures
US20020038662A1 (en) * 1999-06-28 2002-04-04 Intersil Corporation Potted transducer array with matching network in a multiple pass configuration
US6368988B1 (en) * 1999-07-16 2002-04-09 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6383951B1 (en) * 1998-09-03 2002-05-07 Micron Technology, Inc. Low dielectric constant material for integrated circuit fabrication
US6387287B1 (en) * 1998-03-27 2002-05-14 Applied Materials, Inc. Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window
US6395647B1 (en) * 1999-09-02 2002-05-28 Micron Technology, Inc. Chemical treatment of semiconductor substrates
US6413879B1 (en) * 1999-03-17 2002-07-02 Canon Sales Co., Inc. Method for forming an interlayer insulating film, and semiconductor device
US20020098684A1 (en) * 1999-09-01 2002-07-25 Weimin Li Low k interlevel dielectric layer fabrication methods
US6436808B1 (en) * 2000-12-07 2002-08-20 Advanced Micro Devices, Inc. NH3/N2-plasma treatment to prevent organic ILD degradation
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation
US6455394B1 (en) * 1998-03-13 2002-09-24 Micron Technology, Inc. Method for trench isolation by selective deposition of low temperature oxide films
US6465829B2 (en) * 2000-05-26 2002-10-15 Fujitsu Limited Semiconductor device with memory and logic cells
US6465828B2 (en) * 1999-07-30 2002-10-15 Micron Technology, Inc. Semiconductor container structure with diffusion barrier
US6465366B1 (en) * 2000-09-12 2002-10-15 Applied Materials, Inc. Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
US20020163028A1 (en) * 2001-05-07 2002-11-07 Applied Materials, Inc. Methods of forming gap fill and layers formed thereby
US6485815B1 (en) * 1999-05-24 2002-11-26 Samsung Electronics Co., Ltd. Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same
US6593247B1 (en) * 1998-02-11 2003-07-15 Applied Materials, Inc. Method of depositing low k films using an oxidizing plasma
US6602434B1 (en) * 1998-03-27 2003-08-05 Applied Materials, Inc. Process for etching oxide using hexafluorobutadiene or related fluorocarbons and manifesting a wide process window
US6630390B2 (en) * 2001-11-20 2003-10-07 Intel Corporation Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer
US6635575B1 (en) * 1999-08-17 2003-10-21 Applied Materials, Inc. Methods and apparatus to enhance properties of Si-O-C low K films
US6798038B2 (en) * 2001-09-20 2004-09-28 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device with filling insulating film into trench

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE507745C2 (en) * 1996-11-05 1998-07-06 Alfa Laval Ab sealing device

Patent Citations (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3695647A (en) * 1970-07-16 1972-10-03 Hoke Inc Pipe coupling
US5314724A (en) * 1991-01-08 1994-05-24 Fujitsu Limited Process for forming silicon oxide film
US5436808A (en) * 1991-04-30 1995-07-25 Transducer Valley Inc. Headlamp
US5874367A (en) * 1992-07-04 1999-02-23 Trikon Technologies Limited Method of treating a semi-conductor wafer
US5858880A (en) * 1994-05-14 1999-01-12 Trikon Equipment Limited Method of treating a semi-conductor wafer
US5665849A (en) * 1995-02-17 1997-09-09 Texas Instruments Incorporated Modified hydrogen silsesquioxane spin-on glass
US5749975A (en) * 1995-12-28 1998-05-12 Micron Technology, Inc. Process for dry cleaning wafer surfaces using a surface diffusion layer
US5895272A (en) * 1996-03-06 1999-04-20 Micron Technology, Inc. Ion-implanted resist removal method
US5882981A (en) * 1996-07-30 1999-03-16 Texas Instruments Incorporated Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material
US20010039125A1 (en) * 1997-06-30 2001-11-08 Masaki Hara Method for making an insulating film
US6806207B2 (en) * 1998-02-11 2004-10-19 Applied Materials Inc. Method of depositing low K films
US6593247B1 (en) * 1998-02-11 2003-07-15 Applied Materials, Inc. Method of depositing low k films using an oxidizing plasma
US6455394B1 (en) * 1998-03-13 2002-09-24 Micron Technology, Inc. Method for trench isolation by selective deposition of low temperature oxide films
US6387287B1 (en) * 1998-03-27 2002-05-14 Applied Materials, Inc. Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window
US6613691B1 (en) * 1998-03-27 2003-09-02 Applied Materials, Inc. Highly selective oxide etch process using hexafluorobutadiene
US6602434B1 (en) * 1998-03-27 2003-08-05 Applied Materials, Inc. Process for etching oxide using hexafluorobutadiene or related fluorocarbons and manifesting a wide process window
US6174451B1 (en) * 1998-03-27 2001-01-16 Applied Materials, Inc. Oxide etch process using hexafluorobutadiene and related unsaturated hydrofluorocarbons
US6294476B1 (en) * 1998-03-30 2001-09-25 Vanguard International Semiconductor Corporation Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
US6105588A (en) * 1998-05-27 2000-08-22 Micron Technology, Inc. Method of resist stripping during semiconductor device fabrication
US20020134405A1 (en) * 1998-05-27 2002-09-26 Li Li Reduction/oxidation material removal method
US6355580B1 (en) * 1998-09-03 2002-03-12 Micron Technology, Inc. Ion-assisted oxidation methods and the resulting structures
US6383951B1 (en) * 1998-09-03 2002-05-07 Micron Technology, Inc. Low dielectric constant material for integrated circuit fabrication
US6323101B1 (en) * 1998-09-03 2001-11-27 Micron Technology, Inc. Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers
US6429496B1 (en) * 1998-09-03 2002-08-06 Micron Technology, Inc. Ion-assisted oxidation methods and the resulting structures
US20020105084A1 (en) * 1998-09-03 2002-08-08 Weimin Li Low dielectric constant material for integrated circuit fabrication
US6156674A (en) * 1998-11-25 2000-12-05 Micron Technology, Inc. Semiconductor processing methods of forming insulative materials
US6413879B1 (en) * 1999-03-17 2002-07-02 Canon Sales Co., Inc. Method for forming an interlayer insulating film, and semiconductor device
US6485815B1 (en) * 1999-05-24 2002-11-26 Samsung Electronics Co., Ltd. Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same
US20020038662A1 (en) * 1999-06-28 2002-04-04 Intersil Corporation Potted transducer array with matching network in a multiple pass configuration
US6524975B2 (en) * 1999-07-16 2003-02-25 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6368988B1 (en) * 1999-07-16 2002-04-09 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6465828B2 (en) * 1999-07-30 2002-10-15 Micron Technology, Inc. Semiconductor container structure with diffusion barrier
US6635575B1 (en) * 1999-08-17 2003-10-21 Applied Materials, Inc. Methods and apparatus to enhance properties of Si-O-C low K films
US20020001219A1 (en) * 1999-08-30 2002-01-03 Leonard Forbes Discrete devices including eaprom transistor and nvram memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatus including same
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US20020098684A1 (en) * 1999-09-01 2002-07-25 Weimin Li Low k interlevel dielectric layer fabrication methods
US20020187628A1 (en) * 1999-09-01 2002-12-12 Weimin Li Low k interlevel dielectric layer fabrication methods
US6395647B1 (en) * 1999-09-02 2002-05-28 Micron Technology, Inc. Chemical treatment of semiconductor substrates
US6221780B1 (en) * 1999-09-29 2001-04-24 International Business Machines Corporation Dual damascene flowable oxide insulation structure and metallic barrier
US6465829B2 (en) * 2000-05-26 2002-10-15 Fujitsu Limited Semiconductor device with memory and logic cells
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation
US6465366B1 (en) * 2000-09-12 2002-10-15 Applied Materials, Inc. Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
US6436808B1 (en) * 2000-12-07 2002-08-20 Advanced Micro Devices, Inc. NH3/N2-plasma treatment to prevent organic ILD degradation
US20020163028A1 (en) * 2001-05-07 2002-11-07 Applied Materials, Inc. Methods of forming gap fill and layers formed thereby
US6798038B2 (en) * 2001-09-20 2004-09-28 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device with filling insulating film into trench
US6630390B2 (en) * 2001-11-20 2003-10-07 Intel Corporation Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110081782A1 (en) * 2009-10-05 2011-04-07 Applied Materials, Inc. Post-planarization densification
US20110212620A1 (en) * 2009-10-05 2011-09-01 Applied Materials, Inc. Post-planarization densification
CN102668061A (en) * 2009-10-05 2012-09-12 应用材料公司 Post-planarization densification
US8329587B2 (en) * 2009-10-05 2012-12-11 Applied Materials, Inc. Post-planarization densification
US8466067B2 (en) * 2009-10-05 2013-06-18 Applied Materials, Inc. Post-planarization densification
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films

Also Published As

Publication number Publication date
US20040152342A1 (en) 2004-08-05
WO2004070817A3 (en) 2004-12-23
US7205248B2 (en) 2007-04-17
WO2004070817A2 (en) 2004-08-19

Similar Documents

Publication Publication Date Title
US7205248B2 (en) Method of eliminating residual carbon from flowable oxide fill
US6939817B2 (en) Removal of carbon from an insulative layer using ozone
US9536773B2 (en) Mechanism of forming a trench structure
US6719012B2 (en) Method of forming trench isolation regions
US7521354B2 (en) Low k interlevel dielectric layer fabrication methods
US9396986B2 (en) Mechanism of forming a trench structure
US7947551B1 (en) Method of forming a shallow trench isolation structure
US20090298257A1 (en) Device isolation technology on semiconductor substrate
JP2001168193A (en) LOW k DIELECTRIC COMPOSITE MATERIAL LAYER FOR INTEGRATED CIRCUIT STRUCTURE THAT OFFERS VOID-FREE LOW k DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE RELAXING VIA POISONING
US20210083048A1 (en) Semiconductor device
US7883986B2 (en) Methods of forming trench isolation and methods of forming arrays of FLASH memory cells
US6194328B1 (en) H2 diffusion barrier formation by nitrogen incorporation in oxide layer
KR100884347B1 (en) Method for fabricating isolation layer in semiconductor device
JPH1064998A (en) Method for forming inter-layer film

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION