US20040185609A1 - Semiconductor manufacturing method including forming additional active layer - Google Patents

Semiconductor manufacturing method including forming additional active layer Download PDF

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US20040185609A1
US20040185609A1 US10/814,270 US81427004A US2004185609A1 US 20040185609 A1 US20040185609 A1 US 20040185609A1 US 81427004 A US81427004 A US 81427004A US 2004185609 A1 US2004185609 A1 US 2004185609A1
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insulating film
sidewall insulating
film
circuit part
memory cell
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US10/814,270
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Yoshinori Okumura
Shuichi Ueno
Haruo Furuta
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a semiconductor device which includes MOS (Metal Oxide Semiconductor) transistors, wirings etc. and a manufacturing method thereof.
  • MOS Metal Oxide Semiconductor
  • a semiconductor device which includes MOS transistors, wirings etc. is manufactured by performing an impurity injection in a semiconductor substrate and forming an insulating film and a conductive film on a surface of the semiconductor substrate.
  • an active layer which becomes a source/drain region of a MOS transistor is composed of an extension region and a region whose impurity concentration is higher than that of the extension region.
  • the high impurity concentration region is formed by forming a sidewall insulating film on a side of a gate electrode after forming the extension region and performing an impurity injection with the gate electrode and the sidewall insulating film as a mask.
  • a position where the high impurity concentration region is formed is determined by a forming width of the sidewall insulating film in a channel direction of the transistor.
  • the high impurity concentration region is widely formed so that it is distributed close to the gate electrode. It is performed by reason of reducing a resistance value in the source/drain region. Therefore, the forming width of the sidewall insulating film is arranged to be a small value.
  • the high impurity concentration region is formed distant from the gate electrode as compared with a case of the MOS transistor for the memory cell. It is because, with regard to the high voltage circuit part, it is desirable that the high impurity concentration region is distant from the gate electrode to prevent a phenomenon, that is so-called GIDL (Gate Induced Drain Leakage) generation (a phenomenon that when a high voltage is applied to a gate, atoms which are stably existent in a drain region separates into holes and electrons, and thus a leakage current flows between a drain and a substrate). Therefore, the forming width of the sidewall insulating film is arranged to be a large value.
  • GIDL Gate Induced Drain Leakage
  • both the MOS transistor for the memory cell and the MOS transistor for the high voltage circuit part are formed on one semiconductor substrate.
  • both types of the MOS transistors are formed in the same step without adding the number of steps, and the forming widths of the sidewall insulating films are determined to be identical.
  • the forming width of the sidewall insulating film is arranged to be a value fitting to either of the MOS transistors.
  • the forming width of the sidewall insulating film is determined to suit to the MOS transistor for the high voltage circuit part.
  • the active layer such as the source/drain region etc. which is formed by performing the impurity injection into the semiconductor substrate and the wiring which is formed near the active layer on the semiconductor substrate are short-circuited by a shared contact plug.
  • the sidewall insulating film formed on a side of the wiring is removed.
  • the active layer has a low impurity concentration caused by a low injection rate of the impurity, and thus a value of a contact resistance between that part of the active layer and the shared contact plug is liable to become high.
  • a part of the semiconductor substrate which is under the sidewall insulating film is liable to be damaged caused by an etching when the sidewall insulating film is removed, therefore, a PN junction between the active layer and the semiconductor substrate is not definitely formed, and a junction leakage current often increases.
  • a manufacturing method of a semiconductor device includes the following steps (a) to (f)
  • a conductive film is formed on a semiconductor substrate.
  • the conductive film is patterned by a photolithography technique and an etching technique.
  • a first active layer is formed by performing an impurity injection in proximity of the patterned conductive film in a surface of the semiconductor substrate.
  • a contact hole in which both the first active layer and the conductive film are exposed is formed in the interlayer insulating film by a photolithography technique and an etching technique.
  • a second active layer is formed by performing an impurity injection on a surface of the semiconductor substrate which is exposed in the contact hole.
  • the contact hole in which both the first active layer and the conductive film are exposed is formed, and the second active layer is formed on the surface of the semiconductor substrate which is exposed in the contact hole.
  • a semiconductor device includes a semiconductor substrate, a first transistor and a second transistor.
  • the first transistor includes a first gate electrode which is formed on the semiconductor substrate, a first sidewall insulating film which is formed on a side of the first gate electrode on the semiconductor substrate and first source/drain active layers which are formed in the semiconductor substrate.
  • the second transistor includes a second gate electrode which is formed on the semiconductor substrate, a second sidewall insulating film which is formed on a side of the second gate electrode on the semiconductor substrate and second source/drain active layers which are formed in the semiconductor substrate.
  • Layers of an insulating film which composes the second sidewall insulating film are more in number than layers of an insulating film which composes the first sidewall insulating film, and accordingly, a width of the second sidewall insulating film in a channel direction of the second transistor is larger than a width of the first sidewall insulating film in a channel direction of the first transistor.
  • the source/drain active layer can be formed in the position more distant from the gate electrode as compared with the first transistor.
  • the second transistor for a high voltage circuit part and the first transistor for a memory cell a semiconductor device which is suited for forming both the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • FIGS. 1 to 7 are drawings all illustrating a manufacturing method of a semiconductor device according to the first preferred embodiment.
  • FIGS. 8 to 12 are drawings all illustrating a manufacturing method of a semiconductor device according to the second preferred embodiment.
  • FIGS. 13 and 14 are drawings both illustrating a modification example of the semiconductor device according to the first or second preferred embodiment.
  • the present preferred embodiment is a manufacturing method of a semiconductor device that an additional impurity injection on a part where a sidewall insulating film is removed in a shared contact plug forming portion is performed.
  • an insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film is made small in a MOS transistor for a memory cell, and a forming width of a sidewall insulating film is made large in a MOS transistor for the high voltage circuit part.
  • FIGS. 1 to 7 are drawings all illustrating a manufacturing method of a semiconductor device according to the present preferred embodiment. The present preferred embodiment is described below using these drawings.
  • a semiconductor substrate 1 such as a silicon substrate etc. which is separated into a high voltage circuit part AR 1 , a memory cell part AR 2 and a memory cell peripheral circuit part AR 3 is prepared.
  • a P type impurity ion such as Boron etc. is injected in the whole of the semiconductor substrate 1 .
  • element isolation regions 2 and 2 a to isolate each element are formed on each certain region of a surface of the semiconductor substrate 1 .
  • the element isolation regions 2 and 2 a are formed of an insulating film such as a silicon oxide film etc.
  • the P type impurity ion such as Boron etc. is injected in the region where a N channel type MOS transistor is to be formed, and a N type impurity ion such as phosphorus, arsenic etc. is injected in the region where a P channel type MOS transistor is to be formed.
  • N type wells 3 a and 3 b and a P type well 3 c are formed in each region.
  • an ion injection can be performed to the desired portion with the patterned photo resist as a mask.
  • the same may be said of the injection of the other impurity ions described below.
  • FIGS. 1 to 7 for a simplification of drawings, only a part of the N type wells are illustrated in the high voltage circuit part AR 1 and the memory cell part AR 2 , and only a part of the P type well is illustrated in the memory cell peripheral circuit part AR 3 .
  • the P type wells are also formed in the high voltage circuit part AR 1 and the memory cell part AR 2
  • the N type well is also formed in the memory cell peripheral circuit part AR 3 .
  • the N channel MOS transistor can be formed on the P type well and the P chancel MOS transistor can be formed on the N type well.
  • gate insulating films 5 a to 5 c are formed by a thermal oxidation treatment on a surface of the semiconductor substrate 1 except for the forming part of the element isolation regions 2 and 2 a .
  • a conductive film such as a polysilicon film etc. is formed on the entire surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method, for example, and is patterned into a desired shape by a photolithography technique and an etching technique.
  • gate electrodes 6 a , 6 b and 6 d and a wiring 6 c are formed.
  • the wiring 6 c has a shape which is partly run upon the element isolation region 2 a , as a matter of course, it is not necessary to make it shape like this.
  • the P type impurity ion has to be injected only in a part to be the gate electrode and the wiring on the P type well, and the N type impurity ion has to be injected only in a part to be the gate electrode and the wiring on the N type well.
  • the gate electrodes 6 a and 6 b and the wiring 6 c become an N + doped polysilicon gate and the gate electrode 6 d becomes a P + doped polysilicon gate.
  • extension regions 4 a to 4 d are formed with the element isolation regions 2 and 2 a , the gate electrodes 6 b and 6 d and the wiring 6 c as the masks. More particularly, in both regions, P ⁇ extension regions 4 a and 4 b are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor. In the meantime, N ⁇ extension regions 4 c and 4 d are formed by injecting the N type impurity ion in the forming region of the N channel MOS transistor. In this step, the photo resist is formed on the entire surface of the high voltage circuit part AR 1 and the injection of the impurity ion in the high voltage circuit part AR 1 is prevented.
  • a silicon oxide film 7 is formed over the entire surface of the semiconductor substrate 1 so as to cover the semiconductor substrate 1 , the gate electrodes 6 a , 6 b and 6 d and the wiring 6 c by the CVD method, for example.
  • a silicon nitride film 8 is furthermore formed on the silicon oxide film 7 over the entire surface of the semiconductor substrate 1 so as to cover the semiconductor substrate 1 , the gate electrodes 6 a , 6 b and 6 d and the wiring 6 c by the CVD method, for example.
  • the silicon oxide film 7 is formed under the silicon nitride film 8 is that a stress which the silicon nitride film 8 exerts on the semiconductor substrate 1 is relaxed. Accordingly, the silicon oxide film 7 is not essential, however, it is desirable to form it to prevent a deterioration of a device characteristic.
  • etch-back is performed to the silicon nitride film 8 and the silicon oxide film 7 selectively in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 .
  • a sidewall insulating film 10 a which includes a silicon nitride film 8 a and a silicon oxide film 7 a
  • a sidewall insulating film 10 b which includes a silicon nitride film 8 b and a silicon oxide film 7 b
  • a sidewall insulating film 10 c which includes a silicon nitride film 8 c and a silicon oxide film 7 c are formed.
  • the photo resist is formed on the entire surface of the high voltage circuit part AR 1 and the formation of the sidewall insulating film in the high voltage circuit part AR 1 is prevented.
  • an impurity injection is performed with the gate electrodes 6 b and 6 d , the wiring 6 c and the sidewall insulating films 10 a to 10 c as the masks selectively in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 .
  • source/drain active layers 9 a to 9 d are formed in the semiconductor substrate 1 , and a transistor TR 1 for the memory cell and a transistor TR 2 for the memory cell peripheral circuit are formed.
  • P + source/drain active layers 9 a and 9 b are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor after forming the sidewall insulating films 10 a and 10 b .
  • N + source/drain active layers 9 c and 9 d are formed by injecting the N type impurity ion in the forming region of the N channel MOS transistor after forming the sidewall insulating film 10 c .
  • the photo resist is formed on the entire surface of the high voltage circuit part AR 1 and the formation of the source/drain active layer in the high voltage circuit part AR 1 is prevented.
  • a metal film such as Ti and Co is formed on the entire surface of the semiconductor substrate 1 by a sputtering method, for example, and furthermore, a TiN film is formed on it by the sputtering method, for example.
  • silicide layers 11 a to 11 d and 12 a to 12 c are respectively formed on the gate electrodes 6 b and 6 d , the wiring 6 c and the source/drain active layers 9 a to 9 d by performing an annealing treatment in a nitride atmosphere and making the metal film and the TiN film react to a silicon material. Afterwards, the unreacted metal film and TiN film are removed selectively. Also in this step, the photo resist is formed on the entire surface of the high voltage circuit part AR 1 and the formation of the silicide layer in the high voltage circuit part AR 1 is prevented.
  • the reason why the TiN film is formed on the metal film is that an excessive silicidation of the metal film such as Ti and Co is suppressed.
  • the silicidation of the metal film such as Ti and Co is proceeded excessively, and thus the silicide layers 11 a to 11 d and 12 a to 12 c are liable to be formed thick.
  • a silicon nitride film 13 and a silicon oxide film 14 are formed respectively laminating over the entire surface of the semiconductor substrate 1 so as to cover the silicon nitride film 8 in the high voltage circuit part AR 1 , and the entire surface of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 by the CVD method, for example.
  • the silicon nitride film 13 is formed under the silicon oxide film 14 is that in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , the silicon nitride film is used as an etching stopper when an interlayer insulating film is formed and a contact hole is opened afterwards. Accordingly, the silicon nitride film 13 is not essential, however, it is desirable to form it by reason of benefit under the manufacturing process.
  • an etch-back is performed to a laminating structure of the silicon oxide film 7 , the silicon nitride film 8 , the silicon nitride film 13 and the silicon oxide film 14 selectively in the high voltage circuit part AR 1 .
  • a sidewall insulating film 10 d which includes the silicon oxide film 7 d , the silicon nitride film 8 d and 13 a and the silicon oxide film 14 a is formed on a side of the gate electrode 6 a .
  • the photo resist is formed on the entire surface of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , and in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , the etch-back to the silicon nitride film 13 and the silicon oxide film 14 is prevented.
  • the impurity injections by two stages are performed with the gate electrode 6 a and the sidewall insulating film 10 d as the mask selectively in the high voltage circuit part AR 1 .
  • both the formation of the extension region and the formation of the source/drain active layer are performed.
  • a transistor TR 3 for the high voltage circuit part is formed in the semiconductor substrate 1 .
  • P ⁇ extension regions 4 e and 4 f are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor. Afterwards, P + source/drain active layers 9 e and 9 f are formed within the forming region of the P ⁇ extension regions 4 e and 4 f by the injection of the P type impurity ion whose concentration is raised.
  • the N channel MOS transistor is not shown in the high voltage circuit part AR 1 , however, in the same manner as the case of the P channel MOS transistor, the injection of the N type impurity ion by two stages can be performed with the gate electrode and the sidewall insulating film as the mask.
  • the photo resist is formed on the entire surface of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , and in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , the formation of the extension region and the source/drain active layer is prevented.
  • the formation of the silicide layer on the gate electrode and the source/drain active layer is not performed, however, the reason for this is that an occurrence of a leakage current caused by the formation of the silicide layer is prevented.
  • an interlayer insulating film 15 which is composed of, for example, the silicon oxide film on the surface of the semiconductor substrate 1 is formed by the CVD method.
  • a surface of the interlayer insulating film 15 is flattened by a CMP (Chemical Mechanical Polishing) process etc.
  • the P + source/drain active layer 9 b and the wiring 6 c are short-circuited by a shared contact plug in the memory cell part AR 2 .
  • a contact hole 15 a in which both the P + source/drain active layer 9 b and the wiring 6 c is exposed is formed in the interlayer insulating film 15 by the photolithography technique and the etching technique.
  • the contact hole 15 a When the contact hole 15 a is opened, a part of the silicon oxide film 14 which is an underlayer of the contact hole 15 a formed in the interlayer insulating film 15 is also removed simultaneously. Moreover, it is possible to make the silicon nitride film 13 which has an etching selectivity to the silicon oxide film which composes the interlayer insulating film 15 function as an etching stopper by selecting appropriately an etchant and a temperature condition when the etching are performed.
  • the silicon nitride film 13 and the sidewall insulating film 10 b which is exposed in the contact hole 15 a are also removed by the etching.
  • the etchant and the temperature condition can be appropriately selected when the etching are performed, not to have the etching selectivity to each other.
  • a new P + active layer 16 is formed over the P + source/drain active layer 9 b by the injection of the P type impurity ion in an adjacent part of the wiring 6 c in the surface of the semiconductor substrate 1 which is exposed in the contact hole 15 a . It is not necessary that the P + active layer 16 is formed over the P + source/drain active layer 9 b , but it only has to be in contact with the P + source/drain active layer 9 b.
  • contact holes 15 b to 15 f which respectively connects with each of the source/drain active layers 9 a and 9 c to 9 f are formed in the interlayer insulating film 15 by the photolithography technique and the etching technique. Also when the contact holes 15 d to 15 f are opened, in the same manner as the case of the contact hole 15 a , it is possible to make the silicon nitride film 13 which has the etching selectivity to the silicon oxide film composing the interlayer insulating film 15 function as the etching stopper by selecting appropriately the etchant and the temperature condition when the etching are performed.
  • the metal film such as Ti etc. is formed on a surface of the interlayer insulating film 15 and a bottom surface and a side surface in the contact holes 15 a to 15 f by the sputtering method and the CVD method, and furthermore, the TiN film is formed on it by the sputtering method and the CVD method.
  • silicide layers 11 e and 11 f are formed on parts which are exposed in the contact holes 15 b and 15 c in the P + source/drain active layers 9 e and 9 f of the high voltage circuit part AR 1 by performing the annealing treatment in the ammonia atmosphere and making the metal film and the TiN film react to a silicon material.
  • the silicide layer is formed on a part which is exposed in the contact hole in the N + source/drain active layer.
  • the silicide layer is also formed on a part of non-silicidation in a surface of the P + active layer 16 which is exposed in the contact hole 15 a and a part of non-silicidation in a side surface of the wiring 6 c .
  • the Ti metal film When the Ti metal film is annealed in the ammonia atmosphere, it transforms into the TiN film, thus the TiN film is formed on the side surface of the contact holes 15 a to 15 f and the surface of the interlayer insulating film 15 .
  • the CMP process is performed on the surface of the interlayer insulating film 15 here, TiN films 17 a to 17 f remain only on the side surface of the contact holes 15 a to 15 f.
  • Co can be applied as the metal film instead of Ti, however, it is preferable to perform the annealing treatment in an Ar atmosphere in that case.
  • the silicidation can be proceeded with regard to the surface of the semiconductor substrate 1 and the side surface of the wiring 6 c such as the silicide layers 11 e , 11 f etc., however, Co on the side surface of the contact holes 15 a to 15 f and on the surface of the interlayer insulating film 15 remains unreacted.
  • the unreacted Co is removed by a certain chemical (which enables the Co silicide to remain), and then the TiN film is newly formed by the sputtering method and the CVD method.
  • the CMP process is performed on the surface of the interlayer insulating film 15 , the TiN films 17 a to 17 f remain only on the side surface of the contact holes 15 a to 15 f.
  • the metal film such as W etc. is formed by the sputtering method and the CVD method and is filled in the contact holes 15 a to 15 f enough. Further, the surface of the interlayer insulating film 15 is flattened by the CMP process, and contact plugs 18 a to 18 f are formed in the contact holes 15 a to 15 f.
  • the TiN film and the metal film such as W etc. are laminated on the surface of the interlayer insulating film 15 which is flattened. Further, this laminating film is patterned by the photolithography technique and the etching technique, and wirings composed of each laminating structure of TiN films 19 a to 19 f and metal films 20 a to 20 f are formed.
  • the contact hole 15 a in which both the P + source/drain active layer 9 b and the wiring 6 c are exposed is formed.
  • the P + active layer 16 is formed which is at least in contact with the P + source/drain active layer 9 b on the adjacent part of the wiring 6 c in the surface of the semiconductor substrate 1 which is exposed in the contact hole 15 a .
  • the contact resistance between the shared contact plug 18 a and the P + source/drain active layer 9 b can be reduced than ever.
  • the sidewall insulating film 10 b is removed.
  • the semiconductor substrate 1 which is a part under the sidewall insulating film 10 b is liable to be damaged, however in the present preferred embodiment, the P + active layer 16 is formed, thus the P + source/drain active layer 9 b can be regarded as a new active layer which is incorporated with the P + active layer 16 . According to this, a PN junction between the active layer and the semiconductor substrate 1 can be definitely formed, and an effect upon an electrical characteristic by the damage of the semiconductor substrate 1 can be reduced.
  • the MOS transistor TR 3 of the high voltage circuit part AR 1 and the MOS transistors TR 1 and TR 2 of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 can be manufactured.
  • the sidewall insulating films 10 a to 10 c are formed by the etch-back of the silicon nitride film 8
  • the sidewall insulating film 10 d is formed by the etch-back of the laminating structure of the silicon nitride film 8 and the silicon oxide film 14 .
  • the sidewall insulating film 10 d on which the silicon oxide film 14 is laminated moreover has a wider width than the sidewall insulating films 10 a to 10 c , and the forming width of the sidewall insulating film between the MOS transistor TR 3 and the MOS transistors TR 1 and TR 2 can be changed.
  • the MOS transistor TR 3 which includes the sidewall insulating film 10 d can be applied to the high voltage circuit part
  • the MOS transistors TR 1 and TR 2 which include the sidewall insulating films 10 a and 10 c can be applied to the memory cell, and thus the manufacturing method of the semiconductor device which is suited for forming the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • the semiconductor device by reason that the width of the sidewall insulating film 10 d is larger than the widths of the sidewall insulating films 10 a to 10 c , in the transistor TR 3 , the source/drain active layer can be formed in the position more distant from the gate electrode, as compared with in the MOS transistors TR 1 and TR 2 .
  • the semiconductor device which is suited for forming the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • the silicon nitride film 8 and the silicon oxide film 14 are applied as a material of the sidewall insulating film.
  • the silicon nitride film which enables prevention of a movement of metallic atoms etc. is included in all of the sidewall insulating films 10 a to 10 d , an entrance of the metallic atoms etc. to the gate electrodes of respective transistors from the contact plugs 18 a to 18 f which are connected with respective source/drain active layers can be prevented.
  • the silicon nitride films 8 a to 8 d which compose the sidewall insulating films 10 a to 10 d have an etching selectivity to the interlayer insulating film 15 which is the silicon oxide film, thus even if a slippage of an alignment occurs when each contact hole is formed in the interlayer insulating film 15 , the sidewall insulating films 10 a to 10 d are hard to be removed.
  • the sidewall insulating film 10 d has the wide width by laminating the silicon oxide film 14 a on the silicon nitride film 8 d .
  • the laminating part of the sidewall insulating film 10 d is made of the same material as the interlayer insulating film 15 , and when each contact plug is formed in the interlayer insulating film 15 , the part of the silicon oxide film 14 a in the sidewall insulating film 10 d can also be removed at the same time.
  • the contact plug is easy to be formed between the gate electrodes, even if the distance between the gate electrodes becomes short with an advance of a minuteness.
  • the present preferred embodiment is a modification example of the manufacturing method of the semiconductor device according to the first preferred embodiment, and also in the high voltage circuit part AR 1 , the sidewall insulating film which has the same structure as the sidewall insulating films 10 a to 10 c in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 is formed, and by laminating the insulating film moreover on the sidewall insulating film and performing the etch-back on this, the sidewall insulating film for the high voltage circuit part AR 1 is formed.
  • the structure shown in FIG. 1 is prepared.
  • the silicon nitride film 8 is furthermore formed on the silicon oxide film 7 over the entire surface of the semiconductor substrate 1 so as to cover the semiconductor substrate 1 , the gate electrodes 6 a , 6 b and 6 d and the wiring 6 c by the CVD method, for example.
  • the etch-back is performed on the silicon nitride film 8 and the silicon oxide film 7 in all the regions of the high voltage circuit part AR 1 , the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 .
  • the sidewall insulating film 10 a which includes the silicon nitride film 8 a and the silicon oxide film 7 a
  • the sidewall insulating film 10 b which includes the silicon nitride film 8 b and the silicon oxide film 7 b
  • the sidewall insulating film 10 c which includes the silicon nitride film 8 c and the silicon oxide film 7 c
  • a sidewall insulating film 10 e which includes a silicon nitride film 8 e and a silicon oxide film 7 e are formed in all the regions.
  • the impurity injection is performed with the gate electrodes 6 b and 6 d , the wiring 6 c and the sidewall insulating films 10 a to 10 c as the mask selectively in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 .
  • source/drain active layers 9 a to 9 d are formed in the semiconductor substrate 1 , and the transistor TR 1 for the memory cell and the transistor TR 2 for the memory cell peripheral circuit are formed.
  • the P + source/drain active layers 9 a and 9 b are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor after the sidewall insulating films 10 a and 10 b are formed.
  • the N + source/drain active layers 9 c and 9 d are formed by injecting the N type impurity ion in the forming region of the N channel MOS transistor after the sidewall insulating film 10 c is formed.
  • the photo resist is formed on the entire surface of the high voltage circuit part AR 1 , and in the high voltage circuit part AR 1 , the formation of the source/drain active layer is prevented.
  • the metal film such as Ti and Co is formed on the entire surface of the semiconductor substrate 1 by the sputtering method, for example, and furthermore, the TiN film is formed on it by the sputtering method, for example.
  • the silicide layers 11 a to 11 d and 12 a to 12 c are respectively formed on the gate, electrodes 6 b and 6 d , the wiring 6 c and the source/drain active layers 9 a to 9 d by performing the annealing treatment in the nitride atmosphere and making the metal film and the TiN film react to the silicon material. Afterwards, the unreacted metal film and TiN film are removed selectively. Also in this step, the photo resist is formed on the entire surface of the high voltage circuit part AR 1 and the formation of the silicide layer in the high voltage circuit part AR 1 is prevented.
  • a silicon nitride film 13 and a silicon oxide film 14 are formed respectively laminating over the entire surface of the semiconductor substrate 1 so as to cover the silicon nitride film 7 in the high voltage circuit part AR 1 , and the entire surface of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 by the CVD method, for example.
  • the etch-back is performed to the laminating structure of the silicon nitride film 13 and the silicon oxide film 14 selectively in the high voltage circuit part AR 1 .
  • the sidewall insulating film 10 f which includes the silicon oxide film 7 e , the silicon nitride film 8 e and 13 b and the silicon oxide film 14 b is formed on the side of the gate electrode 6 a .
  • the photo resist is formed on the entire surface of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , and in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , the etch-back to the silicon nitride film 13 and the silicon oxide film 14 is prevented.
  • the impurity injections by two stages are performed with the gate electrode 6 a and the sidewall insulating film 10 f as the mask selectively in the high voltage circuit part AR 1 .
  • both the formation of the extension region and the formation of the source/drain active layer are performed.
  • the transistor TR 3 for the high voltage circuit part is formed in the semiconductor substrate 1 .
  • P ⁇ extension regions 4 e and 4 f are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor. Afterwards, P + source/drain active layers 9 e and 9 f are formed within the forming region of the P ⁇ extension regions 4 e and 4 f by the injection of the P type impurity ion whose concentration is raised.
  • the N channel MOS transistor is not shown in the high voltage circuit part AR 1 , however, in the same manner as the case of the P channel MOS transistor, the injection of the N type impurity ion by two stages can be performed with the gate electrode and the sidewall insulating film as the mask.
  • the photo resist is formed on the entire surface of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , and in the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 , the formation of the extension region and the source/drain active layer is prevented.
  • the interlayer insulating film 15 which is composed of, for example, the silicon oxide film is formed on the surface of the semiconductor substrate 1 by the CVD method.
  • the surface of the interlayer insulating film 15 is flattened by the CMP process etc.
  • the contact hole 15 a is formed in the interlayer insulating film 15 by the photolithography technique and the etching technique. Further, the sidewall insulating film 10 b is removed by the etching. The new P + active layer 16 is also formed over the P + source/drain active layer 9 b.
  • the contact holes 15 b to 15 f are formed in the interlayer insulating film 15 by the photolithography technique and the etching technique. Furthermore, as shown in FIG. 12, in the same manner as the case of the preferred embodiment 1, the silicide layers 11 e and 11 f , the TiN films 17 a to 17 f , the contact plugs 18 a to 18 f , the TiN films 19 a to 19 f and the metal films 20 a to 20 f are formed.
  • the sidewall insulating film 10 f on which the laminating structure of the silicon nitride film 13 b and the silicon oxide film 14 b is laminated moreover has a wider width than the sidewall insulating films 10 a to 10 c , and the forming width of the sidewall insulating film between the MOS transistor TR 3 and the MOS transistors TR 1 and TR 2 can be changed.
  • the MOS transistor TR 3 which includes the sidewall insulating film 10 f can be applied to the high voltage circuit part
  • the MOS transistors TR 1 and TR 2 which includes the sidewall insulating films 10 a and 10 c can be applied to the memory cell, and thus the manufacturing method of the semiconductor device which is suited for forming the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • the polysilicon film is illustrated by example as the material of the gate electrodes 6 a , 6 b and 6 d and the wiring 6 c , and moreover, the silicide layer is formed on the gate electrodes 6 b and 6 d and the wiring 6 c in the regions of the memory cell part AR 2 and the memory cell peripheral circuit part AR 3 .
  • the present invention is not limited to have such a structure of the gate electrode and the wiring, but as shown in FIG. 13, it can also have a structure that the silicide layer is not formed and as shown in FIG. 14, it can also have a structure that the gate electrode 6 b 1 and the wiring 6 c 1 which are formed of the metal film such as Ti, Co, W etc. instead of the polysilicon film are included, for example.
  • the present invention can also have a structure that the silicide layer is moreover formed on the gate electrode 6 b 1 and the wiring 6 c 1 of the metal film in FIG. 14 and that the silicide layer of each source/drain active layer is omitted (none of them are illustrated.)
  • FIGS. 13 and 14 only the memory cell part AR 2 is illustrated to simplify the drawings, however, the structure of the gate electrode and the wiring is also the same with regard to the other regions.

Abstract

A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electrical characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer (16) is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug (18 a). An insulating film is laminated in a high voltage circuit part (AR1) and a sidewall insulating film (10 d) of wide width is formed. According to this, a forming width of a sidewall insulating film (10 a) can be made small in a MOS transistor for a memory cell part (AR2), and a forming width of a sidewall insulating film (10 d) can be made large in a MOS transistor for a high voltage circuit part. Thereupon, in the high voltage circuit part (AR1), a source/drain active layer can be formed in the position more distant from a gate electrode.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a semiconductor device which includes MOS (Metal Oxide Semiconductor) transistors, wirings etc. and a manufacturing method thereof. [0002]
  • 2. Description of the Background Art [0003]
  • Conventionally, a semiconductor device which includes MOS transistors, wirings etc. is manufactured by performing an impurity injection in a semiconductor substrate and forming an insulating film and a conductive film on a surface of the semiconductor substrate. [0004]
  • Information of conventional art documents which relates to the invention of the present application is described below. [0005]
  • Japanese Patent Application Laid-Open No. 2000-353803 [0006]
  • Japanese Patent Application Laid-Open No. 2002-231821 [0007]
  • K. Imai et al., “CMOS device optimization for system-on-a-chip applications”, (U.S.A.), IEDM, 2000, p. 455-458 [0008]
  • H. Watanabe et al., “Novel 0.44 μm[0009] 2 Ti-Salicide STI Cell Technology for high-Density NOR Flash Memories and Performance Embedded Application”, (U.S.A.), IEDM, 1998, p. 975-976
  • It is general that an active layer which becomes a source/drain region of a MOS transistor is composed of an extension region and a region whose impurity concentration is higher than that of the extension region. The high impurity concentration region is formed by forming a sidewall insulating film on a side of a gate electrode after forming the extension region and performing an impurity injection with the gate electrode and the sidewall insulating film as a mask. Thus, a position where the high impurity concentration region is formed is determined by a forming width of the sidewall insulating film in a channel direction of the transistor. [0010]
  • Generally, with regard to a MOS transistor which is used for a memory cell in a SRAM (Static Random Access Memory) etc., the high impurity concentration region is widely formed so that it is distributed close to the gate electrode. It is performed by reason of reducing a resistance value in the source/drain region. Therefore, the forming width of the sidewall insulating film is arranged to be a small value. [0011]
  • In the meantime, with regard to a MOS transistor which is used for a high voltage circuit part, the high impurity concentration region is formed distant from the gate electrode as compared with a case of the MOS transistor for the memory cell. It is because, with regard to the high voltage circuit part, it is desirable that the high impurity concentration region is distant from the gate electrode to prevent a phenomenon, that is so-called GIDL (Gate Induced Drain Leakage) generation (a phenomenon that when a high voltage is applied to a gate, atoms which are stably existent in a drain region separates into holes and electrons, and thus a leakage current flows between a drain and a substrate). Therefore, the forming width of the sidewall insulating film is arranged to be a large value. [0012]
  • In the meantime, there is a case that both the MOS transistor for the memory cell and the MOS transistor for the high voltage circuit part are formed on one semiconductor substrate. In this case, it is general that both types of the MOS transistors are formed in the same step without adding the number of steps, and the forming widths of the sidewall insulating films are determined to be identical. In other words, the forming width of the sidewall insulating film is arranged to be a value fitting to either of the MOS transistors. Generally, in order to give priority to preventing a drain voltage breakdown in the high voltage circuit part, the forming width of the sidewall insulating film is determined to suit to the MOS transistor for the high voltage circuit part. [0013]
  • However, essentially as described above, it is desirable to make small the forming width of the sidewall insulating film in the MOS transistor for the memory cell and make large the forming width of the sidewall insulating film in the MOS transistor for the high voltage circuit part. [0014]
  • Moreover, there is a case that the active layer such as the source/drain region etc. which is formed by performing the impurity injection into the semiconductor substrate and the wiring which is formed near the active layer on the semiconductor substrate are short-circuited by a shared contact plug. In that time, as described in FIG. 23 of the patent document No. 2000-353803, there is a case that the sidewall insulating film formed on a side of the wiring is removed. [0015]
  • When the sidewall insulating film is removed as described above, a problem arises as described below. In other words, under the sidewall insulating film, the active layer has a low impurity concentration caused by a low injection rate of the impurity, and thus a value of a contact resistance between that part of the active layer and the shared contact plug is liable to become high. Moreover, a part of the semiconductor substrate which is under the sidewall insulating film is liable to be damaged caused by an etching when the sidewall insulating film is removed, therefore, a PN junction between the active layer and the semiconductor substrate is not definitely formed, and a junction leakage current often increases. [0016]
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electrical characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed. [0017]
  • According to the first aspect of the present invention, a manufacturing method of a semiconductor device includes the following steps (a) to (f) [0018]
  • (a) A conductive film is formed on a semiconductor substrate. [0019]
  • (b) The conductive film is patterned by a photolithography technique and an etching technique. [0020]
  • (c) A first active layer is formed by performing an impurity injection in proximity of the patterned conductive film in a surface of the semiconductor substrate. [0021]
  • (d) An interlayer insulating film is formed on a surface of the semiconductor substrate. [0022]
  • (e) A contact hole in which both the first active layer and the conductive film are exposed is formed in the interlayer insulating film by a photolithography technique and an etching technique. [0023]
  • (f) A second active layer is formed by performing an impurity injection on a surface of the semiconductor substrate which is exposed in the contact hole. [0024]
  • The contact hole in which both the first active layer and the conductive film are exposed is formed, and the second active layer is formed on the surface of the semiconductor substrate which is exposed in the contact hole. By reason of forming the second active layer, when a conductive substance is filled in the contact hole and a shared contact plug which conducts to both the first active layer and the conductive film is formed, a contact resistance between the shared contact plug and the first active layer can be reduced than ever. [0025]
  • According to the second aspect of the present invention, [0026]
  • a semiconductor device includes a semiconductor substrate, a first transistor and a second transistor. [0027]
  • The first transistor includes a first gate electrode which is formed on the semiconductor substrate, a first sidewall insulating film which is formed on a side of the first gate electrode on the semiconductor substrate and first source/drain active layers which are formed in the semiconductor substrate. [0028]
  • The second transistor includes a second gate electrode which is formed on the semiconductor substrate, a second sidewall insulating film which is formed on a side of the second gate electrode on the semiconductor substrate and second source/drain active layers which are formed in the semiconductor substrate. [0029]
  • Layers of an insulating film which composes the second sidewall insulating film are more in number than layers of an insulating film which composes the first sidewall insulating film, and accordingly, a width of the second sidewall insulating film in a channel direction of the second transistor is larger than a width of the first sidewall insulating film in a channel direction of the first transistor. [0030]
  • By reason that the width of the second sidewall insulating film is larger than the width of the first sidewall insulating film, in the second transistor, the source/drain active layer can be formed in the position more distant from the gate electrode as compared with the first transistor. Thus, while using the second transistor for a high voltage circuit part and the first transistor for a memory cell, a semiconductor device which is suited for forming both the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained. [0031]
  • These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.[0032]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0033] 1 to 7 are drawings all illustrating a manufacturing method of a semiconductor device according to the first preferred embodiment.
  • FIGS. [0034] 8 to 12 are drawings all illustrating a manufacturing method of a semiconductor device according to the second preferred embodiment.
  • FIGS. 13 and 14 are drawings both illustrating a modification example of the semiconductor device according to the first or second preferred embodiment.[0035]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • <First Preferred Embodiment>[0036]
  • The present preferred embodiment is a manufacturing method of a semiconductor device that an additional impurity injection on a part where a sidewall insulating film is removed in a shared contact plug forming portion is performed. With regard to the manufacturing method of the semiconductor device according to the present preferred embodiment, an insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film is made small in a MOS transistor for a memory cell, and a forming width of a sidewall insulating film is made large in a MOS transistor for the high voltage circuit part. [0037]
  • FIGS. [0038] 1 to 7 are drawings all illustrating a manufacturing method of a semiconductor device according to the present preferred embodiment. The present preferred embodiment is described below using these drawings.
  • At first, with reference to FIG. 1, a [0039] semiconductor substrate 1 such as a silicon substrate etc. which is separated into a high voltage circuit part AR1, a memory cell part AR2 and a memory cell peripheral circuit part AR3 is prepared. A P type impurity ion such as Boron etc. is injected in the whole of the semiconductor substrate 1.
  • Next, [0040] element isolation regions 2 and 2 a to isolate each element are formed on each certain region of a surface of the semiconductor substrate 1. The element isolation regions 2 and 2 a are formed of an insulating film such as a silicon oxide film etc. Then, in each part of the high voltage circuit part AR1, the memory cell part AR2 and the memory cell peripheral circuit part AR3, the P type impurity ion such as Boron etc. is injected in the region where a N channel type MOS transistor is to be formed, and a N type impurity ion such as phosphorus, arsenic etc. is injected in the region where a P channel type MOS transistor is to be formed. According to this, N type wells 3 a and 3 b and a P type well 3 c are formed in each region.
  • With regard to the injection of the impurity ion, with patterning a photo resist into a desired shape by a photolithography technique, an ion injection can be performed to the desired portion with the patterned photo resist as a mask. The same may be said of the injection of the other impurity ions described below. [0041]
  • Moreover, in FIGS. [0042] 1 to 7, for a simplification of drawings, only a part of the N type wells are illustrated in the high voltage circuit part AR1 and the memory cell part AR2, and only a part of the P type well is illustrated in the memory cell peripheral circuit part AR3. However, as a matter of course, the P type wells are also formed in the high voltage circuit part AR1 and the memory cell part AR2, and the N type well is also formed in the memory cell peripheral circuit part AR3. Further, the N channel MOS transistor can be formed on the P type well and the P chancel MOS transistor can be formed on the N type well.
  • Next, [0043] gate insulating films 5 a to 5 c are formed by a thermal oxidation treatment on a surface of the semiconductor substrate 1 except for the forming part of the element isolation regions 2 and 2 a. Afterwards, a conductive film such as a polysilicon film etc. is formed on the entire surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method, for example, and is patterned into a desired shape by a photolithography technique and an etching technique. According to this, gate electrodes 6 a, 6 b and 6 d and a wiring 6 c are formed. Although the wiring 6 c has a shape which is partly run upon the element isolation region 2 a, as a matter of course, it is not necessary to make it shape like this.
  • Moreover, prior to patterning the polysilicon film described above, in the polysilicon film, the P type impurity ion has to be injected only in a part to be the gate electrode and the wiring on the P type well, and the N type impurity ion has to be injected only in a part to be the gate electrode and the wiring on the N type well. Then, the [0044] gate electrodes 6 a and 6 b and the wiring 6 c become an N+ doped polysilicon gate and the gate electrode 6 d becomes a P+ doped polysilicon gate.
  • Next, in the memory cell part AR[0045] 2 and the memory cell peripheral circuit part AR3, extension regions 4 a to 4 d are formed with the element isolation regions 2 and 2 a, the gate electrodes 6 b and 6 d and the wiring 6 c as the masks. More particularly, in both regions, P− extension regions 4 a and 4 b are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor. In the meantime, N− extension regions 4 c and 4 d are formed by injecting the N type impurity ion in the forming region of the N channel MOS transistor. In this step, the photo resist is formed on the entire surface of the high voltage circuit part AR1 and the injection of the impurity ion in the high voltage circuit part AR1 is prevented.
  • Further, a [0046] silicon oxide film 7 is formed over the entire surface of the semiconductor substrate 1 so as to cover the semiconductor substrate 1, the gate electrodes 6 a, 6 b and 6 d and the wiring 6 c by the CVD method, for example.
  • Next, with reference to FIG. 2, a [0047] silicon nitride film 8 is furthermore formed on the silicon oxide film 7 over the entire surface of the semiconductor substrate 1 so as to cover the semiconductor substrate 1, the gate electrodes 6 a, 6 b and 6 d and the wiring 6 c by the CVD method, for example.
  • The reason why the [0048] silicon oxide film 7 is formed under the silicon nitride film 8 is that a stress which the silicon nitride film 8 exerts on the semiconductor substrate 1 is relaxed. Accordingly, the silicon oxide film 7 is not essential, however, it is desirable to form it to prevent a deterioration of a device characteristic.
  • Further, an etch-back is performed to the [0049] silicon nitride film 8 and the silicon oxide film 7 selectively in the memory cell part AR2 and the memory cell peripheral circuit part AR3. According to this, in both regions, a sidewall insulating film 10 a which includes a silicon nitride film 8 a and a silicon oxide film 7 a, a sidewall insulating film 10 b which includes a silicon nitride film 8 b and a silicon oxide film 7 b and a sidewall insulating film 10 c which includes a silicon nitride film 8 c and a silicon oxide film 7 c are formed. In this step, the photo resist is formed on the entire surface of the high voltage circuit part AR1 and the formation of the sidewall insulating film in the high voltage circuit part AR1 is prevented.
  • Further, an impurity injection is performed with the [0050] gate electrodes 6 b and 6 d, the wiring 6 c and the sidewall insulating films 10 a to 10 c as the masks selectively in the memory cell part AR2 and the memory cell peripheral circuit part AR3. According to this, source/drain active layers 9 a to 9 d are formed in the semiconductor substrate 1, and a transistor TR1 for the memory cell and a transistor TR2 for the memory cell peripheral circuit are formed.
  • More particularly, in both regions, P[0051] + source/drain active layers 9 a and 9 b are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor after forming the sidewall insulating films 10 a and 10 b. In the meantime, N+ source/drain active layers 9 c and 9 d are formed by injecting the N type impurity ion in the forming region of the N channel MOS transistor after forming the sidewall insulating film 10 c. Also in this step, the photo resist is formed on the entire surface of the high voltage circuit part AR1 and the formation of the source/drain active layer in the high voltage circuit part AR1 is prevented.
  • Further, a metal film such as Ti and Co is formed on the entire surface of the [0052] semiconductor substrate 1 by a sputtering method, for example, and furthermore, a TiN film is formed on it by the sputtering method, for example.
  • Further, silicide layers [0053] 11 a to 11 d and 12 a to 12 c are respectively formed on the gate electrodes 6 b and 6 d, the wiring 6 c and the source/drain active layers 9 a to 9 d by performing an annealing treatment in a nitride atmosphere and making the metal film and the TiN film react to a silicon material. Afterwards, the unreacted metal film and TiN film are removed selectively. Also in this step, the photo resist is formed on the entire surface of the high voltage circuit part AR1 and the formation of the silicide layer in the high voltage circuit part AR1 is prevented.
  • The reason why the TiN film is formed on the metal film is that an excessive silicidation of the metal film such as Ti and Co is suppressed. When the TiN film is not formed, the silicidation of the metal film such as Ti and Co is proceeded excessively, and thus the silicide layers [0054] 11 a to 11 d and 12 a to 12 c are liable to be formed thick.
  • Next, with reference to FIG. 3, a [0055] silicon nitride film 13 and a silicon oxide film 14 are formed respectively laminating over the entire surface of the semiconductor substrate 1 so as to cover the silicon nitride film 8 in the high voltage circuit part AR1, and the entire surface of the memory cell part AR2 and the memory cell peripheral circuit part AR3 by the CVD method, for example.
  • The reason why the [0056] silicon nitride film 13 is formed under the silicon oxide film 14 is that in the memory cell part AR2 and the memory cell peripheral circuit part AR3, the silicon nitride film is used as an etching stopper when an interlayer insulating film is formed and a contact hole is opened afterwards. Accordingly, the silicon nitride film 13 is not essential, however, it is desirable to form it by reason of benefit under the manufacturing process.
  • Further, an etch-back is performed to a laminating structure of the [0057] silicon oxide film 7, the silicon nitride film 8, the silicon nitride film 13 and the silicon oxide film 14 selectively in the high voltage circuit part AR1. According to this, as shown in FIG. 4, a sidewall insulating film 10 d which includes the silicon oxide film 7 d, the silicon nitride film 8 d and 13 a and the silicon oxide film 14 a is formed on a side of the gate electrode 6 a. In this step, the photo resist is formed on the entire surface of the memory cell part AR2 and the memory cell peripheral circuit part AR3, and in the memory cell part AR2 and the memory cell peripheral circuit part AR3, the etch-back to the silicon nitride film 13 and the silicon oxide film 14 is prevented.
  • Further, the impurity injections by two stages are performed with the [0058] gate electrode 6 a and the sidewall insulating film 10 d as the mask selectively in the high voltage circuit part AR1. In other words, both the formation of the extension region and the formation of the source/drain active layer are performed. According to this, a transistor TR3 for the high voltage circuit part is formed in the semiconductor substrate 1.
  • More particularly, in the high voltage circuit part AR[0059] 1, P− extension regions 4 e and 4 f are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor. Afterwards, P+ source/drain active layers 9 e and 9 f are formed within the forming region of the P− extension regions 4 e and 4 f by the injection of the P type impurity ion whose concentration is raised. The N channel MOS transistor is not shown in the high voltage circuit part AR1, however, in the same manner as the case of the P channel MOS transistor, the injection of the N type impurity ion by two stages can be performed with the gate electrode and the sidewall insulating film as the mask.
  • Also in this step, the photo resist is formed on the entire surface of the memory cell part AR[0060] 2 and the memory cell peripheral circuit part AR3, and in the memory cell part AR2 and the memory cell peripheral circuit part AR3, the formation of the extension region and the source/drain active layer is prevented.
  • With regard to the MOS transistor in the high voltage circuit part AR[0061] 1, the formation of the silicide layer on the gate electrode and the source/drain active layer is not performed, however, the reason for this is that an occurrence of a leakage current caused by the formation of the silicide layer is prevented.
  • Next, with reference to FIG. 5, an [0062] interlayer insulating film 15 which is composed of, for example, the silicon oxide film on the surface of the semiconductor substrate 1 is formed by the CVD method. A surface of the interlayer insulating film 15 is flattened by a CMP (Chemical Mechanical Polishing) process etc.
  • In the meantime, with regard to the present preferred embodiment, the P[0063] + source/drain active layer 9 b and the wiring 6 c are short-circuited by a shared contact plug in the memory cell part AR2. For that purpose, a contact hole 15 a in which both the P+ source/drain active layer 9 b and the wiring 6 c is exposed is formed in the interlayer insulating film 15 by the photolithography technique and the etching technique.
  • When the [0064] contact hole 15 a is opened, a part of the silicon oxide film 14 which is an underlayer of the contact hole 15 a formed in the interlayer insulating film 15 is also removed simultaneously. Moreover, it is possible to make the silicon nitride film 13 which has an etching selectivity to the silicon oxide film which composes the interlayer insulating film 15 function as an etching stopper by selecting appropriately an etchant and a temperature condition when the etching are performed.
  • Next, the [0065] silicon nitride film 13 and the sidewall insulating film 10 b which is exposed in the contact hole 15 a are also removed by the etching. In this case, in order to be able to remove both the silicon nitride film 8 b and the silicon oxide film 7 b which compose the sidewall insulating film 10 b, the etchant and the temperature condition can be appropriately selected when the etching are performed, not to have the etching selectivity to each other. In this case, it is possible to make the silicide layers 11 b and 12 b and the P+ source/drain active layer 9 b function as the etching stopper.
  • Next, a new P[0066] + active layer 16 is formed over the P+ source/drain active layer 9 b by the injection of the P type impurity ion in an adjacent part of the wiring 6 c in the surface of the semiconductor substrate 1 which is exposed in the contact hole 15 a. It is not necessary that the P+ active layer 16 is formed over the P+ source/drain active layer 9 b, but it only has to be in contact with the P+ source/drain active layer 9 b.
  • Further, as shown in FIG. 6, contact holes [0067] 15 b to 15 f which respectively connects with each of the source/drain active layers 9 a and 9 c to 9 f are formed in the interlayer insulating film 15 by the photolithography technique and the etching technique. Also when the contact holes 15 d to 15 f are opened, in the same manner as the case of the contact hole 15 a, it is possible to make the silicon nitride film 13 which has the etching selectivity to the silicon oxide film composing the interlayer insulating film 15 function as the etching stopper by selecting appropriately the etchant and the temperature condition when the etching are performed.
  • Next, with reference to FIG. 7, the metal film such as Ti etc. is formed on a surface of the [0068] interlayer insulating film 15 and a bottom surface and a side surface in the contact holes 15 a to 15 f by the sputtering method and the CVD method, and furthermore, the TiN film is formed on it by the sputtering method and the CVD method.
  • Further, silicide layers [0069] 11 e and 11 f are formed on parts which are exposed in the contact holes 15 b and 15 c in the P+ source/drain active layers 9 e and 9 f of the high voltage circuit part AR1 by performing the annealing treatment in the ammonia atmosphere and making the metal film and the TiN film react to a silicon material. Not shown in FIG. 7, in this time, also in the N channel MOS transistor of the high voltage circuit part AR1, the silicide layer is formed on a part which is exposed in the contact hole in the N+ source/drain active layer.
  • In this time, the silicide layer is also formed on a part of non-silicidation in a surface of the P[0070] + active layer 16 which is exposed in the contact hole 15 a and a part of non-silicidation in a side surface of the wiring 6 c. According to this, the silicide layer 11 b already formed and the silicide layer newly formed on the surface of the P+ active layer 16 join each other and thus a region of the silicide layer 11 b is enlarged to an adjacent part of the wiring 6 c, and the silicide layer 12 b already formed and the silicide layer newly formed on a part of the side surface of the wiring 6 c join each other and thus a region of the silicide layer 12 b is enlarged to a surface part of the semiconductor substrate 1.
  • With regard to the other contact holes [0071] 15 d to 15 f where the silicide layer has already been formed on their bottom surface, there is scarcely a reaction of the silicidation.
  • When the Ti metal film is annealed in the ammonia atmosphere, it transforms into the TiN film, thus the TiN film is formed on the side surface of the contact holes [0072] 15 a to 15 f and the surface of the interlayer insulating film 15. When the CMP process is performed on the surface of the interlayer insulating film 15 here, TiN films 17 a to 17 f remain only on the side surface of the contact holes 15 a to 15 f.
  • Co can be applied as the metal film instead of Ti, however, it is preferable to perform the annealing treatment in an Ar atmosphere in that case. In this case, the silicidation can be proceeded with regard to the surface of the [0073] semiconductor substrate 1 and the side surface of the wiring 6 c such as the silicide layers 11 e, 11 f etc., however, Co on the side surface of the contact holes 15 a to 15 f and on the surface of the interlayer insulating film 15 remains unreacted. Thus, the unreacted Co is removed by a certain chemical (which enables the Co silicide to remain), and then the TiN film is newly formed by the sputtering method and the CVD method. Further, when the CMP process is performed on the surface of the interlayer insulating film 15, the TiN films 17 a to 17 f remain only on the side surface of the contact holes 15 a to 15 f.
  • Further, the metal film such as W etc. is formed by the sputtering method and the CVD method and is filled in the contact holes [0074] 15 a to 15 f enough. Further, the surface of the interlayer insulating film 15 is flattened by the CMP process, and contact plugs 18 a to 18 f are formed in the contact holes 15 a to 15 f.
  • Further, the TiN film and the metal film such as W etc. are laminated on the surface of the [0075] interlayer insulating film 15 which is flattened. Further, this laminating film is patterned by the photolithography technique and the etching technique, and wirings composed of each laminating structure of TiN films 19 a to 19 f and metal films 20 a to 20 f are formed.
  • According to the manufacturing method of the semiconductor device according to the present preferred embodiment, the [0076] contact hole 15 a in which both the P+ source/drain active layer 9 b and the wiring 6 c are exposed is formed. And the P+ active layer 16 is formed which is at least in contact with the P+ source/drain active layer 9 b on the adjacent part of the wiring 6 c in the surface of the semiconductor substrate 1 which is exposed in the contact hole 15 a. By reason of forming the P+ active layer 16, when the metal film such as W etc. is filled in the contact hole 15 a and the shared contact plug 18 a conductive to both the P+ source/drain active layer 9 b and the wiring 6 c is formed, the contact resistance between the shared contact plug 18 a and the P+ source/drain active layer 9 b can be reduced than ever.
  • In the present preferred embodiment, when the [0077] contact hole 15 a is formed, the sidewall insulating film 10 b is removed. When the sidewall insulating film 10 b is removed, the semiconductor substrate 1 which is a part under the sidewall insulating film 10 b is liable to be damaged, however in the present preferred embodiment, the P+ active layer 16 is formed, thus the P+ source/drain active layer 9 b can be regarded as a new active layer which is incorporated with the P+ active layer 16. According to this, a PN junction between the active layer and the semiconductor substrate 1 can be definitely formed, and an effect upon an electrical characteristic by the damage of the semiconductor substrate 1 can be reduced. As a result, an increase of a junction leakage current can be suppressed, and thus a semiconductor device which has little deterioration of the electrical characteristic can be obtained, even if it has a structure that the sidewall insulating film in the shared contact plug part is removed.
  • Furthermore, according to the manufacturing method of the semiconductor device according to the present preferred embodiment, the MOS transistor TR[0078] 3 of the high voltage circuit part AR1 and the MOS transistors TR1 and TR2 of the memory cell part AR2 and the memory cell peripheral circuit part AR3 can be manufactured. Moreover, the sidewall insulating films 10 a to 10 c are formed by the etch-back of the silicon nitride film 8, and the sidewall insulating film 10 d is formed by the etch-back of the laminating structure of the silicon nitride film 8 and the silicon oxide film 14.
  • Thus, the [0079] sidewall insulating film 10 d on which the silicon oxide film 14 is laminated moreover has a wider width than the sidewall insulating films 10 a to 10 c, and the forming width of the sidewall insulating film between the MOS transistor TR3 and the MOS transistors TR1 and TR2 can be changed. In other words, the MOS transistor TR3 which includes the sidewall insulating film 10 d can be applied to the high voltage circuit part, the MOS transistors TR1 and TR2 which include the sidewall insulating films 10 a and 10 c can be applied to the memory cell, and thus the manufacturing method of the semiconductor device which is suited for forming the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • Furthermore, according to the semiconductor device according to the present preferred embodiment, by reason that the width of the [0080] sidewall insulating film 10 d is larger than the widths of the sidewall insulating films 10 a to 10 c, in the transistor TR3, the source/drain active layer can be formed in the position more distant from the gate electrode, as compared with in the MOS transistors TR1 and TR2. Thus, the semiconductor device which is suited for forming the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • Furthermore, according to the manufacturing method of the semiconductor device according to the present preferred embodiment, the [0081] silicon nitride film 8 and the silicon oxide film 14 are applied as a material of the sidewall insulating film. By reason that the silicon nitride film which enables prevention of a movement of metallic atoms etc. is included in all of the sidewall insulating films 10 a to 10 d, an entrance of the metallic atoms etc. to the gate electrodes of respective transistors from the contact plugs 18 a to 18 f which are connected with respective source/drain active layers can be prevented.
  • The [0082] silicon nitride films 8 a to 8 d which compose the sidewall insulating films 10 a to 10 d have an etching selectivity to the interlayer insulating film 15 which is the silicon oxide film, thus even if a slippage of an alignment occurs when each contact hole is formed in the interlayer insulating film 15, the sidewall insulating films 10 a to 10 d are hard to be removed.
  • In the meantime, the [0083] sidewall insulating film 10 d has the wide width by laminating the silicon oxide film 14 a on the silicon nitride film 8 d. Thus, the laminating part of the sidewall insulating film 10 d is made of the same material as the interlayer insulating film 15, and when each contact plug is formed in the interlayer insulating film 15, the part of the silicon oxide film 14 a in the sidewall insulating film 10 d can also be removed at the same time. Thereupon, in case that the plural MOS transistors are formed proximately in the high voltage circuit part AR1, the contact plug is easy to be formed between the gate electrodes, even if the distance between the gate electrodes becomes short with an advance of a minuteness.
  • <Second Preferred Embodiment>[0084]
  • The present preferred embodiment is a modification example of the manufacturing method of the semiconductor device according to the first preferred embodiment, and also in the high voltage circuit part AR[0085] 1, the sidewall insulating film which has the same structure as the sidewall insulating films 10 a to 10 c in the memory cell part AR2 and the memory cell peripheral circuit part AR3 is formed, and by laminating the insulating film moreover on the sidewall insulating film and performing the etch-back on this, the sidewall insulating film for the high voltage circuit part AR1 is formed.
  • At first, in the same manner as the case of the first preferred embodiment, the structure shown in FIG. 1 is prepared. Next, the [0086] silicon nitride film 8 is furthermore formed on the silicon oxide film 7 over the entire surface of the semiconductor substrate 1 so as to cover the semiconductor substrate 1, the gate electrodes 6 a, 6 b and 6 d and the wiring 6 c by the CVD method, for example.
  • Further, with reference to FIG. 8, the etch-back is performed on the [0087] silicon nitride film 8 and the silicon oxide film 7 in all the regions of the high voltage circuit part AR1, the memory cell part AR2 and the memory cell peripheral circuit part AR3. According to this, the sidewall insulating film 10 a which includes the silicon nitride film 8 a and the silicon oxide film 7 a, the sidewall insulating film 10 b which includes the silicon nitride film 8 b and the silicon oxide film 7 b, the sidewall insulating film 10 c which includes the silicon nitride film 8 c and the silicon oxide film 7 c and a sidewall insulating film 10 e which includes a silicon nitride film 8 e and a silicon oxide film 7 e are formed in all the regions.
  • Further, the impurity injection is performed with the [0088] gate electrodes 6 b and 6 d, the wiring 6 c and the sidewall insulating films 10 a to 10 c as the mask selectively in the memory cell part AR2 and the memory cell peripheral circuit part AR3. According to this, source/drain active layers 9 a to 9 d are formed in the semiconductor substrate 1, and the transistor TR1 for the memory cell and the transistor TR2 for the memory cell peripheral circuit are formed.
  • More particularly, in both regions, the P[0089] + source/drain active layers 9 a and 9 b are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor after the sidewall insulating films 10 a and 10 b are formed. In the meantime, the N+ source/drain active layers 9 c and 9 d are formed by injecting the N type impurity ion in the forming region of the N channel MOS transistor after the sidewall insulating film 10 c is formed. In this step, the photo resist is formed on the entire surface of the high voltage circuit part AR1, and in the high voltage circuit part AR1, the formation of the source/drain active layer is prevented.
  • Further, the metal film such as Ti and Co is formed on the entire surface of the [0090] semiconductor substrate 1 by the sputtering method, for example, and furthermore, the TiN film is formed on it by the sputtering method, for example.
  • Further, the silicide layers [0091] 11 a to 11 d and 12 a to 12 c are respectively formed on the gate, electrodes 6 b and 6 d, the wiring 6 c and the source/drain active layers 9 a to 9 d by performing the annealing treatment in the nitride atmosphere and making the metal film and the TiN film react to the silicon material. Afterwards, the unreacted metal film and TiN film are removed selectively. Also in this step, the photo resist is formed on the entire surface of the high voltage circuit part AR1 and the formation of the silicide layer in the high voltage circuit part AR1 is prevented.
  • Next, a [0092] silicon nitride film 13 and a silicon oxide film 14 are formed respectively laminating over the entire surface of the semiconductor substrate 1 so as to cover the silicon nitride film 7 in the high voltage circuit part AR1, and the entire surface of the memory cell part AR2 and the memory cell peripheral circuit part AR3 by the CVD method, for example.
  • Further, the etch-back is performed to the laminating structure of the [0093] silicon nitride film 13 and the silicon oxide film 14 selectively in the high voltage circuit part AR1. According to this, as shown in FIG. 9, the sidewall insulating film 10 f which includes the silicon oxide film 7 e, the silicon nitride film 8 e and 13 b and the silicon oxide film 14 b is formed on the side of the gate electrode 6 a. In this step, the photo resist is formed on the entire surface of the memory cell part AR2 and the memory cell peripheral circuit part AR3, and in the memory cell part AR2 and the memory cell peripheral circuit part AR3, the etch-back to the silicon nitride film 13 and the silicon oxide film 14 is prevented.
  • Further, the impurity injections by two stages are performed with the [0094] gate electrode 6 a and the sidewall insulating film 10 f as the mask selectively in the high voltage circuit part AR1. In other words, both the formation of the extension region and the formation of the source/drain active layer are performed. According to this, the transistor TR3 for the high voltage circuit part is formed in the semiconductor substrate 1.
  • More particularly, in the high voltage circuit part AR[0095] 1, P− extension regions 4 e and 4 f are formed by injecting the P type impurity ion in the forming region of the P channel MOS transistor. Afterwards, P+ source/drain active layers 9 e and 9 f are formed within the forming region of the P− extension regions 4 e and 4 f by the injection of the P type impurity ion whose concentration is raised. The N channel MOS transistor is not shown in the high voltage circuit part AR1, however, in the same manner as the case of the P channel MOS transistor, the injection of the N type impurity ion by two stages can be performed with the gate electrode and the sidewall insulating film as the mask.
  • Also in this step, the photo resist is formed on the entire surface of the memory cell part AR[0096] 2 and the memory cell peripheral circuit part AR3, and in the memory cell part AR2 and the memory cell peripheral circuit part AR3, the formation of the extension region and the source/drain active layer is prevented.
  • Next, with reference to FIG. 10, the [0097] interlayer insulating film 15 which is composed of, for example, the silicon oxide film is formed on the surface of the semiconductor substrate 1 by the CVD method. The surface of the interlayer insulating film 15 is flattened by the CMP process etc.
  • Afterwards, in the same manner as the case of the [0098] preferred embodiment 1, the contact hole 15 a is formed in the interlayer insulating film 15 by the photolithography technique and the etching technique. Further, the sidewall insulating film 10 b is removed by the etching. The new P+ active layer 16 is also formed over the P+ source/drain active layer 9 b.
  • Further, as shown in FIG. 11, the contact holes [0099] 15 b to 15 f are formed in the interlayer insulating film 15 by the photolithography technique and the etching technique. Furthermore, as shown in FIG. 12, in the same manner as the case of the preferred embodiment 1, the silicide layers 11 e and 11 f, the TiN films 17 a to 17 f, the contact plugs 18 a to 18 f, the TiN films 19 a to 19 f and the metal films 20 a to 20 f are formed.
  • Also in the present preferred embodiment, the [0100] sidewall insulating film 10 f on which the laminating structure of the silicon nitride film 13 b and the silicon oxide film 14 b is laminated moreover has a wider width than the sidewall insulating films 10 a to 10 c, and the forming width of the sidewall insulating film between the MOS transistor TR3 and the MOS transistors TR1 and TR2 can be changed. In other words, the MOS transistor TR3 which includes the sidewall insulating film 10 f can be applied to the high voltage circuit part, the MOS transistors TR1 and TR2 which includes the sidewall insulating films 10 a and 10 c can be applied to the memory cell, and thus the manufacturing method of the semiconductor device which is suited for forming the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
  • The other effect is the same as that of the first preferred embodiment. [0101]
  • <The Others>[0102]
  • With regard to the preferred embodiment described above, the polysilicon film is illustrated by example as the material of the [0103] gate electrodes 6 a, 6 b and 6 d and the wiring 6 c, and moreover, the silicide layer is formed on the gate electrodes 6 b and 6 d and the wiring 6 c in the regions of the memory cell part AR2 and the memory cell peripheral circuit part AR3.
  • However, as a matter of course, the present invention is not limited to have such a structure of the gate electrode and the wiring, but as shown in FIG. 13, it can also have a structure that the silicide layer is not formed and as shown in FIG. 14, it can also have a structure that the [0104] gate electrode 6 b 1 and the wiring 6 c 1 which are formed of the metal film such as Ti, Co, W etc. instead of the polysilicon film are included, for example.
  • Otherwise, the present invention can also have a structure that the silicide layer is moreover formed on the [0105] gate electrode 6 b 1 and the wiring 6 c 1 of the metal film in FIG. 14 and that the silicide layer of each source/drain active layer is omitted (none of them are illustrated.)
  • In FIGS. 13 and 14, only the memory cell part AR[0106] 2 is illustrated to simplify the drawings, however, the structure of the gate electrode and the wiring is also the same with regard to the other regions.
  • While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention. [0107]

Claims (2)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate;
a first transistor which includes a first gate electrode which is formed on said semiconductor substrate, a first sidewall insulating film which is formed on a side of said first gate electrode on said semiconductor substrate and first source/drain active layers which are formed in said semiconductor substrate; and
a second transistor which includes a second gate electrode which is formed on said semiconductor substrate, a second sidewall insulating film which is formed on a side of said second gate electrode on said semiconductor substrate and second source/drain active layers which are formed in said semiconductor substrate, wherein
layers of insulating films which compose said second sidewall insulating film are more in number than layers of an insulating film which compose said first sidewall insulating film, and accordingly, a width of said second sidewall insulating film in a channel direction of said second transistor is larger than a width of said first sidewall insulating film in a channel direction of said first transistor.
2. The semiconductor device according to claim 1, wherein
said first sidewall insulating film includes a silicon nitride film, and
said second sidewall insulating film includes a silicon nitride film and a silicon oxide film.
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