US20040164803A1 - Power amplifying system with supply and bias enhancements - Google Patents
Power amplifying system with supply and bias enhancements Download PDFInfo
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- US20040164803A1 US20040164803A1 US10/167,530 US16753002A US2004164803A1 US 20040164803 A1 US20040164803 A1 US 20040164803A1 US 16753002 A US16753002 A US 16753002A US 2004164803 A1 US2004164803 A1 US 2004164803A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
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- H03G—CONTROL OF AMPLIFICATION
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- H03G3/004—Control by varying the supply voltage
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- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
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- H—ELECTRICITY
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- H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
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- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/504—Indexing scheme relating to amplifiers the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
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- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7227—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier
Definitions
- This invention relates generally to wireless communication devices, and more specifically, to a radio frequency power amplifying system.
- FIG. 3 is a schematic diagram illustrating decoupled bias circuitry for one of the power amplifiers of the power amplifying system of FIG. 2.
- RF subsystem 144 includes modulator 148 , which after receiving a frequency reference signal or signals, also called a local oscillator signal or LO from synthesizer 168 via connection 166 , modulates the analog information on connection 142 and provides a modulated signal via connection 150 to upconverter 152 .
- Upconverter 152 also receives a frequency reference signal from synthesizer 168 via connection 164 .
- Synthesizer 168 determines the appropriate frequency to which upconverter 152 can upconvert the modulated signal or signals on connection 150 .
- first power amplifier 220 can be used to amplify RF signals at a frequency of 1900 mega hertz (MHz) and second power amplifier 240 can be used to amplify RF signals at a frequency of 860 MHz.
- MHz mega hertz
- second power amplifier 240 can be used to amplify RF signals at a frequency of 860 MHz.
- the regulator circuit 230 outputs a supply voltage Vo of approximately 2.2 volts (DC) when the transceiver controller 280 provides a logic control input level that indicates that the enabled power amplifier is operating at a power level of less than, for example, 22 dBm and greater than 16 dBm.
- DC 2.2 volts
- Voltage Vo is supplied to power amplifier 220 at node Vcc 1 222 and node Vcc 2 224 .
- Vo is supplied to power amplifier 240 at node Vcc 1 242 and node Vcc 2 244 .
- the embodiment of FIG. 2 uses a well-regulated reference voltage to switch from power amplifier 220 to power amplifier 240 (e.g., from PCS to Cellular).
- the reference voltage Vref 2 at node 246 may be a control, or reference, voltage of 3.0 V, for example, that is used to turn on, or enable, the cellular power amplifier 240 when required.
- reference voltage Vref 2 can be the reference voltage supplied on one of the lines of connection 146 of FIG. 1.
- FIG. 8 is a schematic diagram of a fourth exemplar PAS 500 , with emphasis on the another decoupled bias circuit embodiment.
- the power controller 802 used to provide a supply voltage Vo to node 218 is similar to the power controller 202 used in FIG. 2.
- Power controller 802 is depicted as a simplified block diagram, with the battery not shown, to simplify discussion.
- the bias circuit 810 is duplicated for input into each base terminal of each stage power transistor (e.g., first and second stage RF power transistor 354 and 358 ).
- the power amplifier 820 uses the RF circuitry similar to that used for the power amplifier 220 of FIG.
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- Amplifiers (AREA)
- Control Of Amplification And Gain Control (AREA)
- Transmitters (AREA)
Abstract
Description
- This application is a continuation-in-part of copending U.S. utility application entitled, “Power Amplifier With Provisions For Varying Operating Voltage Based Upon Power Amplifier Output Power,” having Ser. No. 09/792,660, filed Feb. 23, 2001, which claims priority to U.S. provisional application entitled, “A Power Amplifying System,” having Ser. No. 60/184,682, filed Feb. 24, 2000, both which are entirely incorporated herein by reference.
- 1. Field of the Invention
- This invention relates generally to wireless communication devices, and more specifically, to a radio frequency power amplifying system.
- 2. Related Art
- In personal communications devices such as cellular telephones, there is a trend toward minimizing size and weight. The size and weight are, however, contingent upon the size and weight of the various components that make up the personal communications device. Briefly, the smaller the various components of the personal communications devices, the smaller the size and overall weight of the personal communications device. Many personal communications devices have an overall size and weight that is, to a large degree, dominated by the size and weight of the battery that provides a supply voltage to the personal communications device. This is so because consumers want personal communications devices to have a prolonged operating time during usage.
- As operating time requirements and power consumption of the personal communications device during operations increase, the size of the battery required to perform under these circumstances will also increase. Thus, the reduction of current and power consumption in the personal communications devices and the reduction in the size of components leads to a reduced battery size. Alternatively, where the size of the battery remains constant, the operating time of the personal communications devices can be increased.
- In typical personal communications devices such as, for example, a portable transceiver, efficiency of the device is optimized at a maximum power output without regard to whether or not the maximum power output is actually needed. Thus, as the power output of a typical transceiver drops below the maximum power output level, the efficiency of the transceiver also drops. This reduces the battery voltage and thus limits the operation time of the transceiver.
- Therefore, there exists a need in the industry for a power amplifying system that makes efficient use of broad operating power ranges.
- The invention provides a radio frequency (RF) power amplifying system for a personal communications device. In one embodiment, the power amplifying system includes a power controller and one or more power amplifiers comprising power transistors and bias circuitry. The bias circuitry is decoupled from the collector terminals of the power transistors to enable substantially reduced supply voltages and consequently a reduced power consumption for the power amplifiers. The bias circuitry provides current to the base of the one or more power transistors in such as manner as to maintain the power transistors in substantially linear operation throughout the variation in collector supply voltage as supplied by the power controller.
- In one embodiment, the bias circuit is supplied with a reference voltage that is independent of the regulated supply voltage provided by the power controller. The power controller monitors the current draw of the bias circuit of each power amplifier. The supply voltage is automatically adjusted based on the current draw of the bias circuit, which is proportional to the power output level of each power amplifier. The bias circuit provides substantially constant current to the base terminals of the power transistors for each predefined power output level of each power amplifier, thus maintaining substantially linear operation of the power transistor.
- In another embodiment, the supply voltage from the power controller and a separate reference voltage are both fed to the bias circuit. The supply voltage from the power controller acts as a “control signal” to the bias circuit, causing the bias circuit current to vary automatically as a function of the supply voltage, thus automatically adjusting the bias point of the power transistors to maintain substantially linear operation.
- Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
- The invention can be better understood with reference to the following figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.
- FIG. 1 is a block diagram illustrating a simplified portable transceiver.
- FIG. 2 is a block diagram illustrating an exemplar radio frequency (RF) power amplifying system for a personal communications device.
- FIG. 3 is a schematic diagram illustrating decoupled bias circuitry for one of the power amplifiers of the power amplifying system of FIG. 2.
- FIG. 4 is a block diagram illustrating a second exemplar power amplifying system.
- FIG. 5 is a schematic diagram illustrating a bias circuit including an enable pin configuration for one of the power amplifiers of the second exemplar power amplifying system of FIG. 4.
- FIG. 6 is a block diagram illustrating a third exemplar power amplifying system.
- FIG. 7 is a detailed block diagram of the power controller of the third exemplar power amplifying system of FIG. 6.
- FIG. 8 is a schematic diagram of a fourth exemplar power amplifying system.
- The invention provides a radio frequency (RF) power amplifying system (PAS) for a personal communications device. An example system using the PAS will be described in association with FIG. 1, with a further description of an example PAS described in association with FIG. 2. Decoupled bias circuitry for one of the power amplifiers of the PAS will be described in accordance with one embodiment of the invention in association with FIG. 3. FIGS.4-8 will then be used to describe various embodiments of the PAS based on various mechanisms for controlling the PAS. For example, in FIGS. 4 and 5, the bias circuit will be described in cooperation with Vmode control. In one embodiment, Vmode control is accomplished through a transceiver controller or a baseband subsystem communication, such as for example, through a Vmode pin. FIGS. 4 and 6 and 7 will be used to illustrate the monitoring of current (Iref) to determine the output power delivered by the power amplifier of the PAS. This current can be used to adjust the voltage supplied by a power controller to the collector supply of a power amplifier transistor automatically, thus substantially reducing, or even eliminating, the need for the baseband subsystem to control power controller output to the power amplifier of the PAS. Finally, FIG. 8 will be used to describe a PAS wherein the Vmode pin is added to the Iref, which can then be controlled by the baseband subsystem. Although described with particular reference to a personal communications device, the power amplifying system can be implemented in any system where it is desirable to reduce power consumption while maintaining efficient, substantially linear operation in a power amplification system. Thus, the power amplifying system can be embodied in many different forms and should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, all “examples” given herein are intended to be non-limiting.
- FIG. 1 is a block diagram illustrating a simplified
portable transceiver 100.Portable transceiver 100 includesspeaker 102,display 104,keyboard 106, and microphone 108, all connected tobaseband subsystem 130. In a particular embodiment,portable transceiver 100 can be, for example but not limited to, a portable telecommunication handset such as a mobile cellular-type telephone.Speaker 102 anddisplay 104 receive signals frombaseband subsystem 130 viaconnections keyboard 106 andmicrophone 108 supply signals tobaseband subsystem 130 viaconnections Baseband subsystem 130 includes microprocessor (μP) 118,memory 120,analog circuitry 122, and digital signal processor (DSP) 124 in communication viabus 128, as well as apower source 126, such as a battery or charging circuit, which will power thebaseband subsystem 130 and theRF subsystem 144. Generally, thebaseband subsystem 130 is the controller for substantially all functions of a cell phone.Bus 128, although shown as a single bus, may be implemented using multiple busses connected as necessary among the subsystems withinbaseband subsystem 130.Microprocessor 118 andmemory 120 provide the signal timing, processing and storage functions forportable transceiver 100.Analog circuitry 122 provides the analog processing functions for the signals withinbaseband subsystem 130.Baseband subsystem 130 provides control signals toRF subsystem 144 viaconnection 134. Although shown as asingle connection 134, the control signals may originate fromDSP 124 or frommicroprocessor 118, and are supplied to a variety of points withinRF subsystem 144. It should be noted that, for simplicity, only the basic components ofportable transceiver 100 are illustrated. -
Baseband subsystem 130 also includes analog-to-digital converter (ADC) 132 and digital-to-analog converters (DACs) 136 and 138.ADC 132,DAC 136 andDAC 138 also communicate withmicroprocessor 118,memory 120,analog circuitry 122 andDSP 124 viabus 128.DAC 136 converts the digital communication information withinbaseband subsystem 130 into an analog signal for transmission toRF subsystem 144 viaconnection 142.DAC 138 provides a reference voltage power level signal or signals to thepower amplifying system 200 viaconnection 146.Connection 142, shown as two directed arrows, includes the information that is to be transmitted byRF subsystem 144 after conversion from the digital domain to the analog domain. -
RF subsystem 144 includesmodulator 148, which after receiving a frequency reference signal or signals, also called a local oscillator signal or LO fromsynthesizer 168 viaconnection 166, modulates the analog information onconnection 142 and provides a modulated signal viaconnection 150 toupconverter 152.Upconverter 152 also receives a frequency reference signal fromsynthesizer 168 viaconnection 164.Synthesizer 168 determines the appropriate frequency to whichupconverter 152 can upconvert the modulated signal or signals onconnection 150. Thesynthesizer 168, in a code division multiple access (CDMA) embodiment, receives instructions from thebaseband subsystem 130 as to what band, personal communications service (PCS), or cellular (CELL), to implement (as indicated by control signals 134). Further, as will be described below, thebaseband subsystem 130 controls a power controller (not shown) of the power amplifying system (PAS) 200 through thecontrol signal 134. The modulated signal or signals onconnection 150 may be any modulated signal, such as a phase modulated signal or an amplitude modulated signal. Furthermore, it is possible to supply a phase modulated signal toupconverter 152 and to introduce an amplitude modulated signal component into thePAS 200 through the power amplifiers control channel. All possible modulation techniques can benefit from the invention to be described below. -
Upconverter 152 supplies the modulated signal or signals viaconnection 154 toPAS 200. Although a single antenna port forantenna 172 is illustrated for simplicity in discussion, it will be appreciated by one having ordinary skill in the art that in a full-duplex transceiver, such as that used in CDMA, the simultaneous transmit/receive signal is accomplished, in one implementation, through the use of a diplexor filter (not shown). The diplexer filter will typically route one set of bands to a first port (not shown), and a second set to a second port (not shown), thus acting as a three port device (e.g., the antenna port handling all frequencies, a receive port handling receive signals, and a transmit port handling transmit frequencies). Note that for PCS, there are typically two sets of these signals and therefore the transceiver is typically a five port device, as is well known in to those having ordinary skill in the art. ThePAS 200 comprises one or more power amplifiers (not shown) and a power controller (not shown), as will be described below. ThePAS 200 amplifies the signal or signals onconnection 154 to a variety of different power levels while maintaining a high efficiency level. ThePAS 200 amplifies the modulated signal(s) onconnection 154 to the appropriate power level for transmission viaconnection 162 toantenna 172.Connection 162 may include an interface, such as, for example, an isolator or a filter. Illustratively, switch 174 controls whether the amplified signal onconnection 162 is transferred toantenna 172 or whether a received signal fromantenna 172 is supplied to filter 176. In one embodiment, the operation ofswitch 174 is controlled by a control signal frombaseband subsystem 130 viaconnection 134. In other embodiments, as described above, a full-duplex communication architecture can be used to simultaneously send and receive signals. - In one embodiment, a portion of the amplified transmit signal energy on
connection 162 is supplied viaconnection 160 to the power controller (not shown) of thePAS 200. The power controller can form a closed power control feedback loop, as will be described below. As mentioned above, a signal received byantenna 172 will, at the appropriate time determined bybaseband system 130, be directed viaswitch 174 to receivefilter 176. Receivefilter 176 will filter the received signal and supply the filtered signal onconnection 178 to low noise amplifier (LNA) 180. Receivefilter 176 is a bandpass filter, which passes all channels of the particular cellular system in which theportable transceiver 100 is operating. As an example, in a 900 MHz GSM system (global system for mobile communications), receivefilter 176 would pass all frequencies from 935.1 MHz to 959.9 MHz, covering all 124 contiguous channels of 200 kHz each. The purpose of this filter is to reject all frequencies outside the desired region.LNA 180 amplifies the weak signal onconnection 178 to a level at whichdownconverter 184 can translate the signal from the transmitted frequency back to a baseband frequency. Alternatively, the functionality ofLNA 180 anddownconverter 184 can be accomplished using other elements, such as for example but not limited to, a low noise block downconverter (LNB). -
Downconverter 184 receives a frequency reference signal, also called a local oscillator signal or LO fromsynthesizer 168, viaconnection 170. This LO signal instructs thedownconverter 184 as to the proper frequency to which to downconvert the signal received fromLNA 180 viaconnection 182. The downeonverted frequency is called the intermediate frequency or “IF”.Downconverter 184 sends the downconverted signal viaconnection 186 tochannel filter 188, also called the “IF filter”.Channel filter 188 filters the downconverted signal and supplies it viaconnection 190 toamplifier 192. Thechannel filter 188 selects the one desired channel and rejects all others. Using the GSM system as an example, only one of the 124 contiguous channels is actually to be received. After all channels are passed by receivefilter 176 and downconverted in frequency bydownconverter 184, only the one desired channel will appear precisely at the center frequency ofchannel filter 188. Thesynthesizer 168, by controlling the local oscillator frequency supplied onconnection 170 todownconverter 184, determines the selected channel.Amplifier 192 amplifies the received signal and supplies the amplified signal viaconnection 194 todemodulator 196.Demodulator 196 recovers the transmitted analog information and supplies a signal representing this information viaconnection 198 toADC 132.ADC 132 converts these analog signals to a digital signal at baseband frequency and transfers it viabus 128 toDSP 124 for further processing. - FIG. 2 is a block diagram illustrating one example power amplifying system (PAS)200 for the
portable transceiver 100 of FIG. 1. The portable transceiver 100 (FIG. 1) can be, for example, a portable dual band, triple mode phone that provides advanced mobile phone system (AMPS), cellular, cellular code division mobile access (CDMA), and/or personal communications system (PCS) CDMA.PAS 200 is a subsystem of portable transceiver 100 (FIG. 1), andPAS 200 includespower controller 202, afirst power amplifier 220, and asecond power amplifier 240. In aportable transceiver 100 such as a dual mode phone providing PCS CDMA and cellular CDMA, for instance,first power amplifier 220 can be used to amplify RF signals at a frequency of 1900 mega hertz (MHz) andsecond power amplifier 240 can be used to amplify RF signals at a frequency of 860 MHz. Although shown and described with two power amplifiers, fewer or greater numbers of power amplifiers can be implemented while still being within the scope of the embodiments of the invention. -
Power controller 202 receives energy from a voltage supply, such asbattery 210.Battery 210 can be external or internal to portable transceiver 100 (such as, for example,voltage source 126 of FIG. 1), as well as internal or external to thePAS 200.Power controller 202 integrates power supply and battery charging functions for thePAS 200. In one embodiment, thepower controller 202 includes abypass switch 204,regulator switch 206, andvoltage controller 208.Bypass switch 204 andregulator switch 206 can be implemented using one or more field effect transistors (FETs). However, other transistor devices, such as bipolar junction transistors (BJTs) can be used. In other embodiments, electrically actuated mechanical switching devices can be used. -
Regulator switch 206,voltage controller 208,inductor 212, andcapacitor 214 comprise aregulator circuit 230. Theregulator circuit 230 receives energy frombattery 210, and reduces the voltage to a predetermined regulated supply voltage, supply voltage Vo atnode 218 as determined by atransceiver controller 280, as will be explained below. Note that the downward pointing, open arrow below thebattery 210, and as depicted in other drawings, will be understood to designate ground. The voltage supply Vo, atnode 218, can be selected from any one of a predetermined number of voltage levels. For example, Vo can be between 0 volts and the voltage at thebattery 210. Further, Vo may be linearly variable between, for example, 0 volts and the voltage at thebattery 210, in accordance with a logic control input level provided bytransceiver controller 280, as will be described below. - The
transceiver controller 280 determines the voltage that thepower controller 202 will supply to thepower amplifiers appropriate power amplifier appropriate pin Vref1 226 orVref2 246. Thus, in one embodiment, thetransceiver controller 280 is controlled by the baseband subsystem 130 (FIG. 1). Thebaseband subsystem 130 typically determines how much power thepower amplifier transceiver controller 280 can be external to thepower controller 202 or internal topower controller 202. Further, thetransceiver controller 280 can be external or internal toPAS 200. Thepower controller 202 operates by passing various ranges of voltages to either of thepower amplifiers transceiver controller 280. In other embodiments, thetransceiver controller 280 can sense current consumption, reference current, or the actual power at the output of a first or second stage (not shown). - When a maximum power output is required from either
power amplifier transceiver controller 280 provides a logic control input (via En, s1, s2) to thevoltage controller 208, which causesbypass switch 204 to turn on (i.e., to close) andregulator switch 206 to also close to help minimize the voltage drop across the switches (e.g., 204 and 206). For example, when either power amplifier is drawing current that results in a power amplification of greater than 22-24 decibels relative to one milliwatt (dBm), thetransceiver controller 280 provides a logic control input to thevoltage controller 208 to close thebypass switch 204. When theswitches node 218 applied to the enabled power amplifier (i.e., eitherpower amplifier battery 210 for maximum power output by the enabled power amplifier. - When the power output requirement for transmission is less than maximum, the
transceiver controller 280 provides one of several different logic control input levels to thevoltage controller 208, which causes theregulator circuit 230 to operate while thebypass switch 204 is off.Regulator circuit 230 receives current to chargeinductor 212 andcapacitor 214. When thecapacitor 214 reaches one of the specified voltage control input levels fromtransceiver controller 280,regulator switch 206 opens andinductor 212 replenishes the voltage discharged bycapacitor 214 to ground in order to maintain the specified supply voltage Vo atnode 218. When the voltage level Vo atnode 218 declines below the level specified by thetransceiver controller 280,regulator switch 206 closes to charge theregulator circuit 230. In one embodiment, theregulator circuit 230 outputs a supply voltage Vo of approximately 2.2 volts (DC) when thetransceiver controller 280 provides a logic control input level that indicates that the enabled power amplifier is operating at a power level of less than, for example, 22 dBm and greater than 16 dBm. - Voltage Vo is supplied to
power amplifier 220 atnode Vcc1 222 andnode Vcc2 224. Similarly, Vo is supplied topower amplifier 240 atnode Vcc1 242 andnode Vcc2 244. The embodiment of FIG. 2 uses a well-regulated reference voltage to switch frompower amplifier 220 to power amplifier 240 (e.g., from PCS to Cellular). The reference voltage Vref2 atnode 246 may be a control, or reference, voltage of 3.0 V, for example, that is used to turn on, or enable, thecellular power amplifier 240 when required. For instance, reference voltage Vref2 can be the reference voltage supplied on one of the lines ofconnection 146 of FIG. 1. Similarly, the reference voltage Vref1 atnode 226 may be a control, or reference, voltage of 3.0V, for example, that is used to turn on thepower amplifier 220. A 0V value for reference voltage Vref2 atnode 246 or reference voltage Vref1 atnode 226 disables, or turns off, thecorresponding power amplifier transceiver controller 280, as discussed above. -
Power amplifier 220 includes aninput node 290 for receiving a radio frequency (RF) signal and anoutput node 292 for outputting an amplified RF signal. Similarly,power amplifier 240 includes aninput node 294 for receiving a radio frequency (RF) signal and anoutput node 296 for outputting an amplified RF signal.Input nodes input connection 154 in FIG. 1. Similarly, theoutput nodes output connection 162 of FIG. 1.Power amplifiers power controller 202 can be fabricated using complementary metal oxide semiconductor (CMOS) technology. Further, bothpower amplifier power controller 202 can be fabricated on a single integrated circuit, or each component on separate integrated circuits. - FIG. 3 is a schematic diagram illustrating decoupled bias circuitry for the
power amplifier 220 of theexemplar PAS 200 of FIG. 2. In this example,power amplifier 220 includes abias circuit 310 and multi-stage RF power transistor circuitry. Although shown with two transistor stages, a fewer or greater number of stages are contemplated to be within the scope of the embodiments of the invention. Further, although described in association withpower amplifier 220, the same or similar description forpower amplifier 220 can be applied to power amplifier 240 (FIG. 2) or likeembodiments. Power amplifier 220 includes aninput matching unit 352 for matching the impedance of theinput node 290 to a firststage power transistor 354. Note that the firststage power transistor 354, as well as other bipolar junction transistors (BJTs) contained in the embodiments described within this document, comprises a base terminal designated by the letter “B”, a collector terminal designated by the letter “C”, and an emitter terminal designated by the letter “E”. The output ofpower transistor 354 is connected to a second stage (inter-stage)matching unit 356.Inter-stage matching unit 356 matches the output impedance ofpower transistor 354 to the input impedance of a secondstage power transistor 358. Anoutput matching unit 360 is provided to match the output impedance ofpower transistor 358 to theoutput node 292. Matchingunits - The reference voltage Vref1 at
node 226 is coupled tobias circuit 310 viaresistor 306.Bias circuit 310 is energized by providing the reference voltage Vref1 as described in association with FIG. 2, from a power controller (similar to thepower controller 202 of FIG. 2), or by providing an enable input or by applying a battery voltage, such as frombattery 210 of FIG. 2, as will be described below. Note that, in one embodiment, Vref1 is independent of RF transistor collectorsupply voltages Vcc1 222 andVcc2 224, as supplied by Vo (FIG. 2). Further, thebias circuit 310 is decoupled from the collector terminals ofpower transistor - Further, Vref1 is substantially free of noise, and common to both
power amplifiers 220 and 240 (FIG. 2). In one embodiment, reference voltage Vref1 is substantially constant at three volts (+3.0 VDC).Bias circuit 310 comprises diode-configuredtransistor 312,driver transistors inductors 322 and 326 (although not shown as encompassed by the dotted block corresponding to 310 for convenience), and constantcurrent source 302. Theinductors transistors transistor 312 is connected as a diode by shorting the collector to the base of diode-configuredtransistor 312. Diode-configuredtransistor 312 is matched (i.e., has substantially similar physical and electrical characteristics) to each ofdriver transistors power amplifier 220, thebias circuit 310 can be externally coupled topower amplifier 220 in some embodiments. - In one embodiment,
transistors current source 302 is equal to the current density flowing into the base terminals ofdriver transistors bias circuit 310 from the collector terminal oftransistors transistors transistors node 226, in combination with the current mirror and constant current source of thebias circuit 310, provides a substantially constant Ib to the base terminal of eachRF power transistor - Alternatively, although shown and described with BJT transistors, other transistor devices can similarly be employed and configured as current devices to provide a substantially constant source of base current.
- FIG. 4 is a block diagram illustrating a second exemplar power amplifying system. The
PAS 300 is similar to the power amplifying system shown in FIG. 2. For instance,power amplifiers PAS 300 are like thepower amplifiers PAS 200 of FIG. 2 but with added enable pins and Vmode pins and added functionality corresponding to these added pins. Also, the power controller 402 (FIG. 4) is like thepower controller 202 of FIG. 2 with an added Vref—Isense pin and its corresponding functionality. Consistent with the decoupled bias scheme, Vo at node 218 (Vo supplies voltage to theVcc1 node 222 andVcc2 node 224 in FIG. 2) is provided as an input to the collector terminals (not shown, but similar to collector terminals ofpower transistors power amplifiers power amplifiers power controller 402 includes a Vref—Isense pin 422. In other embodiments, the Vref—Isense connection can be made directly to thetransceiver controller 480. Thepower controller 402 provides a relatively constant reference voltage Vref atnode 470, of 3.0 VDC, for example, to eachpower amplifier Isense 422 pin. Note that Vref is common to bothpower amplifiers power amplifiers power amplifier power controller 402, or current monitoring circuitry (as described below) associated withpower controller 402, such as bytransceiver controller 480. Note that in some embodiments,transceiver controller 480 can be internal topower controller 402. The Vref—Isense pin 422 provides a connection that couples (and thus associates) the constant voltage source located in 408 to the amplifier bias of each power amplifier. Thus, the current draw of the bias circuit ofpower amplifiers power amplifiers power amplifying system 300. - Also included with each power amplifier is an
optional Vmode pin power amplifiers power amplifiers power amplifiers power amplifier transceiver controller 480 or the baseband subsystem 130 (FIG. 1). Enable pins 402 and 404 thus, in this embodiment, replace the enable function of Vref1 and Vref2 in the power amplifying system of FIG. 2. - FIG. 5 is a schematic diagram illustrating one exemplar enable pin configuration to a
bias circuit 410 ofpower amplifiers 420 of the second exemplarpower amplifying system 300 of FIG. 4.Power amplifier 420 is similar topower amplifier 220 depicted in FIG. 3, but with abias circuit 410 having an addedVmodel pin 434 and enablepin 432, and added functionality corresponding to the availability of theVmodel pin 434 and enablepin 432. Further,power amplifier 420 replaces Vref1 of FIG. 3 with a Vref common to bothpower amplifiers transistor 408 causes the base bias voltage to be shorted to ground therefore turning offtransistors pin transistor 408 can be removed from its illustrated location in FIG. 5, and placed between the output of thecurrent source 402 and ground. - FIG. 6 is a block diagram illustrating a third exemplar power amplifying system, similar to
PAS 300 shown in FIG. 4 but with an added supply voltage control module (SVCM) 610 and without aVmode pin 434 and 444 (FIG. 4).SVCM 610 is internal topower controller 602, but in other embodiments, can be external topower controller 602.SVCM 610 provides for the “Isense” function associated with supplying “Vref”, as explained above. Thepower amplifying system 400 illustrated in FIG. 6 uses power amplifiers with decoupled bias circuitry, similar to thepower amplifier 420 shown in FIG. 5 but without theVmodel pin 434. Thepower controller 602 of FIG. 6 automatically varies the supply voltage Vo, such as supply voltage atnode 650, to the collector terminals (not shown, but similar to collector terminals ofpower transistors power amplifier 420 in FIG. 5) of the first and second stage RF transistor collector terminals for thepower amplifiers 620. Thepower controller 602 varies the supply voltage Vo topower amplifiers node 652 as monitored by SVCM 610) of the enabledpower amplifier - FIG. 7 is a detailed block diagram of the
power controller 602 of FIG. 6. With continued reference to FIG. 6, the power output of the enabledpower amplifier power amplifier power amplifiers power controller 602 includesSVCM 610. TheSVCM 610 includes avoltage regulator 660 to provide a substantially constant reference voltage, acurrent meter 662, and a look up table (LUT) 664. TheSVCM 610 provides the reference current Iref.Current meter 662 measures, or senses, the DC current flow, Iref, consumed by the enabled power amplifier (620 or 640). - Each power amplifier has a current consumption (Iref), or draw, that varies depending largely on the required power output of each power amplifier. Thus, by monitoring reference current Iref, it is possible to determine the power output of the enabled power amplifier. The measured current value of Iref is supplied to the
LUT 664. TheLUT 664 provides a data table, or data structure (not shown), that maps the measured current level of reference current Iref to a corresponding logic input value associated with a predetermined supply voltage Vo. This logic input value can be retrieved from the processor 118 (FIG. 1) and input to thevoltage controller 608, similar to the mechanism employed by thetransceiver controller 280 of FIG. 2. Thus, the supply voltage Vo is a function of the reference current Iref. In one embodiment, theLUT 664 maps 16 states (e.g., 0.5V to 2.2V in 0.10V increments), with lower and upper bounds of 5 mA and 25 mA, respectively. TheLUT 664 maps a corresponding Vo of 0.5V and 2.2V, for the 5 mA and 25 mA, respectively. A substantially linear plot of Vo is mapped by theLUT 664 for current levels between 5 mA and 25 mA. TheLUT 664 can be incorporated as an integral part of thepower controller 602. Alternatively, it may be external to thepower controller 602. - FIG. 8 is a schematic diagram of a
fourth exemplar PAS 500, with emphasis on the another decoupled bias circuit embodiment. The power controller 802 used to provide a supply voltage Vo tonode 218 is similar to thepower controller 202 used in FIG. 2. Power controller 802 is depicted as a simplified block diagram, with the battery not shown, to simplify discussion. Thebias circuit 810 is duplicated for input into each base terminal of each stage power transistor (e.g., first and second stageRF power transistor 354 and 358). Thepower amplifier 820 uses the RF circuitry similar to that used for thepower amplifier 220 of FIG. 3, including receiving an RF signal atnode 290, outputting an amplified RF signal atnode 292, and usinginput match 352,power transistors interstage matching unit 356,output match 360, andcapacitor 362. Thisbias circuit 810 automatically performs the functionality of the “Iref” sensing and look-up table functionality of the power controller of FIG. 7. Vbias atnode 210 represents the voltage at the battery (not shown). Vbias provides for three modes of operation, including “Off”, “High-bias”, and “Medium-bias.” “Medium-bias” will apply when Vmode is enabled, and is valid between the ranges of −100 dBm and 16 dBm. Because the bias voltage on the base of thetransistor 354 is, for example, approximately 1.5V, assuming some overhead for the biasing and/or thecurrent source 912, Vbias is typically maintained at a level greater than 2V. As the battery voltage, Vbias, reduces due to reduced power demand by the power amplifier, current from the battery also reduces. Thus a feedback path is established between power consumption of the power amplifier and Vbias. - The supply voltage Vo at
node 218 represents the supply voltage of the power controller 802. The reference voltage Vref1 atnode 226 represents the reference voltage, which is a regulated voltage of, for example, 3.0 VDC below the float voltage of the battery (not shown). Vref1, as described in relation to FIG. 2, enables or disables the power amplifier. Transistors 900-906, and 910 and 912 comprise a current mirror bias circuit. Diode-configuredtransistor 908 andtransistor 354 are matched and scaled to provide a defined ratio, for example 10:1 , of the current drain across theresistor 918.Resistor 924 comprises a reference resistor fortransistors resistor 924 is used to set the voltage at the base terminal of theRF power transistor 354.Resistors Transistors transistors transistors resistor 922 and increased current to the base terminal oftransistor 912. An increase in current throughtransistor 912 results in more current into the base terminal ofRF power transistor 354. One of the effects of this biasing arrangement is that a change in the supply voltage Vo from the power controller 802 automatically varies the bias current to the base terminal of theRF power transistor 354. In effect, the bias point of theRF power transistor 354 can be continually and automatically adjusted to perform at optimum efficiency. - At a Vo below 3.0 VDC (i.e. lower power controller output voltage Vo due to reduced power output demand of the power amplifier),
transistor 906 turns off causing increased current draw throughtransistor 900 fromVref1 226. This increased current draw throughresistor dividers transistor 912, which results in reduced current to the base terminal ofRF transistor 354. - The power amplifying systems described above can be implemented in software, hardware, or a combination of software and hardware. In the several embodiments shown and described above, the power amplifiers are implemented in hardware, and the power controller is implemented as a combination of hardware, for example at the regulating circuit, and software, for example at portions of the
SCVM 610. The hardware portion of the power amplifying systems can be implemented using specialized hardware logic. The software portion can be stored in a memory and can be executed by a suitable instruction execution system (microprocessor). The hardware implementation of the power amplifying systems can include any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc. - Furthermore, the power controller software portion of the power amplifying systems (and in the
baseband subsystem 130, FIG. 1), which comprise, in part, an ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. - In the context of this document, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a nonexhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory) (magnetic), an optical fiber (optical), and a portable compact disc read-only memory (CDROM) (optical). Note that the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
- While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the invention.
Claims (30)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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US10/167,530 US6784748B1 (en) | 2000-02-24 | 2002-06-11 | Power amplifying system with supply and bias enhancements |
PCT/US2003/017747 WO2003105338A1 (en) | 2002-06-11 | 2003-06-06 | Power amplifying system with supply and bias enhancements |
EP03741882.9A EP1512221B1 (en) | 2002-06-11 | 2003-06-06 | Power amplifying system with supply and bias enhancements |
AU2003274387A AU2003274387A1 (en) | 2002-06-11 | 2003-06-06 | Power amplifying system with supply and bias enhancements |
JP2004512285A JP4810094B2 (en) | 2002-06-11 | 2003-06-06 | Power amplification system with improved supply and bias |
JP2011156505A JP5330464B2 (en) | 2002-06-11 | 2011-07-15 | Power amplification system with improved supply and bias |
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US09/792,660 US6630867B2 (en) | 2000-02-24 | 2001-02-23 | Power amplifier with provisions for varying operating voltage based upon power amplifier output power |
US10/167,530 US6784748B1 (en) | 2000-02-24 | 2002-06-11 | Power amplifying system with supply and bias enhancements |
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US09/792,660 Continuation-In-Part US6630867B2 (en) | 2000-02-24 | 2001-02-23 | Power amplifier with provisions for varying operating voltage based upon power amplifier output power |
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US20080081578A1 (en) * | 2006-09-29 | 2008-04-03 | Ahmadreza Rofougaran | Method And System For Compensating For Antenna Pulling |
US8032096B2 (en) * | 2006-09-29 | 2011-10-04 | Broadcom Corporation | Method and system for compensating for antenna pulling |
US20120034956A1 (en) * | 2010-08-09 | 2012-02-09 | Skyworks Solutions, Inc. | System and method for biasing a power amplifier |
US8688061B2 (en) * | 2010-08-09 | 2014-04-01 | Skyworks Solutions, Inc. | System and method for biasing a power amplifier |
JP2015149519A (en) * | 2014-02-04 | 2015-08-20 | 株式会社村田製作所 | power amplifier module |
US9461594B2 (en) | 2014-02-04 | 2016-10-04 | Murata Manufacturing Co., Ltd. | Power amplifier module |
US9602154B2 (en) * | 2015-08-18 | 2017-03-21 | Wistron Neweb Corp. | Wireless communication apparatus and method for improving specific absorption ratio thereof |
US10090806B2 (en) * | 2016-08-31 | 2018-10-02 | Murata Manufacturing Co., Ltd. | Power amplifier circuit |
FR3059493A1 (en) * | 2016-11-29 | 2018-06-01 | Stmicroelectronics Sa | REGULATING AN RF AMPLIFIER |
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Also Published As
Publication number | Publication date |
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EP1512221A4 (en) | 2007-08-08 |
JP4810094B2 (en) | 2011-11-09 |
EP1512221A1 (en) | 2005-03-09 |
WO2003105338A1 (en) | 2003-12-18 |
JP2005530387A (en) | 2005-10-06 |
JP5330464B2 (en) | 2013-10-30 |
US6784748B1 (en) | 2004-08-31 |
JP2011239457A (en) | 2011-11-24 |
AU2003274387A1 (en) | 2003-12-22 |
EP1512221B1 (en) | 2013-08-28 |
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