US20040145035A1 - Signal transmission plate used in an assembly package - Google Patents
Signal transmission plate used in an assembly package Download PDFInfo
- Publication number
- US20040145035A1 US20040145035A1 US10/757,808 US75780804A US2004145035A1 US 20040145035 A1 US20040145035 A1 US 20040145035A1 US 75780804 A US75780804 A US 75780804A US 2004145035 A1 US2004145035 A1 US 2004145035A1
- Authority
- US
- United States
- Prior art keywords
- signal transmission
- die
- transmission plate
- layer
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the invention relates to a signal transmission plate used in an assembly package.
- a conventional ball grid array (BGA) package 1 mainly includes a bottom die 12 , a top die 15 , and a plurality of conductive wires 16 and 17 .
- the bottom die 12 is provided on the substrate 11 and the top die 15 is provided on the bottom die 12 .
- a non-conductive adhesive 13 silver paste for example, is applied, so that the top die 15 is fixed to the bottom die 12 while also insulated from the bottom die 12 .
- the bottom die 12 and the top die 15 are signally connected with the substrate 11 via the conductive wires 16 and 17 , gold wires for example, respectively.
- Thermosetting plastics are used as the molding compound 18 , through molds and by a molding press, to fill and encapsulate the conductive wires 16 and 17 , the bottom die 12 , and the top die 15 , thereby casting by baking.
- solder balls 19 are placed onto the solder pads on the substrate 11 and connected with the exterior to transmit signals.
- two or more dies may be integrated into a same package.
- the signal transmission quality of the die may be affected by the transmission distance and the number of conductive wires. More particularly, driven by the multi-function and high performance requirements demanded by the modern electronic products, dies having high I/O pin-counts are the development trend. However, the longer the transmission distance of conductive wires gets, the noise increases accordingly, and the signal distortion and hysteresis become more apparent, thereby dropping the signal transmission quality.
- the object of the invention is to provide an assembly package having good signal transmission quality and fast transmission rate.
- the invention provides an assembly package including a substrate, a first die, at least one signal transmission plate, at least one second die, a plurality of conductive wires, and a molding compound.
- the first die is electrically connected to the substrate using flip-chip bonding.
- the signal transmission plate is provided on the first die and has at least one insulating layer, at least one layout wire layer, and a solder mask layer.
- the layout wire layer is formed on the insulating layer, and the solder mask layer is formed on the layout wire layer.
- the solder mask layer exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads.
- the second die is electrically connected with the die bonding pads using flip-chip bonding, and the wire bonding pads are electrically connected to the substrate via the conductive wires so that signals from the second die are transmitted to the substrate. Furthermore, thermosetting plastics are used to encapsulate the first die, the signal transmission plate, the second die and the conductive wires.
- the assembly package of the invention employs flip-chip bonding, so that the signals from the first die (the bottom die) are transmitted to the substrate. Therefore, imperfect electricity caused by using lead connection is prevented.
- the second die also utilizes flip-chip bonding so that the signals are transmitted to the signal transmission plate and then to the substrate via the conductive wires.
- the conductive wires are not required to connect to the joints on the top die; only the signal transmission plate is needed to connect with the wire bonding pads, and signals from the top die can be transmitted to the substrate. In other words, the signal transmission quality is improved, and the signal transmission rate is also increased, for that the transmission distance of the conductive wires is shortened.
- FIG. 1 shows a conventional assembly package.
- FIG. 2 shows an assembly package in accordance with the invention, which uses a signal transmission plate to integrate two dies into one package.
- FIG. 3 is a sectional view showing a signal transmission plate in the assembly package of the invention.
- FIG. 4 is a front view showing the signal transmission plate in the assembly package of the invention.
- an assembly package 2 of the invention includes a first die 202 , a signal transmission plate 204 , a second die 205 , and a plurality of conductive wires 206 .
- the first die 202 is provided with a plurality of first bumps 212 , solder bumps for instance, which are electrically connected with a substrate 201 using flip-chip bonding.
- an underfill 222 Between the substrate 201 and the first die 202 is an underfill 222 to prevent the stress concentration brought about by different thermal expansion coefficients of the substrate 201 and the first die 202 .
- the signal transmission plate 204 is fixed onto the first die 202 by using an adhesive 203 , for example, silver paste or non-conductive materials such as epoxy.
- the signal transmission plate 204 includes an insulating layer 214 , a layout wire layer 224 , and a solder mask layer 234 .
- the insulating layer 214 can be formed of glass epoxy (FR-4, FR-5) or bismaleimide triazine (BT).
- BT bismaleimide triazine
- On the surface of the insulating layer 214 is a copper foil or a foil of other metal with good conductance.
- the metal foil forms the layout wire layer 224 after patterning processes namely applying photoresist, exposure, developing, and removing photoresist.
- the solder mask layer 234 On the surface of the layout wire layer 224 is provided with the solder mask layer 234 , which can be formed of epoxy.
- the solder mask layer can also be formed of UV cure green enamel or thermal cure green enamel via roller coating or curtain coating.
- the solder mask layer 234 is patterned to have its partial area expose the layout wire layer 224 to form a plurality of die bonding pads 224 a and a.plurality of wire bonding pads 224 b . Referring to FIG. 4, the die bonding pads 224 a are provided in the central part of the signal transmission plate 224 , whereas the wire bonding pads 224 b are provided on the peripheries of the signal transmission plate 224 .
- the second die 205 is provided on the signal transmission plate 204 , and one side of the second die 205 is provided with metal bumps 215 such as solder bumps.
- the metal bumps 215 are first applied with flux so that the solder bumps 215 are jointed with the die bonding pads 224 of the signal transmission plate 224 after reflow. That is, the second die 205 is electrically connected with the signal transmission plate 204 using flip-chip bonding. Moreover, an underfill is filled between the signal transmission plate 205 and the solder bumps 215 to prevent the stress concentration effect brought about by thermal stress, which decreases the yield rate.
- the second die 205 uses flip-chip bonding so that signals from the second die 205 can be transmitted to the die bonding pads 224 a via the second metal bumps 215 .
- the die bonding pads 224 a and the wire bonding pads 224 b are the layout wire layer 224 exposed at the solder mask layer 234 , and therefore the two are electrically connected with each other. Therefore, signals from the second die 205 can be transmitted to the wire bonding pads 224 b via the layout wire layer 224 . Then, signals from the second die 205 can be transmitted onto the substrate 201 via the conductive wires, gold wires for example, connecting the wire bonding pads 224 b and the substrate pad 211 .
- thermosetting plastics are used as the molding compound 208 , which is used to encapsulate the first die 202 , the signal transmission plate 204 , the second die 205 , and the conductive wires 206 to prevent contamination of the surroundings and damage of external forces.
- Solder balls 209 can be formed by placing a lead-tin alloy or other metallic materials onto the solder pads on the substrate 201 , so as to connect with the exterior, a circuit board for instance, for signal transmission.
- the signal transmission plate of this embodiment is a two-layer plate composed of an insulating layer and a layout mask layer.
- a signal transmission plated formed by several insulating layers and several layout mask layers alternately overlapping one another can be used to fulfill the wire layout requirement.
- through holes among the insulating layers are demanded between the layout mask layers to accomplish signal connection.
- the through holes may be provided by machine drilling. Sidewalls of the through holes are plated with a metal layer, and a hole-filling material is stuffed into the through holes.
- a two-layer stacked die is used as an example. Furthermore, another transmission plate and die can be stacked onto the second die to achieve another type of assembly package.
- the assembly package of the invention employs flip-chip bonding to have signals of the first die (the bottom die) transmitted to the substrate, and therefore imperfect electricity caused by using lead connection is prevented.
- the second die also uses flip-chip bonding to have signals transmitted to the signal transmission plate, and then the signals are transmitted to the substrate via the conductive wires.
- the conductive wires do not need to connect to the joints on the top die, but only need to connect to the wire bonding pads on the signal transmission plate.
- the signal transmission plate can be a multi-layer pressed or laminated substrate to fulfill the requirements of devices with high I/O pin-counts.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
A signal transmission plate used in an assembly package includes at least one insulating layer, at least one layout wire layer formed on the insulating layer, and a solder mask layer formed on the layout wire layer. The solder mask layer exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads.
Description
- This is a Divisional application claiming priority under 35 U.S.C. §120, of co-pending prior application Ser. No. 10/293,123 filed on Nov. 12, 2002, the disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to a signal transmission plate used in an assembly package.
- 2. Description of the Related Art
- During the recent years, due to the steady increase of demand of consumer electronic products, namely, cellular phones, personal digital assistants (PDAs) and digital cameras, package structures are developed toward being light in weight and small in size with short signal transmission distances. Based upon such trend, in order to save package area as well as to improve problems such as signal distortion, delay or power loss, an assembly package integrates at least one die into a same package structure by perpendicular stacking.
- Referring to FIG. 1, a conventional ball grid array (BGA) package1 mainly includes a bottom die 12, a
top die 15, and a plurality ofconductive wires substrate 11 and the top die 15 is provided on the bottom die 12. Between thetop die 15 and the bottom die 12, anon-conductive adhesive 13, silver paste for example, is applied, so that thetop die 15 is fixed to the bottom die 12 while also insulated from the bottom die 12. Thebottom die 12 and thetop die 15 are signally connected with thesubstrate 11 via theconductive wires molding compound 18, through molds and by a molding press, to fill and encapsulate theconductive wires bottom die 12, and thetop die 15, thereby casting by baking. In addition, on the other side of thesubstrate 11 is provided withsolder balls 19, which are placed onto the solder pads on thesubstrate 11 and connected with the exterior to transmit signals. - With such an assembly package technique, two or more dies may be integrated into a same package. Nevertheless, by using conductive wires to electrically connect I/O pins of individual die with the substrate for signal transmission, the signal transmission quality of the die may be affected by the transmission distance and the number of conductive wires. More particularly, driven by the multi-function and high performance requirements demanded by the modern electronic products, dies having high I/O pin-counts are the development trend. However, the longer the transmission distance of conductive wires gets, the noise increases accordingly, and the signal distortion and hysteresis become more apparent, thereby dropping the signal transmission quality.
- Therefore, it is a vital task to improve the signal transmission quality and speed up the signal transmission rate of assembly packages.
- In view of the above issue, the object of the invention is to provide an assembly package having good signal transmission quality and fast transmission rate.
- To achieve the above object, the invention provides an assembly package including a substrate, a first die, at least one signal transmission plate, at least one second die, a plurality of conductive wires, and a molding compound. The first die is electrically connected to the substrate using flip-chip bonding. The signal transmission plate is provided on the first die and has at least one insulating layer, at least one layout wire layer, and a solder mask layer. The layout wire layer is formed on the insulating layer, and the solder mask layer is formed on the layout wire layer. The solder mask layer exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads. The second die is electrically connected with the die bonding pads using flip-chip bonding, and the wire bonding pads are electrically connected to the substrate via the conductive wires so that signals from the second die are transmitted to the substrate. Furthermore, thermosetting plastics are used to encapsulate the first die, the signal transmission plate, the second die and the conductive wires.
- The assembly package of the invention employs flip-chip bonding, so that the signals from the first die (the bottom die) are transmitted to the substrate. Therefore, imperfect electricity caused by using lead connection is prevented. Also, the second die also utilizes flip-chip bonding so that the signals are transmitted to the signal transmission plate and then to the substrate via the conductive wires. As a result, the conductive wires are not required to connect to the joints on the top die; only the signal transmission plate is needed to connect with the wire bonding pads, and signals from the top die can be transmitted to the substrate. In other words, the signal transmission quality is improved, and the signal transmission rate is also increased, for that the transmission distance of the conductive wires is shortened.
- FIG. 1 shows a conventional assembly package.
- FIG. 2 shows an assembly package in accordance with the invention, which uses a signal transmission plate to integrate two dies into one package.
- FIG. 3 is a sectional view showing a signal transmission plate in the assembly package of the invention.
- FIG. 4 is a front view showing the signal transmission plate in the assembly package of the invention.
- The assembly package of the invention will be described with reference to the accompanying drawings.
- Referring to FIG. 2, an
assembly package 2 of the invention includes afirst die 202, asignal transmission plate 204, asecond die 205, and a plurality ofconductive wires 206. Thefirst die 202 is provided with a plurality offirst bumps 212, solder bumps for instance, which are electrically connected with asubstrate 201 using flip-chip bonding. Between thesubstrate 201 and thefirst die 202 is anunderfill 222 to prevent the stress concentration brought about by different thermal expansion coefficients of thesubstrate 201 and thefirst die 202. - The
signal transmission plate 204 is fixed onto thefirst die 202 by using anadhesive 203, for example, silver paste or non-conductive materials such as epoxy. Referring to FIG. 3, thesignal transmission plate 204 includes aninsulating layer 214, alayout wire layer 224, and asolder mask layer 234. Theinsulating layer 214 can be formed of glass epoxy (FR-4, FR-5) or bismaleimide triazine (BT). On the surface of theinsulating layer 214 is a copper foil or a foil of other metal with good conductance. The metal foil forms thelayout wire layer 224 after patterning processes namely applying photoresist, exposure, developing, and removing photoresist. On the surface of thelayout wire layer 224 is provided with thesolder mask layer 234, which can be formed of epoxy. The solder mask layer can also be formed of UV cure green enamel or thermal cure green enamel via roller coating or curtain coating. Similarly, thesolder mask layer 234 is patterned to have its partial area expose thelayout wire layer 224 to form a plurality ofdie bonding pads 224 a and a.plurality ofwire bonding pads 224 b. Referring to FIG. 4, thedie bonding pads 224 a are provided in the central part of thesignal transmission plate 224, whereas thewire bonding pads 224 b are provided on the peripheries of thesignal transmission plate 224. - Referring to FIG. 2 again, the
second die 205 is provided on thesignal transmission plate 204, and one side of thesecond die 205 is provided withmetal bumps 215 such as solder bumps. Themetal bumps 215 are first applied with flux so that thesolder bumps 215 are jointed with thedie bonding pads 224 of thesignal transmission plate 224 after reflow. That is, thesecond die 205 is electrically connected with thesignal transmission plate 204 using flip-chip bonding. Moreover, an underfill is filled between thesignal transmission plate 205 and thesolder bumps 215 to prevent the stress concentration effect brought about by thermal stress, which decreases the yield rate. - The second die205 uses flip-chip bonding so that signals from the
second die 205 can be transmitted to thedie bonding pads 224 a via thesecond metal bumps 215. Thedie bonding pads 224 a and thewire bonding pads 224 b are thelayout wire layer 224 exposed at thesolder mask layer 234, and therefore the two are electrically connected with each other. Therefore, signals from thesecond die 205 can be transmitted to thewire bonding pads 224 b via thelayout wire layer 224. Then, signals from thesecond die 205 can be transmitted onto thesubstrate 201 via the conductive wires, gold wires for example, connecting thewire bonding pads 224 b and thesubstrate pad 211. - Generally, thermosetting plastics are used as the
molding compound 208, which is used to encapsulate thefirst die 202, thesignal transmission plate 204, thesecond die 205, and theconductive wires 206 to prevent contamination of the surroundings and damage of external forces.Solder balls 209 can be formed by placing a lead-tin alloy or other metallic materials onto the solder pads on thesubstrate 201, so as to connect with the exterior, a circuit board for instance, for signal transmission. - It is to be noted that the signal transmission plate of this embodiment is a two-layer plate composed of an insulating layer and a layout mask layer. However, for dies with high pin-counts, a signal transmission plated formed by several insulating layers and several layout mask layers alternately overlapping one another can be used to fulfill the wire layout requirement. Like common multi-layer plates, through holes among the insulating layers are demanded between the layout mask layers to accomplish signal connection. The through holes may be provided by machine drilling. Sidewalls of the through holes are plated with a metal layer, and a hole-filling material is stuffed into the through holes.
- Furthermore, in this embodiment, a two-layer stacked die is used as an example. Furthermore, another transmission plate and die can be stacked onto the second die to achieve another type of assembly package.
- Conclusive from the above, the assembly package of the invention employs flip-chip bonding to have signals of the first die (the bottom die) transmitted to the substrate, and therefore imperfect electricity caused by using lead connection is prevented. In addition, the second die (the top die) also uses flip-chip bonding to have signals transmitted to the signal transmission plate, and then the signals are transmitted to the substrate via the conductive wires. As a result, in order to have the signals of the top die transmitted to the substrate, the conductive wires do not need to connect to the joints on the top die, but only need to connect to the wire bonding pads on the signal transmission plate. That is, by shortening the transmission distance of the conductive wires, the objects namely reducing the impedance and signal hysteresis, and speeding up the signal transmission rate can be accomplished, thereby enhancing the performance of the product as a whole. Also, the signal transmission plate can be a multi-layer pressed or laminated substrate to fulfill the requirements of devices with high I/O pin-counts.
- The embodiment described is only illustrative to the technical content of the invention, but not to limit the invention within them. Various modifications can be made without departing from the true spirit and the scope of the appended claims.
Claims (6)
1. A signal transmission plate used in an assembly package having a die, a plurality of conductive wires, and a substrate, the signal transmission plate comprising:
at least one insulating layer;
at least one layout wire layer formed on the insulating layer; and
a solder mask layer formed on the layout wire layer, wherein the solder mask layer exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads.
2. The signal transmission plate as claimed in claim 1 , wherein the die is electrically connected with the die bonding pads, the wire bonding pads are electrically connected with the substrate via the conductive wires.
3. The signal transmission plate as claimed in claim 1 , wherein the layout wire layer is formed by patterning a metal foil.
4. The signal transmission plate as claimed in claim 1 , wherein the metal foil is a copper foil.
5. The signal transmission plate as claimed in claim 1 , wherein the insulating layer is formed of bismaleimide triazine (BT).
6. The signal transmission plate as claimed in claim 1 , wherein the insulating layer is formed of glass epoxy.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/757,808 US20040145035A1 (en) | 2002-01-31 | 2004-01-13 | Signal transmission plate used in an assembly package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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TW091101714A TWI237354B (en) | 2002-01-31 | 2002-01-31 | Stacked package structure |
TW91101714 | 2002-01-31 | ||
US10/293,123 US6717253B2 (en) | 2002-01-31 | 2002-11-12 | Assembly package with stacked dies and signal transmission plate |
US10/757,808 US20040145035A1 (en) | 2002-01-31 | 2004-01-13 | Signal transmission plate used in an assembly package |
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Application Number | Title | Priority Date | Filing Date |
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US10/293,123 Division US6717253B2 (en) | 2002-01-31 | 2002-11-12 | Assembly package with stacked dies and signal transmission plate |
Publications (1)
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US20040145035A1 true US20040145035A1 (en) | 2004-07-29 |
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US10/757,808 Abandoned US20040145035A1 (en) | 2002-01-31 | 2004-01-13 | Signal transmission plate used in an assembly package |
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US10/293,123 Expired - Lifetime US6717253B2 (en) | 2002-01-31 | 2002-11-12 | Assembly package with stacked dies and signal transmission plate |
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Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003273317A (en) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
KR100618812B1 (en) * | 2002-11-18 | 2006-09-05 | 삼성전자주식회사 | Multi chip package having increased reliability |
US20050199996A1 (en) * | 2004-03-10 | 2005-09-15 | Ho Tony H. | Two solder array structure with two high melting solder joints |
DE102004027074B4 (en) * | 2004-06-02 | 2009-06-04 | Infineon Technologies Ag | Method for producing a BGA (Ball Grid Array) component with a thin metallic cooling foil |
WO2006012234A2 (en) * | 2004-06-25 | 2006-02-02 | Sarnoff Corporation | Nitride phosphors and devices |
US7375434B2 (en) * | 2004-09-13 | 2008-05-20 | Infineon Technologies Ag | Semiconductor chip with flexible contacts at a face |
TWI268431B (en) * | 2004-10-21 | 2006-12-11 | Via Tech Inc | Integrated structure with CPU and north bridge chip |
US20070109756A1 (en) * | 2005-02-10 | 2007-05-17 | Stats Chippac Ltd. | Stacked integrated circuits package system |
US20060212842A1 (en) * | 2005-03-15 | 2006-09-21 | Microsoft Corporation | Rich data-bound application |
CN100448002C (en) * | 2005-10-09 | 2008-12-31 | 采钰科技股份有限公司 | Method for producing stacked wafer |
TW200723495A (en) * | 2005-12-07 | 2007-06-16 | Chipmos Technologies Inc | Chip package structure |
US20080042265A1 (en) * | 2006-08-15 | 2008-02-21 | Merilo Leo A | Chip scale module package in bga semiconductor package |
US8138591B2 (en) * | 2006-09-23 | 2012-03-20 | Stats Chippac Ltd | Integrated circuit package system with stacked die |
WO2008078899A1 (en) * | 2006-12-23 | 2008-07-03 | Lg Innotek Co., Ltd | Semiconductor package and manufacturing method thereof |
US8134227B2 (en) * | 2007-03-30 | 2012-03-13 | Stats Chippac Ltd. | Stacked integrated circuit package system with conductive spacer |
TW200843066A (en) * | 2007-04-30 | 2008-11-01 | Chipmos Technologies Inc | Chip stacked package structure and applications thereof |
US7799608B2 (en) * | 2007-08-01 | 2010-09-21 | Advanced Micro Devices, Inc. | Die stacking apparatus and method |
KR100881399B1 (en) * | 2007-08-31 | 2009-02-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
KR20090039411A (en) * | 2007-10-18 | 2009-04-22 | 삼성전자주식회사 | Semiconductor package, module, system having a solder ball being coupled to a chip pad and manufacturing method thereof |
CN101572261A (en) * | 2008-04-28 | 2009-11-04 | 鸿富锦精密工业(深圳)有限公司 | Chip encapsulation structure |
KR101000479B1 (en) * | 2008-10-07 | 2010-12-14 | 박범욱 | Multi chip package |
US20100102457A1 (en) * | 2008-10-28 | 2010-04-29 | Topacio Roden R | Hybrid Semiconductor Chip Package |
JP5671681B2 (en) * | 2009-03-05 | 2015-02-18 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Multilayer semiconductor device |
US8916958B2 (en) * | 2009-04-24 | 2014-12-23 | Infineon Technologies Ag | Semiconductor package with multiple chips and substrate in metal cap |
US8421201B2 (en) * | 2009-06-22 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with underfill and methods of manufacture thereof |
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US8299633B2 (en) * | 2009-12-21 | 2012-10-30 | Advanced Micro Devices, Inc. | Semiconductor chip device with solder diffusion protection |
CN102194779B (en) * | 2010-03-02 | 2013-04-17 | 日月光半导体制造股份有限公司 | Packaging structure |
WO2012126377A1 (en) * | 2011-03-22 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | System-level packaging methods and structures |
US9543269B2 (en) * | 2011-03-22 | 2017-01-10 | Nantong Fujitsu Microelectronics Co., Ltd. | System-level packaging methods and structures |
CN114949526A (en) * | 2011-06-16 | 2022-08-30 | 瑞思迈私人有限公司 | Humidifier and layered heating element |
US8698297B2 (en) * | 2011-09-23 | 2014-04-15 | Stats Chippac Ltd. | Integrated circuit packaging system with stack device |
US8716065B2 (en) | 2011-09-23 | 2014-05-06 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and method of manufacture thereof |
KR20130105175A (en) * | 2012-03-16 | 2013-09-25 | 삼성전자주식회사 | Semiconductor package having protective layer and method of forming the same |
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US9016552B2 (en) * | 2013-03-15 | 2015-04-28 | Sanmina Corporation | Method for forming interposers and stacked memory devices |
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US10510721B2 (en) | 2017-08-11 | 2019-12-17 | Advanced Micro Devices, Inc. | Molded chip combination |
US10593628B2 (en) | 2018-04-24 | 2020-03-17 | Advanced Micro Devices, Inc. | Molded die last chip combination |
US10672712B2 (en) | 2018-07-30 | 2020-06-02 | Advanced Micro Devices, Inc. | Multi-RDL structure packages and methods of fabricating the same |
JP2020043258A (en) * | 2018-09-12 | 2020-03-19 | キオクシア株式会社 | Semiconductor memory and manufacturing method thereof |
CN112151523A (en) * | 2019-06-28 | 2020-12-29 | 中芯长电半导体(江阴)有限公司 | Packaging structure and packaging method of fan-out type fingerprint identification chip |
US10923430B2 (en) | 2019-06-30 | 2021-02-16 | Advanced Micro Devices, Inc. | High density cross link die with polymer routing layer |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4169001A (en) * | 1976-10-18 | 1979-09-25 | International Business Machines Corporation | Method of making multilayer module having optical channels therein |
US4949224A (en) * | 1985-09-20 | 1990-08-14 | Sharp Kabushiki Kaisha | Structure for mounting a semiconductor device |
US20020003160A1 (en) * | 1998-03-26 | 2002-01-10 | Masud Beroz | Components with conductive solder mask layers |
US20020126951A1 (en) * | 2001-03-12 | 2002-09-12 | Sutherland Robert A. | Optical converter flex assemblies |
US6507115B2 (en) * | 2000-12-14 | 2003-01-14 | International Business Machines Corporation | Multi-chip integrated circuit module |
US6509646B1 (en) * | 2000-05-22 | 2003-01-21 | Silicon Integrated Systems Corp. | Apparatus for reducing an electrical noise inside a ball grid array package |
US6552272B1 (en) * | 2001-10-19 | 2003-04-22 | Primax Electronics, Ltd. | Anti-abrasive flat flexible cable |
US6665025B2 (en) * | 1998-09-24 | 2003-12-16 | Samsung Electronics Co., Ltd. | Liquid crystal display device and a method for manufacturing a grounding device |
US6730858B2 (en) * | 1997-07-22 | 2004-05-04 | Tdk Corporation | Circuit board having bonding areas to be joined with bumps by ultrasonic bonding |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05175279A (en) * | 1991-12-25 | 1993-07-13 | Fujitsu Ltd | Integrated circuit element packaging device |
JP3109477B2 (en) * | 1998-05-26 | 2000-11-13 | 日本電気株式会社 | Multi-chip module |
KR100266693B1 (en) * | 1998-05-30 | 2000-09-15 | 김영환 | Stackable ball grid array semiconductor package and fabrication method thereof |
JP3179420B2 (en) * | 1998-11-10 | 2001-06-25 | 日本電気株式会社 | Semiconductor device |
US6043109A (en) * | 1999-02-09 | 2000-03-28 | United Microelectronics Corp. | Method of fabricating wafer-level package |
JP3670917B2 (en) * | 1999-12-16 | 2005-07-13 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
KR20010064907A (en) * | 1999-12-20 | 2001-07-11 | 마이클 디. 오브라이언 | wire bonding method and semiconductor package using it |
JP2001227902A (en) * | 2000-02-16 | 2001-08-24 | Mitsubishi Electric Corp | Semiconductor device |
JP2002076248A (en) * | 2000-08-29 | 2002-03-15 | Oki Micro Design Co Ltd | Multi-chip package |
JP3631120B2 (en) * | 2000-09-28 | 2005-03-23 | 沖電気工業株式会社 | Semiconductor device |
US6889429B2 (en) * | 2001-03-26 | 2005-05-10 | Semiconductor Components Industries, L.L.C. | Method of making a lead-free integrated circuit package |
JP3959264B2 (en) * | 2001-09-29 | 2007-08-15 | 株式会社東芝 | Multilayer semiconductor device |
-
2002
- 2002-01-31 TW TW091101714A patent/TWI237354B/en not_active IP Right Cessation
- 2002-11-12 US US10/293,123 patent/US6717253B2/en not_active Expired - Lifetime
-
2004
- 2004-01-13 US US10/757,808 patent/US20040145035A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4169001A (en) * | 1976-10-18 | 1979-09-25 | International Business Machines Corporation | Method of making multilayer module having optical channels therein |
US4949224A (en) * | 1985-09-20 | 1990-08-14 | Sharp Kabushiki Kaisha | Structure for mounting a semiconductor device |
US6730858B2 (en) * | 1997-07-22 | 2004-05-04 | Tdk Corporation | Circuit board having bonding areas to be joined with bumps by ultrasonic bonding |
US20020003160A1 (en) * | 1998-03-26 | 2002-01-10 | Masud Beroz | Components with conductive solder mask layers |
US6665025B2 (en) * | 1998-09-24 | 2003-12-16 | Samsung Electronics Co., Ltd. | Liquid crystal display device and a method for manufacturing a grounding device |
US6509646B1 (en) * | 2000-05-22 | 2003-01-21 | Silicon Integrated Systems Corp. | Apparatus for reducing an electrical noise inside a ball grid array package |
US6507115B2 (en) * | 2000-12-14 | 2003-01-14 | International Business Machines Corporation | Multi-chip integrated circuit module |
US20020126951A1 (en) * | 2001-03-12 | 2002-09-12 | Sutherland Robert A. | Optical converter flex assemblies |
US6552272B1 (en) * | 2001-10-19 | 2003-04-22 | Primax Electronics, Ltd. | Anti-abrasive flat flexible cable |
Also Published As
Publication number | Publication date |
---|---|
TWI237354B (en) | 2005-08-01 |
US6717253B2 (en) | 2004-04-06 |
US20030141583A1 (en) | 2003-07-31 |
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